f3387f38e3e5e6f48c8a2c7236d27b67e96e095a
[dpdk.git] / drivers / raw / cnxk_bphy / rte_pmd_bphy.h
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(C) 2021 Marvell.
3  */
4
5 #ifndef _CNXK_BPHY_H_
6 #define _CNXK_BPHY_H_
7
8 #include "cnxk_bphy_irq.h"
9
10 enum cnxk_bphy_cgx_msg_type {
11         CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
12         CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
13         CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE,
14         CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE,
15         CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE,
16         CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE,
17         CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE,
18         CNXK_BPHY_CGX_MSG_TYPE_START_RXTX,
19         CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX,
20 };
21
22 enum cnxk_bphy_cgx_eth_link_speed {
23         CNXK_BPHY_CGX_ETH_LINK_SPEED_NONE,
24         CNXK_BPHY_CGX_ETH_LINK_SPEED_10M,
25         CNXK_BPHY_CGX_ETH_LINK_SPEED_100M,
26         CNXK_BPHY_CGX_ETH_LINK_SPEED_1G,
27         CNXK_BPHY_CGX_ETH_LINK_SPEED_2HG,
28         CNXK_BPHY_CGX_ETH_LINK_SPEED_5G,
29         CNXK_BPHY_CGX_ETH_LINK_SPEED_10G,
30         CNXK_BPHY_CGX_ETH_LINK_SPEED_20G,
31         CNXK_BPHY_CGX_ETH_LINK_SPEED_25G,
32         CNXK_BPHY_CGX_ETH_LINK_SPEED_40G,
33         CNXK_BPHY_CGX_ETH_LINK_SPEED_50G,
34         CNXK_BPHY_CGX_ETH_LINK_SPEED_80G,
35         CNXK_BPHY_CGX_ETH_LINK_SPEED_100G,
36         __CNXK_BPHY_CGX_ETH_LINK_SPEED_MAX
37 };
38
39 enum cnxk_bphy_cgx_eth_link_fec {
40         CNXK_BPHY_CGX_ETH_LINK_FEC_NONE,
41         CNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R,
42         CNXK_BPHY_CGX_ETH_LINK_FEC_RS,
43         __CNXK_BPHY_CGX_ETH_LINK_FEC_MAX
44 };
45
46 enum cnxk_bphy_cgx_eth_link_mode {
47         CNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
48         CNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
49         CNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
50         CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
51         CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
52         CNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
53         CNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
54         CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
55         CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
56         CNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
57         CNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
58         CNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
59         CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
60         CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
61         CNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
62         CNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
63         CNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
64         CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
65         CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
66         CNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
67         CNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
68         CNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
69         CNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
70         CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
71         CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
72         CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
73         CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
74         __CNXK_BPHY_CGX_ETH_LINK_MODE_MAX
75 };
76
77 struct cnxk_bphy_cgx_msg_link_mode {
78         bool full_duplex;
79         bool autoneg;
80         enum cnxk_bphy_cgx_eth_link_speed speed;
81         enum cnxk_bphy_cgx_eth_link_mode mode;
82 };
83
84 struct cnxk_bphy_cgx_msg_link_info {
85         bool link_up;
86         bool full_duplex;
87         enum cnxk_bphy_cgx_eth_link_speed speed;
88         bool autoneg;
89         enum cnxk_bphy_cgx_eth_link_fec fec;
90         enum cnxk_bphy_cgx_eth_link_mode mode;
91 };
92
93 struct cnxk_bphy_cgx_msg_set_link_state {
94         bool state; /* up or down */
95 };
96
97 struct cnxk_bphy_cgx_msg {
98         enum cnxk_bphy_cgx_msg_type type;
99         /*
100          * data depends on message type and whether
101          * it's a request or a response
102          */
103         void *data;
104 };
105
106 #define cnxk_bphy_mem       bphy_mem
107 #define CNXK_BPHY_DEF_QUEUE 0
108
109 enum cnxk_bphy_irq_msg_type {
110         CNXK_BPHY_IRQ_MSG_TYPE_INIT,
111         CNXK_BPHY_IRQ_MSG_TYPE_FINI,
112         CNXK_BPHY_IRQ_MSG_TYPE_REGISTER,
113         CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER,
114         CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,
115 };
116
117 struct cnxk_bphy_irq_msg {
118         enum cnxk_bphy_irq_msg_type type;
119         /*
120          * The data field, depending on message type, may point to
121          * - (enq) full struct cnxk_bphy_irq_info for registration request
122          * - (enq) struct cnxk_bphy_irq_info with irq_num set for unregistration
123          * - (deq) struct cnxk_bphy_mem for memory range request response
124          * - (xxx) NULL
125          */
126         void *data;
127 };
128
129 struct cnxk_bphy_irq_info {
130         int irq_num;
131         cnxk_bphy_intr_handler_t handler;
132         void *data;
133         int cpu;
134 };
135
136 static __rte_always_inline int
137 rte_pmd_bphy_intr_init(uint16_t dev_id)
138 {
139         struct cnxk_bphy_irq_msg msg = {
140                 .type = CNXK_BPHY_IRQ_MSG_TYPE_INIT,
141         };
142         struct rte_rawdev_buf *bufs[1];
143         struct rte_rawdev_buf buf;
144
145         buf.buf_addr = &msg;
146         bufs[0] = &buf;
147
148         return rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
149 }
150
151 static __rte_always_inline void
152 rte_pmd_bphy_intr_fini(uint16_t dev_id)
153 {
154         struct cnxk_bphy_irq_msg msg = {
155                 .type = CNXK_BPHY_IRQ_MSG_TYPE_FINI,
156         };
157         struct rte_rawdev_buf *bufs[1];
158         struct rte_rawdev_buf buf;
159
160         buf.buf_addr = &msg;
161         bufs[0] = &buf;
162
163         rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
164 }
165
166 static __rte_always_inline int
167 rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num,
168                            cnxk_bphy_intr_handler_t handler, void *data,
169                            int cpu)
170 {
171         struct cnxk_bphy_irq_info info = {
172                 .irq_num = irq_num,
173                 .handler = handler,
174                 .data = data,
175                 .cpu = cpu,
176         };
177         struct cnxk_bphy_irq_msg msg = {
178                 .type = CNXK_BPHY_IRQ_MSG_TYPE_REGISTER,
179                 .data = &info
180         };
181         struct rte_rawdev_buf *bufs[1];
182         struct rte_rawdev_buf buf;
183
184         buf.buf_addr = &msg;
185         bufs[0] = &buf;
186
187         return rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
188 }
189
190 static __rte_always_inline void
191 rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num)
192 {
193         struct cnxk_bphy_irq_info info = {
194                 .irq_num = irq_num,
195         };
196         struct cnxk_bphy_irq_msg msg = {
197                 .type = CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER,
198                 .data = &info
199         };
200         struct rte_rawdev_buf *bufs[1];
201         struct rte_rawdev_buf buf;
202
203         buf.buf_addr = &msg;
204         bufs[0] = &buf;
205
206         rte_rawdev_enqueue_buffers(dev_id, bufs, 1, 0);
207 }
208
209 static __rte_always_inline struct cnxk_bphy_mem *
210 rte_pmd_bphy_intr_mem_get(uint16_t dev_id)
211 {
212         struct cnxk_bphy_irq_msg msg = {
213                 .type = CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,
214         };
215         struct rte_rawdev_buf *bufs[1];
216         struct rte_rawdev_buf buf;
217         int ret;
218
219         buf.buf_addr = &msg;
220         bufs[0] = &buf;
221
222         ret = rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
223         if (ret)
224                 return NULL;
225
226         ret = rte_rawdev_dequeue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
227         if (ret)
228                 return NULL;
229
230         return buf.buf_addr;
231 }
232
233 #endif /* _CNXK_BPHY_H_ */