1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
11 #include <sys/ioctl.h>
12 #include <sys/epoll.h>
15 #include <rte_malloc.h>
16 #include <rte_devargs.h>
17 #include <rte_memcpy.h>
19 #include <rte_bus_pci.h>
20 #include <rte_kvargs.h>
21 #include <rte_alarm.h>
22 #include <rte_interrupts.h>
23 #include <rte_errno.h>
24 #include <rte_per_lcore.h>
25 #include <rte_memory.h>
26 #include <rte_memzone.h>
28 #include <rte_common.h>
29 #include <rte_bus_vdev.h>
30 #include <rte_string_fns.h>
31 #include <rte_pmd_i40e.h>
33 #include "base/opae_hw_api.h"
34 #include "base/opae_ifpga_hw_api.h"
35 #include "base/ifpga_api.h"
36 #include "rte_rawdev.h"
37 #include "rte_rawdev_pmd.h"
38 #include "rte_bus_ifpga.h"
39 #include "ifpga_common.h"
40 #include "ifpga_logs.h"
41 #include "ifpga_rawdev.h"
42 #include "ipn3ke_rawdev_api.h"
44 #define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
45 #define RTE_PCI_CFG_SPACE_SIZE 256
46 #define RTE_PCI_CFG_SPACE_EXP_SIZE 4096
47 #define RTE_PCI_EXT_CAP_ID(header) (int)(header & 0x0000ffff)
48 #define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
50 #define PCI_VENDOR_ID_INTEL 0x8086
52 #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
53 #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
54 #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
55 #define PCIE_DEVICE_ID_PAC_N3000 0x0B30
57 #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
58 #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
59 #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
60 #define PCIE_DEVICE_ID_VF_PAC_N3000 0x0B31
61 #define RTE_MAX_RAW_DEVICE 10
63 static const struct rte_pci_id pci_ifpga_map[] = {
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
72 { .vendor_id = 0, /* sentinel */ },
75 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
77 static int ifpga_monitor_start;
78 static pthread_t ifpga_monitor_start_thread;
80 #define IFPGA_MAX_IRQ 12
81 /* 0 for FME interrupt, others are reserved for AFU irq */
82 static struct rte_intr_handle ifpga_irq_handle[IFPGA_MAX_IRQ];
84 static struct ifpga_rawdev *
85 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
86 static int set_surprise_link_check_aer(
87 struct ifpga_rawdev *ifpga_rdev, int force_disable);
88 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
90 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap);
93 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
95 struct ifpga_rawdev *dev;
101 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
102 dev = &ifpga_rawdevices[i];
103 if (dev->rawdev == rawdev)
110 static inline uint8_t
111 ifpga_rawdev_find_free_device_index(void)
115 for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
116 if (ifpga_rawdevices[dev_id].rawdev == NULL)
120 return IFPGA_RAWDEV_NUM;
122 static struct ifpga_rawdev *
123 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
125 struct ifpga_rawdev *dev;
128 dev = ifpga_rawdev_get(rawdev);
130 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
134 dev_id = ifpga_rawdev_find_free_device_index();
135 if (dev_id == IFPGA_RAWDEV_NUM) {
136 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
140 dev = &ifpga_rawdevices[dev_id];
141 dev->rawdev = rawdev;
142 dev->dev_id = dev_id;
147 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
152 int pos = RTE_PCI_CFG_SPACE_SIZE;
155 /* minimum 8 bytes per capability */
156 ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
160 ret = pread(fd, &header, sizeof(header), pos);
165 * If we have no capabilities, this is indicated by cap ID,
166 * cap version and next pointer all being 0.
172 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
175 pos = RTE_PCI_EXT_CAP_NEXT(header);
176 if (pos < RTE_PCI_CFG_SPACE_SIZE)
178 ret = pread(fd, &header, sizeof(header), pos);
186 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap)
188 return ifpga_pci_find_next_ext_capability(fd, 0, cap);
191 static int ifpga_get_dev_vendor_id(const char *bdf,
192 uint32_t *dev_id, uint32_t *vendor_id)
199 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
200 strlcat(path, bdf, sizeof(path));
201 strlcat(path, "/config", sizeof(path));
202 fd = open(path, O_RDWR);
205 ret = pread(fd, &header, sizeof(header), 0);
210 (*vendor_id) = header & 0xffff;
211 (*dev_id) = (header >> 16) & 0xffff;
216 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev,
219 char path[1024] = "/sys/bus/pci/devices/0000:";
220 char link[1024], link1[1024];
221 char dir[1024] = "/sys/devices/";
224 char sub_brg_bdf[4][16];
227 struct dirent *entry;
230 unsigned int dom, bus, dev;
232 uint32_t dev_id, vendor_id;
234 strlcat(path, bdf, sizeof(path));
235 memset(link, 0, sizeof(link));
236 memset(link1, 0, sizeof(link1));
237 ret = readlink(path, link, (sizeof(link)-1));
240 strlcpy(link1, link, sizeof(link1));
241 memset(ifpga_dev->parent_bdf, 0, 16);
242 point = strlen(link);
250 rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
252 point = strlen(link1);
260 c = strchr(link1, 'p');
263 strlcat(dir, c, sizeof(dir));
270 while ((entry = readdir(dp)) != NULL) {
273 if (entry->d_name[0] == '.')
275 if (strlen(entry->d_name) > 12)
277 if (sscanf(entry->d_name, "%x:%x:%x.%d",
278 &dom, &bus, &dev, &func) < 4)
281 strlcpy(sub_brg_bdf[i],
283 sizeof(sub_brg_bdf[i]));
289 /* get fpga and fvl */
291 for (i = 0; i < 4; i++) {
292 strlcpy(link, dir, sizeof(link));
293 strlcat(link, "/", sizeof(link));
294 strlcat(link, sub_brg_bdf[i], sizeof(link));
298 while ((entry = readdir(dp)) != NULL) {
301 if (entry->d_name[0] == '.')
304 if (strlen(entry->d_name) > 12)
306 if (sscanf(entry->d_name, "%x:%x:%x.%d",
307 &dom, &bus, &dev, &func) < 4)
310 if (ifpga_get_dev_vendor_id(entry->d_name,
311 &dev_id, &vendor_id))
313 if (vendor_id == 0x8086 &&
317 strlcpy(ifpga_dev->fvl_bdf[j],
319 sizeof(ifpga_dev->fvl_bdf[j]));
330 #define HIGH_FATAL(_sens, value)\
331 (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
332 (value > (_sens)->high_fatal))
334 #define HIGH_WARN(_sens, value)\
335 (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
336 (value > (_sens)->high_warn))
338 #define LOW_FATAL(_sens, value)\
339 (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
340 (value > (_sens)->low_fatal))
342 #define LOW_WARN(_sens, value)\
343 (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
344 (value > (_sens)->low_warn))
346 #define AUX_VOLTAGE_WARN 11400
349 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
352 struct opae_adapter *adapter;
353 struct opae_manager *mgr;
354 struct opae_sensor_info *sensor;
358 adapter = ifpga_rawdev_get_priv(raw_dev);
362 mgr = opae_adapter_get_mgr(adapter);
366 opae_mgr_for_each_sensor(mgr, sensor) {
367 if (!(sensor->flags & OPAE_SENSOR_VALID))
370 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
374 if (value == 0xdeadbeef) {
375 IFPGA_RAWDEV_PMD_ERR("dev_id %d sensor %s value %x\n",
376 raw_dev->dev_id, sensor->name, value);
380 /* monitor temperature sensors */
381 if (!strcmp(sensor->name, "Board Temperature") ||
382 !strcmp(sensor->name, "FPGA Die Temperature")) {
383 IFPGA_RAWDEV_PMD_INFO("read sensor %s %d %d %d\n",
384 sensor->name, value, sensor->high_warn,
387 if (HIGH_WARN(sensor, value) ||
388 LOW_WARN(sensor, value)) {
389 IFPGA_RAWDEV_PMD_INFO("%s reach theshold %d\n",
390 sensor->name, value);
396 /* monitor 12V AUX sensor */
397 if (!strcmp(sensor->name, "12V AUX Voltage")) {
398 if (value < AUX_VOLTAGE_WARN) {
399 IFPGA_RAWDEV_PMD_INFO(
400 "%s reach theshold %d mV\n",
401 sensor->name, value);
413 static int set_surprise_link_check_aer(
414 struct ifpga_rawdev *ifpga_rdev, int force_disable)
416 struct rte_rawdev *rdev;
423 uint32_t aer_new0, aer_new1;
426 printf("\n device does not exist\n");
430 rdev = ifpga_rdev->rawdev;
431 if (ifpga_rdev->aer_enable)
433 if (ifpga_monitor_sensor(rdev, &enable))
435 if (enable || force_disable) {
436 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
437 ifpga_rdev->aer_enable = 1;
439 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
440 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
441 strlcat(path, "/config", sizeof(path));
442 fd = open(path, O_RDWR);
445 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
448 /* save previout ECAP_AER+0x08 */
449 ret = pread(fd, &data, sizeof(data), pos+0x08);
452 ifpga_rdev->aer_old[0] = data;
453 /* save previout ECAP_AER+0x14 */
454 ret = pread(fd, &data, sizeof(data), pos+0x14);
457 ifpga_rdev->aer_old[1] = data;
459 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
461 ret = pwrite(fd, &data, 4, pos+0x08);
464 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
465 ret = pwrite(fd, &data, 4, pos+0x14);
469 /* read current ECAP_AER+0x08 */
470 ret = pread(fd, &data, sizeof(data), pos+0x08);
474 /* read current ECAP_AER+0x14 */
475 ret = pread(fd, &data, sizeof(data), pos+0x14);
483 printf(">>>>>>Set AER %x,%x %x,%x\n",
484 ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
497 ifpga_rawdev_gsd_handle(__rte_unused void *param)
499 struct ifpga_rawdev *ifpga_rdev;
506 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
507 ifpga_rdev = &ifpga_rawdevices[i];
508 if (ifpga_rdev->rawdev) {
509 ret = set_surprise_link_check_aer(ifpga_rdev,
511 if (ret == 1 && !gsd_enable) {
519 printf(">>>>>>Pls Shutdown APP\n");
521 rte_delay_us(100 * MS);
528 ifpga_monitor_start_func(void)
532 if (ifpga_monitor_start == 0) {
533 ret = pthread_create(&ifpga_monitor_start_thread,
535 ifpga_rawdev_gsd_handle, NULL);
537 IFPGA_RAWDEV_PMD_ERR(
538 "Fail to create ifpga nonitor thread");
541 ifpga_monitor_start = 1;
547 ifpga_monitor_stop_func(void)
551 if (ifpga_monitor_start == 1) {
552 ret = pthread_cancel(ifpga_monitor_start_thread);
554 IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
556 ret = pthread_join(ifpga_monitor_start_thread, NULL);
558 IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
560 ifpga_monitor_start = 0;
569 ifpga_fill_afu_dev(struct opae_accelerator *acc,
570 struct rte_afu_device *afu_dev)
572 struct rte_mem_resource *res = afu_dev->mem_resource;
573 struct opae_acc_region_info region_info;
574 struct opae_acc_info info;
578 ret = opae_acc_get_info(acc, &info);
582 if (info.num_regions > PCI_MAX_RESOURCE)
585 afu_dev->num_region = info.num_regions;
587 for (i = 0; i < info.num_regions; i++) {
588 region_info.index = i;
589 ret = opae_acc_get_region_info(acc, ®ion_info);
593 if ((region_info.flags & ACC_REGION_MMIO) &&
594 (region_info.flags & ACC_REGION_READ) &&
595 (region_info.flags & ACC_REGION_WRITE)) {
596 res[i].phys_addr = region_info.phys_addr;
597 res[i].len = region_info.len;
598 res[i].addr = region_info.addr;
607 ifpga_rawdev_info_get(struct rte_rawdev *dev,
608 rte_rawdev_obj_t dev_info)
610 struct opae_adapter *adapter;
611 struct opae_accelerator *acc;
612 struct rte_afu_device *afu_dev;
613 struct opae_manager *mgr = NULL;
614 struct opae_eth_group_region_info opae_lside_eth_info;
615 struct opae_eth_group_region_info opae_nside_eth_info;
616 int lside_bar_idx, nside_bar_idx;
618 IFPGA_RAWDEV_PMD_FUNC_TRACE();
621 IFPGA_RAWDEV_PMD_ERR("Invalid request");
625 adapter = ifpga_rawdev_get_priv(dev);
630 afu_dev->rawdev = dev;
632 /* find opae_accelerator and fill info into afu_device */
633 opae_adapter_for_each_acc(adapter, acc) {
634 if (acc->index != afu_dev->id.port)
637 if (ifpga_fill_afu_dev(acc, afu_dev)) {
638 IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
643 /* get opae_manager to rawdev */
644 mgr = opae_adapter_get_mgr(adapter);
646 /* get LineSide BAR Index */
647 if (opae_manager_get_eth_group_region_info(mgr, 0,
648 &opae_lside_eth_info)) {
651 lside_bar_idx = opae_lside_eth_info.mem_idx;
653 /* get NICSide BAR Index */
654 if (opae_manager_get_eth_group_region_info(mgr, 1,
655 &opae_nside_eth_info)) {
658 nside_bar_idx = opae_nside_eth_info.mem_idx;
660 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
661 nside_bar_idx >= PCI_MAX_RESOURCE ||
662 lside_bar_idx == nside_bar_idx)
665 /* fill LineSide BAR Index */
666 afu_dev->mem_resource[lside_bar_idx].phys_addr =
667 opae_lside_eth_info.phys_addr;
668 afu_dev->mem_resource[lside_bar_idx].len =
669 opae_lside_eth_info.len;
670 afu_dev->mem_resource[lside_bar_idx].addr =
671 opae_lside_eth_info.addr;
673 /* fill NICSide BAR Index */
674 afu_dev->mem_resource[nside_bar_idx].phys_addr =
675 opae_nside_eth_info.phys_addr;
676 afu_dev->mem_resource[nside_bar_idx].len =
677 opae_nside_eth_info.len;
678 afu_dev->mem_resource[nside_bar_idx].addr =
679 opae_nside_eth_info.addr;
684 ifpga_rawdev_configure(const struct rte_rawdev *dev,
685 rte_rawdev_obj_t config)
687 IFPGA_RAWDEV_PMD_FUNC_TRACE();
689 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
691 return config ? 0 : 1;
695 ifpga_rawdev_start(struct rte_rawdev *dev)
698 struct opae_adapter *adapter;
700 IFPGA_RAWDEV_PMD_FUNC_TRACE();
702 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
704 adapter = ifpga_rawdev_get_priv(dev);
712 ifpga_rawdev_stop(struct rte_rawdev *dev)
718 ifpga_rawdev_close(struct rte_rawdev *dev)
724 ifpga_rawdev_reset(struct rte_rawdev *dev)
730 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
734 struct opae_adapter *adapter;
735 struct opae_manager *mgr;
736 struct opae_accelerator *acc;
737 struct opae_bridge *br;
740 adapter = ifpga_rawdev_get_priv(raw_dev);
744 mgr = opae_adapter_get_mgr(adapter);
748 acc = opae_adapter_get_acc(adapter, port_id);
752 br = opae_acc_get_br(acc);
756 ret = opae_manager_flash(mgr, port_id, buffer, size, status);
758 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
762 ret = opae_bridge_reset(br);
764 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
765 __func__, port_id, ret);
773 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
774 const char *file_name)
776 struct stat file_stat;
786 file_fd = open(file_name, O_RDONLY);
788 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
789 __func__, file_name);
790 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
793 ret = stat(file_name, &file_stat);
795 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
800 buffer_size = file_stat.st_size;
801 if (buffer_size <= 0) {
806 IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
807 buffer = rte_malloc(NULL, buffer_size, 0);
813 /*read the raw data*/
814 if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
820 ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
821 IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
822 ret ? "failed" : "success");
838 ifpga_rawdev_pr(struct rte_rawdev *dev,
839 rte_rawdev_obj_t pr_conf)
841 struct opae_adapter *adapter;
842 struct opae_manager *mgr;
843 struct opae_board_info *info;
844 struct rte_afu_pr_conf *afu_pr_conf;
847 struct opae_accelerator *acc;
849 IFPGA_RAWDEV_PMD_FUNC_TRACE();
851 adapter = ifpga_rawdev_get_priv(dev);
858 afu_pr_conf = pr_conf;
860 if (afu_pr_conf->pr_enable) {
861 ret = rte_fpga_do_pr(dev,
862 afu_pr_conf->afu_id.port,
863 afu_pr_conf->bs_path);
865 IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
870 mgr = opae_adapter_get_mgr(adapter);
872 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
876 if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
877 IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
881 if (info->lightweight) {
882 /* set uuid to all 0, when fpga is lightweight image */
883 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
884 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
886 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
890 ret = opae_acc_get_uuid(acc, &uuid);
894 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
896 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
899 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
901 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
902 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
908 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
909 const char *attr_name, uint64_t *attr_value)
911 struct opae_adapter *adapter;
912 struct opae_manager *mgr;
913 struct opae_retimer_info opae_rtm_info;
914 struct opae_retimer_status opae_rtm_status;
915 struct opae_eth_group_info opae_eth_grp_info;
916 struct opae_eth_group_region_info opae_eth_grp_reg_info;
917 int eth_group_num = 0;
918 uint64_t port_link_bitmap = 0, port_link_bit;
921 #define MAX_PORT_PER_RETIMER 4
923 IFPGA_RAWDEV_PMD_FUNC_TRACE();
925 if (!dev || !attr_name || !attr_value) {
926 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
930 adapter = ifpga_rawdev_get_priv(dev);
932 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
936 mgr = opae_adapter_get_mgr(adapter);
938 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
942 /* currently, eth_group_num is always 2 */
943 eth_group_num = opae_manager_get_eth_group_nums(mgr);
944 if (eth_group_num < 0)
947 if (!strcmp(attr_name, "LineSideBaseMAC")) {
948 /* Currently FPGA not implement, so just set all zeros*/
949 *attr_value = (uint64_t)0;
952 if (!strcmp(attr_name, "LineSideMACType")) {
953 /* eth_group 0 on FPGA connect to LineSide */
954 if (opae_manager_get_eth_group_info(mgr, 0,
957 switch (opae_eth_grp_info.speed) {
960 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
964 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
968 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
973 if (!strcmp(attr_name, "LineSideLinkSpeed")) {
974 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
976 switch (opae_rtm_status.speed) {
979 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
983 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
987 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
991 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
995 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
999 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
1003 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1005 case MXD_SPEED_UNKNOWN:
1007 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1011 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1016 if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1017 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1019 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1022 if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1023 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1025 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1026 (uint64_t)opae_rtm_info.nums_retimer;
1030 if (!strcmp(attr_name, "LineSideLinkStatus")) {
1031 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1033 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1037 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1038 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1039 p = i * MAX_PORT_PER_RETIMER;
1040 for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1042 IFPGA_BIT_SET(port_link_bit, (p+j));
1043 port_link_bit &= port_link_bitmap;
1045 IFPGA_BIT_SET((*attr_value), q);
1051 if (!strcmp(attr_name, "LineSideBARIndex")) {
1052 /* eth_group 0 on FPGA connect to LineSide */
1053 if (opae_manager_get_eth_group_region_info(mgr, 0,
1054 &opae_eth_grp_reg_info))
1056 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1059 if (!strcmp(attr_name, "NICSideMACType")) {
1060 /* eth_group 1 on FPGA connect to NicSide */
1061 if (opae_manager_get_eth_group_info(mgr, 1,
1062 &opae_eth_grp_info))
1064 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1067 if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1068 /* eth_group 1 on FPGA connect to NicSide */
1069 if (opae_manager_get_eth_group_info(mgr, 1,
1070 &opae_eth_grp_info))
1072 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1075 if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1076 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1078 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1079 (uint64_t)opae_rtm_info.ports_per_fvl;
1083 if (!strcmp(attr_name, "NICSideLinkStatus"))
1085 if (!strcmp(attr_name, "NICSideBARIndex")) {
1086 /* eth_group 1 on FPGA connect to NicSide */
1087 if (opae_manager_get_eth_group_region_info(mgr, 1,
1088 &opae_eth_grp_reg_info))
1090 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1094 IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1098 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1099 .dev_info_get = ifpga_rawdev_info_get,
1100 .dev_configure = ifpga_rawdev_configure,
1101 .dev_start = ifpga_rawdev_start,
1102 .dev_stop = ifpga_rawdev_stop,
1103 .dev_close = ifpga_rawdev_close,
1104 .dev_reset = ifpga_rawdev_reset,
1106 .queue_def_conf = NULL,
1107 .queue_setup = NULL,
1108 .queue_release = NULL,
1110 .attr_get = ifpga_rawdev_get_attr,
1113 .enqueue_bufs = NULL,
1114 .dequeue_bufs = NULL,
1119 .xstats_get_names = NULL,
1120 .xstats_get_by_name = NULL,
1121 .xstats_reset = NULL,
1123 .firmware_status_get = NULL,
1124 .firmware_version_get = NULL,
1125 .firmware_load = ifpga_rawdev_pr,
1126 .firmware_unload = NULL,
1128 .dev_selftest = NULL,
1132 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1133 u64 prop_id, u64 *val)
1135 struct feature_prop prop;
1137 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1138 prop.prop_id = prop_id;
1140 if (opae_manager_ifpga_get_prop(mgr, &prop))
1149 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1150 u64 prop_id, u64 val)
1152 struct feature_prop prop;
1154 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1155 prop.prop_id = prop_id;
1159 if (opae_manager_ifpga_set_prop(mgr, &prop))
1166 fme_err_read_seu_emr(struct opae_manager *mgr)
1171 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1175 IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1177 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1181 IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1186 static int fme_clear_warning_intr(struct opae_manager *mgr)
1190 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1193 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1195 if ((val & 0x40) != 0)
1196 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1201 static int fme_clean_fme_error(struct opae_manager *mgr)
1205 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1208 IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1210 ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1212 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1215 IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1221 fme_err_handle_error0(struct opae_manager *mgr)
1223 struct feature_fme_error0 fme_error0;
1226 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1229 if (fme_clean_fme_error(mgr))
1232 fme_error0.csr = val;
1234 if (fme_error0.fabric_err)
1235 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1236 else if (fme_error0.fabfifo_overflow)
1237 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1238 else if (fme_error0.afu_acc_mode_err)
1239 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1240 else if (fme_error0.pcie0cdc_parity_err)
1241 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1242 else if (fme_error0.cvlcdc_parity_err)
1243 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1244 else if (fme_error0.fpgaseuerr)
1245 fme_err_read_seu_emr(mgr);
1247 /* clean the errors */
1248 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1255 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1257 struct feature_fme_ras_catfaterror fme_catfatal;
1260 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1263 fme_catfatal.csr = val;
1265 if (fme_catfatal.cci_fatal_err)
1266 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1267 else if (fme_catfatal.fabric_fatal_err)
1268 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1269 else if (fme_catfatal.pcie_poison_err)
1270 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1271 else if (fme_catfatal.inject_fata_err)
1272 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1273 else if (fme_catfatal.crc_catast_err)
1274 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1275 else if (fme_catfatal.injected_catast_err)
1276 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1277 else if (fme_catfatal.bmc_seu_catast_err)
1278 fme_err_read_seu_emr(mgr);
1284 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1286 struct feature_fme_ras_nonfaterror nonfaterr;
1289 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1292 nonfaterr.csr = val;
1294 if (nonfaterr.temp_thresh_ap1)
1295 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1296 else if (nonfaterr.temp_thresh_ap2)
1297 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1298 else if (nonfaterr.pcie_error)
1299 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1300 else if (nonfaterr.portfatal_error)
1301 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1302 else if (nonfaterr.proc_hot)
1303 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1304 else if (nonfaterr.afu_acc_mode_err)
1305 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1306 else if (nonfaterr.injected_nonfata_err) {
1307 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1308 fme_clear_warning_intr(mgr);
1309 } else if (nonfaterr.temp_thresh_AP6)
1310 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1311 else if (nonfaterr.power_thresh_AP1)
1312 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1313 else if (nonfaterr.power_thresh_AP2)
1314 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1315 else if (nonfaterr.mbp_err)
1316 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1322 fme_interrupt_handler(void *param)
1324 struct opae_manager *mgr = (struct opae_manager *)param;
1326 IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1328 fme_err_handle_error0(mgr);
1329 fme_err_handle_nonfaterror(mgr);
1330 fme_err_handle_catfatal_error(mgr);
1334 ifpga_unregister_msix_irq(enum ifpga_irq_type type,
1335 int vec_start, rte_intr_callback_fn handler, void *arg)
1337 struct rte_intr_handle intr_handle;
1339 if (type == IFPGA_FME_IRQ)
1340 intr_handle = ifpga_irq_handle[0];
1341 else if (type == IFPGA_AFU_IRQ)
1342 intr_handle = ifpga_irq_handle[vec_start + 1];
1344 rte_intr_efd_disable(&intr_handle);
1346 return rte_intr_callback_unregister(&intr_handle,
1351 ifpga_register_msix_irq(struct rte_rawdev *dev, int port_id,
1352 enum ifpga_irq_type type, int vec_start, int count,
1353 rte_intr_callback_fn handler, const char *name,
1357 struct rte_intr_handle intr_handle;
1358 struct opae_adapter *adapter;
1359 struct opae_manager *mgr;
1360 struct opae_accelerator *acc;
1362 adapter = ifpga_rawdev_get_priv(dev);
1366 mgr = opae_adapter_get_mgr(adapter);
1370 if (type == IFPGA_FME_IRQ) {
1371 intr_handle = ifpga_irq_handle[0];
1373 } else if (type == IFPGA_AFU_IRQ)
1374 intr_handle = ifpga_irq_handle[vec_start + 1];
1376 intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
1378 ret = rte_intr_efd_enable(&intr_handle, count);
1382 intr_handle.fd = intr_handle.efds[0];
1384 IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
1385 name, intr_handle.vfio_dev_fd,
1388 if (type == IFPGA_FME_IRQ) {
1389 struct fpga_fme_err_irq_set err_irq_set;
1390 err_irq_set.evtfd = intr_handle.efds[0];
1392 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1395 } else if (type == IFPGA_AFU_IRQ) {
1396 acc = opae_adapter_get_acc(adapter, port_id);
1400 ret = opae_acc_set_irq(acc, vec_start, count, intr_handle.efds);
1405 /* register interrupt handler using DPDK API */
1406 ret = rte_intr_callback_register(&intr_handle,
1407 handler, (void *)arg);
1411 IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
1417 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1421 struct rte_rawdev *rawdev = NULL;
1422 struct ifpga_rawdev *dev = NULL;
1423 struct opae_adapter *adapter = NULL;
1424 struct opae_manager *mgr = NULL;
1425 struct opae_adapter_data_pci *data = NULL;
1426 char name[RTE_RAWDEV_NAME_MAX_LEN];
1430 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1435 memset(name, 0, sizeof(name));
1436 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%02x:%02x.%x",
1437 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1439 IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1441 /* Allocate device structure */
1442 rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1444 if (rawdev == NULL) {
1445 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1450 ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1451 ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1453 dev = ifpga_rawdev_allocate(rawdev);
1455 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1459 dev->aer_enable = 0;
1461 /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1462 data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1468 /* init opae_adapter_data_pci for device specific information */
1469 for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1470 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1471 data->region[i].len = pci_dev->mem_resource[i].len;
1472 data->region[i].addr = pci_dev->mem_resource[i].addr;
1474 data->device_id = pci_dev->id.device_id;
1475 data->vendor_id = pci_dev->id.vendor_id;
1476 data->bus = pci_dev->addr.bus;
1477 data->devid = pci_dev->addr.devid;
1478 data->function = pci_dev->addr.function;
1479 data->vfio_dev_fd = pci_dev->intr_handle.vfio_dev_fd;
1481 adapter = rawdev->dev_private;
1482 /* create a opae_adapter based on above device data */
1483 ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1486 goto free_adapter_data;
1489 rawdev->dev_ops = &ifpga_rawdev_ops;
1490 rawdev->device = &pci_dev->device;
1491 rawdev->driver_name = pci_dev->driver->driver.name;
1493 /* must enumerate the adapter before use it */
1494 ret = opae_adapter_enumerate(adapter);
1496 goto free_adapter_data;
1498 /* get opae_manager to rawdev */
1499 mgr = opae_adapter_get_mgr(adapter);
1502 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1505 ret = ifpga_register_msix_irq(rawdev, 0, IFPGA_FME_IRQ, 0, 0,
1506 fme_interrupt_handler, "fme_irq", mgr);
1508 goto free_adapter_data;
1514 opae_adapter_data_free(data);
1517 rte_rawdev_pmd_release(rawdev);
1523 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1526 struct rte_rawdev *rawdev;
1527 char name[RTE_RAWDEV_NAME_MAX_LEN];
1528 struct opae_adapter *adapter;
1529 struct opae_manager *mgr;
1532 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1537 memset(name, 0, sizeof(name));
1538 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%x:%02x.%x",
1539 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1541 IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1542 name, rte_socket_id());
1544 rawdev = rte_rawdev_pmd_get_named_dev(name);
1546 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1550 adapter = ifpga_rawdev_get_priv(rawdev);
1554 mgr = opae_adapter_get_mgr(adapter);
1558 if (ifpga_unregister_msix_irq(IFPGA_FME_IRQ, 0,
1559 fme_interrupt_handler, mgr))
1562 opae_adapter_data_free(adapter->data);
1563 opae_adapter_free(adapter);
1565 /* rte_rawdev_close is called by pmd_release */
1566 ret = rte_rawdev_pmd_release(rawdev);
1568 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1574 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1575 struct rte_pci_device *pci_dev)
1577 IFPGA_RAWDEV_PMD_FUNC_TRACE();
1578 return ifpga_rawdev_create(pci_dev, rte_socket_id());
1582 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1584 ifpga_monitor_stop_func();
1585 return ifpga_rawdev_destroy(pci_dev);
1588 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1589 .id_table = pci_ifpga_map,
1590 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1591 .probe = ifpga_rawdev_pci_probe,
1592 .remove = ifpga_rawdev_pci_remove,
1595 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1596 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1597 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1598 RTE_LOG_REGISTER(ifpga_rawdev_logtype, driver.raw.init, NOTICE);
1600 static const char * const valid_args[] = {
1601 #define IFPGA_ARG_NAME "ifpga"
1603 #define IFPGA_ARG_PORT "port"
1605 #define IFPGA_AFU_BTS "afu_bts"
1610 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1611 const char *value, void *extra_args)
1614 if (!value || !extra_args)
1617 size = strlen(value) + 1;
1618 *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1619 if (!*(char **)extra_args)
1622 strlcpy(*(char **)extra_args, value, size);
1627 ifpga_cfg_probe(struct rte_vdev_device *dev)
1629 struct rte_devargs *devargs;
1630 struct rte_kvargs *kvlist = NULL;
1631 struct rte_rawdev *rawdev = NULL;
1632 struct ifpga_rawdev *ifpga_dev;
1636 char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1639 devargs = dev->device.devargs;
1641 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1643 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1647 if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1648 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1649 &ifpga_rawdev_get_string_arg,
1651 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1656 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1661 if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1662 if (rte_kvargs_process(kvlist,
1664 &rte_ifpga_get_integer32_arg,
1666 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1671 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1676 memset(dev_name, 0, sizeof(dev_name));
1677 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1678 rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1681 ifpga_dev = ifpga_rawdev_get(rawdev);
1685 ifpga_rawdev_fill_info(ifpga_dev, bdf);
1687 ifpga_monitor_start_func();
1689 memset(dev_name, 0, sizeof(dev_name));
1690 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1693 ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1694 dev_name, devargs->args);
1697 rte_kvargs_free(kvlist);
1705 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1707 IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1713 static struct rte_vdev_driver ifpga_cfg_driver = {
1714 .probe = ifpga_cfg_probe,
1715 .remove = ifpga_cfg_remove,
1718 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1719 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1720 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,