drivers/raw/ifpga_rawdev/base/ifpga_defines.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #ifndef _IFPGA_DEFINES_H_
   6 #define _IFPGA_DEFINES_H_
   7
   8 #include "ifpga_compat.h"
   9
  10 #define MAX_FPGA_PORT_NUM  4
  11
  12 #define FME_FEATURE_HEADER          "fme_hdr"
  13 #define FME_FEATURE_THERMAL_MGMT    "fme_thermal"
  14 #define FME_FEATURE_POWER_MGMT      "fme_power"
  15 #define FME_FEATURE_GLOBAL_IPERF    "fme_iperf"
  16 #define FME_FEATURE_GLOBAL_ERR      "fme_error"
  17 #define FME_FEATURE_PR_MGMT         "fme_pr"
  18 #define FME_FEATURE_EMIF_MGMT       "fme_emif"
  19 #define FME_FEATURE_HSSI_ETH        "fme_hssi"
  20 #define FME_FEATURE_GLOBAL_DPERF    "fme_dperf"
  21 #define FME_FEATURE_QSPI_FLASH      "fme_qspi_flash"
  22 #define FME_FEATURE_MAX10_SPI       "fme_max10_spi"
  23 #define FME_FEATURE_NIOS_SPI        "fme_nios_spi"
  24 #define FME_FEATURE_I2C_MASTER      "fme_i2c_master"
  25 #define FME_FEATURE_ETH_GROUP       "fme_eth_group"
  26
  27 #define PORT_FEATURE_HEADER         "port_hdr"
  28 #define PORT_FEATURE_UAFU           "port_uafu"
  29 #define PORT_FEATURE_ERR            "port_err"
  30 #define PORT_FEATURE_UMSG           "port_umsg"
  31 #define PORT_FEATURE_PR             "port_pr"
  32 #define PORT_FEATURE_UINT           "port_uint"
  33 #define PORT_FEATURE_STP            "port_stp"
  34
  35 /*
  36  * do not check the revision id as id may be dynamic under
  37  * some cases, e.g, UAFU.
  38  */
  39 #define SKIP_REVISION_CHECK             0xff
  40
  41 #define FME_HEADER_REVISION             1
  42 #define FME_THERMAL_MGMT_REVISION       0
  43 #define FME_POWER_MGMT_REVISION         1
  44 #define FME_GLOBAL_IPERF_REVISION       1
  45 #define FME_GLOBAL_ERR_REVISION         1
  46 #define FME_PR_MGMT_REVISION            2
  47 #define FME_HSSI_ETH_REVISION           0
  48 #define FME_GLOBAL_DPERF_REVISION       0
  49 #define FME_QSPI_REVISION               0
  50 #define FME_MAX10_SPI                   0
  51 #define FME_I2C_MASTER                  0
  52
  53 #define PORT_HEADER_REVISION            0
  54 /* UAFU's header info depends on the downloaded GBS */
  55 #define PORT_UAFU_REVISION              SKIP_REVISION_CHECK
  56 #define PORT_ERR_REVISION               1
  57 #define PORT_UMSG_REVISION              0
  58 #define PORT_UINT_REVISION              0
  59 #define PORT_STP_REVISION               1
  60
  61 #define FEATURE_TYPE_AFU        0x1
  62 #define FEATURE_TYPE_BBB        0x2
  63 #define FEATURE_TYPE_PRIVATE    0x3
  64 #define FEATURE_TYPE_FIU        0x4
  65
  66 #define FEATURE_FIU_ID_FME      0x0
  67 #define FEATURE_FIU_ID_PORT     0x1
  68
  69 /* Reserved 0xfe for Header, 0xff for AFU*/
  70 #define FEATURE_ID_FIU_HEADER   0xfe
  71 #define FEATURE_ID_AFU          0xff
  72
  73 enum fpga_id_type {
  74         FME_ID,
  75         PORT_ID,
  76         FPGA_ID_MAX,
  77 };
  78
  79 #define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
  80 #define FME_FEATURE_ID_THERMAL_MGMT 0x1
  81 #define FME_FEATURE_ID_POWER_MGMT 0x2
  82 #define FME_FEATURE_ID_GLOBAL_IPERF 0x3
  83 #define FME_FEATURE_ID_GLOBAL_ERR 0x4
  84 #define FME_FEATURE_ID_PR_MGMT 0x5
  85 #define FME_FEATURE_ID_HSSI_ETH 0x6
  86 #define FME_FEATURE_ID_GLOBAL_DPERF 0x7
  87 #define FME_FEATURE_ID_QSPI_FLASH 0x8
  88 #define FME_FEATURE_ID_EMIF_MGMT  0x9
  89 #define FME_FEATURE_ID_MAX10_SPI  0xe
  90 #define FME_FEATURE_ID_NIOS_SPI 0xd
  91 #define FME_FEATURE_ID_I2C_MASTER  0xf
  92 #define FME_FEATURE_ID_ETH_GROUP 0x10
  93
  94 #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
  95 #define PORT_FEATURE_ID_ERROR 0x10
  96 #define PORT_FEATURE_ID_UMSG 0x12
  97 #define PORT_FEATURE_ID_UINT 0x13
  98 #define PORT_FEATURE_ID_STP 0x14
  99 #define PORT_FEATURE_ID_UAFU FEATURE_ID_AFU
 100
 101 /*
 102  * All headers and structures must be byte-packed to match the spec.
 103  */
 104 #pragma pack(push, 1)
 105
 106 struct feature_header {
 107         union {
 108                 u64 csr;
 109                 struct {
 110                         u16 id:12;
 111                         u8  revision:4;
 112                         u32 next_header_offset:24;
 113                         u8  end_of_list:1;
 114                         u32 reserved:19;
 115                         u8  type:4;
 116                 };
 117         };
 118 };
 119
 120 struct feature_bbb_header {
 121         struct uuid guid;
 122 };
 123
 124 struct feature_afu_header {
 125         struct uuid guid;
 126         union {
 127                 u64 csr;
 128                 struct {
 129                         u64 next_afu:24;
 130                         u64 reserved:40;
 131                 };
 132         };
 133 };
 134
 135 struct feature_fiu_header {
 136         struct uuid guid;
 137         union {
 138                 u64 csr;
 139                 struct {
 140                         u64 next_afu:24;
 141                         u64 reserved:40;
 142                 };
 143         };
 144 };
 145
 146 struct feature_fme_capability {
 147         union {
 148                 u64 csr;
 149                 struct {
 150                         u8  fabric_verid;       /* Fabric version ID */
 151                         u8  socket_id:1;        /* Socket id */
 152                         u8  rsvd1:3;            /* Reserved */
 153                         /* pci0 link available yes /no */
 154                         u8  pci0_link_avile:1;
 155                         /* pci1 link available yes /no */
 156                         u8  pci1_link_avile:1;
 157                         /* Coherent (QPI/UPI) link available yes /no */
 158                         u8  qpi_link_avile:1;
 159                         u8  rsvd2:1;            /* Reserved */
 160                         /* IOMMU or VT-d supported  yes/no */
 161                         u8  iommu_support:1;
 162                         u8  num_ports:3;        /* Number of ports */
 163                         u8  sf_fab_ctl:1;       /* Internal validation bit */
 164                         u8  rsvd3:3;            /* Reserved */
 165                         /*
 166                          * Address width supported in bits
 167                          * BXT -0x26 , SKX -0x30
 168                          */
 169                         u8  address_width_bits:6;
 170                         u8  rsvd4:2;            /* Reserved */
 171                         /* Size of cache supported in kb */
 172                         u16 cache_size:12;
 173                         u8  cache_assoc:4;      /* Cache Associativity */
 174                         u16 rsvd5:15;           /* Reserved */
 175                         u8  lock_bit:1;         /* Lock bit */
 176                 };
 177         };
 178 };
 179
 180 #define FME_AFU_ACCESS_PF               0
 181 #define FME_AFU_ACCESS_VF               1
 182
 183 struct feature_fme_port {
 184         union {
 185                 u64 csr;
 186                 struct {
 187                         u32 port_offset:24;
 188                         u8  reserved1;
 189                         u8  port_bar:3;
 190                         u32 reserved2:20;
 191                         u8  afu_access_control:1;
 192                         u8  reserved3:4;
 193                         u8  port_implemented:1;
 194                         u8  reserved4:3;
 195                 };
 196         };
 197 };
 198
 199 struct feature_fme_fab_status {
 200         union {
 201                 u64 csr;
 202                 struct {
 203                         u8  upilink_status:4;   /* UPI Link Status */
 204                         u8  rsvd1:4;            /* Reserved */
 205                         u8  pci0link_status:1;  /* pci0 link status */
 206                         u8  rsvd2:3;            /* Reserved */
 207                         u8  pci1link_status:1;  /* pci1 link status */
 208                         u64 rsvd3:51;           /* Reserved */
 209                 };
 210         };
 211 };
 212
 213 struct feature_fme_genprotrange2_base {
 214         union {
 215                 u64 csr;
 216                 struct {
 217                         u16 rsvd1;           /* Reserved */
 218                         /* Base Address of memory range */
 219                         u8  protected_base_addrss:4;
 220                         u64 rsvd2:44;           /* Reserved */
 221                 };
 222         };
 223 };
 224
 225 struct feature_fme_genprotrange2_limit {
 226         union {
 227                 u64 csr;
 228                 struct {
 229                         u16 rsvd1;           /* Reserved */
 230                         /* Limit Address of memory range */
 231                         u8  protected_limit_addrss:4;
 232                         u16 rsvd2:11;           /* Reserved */
 233                         u8  enable:1;        /* Enable GENPROTRANGE check */
 234                         u32 rsvd3;           /* Reserved */
 235                 };
 236         };
 237 };
 238
 239 struct feature_fme_dxe_lock {
 240         union {
 241                 u64 csr;
 242                 struct {
 243                         /*
 244                          * Determines write access to the DXE region CSRs
 245                          * 1 - CSR region is locked;
 246                          * 0 - it is open for write access.
 247                          */
 248                         u8  dxe_early_lock:1;
 249                         /*
 250                          * Determines write access to the HSSI CSR
 251                          * 1 - CSR region is locked;
 252                          * 0 - it is open for write access.
 253                          */
 254                         u8  dxe_late_lock:1;
 255                         u64 rsvd:62;
 256                 };
 257         };
 258 };
 259
 260 #define HSSI_ID_NO_HASSI        0
 261 #define HSSI_ID_PCIE_RP         1
 262 #define HSSI_ID_ETHERNET        2
 263
 264 struct feature_fme_bitstream_id {
 265         union {
 266                 u64 csr;
 267                 struct {
 268                         u32 gitrepo_hash:32;    /* GIT repository hash */
 269                         /*
 270                          * HSSI configuration identifier:
 271                          * 0 - No HSSI
 272                          * 1 - PCIe-RP
 273                          * 2 - Ethernet
 274                          */
 275                         u8  hssi_id:4;
 276                         u16 rsvd1:12;           /* Reserved */
 277                         /* Bitstream version patch number */
 278                         u8  bs_verpatch:4;
 279                         /* Bitstream version minor number */
 280                         u8  bs_verminor:4;
 281                         /* Bitstream version major number */
 282                         u8  bs_vermajor:4;
 283                         /* Bitstream version debug number */
 284                         u8  bs_verdebug:4;
 285                 };
 286         };
 287 };
 288
 289 struct feature_fme_bitstream_md {
 290         union {
 291                 u64 csr;
 292                 struct {
 293                         /* Seed number userd for synthesis flow */
 294                         u8  synth_seed:4;
 295                         /* Synthesis date(day number - 2 digits) */
 296                         u8  synth_day:8;
 297                         /* Synthesis date(month number - 2 digits) */
 298                         u8  synth_month:8;
 299                         /* Synthesis date(year number - 2 digits) */
 300                         u8  synth_year:8;
 301                         u64 rsvd:36;            /* Reserved */
 302                 };
 303         };
 304 };
 305
 306 struct feature_fme_iommu_ctrl {
 307         union {
 308                 u64 csr;
 309                 struct {
 310                         /* Disables IOMMU prefetcher for C0 channel */
 311                         u8 prefetch_disableC0:1;
 312                         /* Disables IOMMU prefetcher for C1 channel */
 313                         u8 prefetch_disableC1:1;
 314                         /* Disables IOMMU partial cache line writes */
 315                         u8 prefetch_wrdisable:1;
 316                         u8 rsvd1:1;             /* Reserved */
 317                         /*
 318                          * Select counter and read value from register
 319                          * iommu_stat.dbg_counters
 320                          * 0 - Number of 4K page translation response
 321                          * 1 - Number of 2M page translation response
 322                          * 2 - Number of 1G page translation response
 323                          */
 324                         u8 counter_sel:2;
 325                         u32 rsvd2:26;           /* Reserved */
 326                         /* Connected to IOMMU SIP Capabilities */
 327                         u32 capecap_defeature;
 328                 };
 329         };
 330 };
 331
 332 struct feature_fme_iommu_stat {
 333         union {
 334                 u64 csr;
 335                 struct {
 336                         /* Translation Enable bit from IOMMU SIP */
 337                         u8 translation_enable:1;
 338                         /* Drain request in progress */
 339                         u8 drain_req_inprog:1;
 340                         /* Invalidation current state */
 341                         u8 inv_state:3;
 342                         /* C0 Response Buffer current state */
 343                         u8 respbuffer_stateC0:3;
 344                         /* C1 Response Buffer current state */
 345                         u8 respbuffer_stateC1:3;
 346                         /* Last request ID to IOMMU SIP */
 347                         u8 last_reqID:4;
 348                         /* Last IOMMU SIP response ID value */
 349                         u8 last_respID:4;
 350                         /* Last IOMMU SIP response status value */
 351                         u8 last_respstatus:3;
 352                         /* C0 Transaction Buffer is not empty */
 353                         u8 transbuf_notEmptyC0:1;
 354                         /* C1 Transaction Buffer is not empty */
 355                         u8 transbuf_notEmptyC1:1;
 356                         /* C0 Request FIFO is not empty */
 357                         u8 reqFIFO_notemptyC0:1;
 358                         /* C1 Request FIFO is not empty */
 359                         u8 reqFIFO_notemptyC1:1;
 360                         /* C0 Response FIFO is not empty */
 361                         u8 respFIFO_notemptyC0:1;
 362                         /* C1 Response FIFO is not empty */
 363                         u8 respFIFO_notemptyC1:1;
 364                         /* C0 Response FIFO overflow detected */
 365                         u8 respFIFO_overflowC0:1;
 366                         /* C1 Response FIFO overflow detected */
 367                         u8 respFIFO_overflowC1:1;
 368                         /* C0 Transaction Buffer overflow detected */
 369                         u8 tranbuf_overflowC0:1;
 370                         /* C1 Transaction Buffer overflow detected */
 371                         u8 tranbuf_overflowC1:1;
 372                         /* Request FIFO overflow detected */
 373                         u8 reqFIFO_overflow:1;
 374                         /* IOMMU memory read in progress */
 375                         u8 memrd_inprog:1;
 376                         /* IOMMU memory write in progress */
 377                         u8 memwr_inprog:1;
 378                         u8 rsvd1:1;     /* Reserved */
 379                         /* Value of counter selected by iommu_ctl.counter_sel */
 380                         u16 dbg_counters:16;
 381                         u16 rsvd2:12;   /* Reserved */
 382                 };
 383         };
 384 };
 385
 386 struct feature_fme_pcie0_ctrl {
 387         union {
 388                 u64 csr;
 389                 struct {
 390                         u64 vtd_bar_lock:1;     /* Lock VT-D BAR register */
 391                         u64 rsvd1:3;
 392                         u64 rciep:1;            /* Configure PCIE0 as RCiEP */
 393                         u64 rsvd2:59;
 394                 };
 395         };
 396 };
 397
 398 struct feature_fme_llpr_smrr_base {
 399         union {
 400                 u64 csr;
 401                 struct {
 402                         u64 rsvd1:12;
 403                         u64 base:20;    /* SMRR2 memory range base address */
 404                         u64 rsvd2:32;
 405                 };
 406         };
 407 };
 408
 409 struct feature_fme_llpr_smrr_mask {
 410         union {
 411                 u64 csr;
 412                 struct {
 413                         u64 rsvd1:11;
 414                         u64 valid:1;    /* LLPR_SMRR rule is valid or not */
 415                         /*
 416                          * SMRR memory range mask which determines the range
 417                          * of region being mapped
 418                          */
 419                         u64 phys_mask:20;
 420                         u64 rsvd2:32;
 421                 };
 422         };
 423 };
 424
 425 struct feature_fme_llpr_smrr2_base {
 426         union {
 427                 u64 csr;
 428                 struct {
 429                         u64 rsvd1:12;
 430                         u64 base:20;    /* SMRR2 memory range base address */
 431                         u64 rsvd2:32;
 432                 };
 433         };
 434 };
 435
 436 struct feature_fme_llpr_smrr2_mask {
 437         union {
 438                 u64 csr;
 439                 struct {
 440                         u64 rsvd1:11;
 441                         u64 valid:1;    /* LLPR_SMRR2 rule is valid or not */
 442                         /*
 443                          * SMRR2 memory range mask which determines the range
 444                          * of region being mapped
 445                          */
 446                         u64 phys_mask:20;
 447                         u64 rsvd2:32;
 448                 };
 449         };
 450 };
 451
 452 struct feature_fme_llpr_meseg_base {
 453         union {
 454                 u64 csr;
 455                 struct {
 456                         /* A[45:19] of base address memory range */
 457                         u64 me_base:27;
 458                         u64 rsvd:37;
 459                 };
 460         };
 461 };
 462
 463 struct feature_fme_llpr_meseg_limit {
 464         union {
 465                 u64 csr;
 466                 struct {
 467                         /* A[45:19] of limit address memory range */
 468                         u64 me_limit:27;
 469                         u64 rsvd1:4;
 470                         u64 enable:1;   /* Enable LLPR MESEG rule */
 471                         u64 rsvd2:32;
 472                 };
 473         };
 474 };
 475
 476 struct feature_fme_header {
 477         struct feature_header header;
 478         struct feature_afu_header afu_header;
 479         u64 reserved;
 480         u64 scratchpad;
 481         struct feature_fme_capability capability;
 482         struct feature_fme_port port[MAX_FPGA_PORT_NUM];
 483         struct feature_fme_fab_status fab_status;
 484         struct feature_fme_bitstream_id bitstream_id;
 485         struct feature_fme_bitstream_md bitstream_md;
 486         struct feature_fme_genprotrange2_base genprotrange2_base;
 487         struct feature_fme_genprotrange2_limit genprotrange2_limit;
 488         struct feature_fme_dxe_lock dxe_lock;
 489         struct feature_fme_iommu_ctrl iommu_ctrl;
 490         struct feature_fme_iommu_stat iommu_stat;
 491         struct feature_fme_pcie0_ctrl pcie0_control;
 492         struct feature_fme_llpr_smrr_base smrr_base;
 493         struct feature_fme_llpr_smrr_mask smrr_mask;
 494         struct feature_fme_llpr_smrr2_base smrr2_base;
 495         struct feature_fme_llpr_smrr2_mask smrr2_mask;
 496         struct feature_fme_llpr_meseg_base meseg_base;
 497         struct feature_fme_llpr_meseg_limit meseg_limit;
 498 };
 499
 500 struct feature_port_capability {
 501         union {
 502                 u64 csr;
 503                 struct {
 504                         u8 port_number:2;       /* Port Number 0-3 */
 505                         u8 rsvd1:6;             /* Reserved */
 506                         u16 mmio_size;          /* User MMIO size in KB */
 507                         u8 rsvd2;               /* Reserved */
 508                         u8 sp_intr_num:4;       /* Supported interrupts num */
 509                         u32 rsvd3:28;           /* Reserved */
 510                 };
 511         };
 512 };
 513
 514 struct feature_port_control {
 515         union {
 516                 u64 csr;
 517                 struct {
 518                         u8 port_sftrst:1;       /* Port Soft Reset */
 519                         u8 rsvd1:1;             /* Reserved */
 520                         u8 latency_tolerance:1;/* '1' >= 40us, '0' < 40us */
 521                         u8 rsvd2:1;             /* Reserved */
 522                         u8 port_sftrst_ack:1;   /* HW ACK for Soft Reset */
 523                         u64 rsvd3:59;           /* Reserved */
 524                 };
 525         };
 526 };
 527
 528 #define PORT_POWER_STATE_NORMAL         0
 529 #define PORT_POWER_STATE_AP1            1
 530 #define PORT_POWER_STATE_AP2            2
 531 #define PORT_POWER_STATE_AP6            6
 532
 533 struct feature_port_status {
 534         union {
 535                 u64 csr;
 536                 struct {
 537                         u8 port_freeze:1;       /* '1' - freezed '0' - normal */
 538                         u8 rsvd1:7;             /* Reserved */
 539                         u8 power_state:4;       /* Power State */
 540                         u8 ap1_event:1;         /* AP1 event was detected  */
 541                         u8 ap2_event:1;         /* AP2 event was detected  */
 542                         u64 rsvd2:50;           /* Reserved */
 543                 };
 544         };
 545 };
 546
 547 /* Port Header Register Set */
 548 struct feature_port_header {
 549         struct feature_header header;
 550         struct feature_afu_header afu_header;
 551         u64 port_mailbox;
 552         u64 scratchpad;
 553         struct feature_port_capability capability;
 554         struct feature_port_control control;
 555         struct feature_port_status status;
 556         u64 rsvd2;
 557         u64 user_clk_freq_cmd0;
 558         u64 user_clk_freq_cmd1;
 559         u64 user_clk_freq_sts0;
 560         u64 user_clk_freq_sts1;
 561 };
 562
 563 struct feature_fme_tmp_threshold {
 564         union {
 565                 u64 csr;
 566                 struct {
 567                         u8  tmp_thshold1:7;       /* temperature Threshold 1 */
 568                         /* temperature Threshold 1 enable/disable */
 569                         u8  tmp_thshold1_enable:1;
 570                         u8  tmp_thshold2:7;       /* temperature Threshold 2 */
 571                         /* temperature Threshold 2 enable /disable */
 572                         u8  tmp_thshold2_enable:1;
 573                         u8  pro_hot_setpoint:7;   /* Proc Hot set point */
 574                         u8  rsvd4:1;              /* Reserved */
 575                         u8  therm_trip_thshold:7; /* Thermeal Trip Threshold */
 576                         u8  rsvd3:1;              /* Reserved */
 577                         u8  thshold1_status:1;    /* Threshold 1 Status */
 578                         u8  thshold2_status:1;    /* Threshold 2 Status */
 579                         u8  rsvd5:1;              /* Reserved */
 580                         /* Thermeal Trip Threshold status */
 581                         u8  therm_trip_thshold_status:1;
 582                         u8  rsvd6:4;              /* Reserved */
 583                         /* Validation mode- Force Proc Hot */
 584                         u8  valmodeforce:1;
 585                         /* Validation mode - Therm trip Hot */
 586                         u8  valmodetherm:1;
 587                         u8  rsvd2:2;              /* Reserved */
 588                         u8  thshold_policy:1;     /* threshold policy */
 589                         u32 rsvd:19;              /* Reserved */
 590                 };
 591         };
 592 };
 593
 594 /* Temperature Sensor Read values format 1 */
 595 struct feature_fme_temp_rdsensor_fmt1 {
 596         union {
 597                 u64 csr;
 598                 struct {
 599                         /* Reads out FPGA temperature in celsius */
 600                         u8  fpga_temp:7;
 601                         u8  rsvd0:1;                    /* Reserved */
 602                         /* Temperature reading sequence number */
 603                         u16 tmp_reading_seq_num;
 604                         /* Temperature reading is valid */
 605                         u8  tmp_reading_valid:1;
 606                         u8  rsvd1:7;                    /* Reserved */
 607                         u16 dbg_mode:10;                /* Debug mode */
 608                         u32 rsvd2:22;                   /* Reserved */
 609                 };
 610         };
 611 };
 612
 613 /* Temperature sensor read values format 2 */
 614 struct feature_fme_temp_rdsensor_fmt2 {
 615         u64 rsvd;       /* Reserved */
 616 };
 617
 618 /* Temperature Threshold Capability Register */
 619 struct feature_fme_tmp_threshold_cap {
 620         union {
 621                 u64 csr;
 622                 struct {
 623                         /* Temperature Threshold Unsupported */
 624                         u8  tmp_thshold_disabled:1;
 625                         u64 rsvd:63;                    /* Reserved */
 626                 };
 627         };
 628 };
 629
 630 /* FME THERNAL FEATURE */
 631 struct feature_fme_thermal {
 632         struct feature_header header;
 633         struct feature_fme_tmp_threshold threshold;
 634         struct feature_fme_temp_rdsensor_fmt1 rdsensor_fm1;
 635         struct feature_fme_temp_rdsensor_fmt2 rdsensor_fm2;
 636         struct feature_fme_tmp_threshold_cap threshold_cap;
 637 };
 638
 639 /* Power Status register */
 640 struct feature_fme_pm_status {
 641         union {
 642                 u64 csr;
 643                 struct {
 644                         /* FPGA Power consumed, The format is to be defined */
 645                         u32 pwr_consumed:18;
 646                         /* FPGA Latency Tolerance Reporting */
 647                         u8  fpga_latency_report:1;
 648                         u64 rsvd:45;                    /* Reserved */
 649                 };
 650         };
 651 };
 652
 653 /* AP Thresholds */
 654 struct feature_fme_pm_ap_threshold {
 655         union {
 656                 u64 csr;
 657                 struct {
 658                         /*
 659                          * Number of clocks (5ns period) for assertion
 660                          * of FME_data
 661                          */
 662                         u8  threshold1:7;
 663                         u8  rsvd1:1;
 664                         u8  threshold2:7;
 665                         u8  rsvd2:1;
 666                         u8  threshold1_status:1;
 667                         u8  threshold2_status:1;
 668                         u64 rsvd3:46;           /* Reserved */
 669                 };
 670         };
 671 };
 672
 673 /* Xeon Power Limit */
 674 struct feature_fme_pm_xeon_limit {
 675         union {
 676                 u64 csr;
 677                 struct {
 678                         /* Power limit in Watts in 12.3 format */
 679                         u16 pwr_limit:15;
 680                         /* Indicates that power limit has been written */
 681                         u8  enable:1;
 682                         /* 0 - Turbe range, 1 - Entire range */
 683                         u8  clamping:1;
 684                         /* Time constant in XXYYY format */
 685                         u8  time:7;
 686                         u64 rsvd:40;            /* Reserved */
 687                 };
 688         };
 689 };
 690
 691 /* FPGA Power Limit */
 692 struct feature_fme_pm_fpga_limit {
 693         union {
 694                 u64 csr;
 695                 struct {
 696                         /* Power limit in Watts in 12.3 format */
 697                         u16 pwr_limit:15;
 698                         /* Indicates that power limit has been written */
 699                         u8  enable:1;
 700                         /* 0 - Turbe range, 1 - Entire range */
 701                         u8  clamping:1;
 702                         /* Time constant in XXYYY format */
 703                         u8  time:7;
 704                         u64 rsvd:40;            /* Reserved */
 705                 };
 706         };
 707 };
 708
 709 /* FME POWER FEATURE */
 710 struct feature_fme_power {
 711         struct feature_header header;
 712         struct feature_fme_pm_status status;
 713         struct feature_fme_pm_ap_threshold threshold;
 714         struct feature_fme_pm_xeon_limit xeon_limit;
 715         struct feature_fme_pm_fpga_limit fpga_limit;
 716 };
 717
 718 #define CACHE_CHANNEL_RD        0
 719 #define CACHE_CHANNEL_WR        1
 720
 721 enum iperf_cache_events {
 722         IPERF_CACHE_RD_HIT,
 723         IPERF_CACHE_WR_HIT,
 724         IPERF_CACHE_RD_MISS,
 725         IPERF_CACHE_WR_MISS,
 726         IPERF_CACHE_RSVD, /* reserved */
 727         IPERF_CACHE_HOLD_REQ,
 728         IPERF_CACHE_DATA_WR_PORT_CONTEN,
 729         IPERF_CACHE_TAG_WR_PORT_CONTEN,
 730         IPERF_CACHE_TX_REQ_STALL,
 731         IPERF_CACHE_RX_REQ_STALL,
 732         IPERF_CACHE_EVICTIONS,
 733 };
 734
 735 /* FPMON Cache Control */
 736 struct feature_fme_ifpmon_ch_ctl {
 737         union {
 738                 u64 csr;
 739                 struct {
 740                         u8  reset_counters:1;   /* Reset Counters */
 741                         u8  rsvd1:7;            /* Reserved */
 742                         u8  freeze:1;           /* Freeze if set to 1 */
 743                         u8  rsvd2:7;            /* Reserved */
 744                         u8  cache_event:4;      /* Select the cache event */
 745                         u8  cci_chsel:1;        /* Select the channel */
 746                         u64 rsvd3:43;           /* Reserved */
 747                 };
 748         };
 749 };
 750
 751 /* FPMON Cache Counter */
 752 struct feature_fme_ifpmon_ch_ctr {
 753         union {
 754                 u64 csr;
 755                 struct {
 756                         /* Cache Counter for even addresse */
 757                         u64 cache_counter:48;
 758                         u16 rsvd:12;            /* Reserved */
 759                         /* Cache Event being reported */
 760                         u8  event_code:4;
 761                 };
 762         };
 763 };
 764
 765 enum iperf_fab_events {
 766         IPERF_FAB_PCIE0_RD,
 767         IPERF_FAB_PCIE0_WR,
 768         IPERF_FAB_PCIE1_RD,
 769         IPERF_FAB_PCIE1_WR,
 770         IPERF_FAB_UPI_RD,
 771         IPERF_FAB_UPI_WR,
 772         IPERF_FAB_MMIO_RD,
 773         IPERF_FAB_MMIO_WR,
 774 };
 775
 776 #define FAB_DISABLE_FILTER     0
 777 #define FAB_ENABLE_FILTER      1
 778
 779 /* FPMON FAB Control */
 780 struct feature_fme_ifpmon_fab_ctl {
 781         union {
 782                 u64 csr;
 783                 struct {
 784                         u8  reset_counters:1;   /* Reset Counters */
 785                         u8  rsvd:7;             /* Reserved */
 786                         u8  freeze:1;           /* Set to 1 frozen counter */
 787                         u8  rsvd1:7;            /* Reserved */
 788                         u8  fab_evtcode:4;      /* Fabric Event Code */
 789                         u8  port_id:2;          /* Port ID */
 790                         u8  rsvd2:1;            /* Reserved */
 791                         u8  port_filter:1;      /* Port Filter */
 792                         u64 rsvd3:40;           /* Reserved */
 793                 };
 794         };
 795 };
 796
 797 /* FPMON Event Counter */
 798 struct feature_fme_ifpmon_fab_ctr {
 799         union {
 800                 u64 csr;
 801                 struct {
 802                         u64 fab_cnt:60; /* Fabric event counter */
 803                         /* Fabric event code being reported */
 804                         u8  event_code:4;
 805                 };
 806         };
 807 };
 808
 809 /* FPMON Clock Counter */
 810 struct feature_fme_ifpmon_clk_ctr {
 811         u64 afu_interf_clock;           /* Clk_16UI (AFU clock) counter. */
 812 };
 813
 814 enum iperf_vtd_events {
 815         IPERF_VTD_AFU_MEM_RD_TRANS,
 816         IPERF_VTD_AFU_MEM_WR_TRANS,
 817         IPERF_VTD_AFU_DEVTLB_RD_HIT,
 818         IPERF_VTD_AFU_DEVTLB_WR_HIT,
 819         IPERF_VTD_DEVTLB_4K_FILL,
 820         IPERF_VTD_DEVTLB_2M_FILL,
 821         IPERF_VTD_DEVTLB_1G_FILL,
 822 };
 823
 824 /* VT-d control register */
 825 struct feature_fme_ifpmon_vtd_ctl {
 826         union {
 827                 u64 csr;
 828                 struct {
 829                         u8  reset_counters:1;   /* Reset Counters */
 830                         u8  rsvd:7;             /* Reserved */
 831                         u8  freeze:1;           /* Set to 1 frozen counter */
 832                         u8  rsvd1:7;            /* Reserved */
 833                         u8  vtd_evtcode:4;      /* VTd and TLB event code */
 834                         u64 rsvd2:44;           /* Reserved */
 835                 };
 836         };
 837 };
 838
 839 /* VT-d event counter */
 840 struct feature_fme_ifpmon_vtd_ctr {
 841         union {
 842                 u64 csr;
 843                 struct {
 844                         u64 vtd_counter:48;     /* VTd event counter */
 845                         u16 rsvd:12;            /* Reserved */
 846                         u8  event_code:4;       /* VTd event code */
 847                 };
 848         };
 849 };
 850
 851 enum iperf_vtd_sip_events {
 852         IPERF_VTD_SIP_IOTLB_4K_HIT,
 853         IPERF_VTD_SIP_IOTLB_2M_HIT,
 854         IPERF_VTD_SIP_IOTLB_1G_HIT,
 855         IPERF_VTD_SIP_SLPWC_L3_HIT,
 856         IPERF_VTD_SIP_SLPWC_L4_HIT,
 857         IPERF_VTD_SIP_RCC_HIT,
 858         IPERF_VTD_SIP_IOTLB_4K_MISS,
 859         IPERF_VTD_SIP_IOTLB_2M_MISS,
 860         IPERF_VTD_SIP_IOTLB_1G_MISS,
 861         IPERF_VTD_SIP_SLPWC_L3_MISS,
 862         IPERF_VTD_SIP_SLPWC_L4_MISS,
 863         IPERF_VTD_SIP_RCC_MISS,
 864 };
 865
 866 /* VT-d SIP control register */
 867 struct feature_fme_ifpmon_vtd_sip_ctl {
 868         union {
 869                 u64 csr;
 870                 struct {
 871                         u8  reset_counters:1;   /* Reset Counters */
 872                         u8  rsvd:7;             /* Reserved */
 873                         u8  freeze:1;           /* Set to 1 frozen counter */
 874                         u8  rsvd1:7;            /* Reserved */
 875                         u8  vtd_evtcode:4;      /* VTd and TLB event code */
 876                         u64 rsvd2:44;           /* Reserved */
 877                 };
 878         };
 879 };
 880
 881 /* VT-d SIP event counter */
 882 struct feature_fme_ifpmon_vtd_sip_ctr {
 883         union {
 884                 u64 csr;
 885                 struct {
 886                         u64 vtd_counter:48;     /* VTd event counter */
 887                         u16 rsvd:12;            /* Reserved */
 888                         u8 event_code:4;        /* VTd event code */
 889                 };
 890         };
 891 };
 892
 893 /* FME IPERF FEATURE */
 894 struct feature_fme_iperf {
 895         struct feature_header header;
 896         struct feature_fme_ifpmon_ch_ctl ch_ctl;
 897         struct feature_fme_ifpmon_ch_ctr ch_ctr0;
 898         struct feature_fme_ifpmon_ch_ctr ch_ctr1;
 899         struct feature_fme_ifpmon_fab_ctl fab_ctl;
 900         struct feature_fme_ifpmon_fab_ctr fab_ctr;
 901         struct feature_fme_ifpmon_clk_ctr clk;
 902         struct feature_fme_ifpmon_vtd_ctl vtd_ctl;
 903         struct feature_fme_ifpmon_vtd_ctr vtd_ctr;
 904         struct feature_fme_ifpmon_vtd_sip_ctl vtd_sip_ctl;
 905         struct feature_fme_ifpmon_vtd_sip_ctr vtd_sip_ctr;
 906 };
 907
 908 enum dperf_fab_events {
 909         DPERF_FAB_PCIE0_RD,
 910         DPERF_FAB_PCIE0_WR,
 911         DPERF_FAB_MMIO_RD = 6,
 912         DPERF_FAB_MMIO_WR,
 913 };
 914
 915 /* FPMON FAB Control */
 916 struct feature_fme_dfpmon_fab_ctl {
 917         union {
 918                 u64 csr;
 919                 struct {
 920                         u8  reset_counters:1;   /* Reset Counters */
 921                         u8  rsvd:7;             /* Reserved */
 922                         u8  freeze:1;           /* Set to 1 frozen counter */
 923                         u8  rsvd1:7;            /* Reserved */
 924                         u8  fab_evtcode:4;      /* Fabric Event Code */
 925                         u8  port_id:2;          /* Port ID */
 926                         u8  rsvd2:1;            /* Reserved */
 927                         u8  port_filter:1;      /* Port Filter */
 928                         u64 rsvd3:40;           /* Reserved */
 929                 };
 930         };
 931 };
 932
 933 /* FPMON Event Counter */
 934 struct feature_fme_dfpmon_fab_ctr {
 935         union {
 936                 u64 csr;
 937                 struct {
 938                         u64 fab_cnt:60; /* Fabric event counter */
 939                         /* Fabric event code being reported */
 940                         u8  event_code:4;
 941                 };
 942         };
 943 };
 944
 945 /* FPMON Clock Counter */
 946 struct feature_fme_dfpmon_clk_ctr {
 947         u64 afu_interf_clock;           /* Clk_16UI (AFU clock) counter. */
 948 };
 949
 950 /* FME DPERF FEATURE */
 951 struct feature_fme_dperf {
 952         struct feature_header header;
 953         u64 rsvd[3];
 954         struct feature_fme_dfpmon_fab_ctl fab_ctl;
 955         struct feature_fme_dfpmon_fab_ctr fab_ctr;
 956         struct feature_fme_dfpmon_clk_ctr clk;
 957 };
 958
 959 struct feature_fme_error0 {
 960 #define FME_ERROR0_MASK        0xFFUL
 961 #define FME_ERROR0_MASK_DEFAULT 0x40UL  /* pcode workaround */
 962         union {
 963                 u64 csr;
 964                 struct {
 965                         u8  fabric_err:1;       /* Fabric error */
 966                         u8  fabfifo_overflow:1; /* Fabric fifo overflow */
 967                         u8  kticdc_parity_err:2;/* KTI CDC Parity Error */
 968                         u8  iommu_parity_err:1; /* IOMMU Parity error */
 969                         /* AFU PF/VF access mismatch detected */
 970                         u8  afu_acc_mode_err:1;
 971                         u8  mbp_err:1;          /* Indicates an MBP event */
 972                         /* PCIE0 CDC Parity Error */
 973                         u8  pcie0cdc_parity_err:5;
 974                         /* PCIE1 CDC Parity Error */
 975                         u8  pcie1cdc_parity_err:5;
 976                         /* CVL CDC Parity Error */
 977                         u8  cvlcdc_parity_err:3;
 978                         u64 rsvd:44;            /* Reserved */
 979                 };
 980         };
 981 };
 982
 983 /* PCIe0 Error Status register */
 984 struct feature_fme_pcie0_error {
 985 #define FME_PCIE0_ERROR_MASK   0xFFUL
 986         union {
 987                 u64 csr;
 988                 struct {
 989                         u8  formattype_err:1;   /* TLP format/type error */
 990                         u8  MWAddr_err:1;       /* TLP MW address error */
 991                         u8  MWAddrLength_err:1; /* TLP MW length error */
 992                         u8  MRAddr_err:1;       /* TLP MR address error */
 993                         u8  MRAddrLength_err:1; /* TLP MR length error */
 994                         u8  cpl_tag_err:1;      /* TLP CPL tag error */
 995                         u8  cpl_status_err:1;   /* TLP CPL status error */
 996                         u8  cpl_timeout_err:1;  /* TLP CPL timeout */
 997                         u8  cci_parity_err:1;   /* CCI bridge parity error */
 998                         u8  rxpoison_tlp_err:1; /* Received a TLP with EP set */
 999                         u64 rsvd:52;            /* Reserved */
1000                         u8  vfnumb_err:1;       /* Number of error VF */
1001                         u8  funct_type_err:1;   /* Virtual (1) or Physical */
1002                 };
1003         };
1004 };
1005
1006 /* PCIe1 Error Status register */
1007 struct feature_fme_pcie1_error {
1008 #define FME_PCIE1_ERROR_MASK   0xFFUL
1009         union {
1010                 u64 csr;
1011                 struct {
1012                         u8  formattype_err:1;   /* TLP format/type error */
1013                         u8  MWAddr_err:1;       /* TLP MW address error */
1014                         u8  MWAddrLength_err:1; /* TLP MW length error */
1015                         u8  MRAddr_err:1;       /* TLP MR address error */
1016                         u8  MRAddrLength_err:1; /* TLP MR length error */
1017                         u8  cpl_tag_err:1;      /* TLP CPL tag error */
1018                         u8  cpl_status_err:1;   /* TLP CPL status error */
1019                         u8  cpl_timeout_err:1;  /* TLP CPL timeout */
1020                         u8  cci_parity_err:1;   /* CCI bridge parity error */
1021                         u8  rxpoison_tlp_err:1; /* Received a TLP with EP set */
1022                         u64 rsvd:54;            /* Reserved */
1023                 };
1024         };
1025 };
1026
1027 /* FME First Error register */
1028 struct feature_fme_first_error {
1029 #define FME_FIRST_ERROR_MASK   ((1ULL << 60) - 1)
1030         union {
1031                 u64 csr;
1032                 struct {
1033                         /*
1034                          * Indicates the Error Register that was
1035                          * triggered first
1036                          */
1037                         u64 err_reg_status:60;
1038                         /*
1039                          * Holds 60 LSBs from the Error register that was
1040                          * triggered first
1041                          */
1042                         u8 errReg_id:4;
1043                 };
1044         };
1045 };
1046
1047 /* FME Next Error register */
1048 struct feature_fme_next_error {
1049 #define FME_NEXT_ERROR_MASK    ((1ULL << 60) - 1)
1050         union {
1051                 u64 csr;
1052                 struct {
1053                         /*
1054                          * Indicates the Error Register that was
1055                          * triggered second
1056                          */
1057                         u64 err_reg_status:60;
1058                         /*
1059                          * Holds 60 LSBs from the Error register that was
1060                          * triggered second
1061                          */
1062                         u8  errReg_id:4;
1063                 };
1064         };
1065 };
1066
1067 /* RAS Non Fatal Error Status register */
1068 struct feature_fme_ras_nonfaterror {
1069         union {
1070                 u64 csr;
1071                 struct {
1072                         /* thremal threshold AP1 */
1073                         u8  temp_thresh_ap1:1;
1074                         /* thremal threshold AP2 */
1075                         u8  temp_thresh_ap2:1;
1076                         u8  pcie_error:1;       /* pcie Error */
1077                         u8  portfatal_error:1;  /* port fatal error */
1078                         u8  proc_hot:1;         /* Indicates a ProcHot event */
1079                         /* Indicates an AFU PF/VF access mismatch */
1080                         u8  afu_acc_mode_err:1;
1081                         /* Injected nonfata Error */
1082                         u8  injected_nonfata_err:1;
1083                         u8  rsvd1:2;
1084                         /* Temperature threshold triggered AP6*/
1085                         u8  temp_thresh_AP6:1;
1086                         /* Power threshold triggered AP1 */
1087                         u8  power_thresh_AP1:1;
1088                         /* Power threshold triggered AP2 */
1089                         u8  power_thresh_AP2:1;
1090                         /* Indicates a MBP event */
1091                         u8  mbp_err:1;
1092                         u64 rsvd2:51;           /* Reserved */
1093                 };
1094         };
1095 };
1096
1097 /* RAS Catastrophic Fatal Error Status register */
1098 struct feature_fme_ras_catfaterror {
1099         union {
1100                 u64 csr;
1101                 struct {
1102                         /* KTI Link layer error detected */
1103                         u8  ktilink_fatal_err:1;
1104                         /* tag-n-cache error detected */
1105                         u8  tagcch_fatal_err:1;
1106                         /* CCI error detected */
1107                         u8  cci_fatal_err:1;
1108                         /* KTI Protocol error detected */
1109                         u8  ktiprpto_fatal_err:1;
1110                         /* Fatal DRAM error detected */
1111                         u8  dram_fatal_err:1;
1112                         /* IOMMU detected */
1113                         u8  iommu_fatal_err:1;
1114                         /* Fabric Fatal Error */
1115                         u8  fabric_fatal_err:1;
1116                         /* PCIe possion Error */
1117                         u8  pcie_poison_err:1;
1118                         /* Injected fatal Error */
1119                         u8  inject_fata_err:1;
1120                         /* Catastrophic CRC Error */
1121                         u8  crc_catast_err:1;
1122                         /* Catastrophic Thermal Error */
1123                         u8  therm_catast_err:1;
1124                         /* Injected Catastrophic Error */
1125                         u8  injected_catast_err:1;
1126                         u64 rsvd:52;
1127                 };
1128         };
1129 };
1130
1131 /* RAS Error injection register */
1132 struct feature_fme_ras_error_inj {
1133 #define FME_RAS_ERROR_INJ_MASK      0x7UL
1134         union {
1135                 u64 csr;
1136                 struct {
1137                         u8  catast_error:1;     /* Catastrophic error flag */
1138                         u8  fatal_error:1;      /* Fatal error flag */
1139                         u8  nonfatal_error:1;   /* NonFatal error flag */
1140                         u64 rsvd:61;            /* Reserved */
1141                 };
1142         };
1143 };
1144
1145 /* FME error capabilities */
1146 struct feature_fme_error_capability {
1147         union {
1148         u64 csr;
1149                 struct {
1150                         u8 support_intr:1;
1151                         /* MSI-X vector table entry number */
1152                         u16 intr_vector_num:12;
1153                         u64 rsvd:51;    /* Reserved */
1154                 };
1155         };
1156 };
1157
1158 /* FME ERR FEATURE */
1159 struct feature_fme_err {
1160         struct feature_header header;
1161         struct feature_fme_error0 fme_err_mask;
1162         struct feature_fme_error0 fme_err;
1163         struct feature_fme_pcie0_error pcie0_err_mask;
1164         struct feature_fme_pcie0_error pcie0_err;
1165         struct feature_fme_pcie1_error pcie1_err_mask;
1166         struct feature_fme_pcie1_error pcie1_err;
1167         struct feature_fme_first_error fme_first_err;
1168         struct feature_fme_next_error fme_next_err;
1169         struct feature_fme_ras_nonfaterror ras_nonfat_mask;
1170         struct feature_fme_ras_nonfaterror ras_nonfaterr;
1171         struct feature_fme_ras_catfaterror ras_catfat_mask;
1172         struct feature_fme_ras_catfaterror ras_catfaterr;
1173         struct feature_fme_ras_error_inj ras_error_inj;
1174         struct feature_fme_error_capability fme_err_capability;
1175 };
1176
1177 /* FME Partial Reconfiguration Control */
1178 struct feature_fme_pr_ctl {
1179         union {
1180                 u64 csr;
1181                 struct {
1182                         u8  pr_reset:1;         /* Reset PR Engine */
1183                         u8  rsvd3:3;            /* Reserved */
1184                         u8  pr_reset_ack:1;     /* Reset PR Engine Ack */
1185                         u8  rsvd4:3;            /* Reserved */
1186                         u8  pr_regionid:2;      /* PR Region ID */
1187                         u8  rsvd1:2;            /* Reserved */
1188                         u8  pr_start_req:1;     /* PR Start Request */
1189                         u8  pr_push_complete:1; /* PR Data push complete */
1190                         u8  pr_kind:1;          /* PR Data push complete */
1191                         u32 rsvd:17;            /* Reserved */
1192                         u32 config_data;        /* Config data TBD */
1193                 };
1194         };
1195 };
1196
1197 /* FME Partial Reconfiguration Status */
1198 struct feature_fme_pr_status {
1199         union {
1200                 u64 csr;
1201                 struct {
1202                         u16 pr_credit:9;        /* PR Credits */
1203                         u8  rsvd2:7;            /* Reserved */
1204                         u8  pr_status:1;        /* PR status */
1205                         u8  rsvd:3;             /* Reserved */
1206                         /* Altra PR Controller Block status */
1207                         u8  pr_controller_status:3;
1208                         u8  rsvd1:1;            /* Reserved */
1209                         u8  pr_host_status:4;   /* PR Host status */
1210                         u8  rsvd3:4;            /* Reserved */
1211                         /* Security Block Status fields (TBD) */
1212                         u32 security_bstatus;
1213                 };
1214         };
1215 };
1216
1217 /* FME Partial Reconfiguration Data */
1218 struct feature_fme_pr_data {
1219         union {
1220                 u64 csr;        /* PR data from the raw-binary file */
1221                 struct {
1222                         /* PR data from the raw-binary file */
1223                         u32 pr_data_raw;
1224                         u32 rsvd;
1225                 };
1226         };
1227 };
1228
1229 /* FME PR Public Key */
1230 struct feature_fme_pr_key {
1231         u64 key;                /* FME PR Public Hash */
1232 };
1233
1234 /* FME PR FEATURE */
1235 struct feature_fme_pr {
1236         struct feature_header header;
1237         /*Partial Reconfiguration control */
1238         struct feature_fme_pr_ctl       ccip_fme_pr_control;
1239
1240         /* Partial Reconfiguration Status */
1241         struct feature_fme_pr_status    ccip_fme_pr_status;
1242
1243         /* Partial Reconfiguration data */
1244         struct feature_fme_pr_data      ccip_fme_pr_data;
1245
1246         /* Partial Reconfiguration data */
1247         u64                             ccip_fme_pr_err;
1248
1249         u64 rsvd1[3];
1250
1251         /* Partial Reconfiguration data registers */
1252         u64 fme_pr_data1;
1253         u64 fme_pr_data2;
1254         u64 fme_pr_data3;
1255         u64 fme_pr_data4;
1256         u64 fme_pr_data5;
1257         u64 fme_pr_data6;
1258         u64 fme_pr_data7;
1259         u64 fme_pr_data8;
1260
1261         u64 rsvd2[5];
1262
1263         /* PR Interface ID */
1264         u64 fme_pr_intfc_id_l;
1265         u64 fme_pr_intfc_id_h;
1266
1267         /* MSIX filed to be Added */
1268 };
1269
1270 /* FME HSSI Control */
1271 struct feature_fme_hssi_eth_ctrl {
1272         union {
1273                 u64 csr;
1274                 struct {
1275                         u32 data:32;            /* HSSI data */
1276                         u16 address:16;         /* HSSI address */
1277                         /*
1278                          * HSSI comamnd
1279                          * 0x0 - No request
1280                          * 0x08 - SW register RD request
1281                          * 0x10 - SW register WR request
1282                          * 0x40 - Auxiliar bus RD request
1283                          * 0x80 - Auxiliar bus WR request
1284                          */
1285                         u16 cmd:16;
1286                 };
1287         };
1288 };
1289
1290 /* FME HSSI Status */
1291 struct feature_fme_hssi_eth_stat {
1292         union {
1293                 u64 csr;
1294                 struct {
1295                         u32 data:32;            /* HSSI data */
1296                         u8  acknowledge:1;      /* HSSI acknowledge */
1297                         u8  spare:1;            /* HSSI spare */
1298                         u32 rsvd:30;            /* Reserved */
1299                 };
1300         };
1301 };
1302
1303 /* FME HSSI FEATURE */
1304 struct feature_fme_hssi {
1305         struct feature_header header;
1306         struct feature_fme_hssi_eth_ctrl        hssi_control;
1307         struct feature_fme_hssi_eth_stat        hssi_status;
1308 };
1309
1310 #define PORT_ERR_MASK           0xfff0703ff001f
1311 struct feature_port_err_key {
1312         union {
1313                 u64 csr;
1314                 struct {
1315                         /* Tx Channel0: Overflow */
1316                         u8 tx_ch0_overflow:1;
1317                         /* Tx Channel0: Invalid request encoding */
1318                         u8 tx_ch0_invaldreq :1;
1319                         /* Tx Channel0: Request with cl_len=3 not supported */
1320                         u8 tx_ch0_cl_len3:1;
1321                         /* Tx Channel0: Request with cl_len=2 not aligned 2CL */
1322                         u8 tx_ch0_cl_len2:1;
1323                         /* Tx Channel0: Request with cl_len=4 not aligned 4CL */
1324                         u8 tx_ch0_cl_len4:1;
1325
1326                         u16 rsvd1:4;                    /* Reserved */
1327
1328                         /* AFU MMIO RD received while PORT is in reset */
1329                         u8 mmio_rd_whilerst:1;
1330                         /* AFU MMIO WR received while PORT is in reset */
1331                         u8 mmio_wr_whilerst:1;
1332
1333                         u16 rsvd2:5;                    /* Reserved */
1334
1335                         /* Tx Channel1: Overflow */
1336                         u8 tx_ch1_overflow:1;
1337                         /* Tx Channel1: Invalid request encoding */
1338                         u8 tx_ch1_invaldreq:1;
1339                         /* Tx Channel1: Request with cl_len=3 not supported */
1340                         u8 tx_ch1_cl_len3:1;
1341                         /* Tx Channel1: Request with cl_len=2 not aligned 2CL */
1342                         u8 tx_ch1_cl_len2:1;
1343                         /* Tx Channel1: Request with cl_len=4 not aligned 4CL */
1344                         u8 tx_ch1_cl_len4:1;
1345
1346                         /* Tx Channel1: Insufficient data payload */
1347                         u8 tx_ch1_insuff_data:1;
1348                         /* Tx Channel1: Data payload overrun */
1349                         u8 tx_ch1_data_overrun:1;
1350                         /* Tx Channel1 : Incorrect address */
1351                         u8 tx_ch1_incorr_addr:1;
1352                         /* Tx Channel1 : NON-Zero SOP Detected */
1353                         u8 tx_ch1_nzsop:1;
1354                         /* Tx Channel1 : Illegal VC_SEL, atomic request VLO */
1355                         u8 tx_ch1_illegal_vcsel:1;
1356
1357                         u8 rsvd3:6;                     /* Reserved */
1358
1359                         /* MMIO Read Timeout in AFU */
1360                         u8 mmioread_timeout:1;
1361
1362                         /* Tx Channel2: FIFO Overflow */
1363                         u8 tx_ch2_fifo_overflow:1;
1364
1365                         /* MMIO read is not matching pending request */
1366                         u8 unexp_mmio_resp:1;
1367
1368                         u8 rsvd4:5;                     /* Reserved */
1369
1370                         /* Number of pending Requests: counter overflow */
1371                         u8 tx_req_counter_overflow:1;
1372                         /* Req with Address violating SMM Range */
1373                         u8 llpr_smrr_err:1;
1374                         /* Req with Address violating second SMM Range */
1375                         u8 llpr_smrr2_err:1;
1376                         /* Req with Address violating ME Stolen message */
1377                         u8 llpr_mesg_err:1;
1378                         /* Req with Address violating Generic Protected Range */
1379                         u8 genprot_range_err:1;
1380                         /* Req with Address violating Legacy Range low */
1381                         u8 legrange_low_err:1;
1382                         /* Req with Address violating Legacy Range High */
1383                         u8 legrange_high_err:1;
1384                         /* Req with Address violating VGA memory range */
1385                         u8 vgmem_range_err:1;
1386                         u8 page_fault_err:1;            /* Page fault */
1387                         u8 pmr_err:1;                   /* PMR Error */
1388                         u8 ap6_event:1;                 /* AP6 event */
1389                         /* VF FLR detected on Port with PF access control */
1390                         u8 vfflr_access_err:1;
1391                         u16 rsvd5:12;                   /* Reserved */
1392                 };
1393         };
1394 };
1395
1396 /* Port first error register, not contain all error bits in error register. */
1397 struct feature_port_first_err_key {
1398         union {
1399                 u64 csr;
1400                 struct {
1401                         u8 tx_ch0_overflow:1;
1402                         u8 tx_ch0_invaldreq :1;
1403                         u8 tx_ch0_cl_len3:1;
1404                         u8 tx_ch0_cl_len2:1;
1405                         u8 tx_ch0_cl_len4:1;
1406                         u8 rsvd1:4;                     /* Reserved */
1407                         u8 mmio_rd_whilerst:1;
1408                         u8 mmio_wr_whilerst:1;
1409                         u8 rsvd2:5;                     /* Reserved */
1410                         u8 tx_ch1_overflow:1;
1411                         u8 tx_ch1_invaldreq:1;
1412                         u8 tx_ch1_cl_len3:1;
1413                         u8 tx_ch1_cl_len2:1;
1414                         u8 tx_ch1_cl_len4:1;
1415                         u8 tx_ch1_insuff_data:1;
1416                         u8 tx_ch1_data_overrun:1;
1417                         u8 tx_ch1_incorr_addr:1;
1418                         u8 tx_ch1_nzsop:1;
1419                         u8 tx_ch1_illegal_vcsel:1;
1420                         u8 rsvd3:6;                     /* Reserved */
1421                         u8 mmioread_timeout:1;
1422                         u8 tx_ch2_fifo_overflow:1;
1423                         u8 rsvd4:6;                     /* Reserved */
1424                         u8 tx_req_counter_overflow:1;
1425                         u32 rsvd5:23;                   /* Reserved */
1426                 };
1427         };
1428 };
1429
1430 /* Port malformed Req0 */
1431 struct feature_port_malformed_req0 {
1432         u64 header_lsb;
1433 };
1434
1435 /* Port malformed Req1 */
1436 struct feature_port_malformed_req1 {
1437         u64 header_msb;
1438 };
1439
1440 /* Port debug register */
1441 struct feature_port_debug {
1442         u64 port_debug;
1443 };
1444
1445 /* Port error capabilities */
1446 struct feature_port_err_capability {
1447         union {
1448                 u64 csr;
1449                 struct {
1450                         u8  support_intr:1;
1451                         /* MSI-X vector table entry number */
1452                         u16 intr_vector_num:12;
1453                         u64 rsvd:51;            /* Reserved */
1454                 };
1455         };
1456 };
1457
1458 /* PORT FEATURE ERROR */
1459 struct feature_port_error {
1460         struct feature_header header;
1461         struct feature_port_err_key error_mask;
1462         struct feature_port_err_key port_error;
1463         struct feature_port_first_err_key port_first_error;
1464         struct feature_port_malformed_req0 malreq0;
1465         struct feature_port_malformed_req1 malreq1;
1466         struct feature_port_debug port_debug;
1467         struct feature_port_err_capability error_capability;
1468 };
1469
1470 /* Port UMSG Capability */
1471 struct feature_port_umsg_cap {
1472         union {
1473                 u64 csr;
1474                 struct {
1475                         /* Number of umsg allocated to this port */
1476                         u8 umsg_allocated;
1477                         /* Enable / Disable UMsg engine for this port */
1478                         u8 umsg_enable:1;
1479                         /* Usmg initialization status */
1480                         u8 umsg_init_complete:1;
1481                         /* IOMMU can not translate the umsg base address */
1482                         u8 umsg_trans_error:1;
1483                         u64 rsvd:53;            /* Reserved */
1484                 };
1485         };
1486 };
1487
1488 /* Port UMSG base address */
1489 struct feature_port_umsg_baseaddr {
1490         union {
1491                 u64 csr;
1492                 struct {
1493                         u64 base_addr:48;       /* 48 bit physical address */
1494                         u16 rsvd;               /* Reserved */
1495                 };
1496         };
1497 };
1498
1499 struct feature_port_umsg_mode {
1500         union {
1501                 u64 csr;
1502                 struct {
1503                         u32 umsg_hint_enable;   /* UMSG hint enable/disable */
1504                         u32 rsvd;               /* Reserved */
1505                 };
1506         };
1507 };
1508
1509 /* PORT FEATURE UMSG */
1510 struct feature_port_umsg {
1511         struct feature_header header;
1512         struct feature_port_umsg_cap capability;
1513         struct feature_port_umsg_baseaddr baseaddr;
1514         struct feature_port_umsg_mode mode;
1515 };
1516
1517 #define UMSG_EN_POLL_INVL 10 /* us */
1518 #define UMSG_EN_POLL_TIMEOUT 1000 /* us */
1519
1520 /* Port UINT Capability */
1521 struct feature_port_uint_cap {
1522         union {
1523                 u64 csr;
1524                 struct {
1525                         u16 intr_num:12;        /* Supported interrupts num */
1526                         /* First MSI-X vector table entry number */
1527                         u16 first_vec_num:12;
1528                         u64 rsvd:40;
1529                 };
1530         };
1531 };
1532
1533 /* PORT FEATURE UINT */
1534 struct feature_port_uint {
1535         struct feature_header header;
1536         struct feature_port_uint_cap capability;
1537 };
1538
1539 /* STP region supports mmap operation, so use page aligned size. */
1540 #define PORT_FEATURE_STP_REGION_SIZE \
1541         IFPGA_PAGE_ALIGN(sizeof(struct feature_port_stp))
1542
1543 /* Port STP status register (for debug only)*/
1544 struct feature_port_stp_status {
1545         union {
1546                 u64 csr;
1547                 struct {
1548                         /* SLD Hub end-point read/write timeout */
1549                         u8 sld_ep_timeout:1;
1550                         /* Remote STP in reset/disable */
1551                         u8 rstp_disabled:1;
1552                         u8 unsupported_read:1;
1553                         /* MMIO timeout detected and faked with a response */
1554                         u8 mmio_timeout:1;
1555                         u8 txfifo_count:4;
1556                         u8 rxfifo_count:4;
1557                         u8 txfifo_overflow:1;
1558                         u8 txfifo_underflow:1;
1559                         u8 rxfifo_overflow:1;
1560                         u8 rxfifo_underflow:1;
1561                         /* Number of MMIO write requests */
1562                         u16 write_requests;
1563                         /* Number of MMIO read requests */
1564                         u16 read_requests;
1565                         /* Number of MMIO read responses */
1566                         u16 read_responses;
1567                 };
1568         };
1569 };
1570
1571 /*
1572  * PORT FEATURE STP
1573  * Most registers in STP region are not touched by driver, but mmapped to user
1574  * space. So they are not defined in below data structure, as its actual size
1575  * is 0x18c per spec.
1576  */
1577 struct feature_port_stp {
1578         struct feature_header header;
1579         struct feature_port_stp_status stp_status;
1580 };
1581
1582 /**
1583  * enum fpga_pr_states - fpga PR states
1584  * @FPGA_PR_STATE_UNKNOWN: can't determine state
1585  * @FPGA_PR_STATE_WRITE_INIT: preparing FPGA for programming
1586  * @FPGA_PR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage
1587  * @FPGA_PR_STATE_WRITE: writing image to FPGA
1588  * @FPGA_PR_STATE_WRITE_ERR: Error while writing FPGA
1589  * @FPGA_PR_STATE_WRITE_COMPLETE: Doing post programming steps
1590  * @FPGA_PR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE
1591  * @FPGA_PR_STATE_OPERATING: FPGA PR done
1592  */
1593 enum fpga_pr_states {
1594         /* canot determine state states */
1595         FPGA_PR_STATE_UNKNOWN,
1596
1597         /* write sequence: init, write, complete */
1598         FPGA_PR_STATE_WRITE_INIT,
1599         FPGA_PR_STATE_WRITE_INIT_ERR,
1600         FPGA_PR_STATE_WRITE,
1601         FPGA_PR_STATE_WRITE_ERR,
1602         FPGA_PR_STATE_WRITE_COMPLETE,
1603         FPGA_PR_STATE_WRITE_COMPLETE_ERR,
1604
1605         /* FPGA PR done */
1606         FPGA_PR_STATE_DONE,
1607 };
1608
1609 /*
1610  * FPGA Manager flags
1611  * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
1612  */
1613 #define FPGA_MGR_PARTIAL_RECONFIG       BIT(0)
1614
1615 /**
1616  * struct fpga_pr_info - specific information to a FPGA PR
1617  * @flags: boolean flags as defined above
1618  * @pr_err: PR error code
1619  * @state: fpga manager state
1620  * @port_id: port id
1621  */
1622 struct fpga_pr_info {
1623         u32 flags;
1624         u64 pr_err;
1625         enum fpga_pr_states state;
1626         int port_id;
1627 };
1628
1629 #define DEFINE_FPGA_PR_ERR_MSG(_name_)                  \
1630 static const char * const _name_[] = {                  \
1631         "PR operation error detected",                  \
1632         "PR CRC error detected",                        \
1633         "PR incompatiable bitstream error detected",    \
1634         "PR IP protocol error detected",                \
1635         "PR FIFO overflow error detected",              \
1636         "PR timeout error detected",                    \
1637         "PR secure load error detected",                \
1638 }
1639
1640 #define RST_POLL_INVL 10 /* us */
1641 #define RST_POLL_TIMEOUT 1000 /* us */
1642
1643 #define PR_WAIT_TIMEOUT   15000000
1644
1645 #define PR_HOST_STATUS_IDLE     0
1646 #define PR_MAX_ERR_NUM  7
1647
1648 DEFINE_FPGA_PR_ERR_MSG(pr_err_msg);
1649
1650 /*
1651  * green bitstream header must be byte-packed to match the
1652  * real file format.
1653  */
1654 struct bts_header {
1655         u64 guid_h;
1656         u64 guid_l;
1657         u32 metadata_len;
1658 };
1659
1660 #define GBS_GUID_H              0x414750466e6f6558
1661 #define GBS_GUID_L              0x31303076534247b7
1662 #define is_valid_bts(bts_hdr)                           \
1663         (((bts_hdr)->guid_h == GBS_GUID_H) &&           \
1664         ((bts_hdr)->guid_l == GBS_GUID_L))
1665
1666 /* bitstream id definition */
1667 struct fme_bitstream_id {
1668         union {
1669                 u64 id;
1670                 struct {
1671                         u64 hash:32;
1672                         u64 interface:4;
1673                         u64 reserved:12;
1674                         u64 debug:4;
1675                         u64 patch:4;
1676                         u64 minor:4;
1677                         u64 major:4;
1678                 };
1679         };
1680 };
1681
1682 enum board_interface {
1683         VC_8_10G = 0,
1684         VC_4_25G = 1,
1685         VC_2_1_25 = 2,
1686         VC_4_25G_2_25G = 3,
1687         VC_2_2_25G = 4,
1688 };
1689
1690 struct ifpga_fme_board_info {
1691         enum board_interface type;
1692         u32 build_hash;
1693         u32 debug_version;
1694         u32 patch_version;
1695         u32 minor_version;
1696         u32 major_version;
1697         u32 nums_of_retimer;
1698         u32 ports_per_retimer;
1699         u32 nums_of_fvl;
1700         u32 ports_per_fvl;
1701 };
1702
1703 #pragma pack(pop)
1704 #endif /* _BASE_IFPGA_DEFINES_H_ */