drivers/vdpa/mlx5/mlx5_vdpa_event.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2019 Mellanox Technologies, Ltd
   3  */
   4 #include <unistd.h>
   5 #include <stdint.h>
   6 #include <fcntl.h>
   7 #include <sys/eventfd.h>
   8
   9 #include <rte_malloc.h>
  10 #include <rte_errno.h>
  11 #include <rte_lcore.h>
  12 #include <rte_atomic.h>
  13 #include <rte_common.h>
  14 #include <rte_io.h>
  15 #include <rte_alarm.h>
  16
  17 #include <mlx5_common.h>
  18
  19 #include "mlx5_vdpa_utils.h"
  20 #include "mlx5_vdpa.h"
  21
  22
  23 void
  24 mlx5_vdpa_event_qp_global_release(struct mlx5_vdpa_priv *priv)
  25 {
  26         if (priv->uar) {
  27                 mlx5_glue->devx_free_uar(priv->uar);
  28                 priv->uar = NULL;
  29         }
  30 #ifdef HAVE_IBV_DEVX_EVENT
  31         if (priv->eventc) {
  32                 union {
  33                         struct mlx5dv_devx_async_event_hdr event_resp;
  34                         uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr)
  35                                                                          + 128];
  36                 } out;
  37
  38                 /* Clean all pending events. */
  39                 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
  40                        sizeof(out.buf)) >=
  41                        (ssize_t)sizeof(out.event_resp.cookie))
  42                         ;
  43                 mlx5_glue->devx_destroy_event_channel(priv->eventc);
  44                 priv->eventc = NULL;
  45         }
  46 #endif
  47         priv->eqn = 0;
  48 }
  49
  50 /* Prepare all the global resources for all the event objects.*/
  51 static int
  52 mlx5_vdpa_event_qp_global_prepare(struct mlx5_vdpa_priv *priv)
  53 {
  54         uint32_t lcore;
  55
  56         if (priv->eventc)
  57                 return 0;
  58         lcore = (uint32_t)rte_lcore_to_cpu_id(-1);
  59         if (mlx5_glue->devx_query_eqn(priv->ctx, lcore, &priv->eqn)) {
  60                 rte_errno = errno;
  61                 DRV_LOG(ERR, "Failed to query EQ number %d.", rte_errno);
  62                 return -1;
  63         }
  64         priv->eventc = mlx5_glue->devx_create_event_channel(priv->ctx,
  65                            MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
  66         if (!priv->eventc) {
  67                 rte_errno = errno;
  68                 DRV_LOG(ERR, "Failed to create event channel %d.",
  69                         rte_errno);
  70                 goto error;
  71         }
  72         priv->uar = mlx5_glue->devx_alloc_uar(priv->ctx, 0);
  73         if (!priv->uar) {
  74                 rte_errno = errno;
  75                 DRV_LOG(ERR, "Failed to allocate UAR.");
  76                 goto error;
  77         }
  78         return 0;
  79 error:
  80         mlx5_vdpa_event_qp_global_release(priv);
  81         return -1;
  82 }
  83
  84 static void
  85 mlx5_vdpa_cq_destroy(struct mlx5_vdpa_cq *cq)
  86 {
  87         if (cq->cq)
  88                 claim_zero(mlx5_devx_cmd_destroy(cq->cq));
  89         if (cq->umem_obj)
  90                 claim_zero(mlx5_glue->devx_umem_dereg(cq->umem_obj));
  91         if (cq->umem_buf)
  92                 rte_free((void *)(uintptr_t)cq->umem_buf);
  93         memset(cq, 0, sizeof(*cq));
  94 }
  95
  96 static inline void __rte_unused
  97 mlx5_vdpa_cq_arm(struct mlx5_vdpa_priv *priv, struct mlx5_vdpa_cq *cq)
  98 {
  99         uint32_t arm_sn = cq->arm_sn << MLX5_CQ_SQN_OFFSET;
 100         uint32_t cq_ci = cq->cq_ci & MLX5_CI_MASK;
 101         uint32_t doorbell_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | cq_ci;
 102         uint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq->id;
 103         uint64_t db_be = rte_cpu_to_be_64(doorbell);
 104         uint32_t *addr = RTE_PTR_ADD(priv->uar->base_addr, MLX5_CQ_DOORBELL);
 105
 106         rte_io_wmb();
 107         cq->db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
 108         rte_wmb();
 109 #ifdef RTE_ARCH_64
 110         *(uint64_t *)addr = db_be;
 111 #else
 112         *(uint32_t *)addr = db_be;
 113         rte_io_wmb();
 114         *((uint32_t *)addr + 1) = db_be >> 32;
 115 #endif
 116         cq->arm_sn++;
 117         cq->armed = 1;
 118 }
 119
 120 static int
 121 mlx5_vdpa_cq_create(struct mlx5_vdpa_priv *priv, uint16_t log_desc_n,
 122                     int callfd, struct mlx5_vdpa_cq *cq)
 123 {
 124         struct mlx5_devx_cq_attr attr;
 125         size_t pgsize = sysconf(_SC_PAGESIZE);
 126         uint32_t umem_size;
 127         uint16_t event_nums[1] = {0};
 128         uint16_t cq_size = 1 << log_desc_n;
 129         int ret;
 130
 131         cq->log_desc_n = log_desc_n;
 132         umem_size = sizeof(struct mlx5_cqe) * cq_size + sizeof(*cq->db_rec) * 2;
 133         cq->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
 134         if (!cq->umem_buf) {
 135                 DRV_LOG(ERR, "Failed to allocate memory for CQ.");
 136                 rte_errno = ENOMEM;
 137                 return -ENOMEM;
 138         }
 139         cq->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
 140                                                 (void *)(uintptr_t)cq->umem_buf,
 141                                                 umem_size,
 142                                                 IBV_ACCESS_LOCAL_WRITE);
 143         if (!cq->umem_obj) {
 144                 DRV_LOG(ERR, "Failed to register umem for CQ.");
 145                 goto error;
 146         }
 147         attr.q_umem_valid = 1;
 148         attr.db_umem_valid = 1;
 149         attr.use_first_only = 1;
 150         attr.overrun_ignore = 0;
 151         attr.uar_page_id = priv->uar->page_id;
 152         attr.q_umem_id = cq->umem_obj->umem_id;
 153         attr.q_umem_offset = 0;
 154         attr.db_umem_id = cq->umem_obj->umem_id;
 155         attr.db_umem_offset = sizeof(struct mlx5_cqe) * cq_size;
 156         attr.eqn = priv->eqn;
 157         attr.log_cq_size = log_desc_n;
 158         attr.log_page_size = rte_log2_u32(pgsize);
 159         cq->cq = mlx5_devx_cmd_create_cq(priv->ctx, &attr);
 160         if (!cq->cq)
 161                 goto error;
 162         cq->db_rec = RTE_PTR_ADD(cq->umem_buf, (uintptr_t)attr.db_umem_offset);
 163         cq->cq_ci = 0;
 164         rte_spinlock_init(&cq->sl);
 165         /* Subscribe CQ event to the event channel controlled by the driver. */
 166         ret = mlx5_glue->devx_subscribe_devx_event(priv->eventc, cq->cq->obj,
 167                                                    sizeof(event_nums),
 168                                                    event_nums,
 169                                                    (uint64_t)(uintptr_t)cq);
 170         if (ret) {
 171                 DRV_LOG(ERR, "Failed to subscribe CQE event.");
 172                 rte_errno = errno;
 173                 goto error;
 174         }
 175         cq->callfd = callfd;
 176         /* Init CQ to ones to be in HW owner in the start. */
 177         cq->cqes[0].op_own = MLX5_CQE_OWNER_MASK;
 178         cq->cqes[0].wqe_counter = rte_cpu_to_be_16(cq_size - 1);
 179         /* First arming. */
 180         mlx5_vdpa_cq_arm(priv, cq);
 181         return 0;
 182 error:
 183         mlx5_vdpa_cq_destroy(cq);
 184         return -1;
 185 }
 186
 187 static inline uint32_t
 188 mlx5_vdpa_cq_poll(struct mlx5_vdpa_cq *cq)
 189 {
 190         struct mlx5_vdpa_event_qp *eqp =
 191                                 container_of(cq, struct mlx5_vdpa_event_qp, cq);
 192         const unsigned int cq_size = 1 << cq->log_desc_n;
 193         const unsigned int cq_mask = cq_size - 1;
 194         union {
 195                 struct {
 196                         uint16_t wqe_counter;
 197                         uint8_t rsvd5;
 198                         uint8_t op_own;
 199                 };
 200                 uint32_t word;
 201         } last_word;
 202         uint16_t next_wqe_counter = cq->cq_ci & cq_mask;
 203         uint16_t cur_wqe_counter;
 204         uint16_t comp;
 205
 206         last_word.word = rte_read32(&cq->cqes[0].wqe_counter);
 207         cur_wqe_counter = rte_be_to_cpu_16(last_word.wqe_counter);
 208         comp = (cur_wqe_counter + 1u - next_wqe_counter) & cq_mask;
 209         if (comp) {
 210                 cq->cq_ci += comp;
 211                 MLX5_ASSERT(!!(cq->cq_ci & cq_size) ==
 212                             MLX5_CQE_OWNER(last_word.op_own));
 213                 MLX5_ASSERT(MLX5_CQE_OPCODE(last_word.op_own) !=
 214                             MLX5_CQE_INVALID);
 215                 if (unlikely(!(MLX5_CQE_OPCODE(last_word.op_own) ==
 216                                MLX5_CQE_RESP_ERR ||
 217                                MLX5_CQE_OPCODE(last_word.op_own) ==
 218                                MLX5_CQE_REQ_ERR)))
 219                         cq->errors++;
 220                 rte_io_wmb();
 221                 /* Ring CQ doorbell record. */
 222                 cq->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
 223                 rte_io_wmb();
 224                 /* Ring SW QP doorbell record. */
 225                 eqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);
 226         }
 227         return comp;
 228 }
 229
 230 static void
 231 mlx5_vdpa_arm_all_cqs(struct mlx5_vdpa_priv *priv)
 232 {
 233         struct mlx5_vdpa_cq *cq;
 234         int i;
 235
 236         for (i = 0; i < priv->nr_virtqs; i++) {
 237                 cq = &priv->virtqs[i].eqp.cq;
 238                 if (cq->cq && !cq->armed)
 239                         mlx5_vdpa_cq_arm(priv, cq);
 240         }
 241 }
 242
 243 static void
 244 mlx5_vdpa_timer_sleep(struct mlx5_vdpa_priv *priv, uint32_t max)
 245 {
 246         if (priv->event_mode == MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER) {
 247                 switch (max) {
 248                 case 0:
 249                         priv->timer_delay_us += priv->event_us;
 250                         break;
 251                 case 1:
 252                         break;
 253                 default:
 254                         priv->timer_delay_us /= max;
 255                         break;
 256                 }
 257         }
 258         usleep(priv->timer_delay_us);
 259 }
 260
 261 static void *
 262 mlx5_vdpa_poll_handle(void *arg)
 263 {
 264         struct mlx5_vdpa_priv *priv = arg;
 265         int i;
 266         struct mlx5_vdpa_cq *cq;
 267         uint32_t max;
 268         uint64_t current_tic;
 269
 270         pthread_mutex_lock(&priv->timer_lock);
 271         while (!priv->timer_on)
 272                 pthread_cond_wait(&priv->timer_cond, &priv->timer_lock);
 273         pthread_mutex_unlock(&priv->timer_lock);
 274         priv->timer_delay_us = priv->event_mode ==
 275                                             MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
 276                                               MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
 277                                                                  priv->event_us;
 278         while (1) {
 279                 max = 0;
 280                 for (i = 0; i < priv->nr_virtqs; i++) {
 281                         cq = &priv->virtqs[i].eqp.cq;
 282                         if (cq->cq && !cq->armed) {
 283                                 uint32_t comp = mlx5_vdpa_cq_poll(cq);
 284
 285                                 if (comp) {
 286                                         /* Notify guest for descs consuming. */
 287                                         if (cq->callfd != -1)
 288                                                 eventfd_write(cq->callfd,
 289                                                               (eventfd_t)1);
 290                                         if (comp > max)
 291                                                 max = comp;
 292                                 }
 293                         }
 294                 }
 295                 current_tic = rte_rdtsc();
 296                 if (!max) {
 297                         /* No traffic ? stop timer and load interrupts. */
 298                         if (current_tic - priv->last_traffic_tic >=
 299                             rte_get_timer_hz() * priv->no_traffic_time_s) {
 300                                 DRV_LOG(DEBUG, "Device %s traffic was stopped.",
 301                                         priv->vdev->device->name);
 302                                 mlx5_vdpa_arm_all_cqs(priv);
 303                                 pthread_mutex_lock(&priv->timer_lock);
 304                                 priv->timer_on = 0;
 305                                 while (!priv->timer_on)
 306                                         pthread_cond_wait(&priv->timer_cond,
 307                                                           &priv->timer_lock);
 308                                 pthread_mutex_unlock(&priv->timer_lock);
 309                                 priv->timer_delay_us = priv->event_mode ==
 310                                             MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
 311                                               MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
 312                                                                  priv->event_us;
 313                                 continue;
 314                         }
 315                 } else {
 316                         priv->last_traffic_tic = current_tic;
 317                 }
 318                 mlx5_vdpa_timer_sleep(priv, max);
 319         }
 320         return NULL;
 321 }
 322
 323 static void
 324 mlx5_vdpa_interrupt_handler(void *cb_arg)
 325 {
 326         struct mlx5_vdpa_priv *priv = cb_arg;
 327 #ifdef HAVE_IBV_DEVX_EVENT
 328         union {
 329                 struct mlx5dv_devx_async_event_hdr event_resp;
 330                 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
 331         } out;
 332
 333         while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
 334                                          sizeof(out.buf)) >=
 335                                        (ssize_t)sizeof(out.event_resp.cookie)) {
 336                 struct mlx5_vdpa_cq *cq = (struct mlx5_vdpa_cq *)
 337                                                (uintptr_t)out.event_resp.cookie;
 338                 struct mlx5_vdpa_event_qp *eqp = container_of(cq,
 339                                                  struct mlx5_vdpa_event_qp, cq);
 340                 struct mlx5_vdpa_virtq *virtq = container_of(eqp,
 341                                                    struct mlx5_vdpa_virtq, eqp);
 342
 343                 mlx5_vdpa_cq_poll(cq);
 344                 /* Notify guest for descs consuming. */
 345                 if (cq->callfd != -1)
 346                         eventfd_write(cq->callfd, (eventfd_t)1);
 347                 if (priv->event_mode == MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
 348                         mlx5_vdpa_cq_arm(priv, cq);
 349                         return;
 350                 }
 351                 /* Don't arm again - timer will take control. */
 352                 DRV_LOG(DEBUG, "Device %s virtq %d cq %d event was captured."
 353                         " Timer is %s, cq ci is %u.\n",
 354                         priv->vdev->device->name,
 355                         (int)virtq->index, cq->cq->id,
 356                         priv->timer_on ? "on" : "off", cq->cq_ci);
 357                 cq->armed = 0;
 358         }
 359 #endif
 360
 361         /* Traffic detected: make sure timer is on. */
 362         priv->last_traffic_tic = rte_rdtsc();
 363         pthread_mutex_lock(&priv->timer_lock);
 364         if (!priv->timer_on) {
 365                 priv->timer_on = 1;
 366                 pthread_cond_signal(&priv->timer_cond);
 367         }
 368         pthread_mutex_unlock(&priv->timer_lock);
 369 }
 370
 371 int
 372 mlx5_vdpa_cqe_event_setup(struct mlx5_vdpa_priv *priv)
 373 {
 374         int flags;
 375         int ret;
 376
 377         if (!priv->eventc)
 378                 /* All virtqs are in poll mode. */
 379                 return 0;
 380         if (priv->event_mode != MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
 381                 pthread_mutex_init(&priv->timer_lock, NULL);
 382                 pthread_cond_init(&priv->timer_cond, NULL);
 383                 priv->timer_on = 0;
 384                 ret = pthread_create(&priv->timer_tid, NULL,
 385                                      mlx5_vdpa_poll_handle, (void *)priv);
 386                 if (ret) {
 387                         DRV_LOG(ERR, "Failed to create timer thread.");
 388                         return -1;
 389                 }
 390         }
 391         flags = fcntl(priv->eventc->fd, F_GETFL);
 392         ret = fcntl(priv->eventc->fd, F_SETFL, flags | O_NONBLOCK);
 393         if (ret) {
 394                 DRV_LOG(ERR, "Failed to change event channel FD.");
 395                 goto error;
 396         }
 397         priv->intr_handle.fd = priv->eventc->fd;
 398         priv->intr_handle.type = RTE_INTR_HANDLE_EXT;
 399         if (rte_intr_callback_register(&priv->intr_handle,
 400                                        mlx5_vdpa_interrupt_handler, priv)) {
 401                 priv->intr_handle.fd = 0;
 402                 DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno);
 403                 goto error;
 404         }
 405         return 0;
 406 error:
 407         mlx5_vdpa_cqe_event_unset(priv);
 408         return -1;
 409 }
 410
 411 void
 412 mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv)
 413 {
 414         int retries = MLX5_VDPA_INTR_RETRIES;
 415         int ret = -EAGAIN;
 416         void *status;
 417
 418         if (priv->intr_handle.fd) {
 419                 while (retries-- && ret == -EAGAIN) {
 420                         ret = rte_intr_callback_unregister(&priv->intr_handle,
 421                                                     mlx5_vdpa_interrupt_handler,
 422                                                     priv);
 423                         if (ret == -EAGAIN) {
 424                                 DRV_LOG(DEBUG, "Try again to unregister fd %d "
 425                                         "of CQ interrupt, retries = %d.",
 426                                         priv->intr_handle.fd, retries);
 427                                 rte_pause();
 428                         }
 429                 }
 430                 memset(&priv->intr_handle, 0, sizeof(priv->intr_handle));
 431         }
 432         if (priv->timer_tid) {
 433                 pthread_cancel(priv->timer_tid);
 434                 pthread_join(priv->timer_tid, &status);
 435         }
 436         priv->timer_tid = 0;
 437 }
 438
 439 void
 440 mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp)
 441 {
 442         if (eqp->sw_qp)
 443                 claim_zero(mlx5_devx_cmd_destroy(eqp->sw_qp));
 444         if (eqp->umem_obj)
 445                 claim_zero(mlx5_glue->devx_umem_dereg(eqp->umem_obj));
 446         if (eqp->umem_buf)
 447                 rte_free(eqp->umem_buf);
 448         if (eqp->fw_qp)
 449                 claim_zero(mlx5_devx_cmd_destroy(eqp->fw_qp));
 450         mlx5_vdpa_cq_destroy(&eqp->cq);
 451         memset(eqp, 0, sizeof(*eqp));
 452 }
 453
 454 static int
 455 mlx5_vdpa_qps2rts(struct mlx5_vdpa_event_qp *eqp)
 456 {
 457         if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RST2INIT_QP,
 458                                           eqp->sw_qp->id)) {
 459                 DRV_LOG(ERR, "Failed to modify FW QP to INIT state(%u).",
 460                         rte_errno);
 461                 return -1;
 462         }
 463         if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RST2INIT_QP,
 464                                           eqp->fw_qp->id)) {
 465                 DRV_LOG(ERR, "Failed to modify SW QP to INIT state(%u).",
 466                         rte_errno);
 467                 return -1;
 468         }
 469         if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_INIT2RTR_QP,
 470                                           eqp->sw_qp->id)) {
 471                 DRV_LOG(ERR, "Failed to modify FW QP to RTR state(%u).",
 472                         rte_errno);
 473                 return -1;
 474         }
 475         if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_INIT2RTR_QP,
 476                                           eqp->fw_qp->id)) {
 477                 DRV_LOG(ERR, "Failed to modify SW QP to RTR state(%u).",
 478                         rte_errno);
 479                 return -1;
 480         }
 481         if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RTR2RTS_QP,
 482                                           eqp->sw_qp->id)) {
 483                 DRV_LOG(ERR, "Failed to modify FW QP to RTS state(%u).",
 484                         rte_errno);
 485                 return -1;
 486         }
 487         if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RTR2RTS_QP,
 488                                           eqp->fw_qp->id)) {
 489                 DRV_LOG(ERR, "Failed to modify SW QP to RTS state(%u).",
 490                         rte_errno);
 491                 return -1;
 492         }
 493         return 0;
 494 }
 495
 496 int
 497 mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,
 498                           int callfd, struct mlx5_vdpa_event_qp *eqp)
 499 {
 500         struct mlx5_devx_qp_attr attr = {0};
 501         uint16_t log_desc_n = rte_log2_u32(desc_n);
 502         uint32_t umem_size = (1 << log_desc_n) * MLX5_WSEG_SIZE +
 503                                                        sizeof(*eqp->db_rec) * 2;
 504
 505         if (mlx5_vdpa_event_qp_global_prepare(priv))
 506                 return -1;
 507         if (mlx5_vdpa_cq_create(priv, log_desc_n, callfd, &eqp->cq))
 508                 return -1;
 509         attr.pd = priv->pdn;
 510         eqp->fw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
 511         if (!eqp->fw_qp) {
 512                 DRV_LOG(ERR, "Failed to create FW QP(%u).", rte_errno);
 513                 goto error;
 514         }
 515         eqp->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
 516         if (!eqp->umem_buf) {
 517                 DRV_LOG(ERR, "Failed to allocate memory for SW QP.");
 518                 rte_errno = ENOMEM;
 519                 goto error;
 520         }
 521         eqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
 522                                                (void *)(uintptr_t)eqp->umem_buf,
 523                                                umem_size,
 524                                                IBV_ACCESS_LOCAL_WRITE);
 525         if (!eqp->umem_obj) {
 526                 DRV_LOG(ERR, "Failed to register umem for SW QP.");
 527                 goto error;
 528         }
 529         attr.uar_index = priv->uar->page_id;
 530         attr.cqn = eqp->cq.cq->id;
 531         attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));
 532         attr.rq_size = 1 << log_desc_n;
 533         attr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);
 534         attr.sq_size = 0; /* No need SQ. */
 535         attr.dbr_umem_valid = 1;
 536         attr.wq_umem_id = eqp->umem_obj->umem_id;
 537         attr.wq_umem_offset = 0;
 538         attr.dbr_umem_id = eqp->umem_obj->umem_id;
 539         attr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE;
 540         eqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
 541         if (!eqp->sw_qp) {
 542                 DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno);
 543                 goto error;
 544         }
 545         eqp->db_rec = RTE_PTR_ADD(eqp->umem_buf, (uintptr_t)attr.dbr_address);
 546         if (mlx5_vdpa_qps2rts(eqp))
 547                 goto error;
 548         /* First ringing. */
 549         rte_write32(rte_cpu_to_be_32(1 << log_desc_n), &eqp->db_rec[0]);
 550         return 0;
 551 error:
 552         mlx5_vdpa_event_qp_destroy(eqp);
 553         return -1;
 554 }