1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016-2017 Intel Corporation
11 #include "pipeline_common.h"
13 struct config_data cdata = {
14 .num_packets = (1L << 25), /* do ~32M packets */
16 .queue_type = RTE_SCHED_TYPE_ATOMIC,
24 core_in_use(unsigned int lcore_id) {
25 return (fdata->rx_core[lcore_id] || fdata->sched_core[lcore_id] ||
26 fdata->tx_core[lcore_id] || fdata->worker_core[lcore_id]);
30 eth_tx_buffer_retry(struct rte_mbuf **pkts, uint16_t unsent,
33 int port_id = (uintptr_t) userdata;
34 unsigned int _sent = 0;
37 /* Note: hard-coded TX queue */
38 _sent += rte_eth_tx_burst(port_id, 0, &pkts[_sent],
40 } while (_sent != unsent);
44 * Parse the coremask given as argument (hexadecimal string) and fill
45 * the global configuration (core role and core count) with the parsed
48 static int xdigit2val(unsigned char c)
62 parse_coremask(const char *coremask)
65 unsigned int count = 0;
69 const int32_t BITS_HEX = 4;
73 /* Remove all blank characters ahead and after .
74 * Remove 0x/0X if exists.
76 while (isblank(*coremask))
78 if (coremask[0] == '0' && ((coremask[1] == 'x')
79 || (coremask[1] == 'X')))
82 while ((i > 0) && isblank(coremask[i - 1]))
87 for (i = i - 1; i >= 0 && idx < MAX_NUM_CORE; i--) {
89 if (isxdigit(c) == 0) {
90 /* invalid characters */
94 for (j = 0; j < BITS_HEX && idx < MAX_NUM_CORE; j++, idx++) {
102 if (coremask[i] != '0')
109 static struct option long_options[] = {
110 {"workers", required_argument, 0, 'w'},
111 {"packets", required_argument, 0, 'n'},
112 {"atomic-flows", required_argument, 0, 'f'},
113 {"num_stages", required_argument, 0, 's'},
114 {"rx-mask", required_argument, 0, 'r'},
115 {"tx-mask", required_argument, 0, 't'},
116 {"sched-mask", required_argument, 0, 'e'},
117 {"cq-depth", required_argument, 0, 'c'},
118 {"work-cycles", required_argument, 0, 'W'},
119 {"queue-priority", no_argument, 0, 'P'},
120 {"parallel", no_argument, 0, 'p'},
121 {"ordered", no_argument, 0, 'o'},
122 {"quiet", no_argument, 0, 'q'},
123 {"use-atq", no_argument, 0, 'a'},
124 {"dump", no_argument, 0, 'D'},
131 const char *usage_str =
132 " Usage: eventdev_demo [options]\n"
134 " -n, --packets=N Send N packets (default ~32M), 0 implies no limit\n"
135 " -f, --atomic-flows=N Use N random flows from 1 to N (default 16)\n"
136 " -s, --num_stages=N Use N atomic stages (default 1)\n"
137 " -r, --rx-mask=core mask Run NIC rx on CPUs in core mask\n"
138 " -w, --worker-mask=core mask Run worker on CPUs in core mask\n"
139 " -t, --tx-mask=core mask Run NIC tx on CPUs in core mask\n"
140 " -e --sched-mask=core mask Run scheduler on CPUs in core mask\n"
141 " -c --cq-depth=N Worker CQ depth (default 16)\n"
142 " -W --work-cycles=N Worker cycles (default 0)\n"
143 " -P --queue-priority Enable scheduler queue prioritization\n"
144 " -o, --ordered Use ordered scheduling\n"
145 " -p, --parallel Use parallel scheduling\n"
146 " -q, --quiet Minimize printed output\n"
147 " -a, --use-atq Use all type queues\n"
148 " -D, --dump Print detailed statistics before exit"
150 fprintf(stderr, "%s", usage_str);
155 parse_app_args(int argc, char **argv)
157 /* Parse cli options*/
161 uint64_t rx_lcore_mask = 0;
162 uint64_t tx_lcore_mask = 0;
163 uint64_t sched_lcore_mask = 0;
164 uint64_t worker_lcore_mask = 0;
168 c = getopt_long(argc, argv, "r:t:e:c:w:n:f:s:paoPqDW:",
169 long_options, &option_index);
176 cdata.num_packets = (int64_t)atol(optarg);
177 if (cdata.num_packets == 0)
178 cdata.num_packets = INT64_MAX;
181 cdata.num_fids = (unsigned int)atoi(optarg);
184 cdata.num_stages = (unsigned int)atoi(optarg);
187 cdata.worker_cq_depth = (unsigned int)atoi(optarg);
190 cdata.worker_cycles = (unsigned int)atoi(optarg);
193 cdata.enable_queue_priorities = 1;
196 cdata.queue_type = RTE_SCHED_TYPE_ORDERED;
199 cdata.queue_type = RTE_SCHED_TYPE_PARALLEL;
202 cdata.all_type_queues = 1;
211 worker_lcore_mask = parse_coremask(optarg);
214 rx_lcore_mask = parse_coremask(optarg);
215 popcnt = __builtin_popcountll(rx_lcore_mask);
216 fdata->rx_single = (popcnt == 1);
219 tx_lcore_mask = parse_coremask(optarg);
220 popcnt = __builtin_popcountll(tx_lcore_mask);
221 fdata->tx_single = (popcnt == 1);
224 sched_lcore_mask = parse_coremask(optarg);
225 popcnt = __builtin_popcountll(sched_lcore_mask);
226 fdata->sched_single = (popcnt == 1);
233 cdata.worker_lcore_mask = worker_lcore_mask;
234 cdata.sched_lcore_mask = sched_lcore_mask;
235 cdata.rx_lcore_mask = rx_lcore_mask;
236 cdata.tx_lcore_mask = tx_lcore_mask;
238 if (cdata.num_stages == 0 || cdata.num_stages > MAX_NUM_STAGES)
241 for (i = 0; i < MAX_NUM_CORE; i++) {
242 fdata->rx_core[i] = !!(rx_lcore_mask & (1UL << i));
243 fdata->tx_core[i] = !!(tx_lcore_mask & (1UL << i));
244 fdata->sched_core[i] = !!(sched_lcore_mask & (1UL << i));
245 fdata->worker_core[i] = !!(worker_lcore_mask & (1UL << i));
247 if (fdata->worker_core[i])
250 cdata.active_cores++;
255 * Initializes a given port using global settings and with the RX buffers
256 * coming from the mbuf_pool passed as a parameter.
259 port_init(uint8_t port, struct rte_mempool *mbuf_pool)
261 static const struct rte_eth_conf port_conf_default = {
263 .mq_mode = ETH_MQ_RX_RSS,
264 .max_rx_pkt_len = ETHER_MAX_LEN,
265 .ignore_offload_bitfield = 1,
269 .rss_hf = ETH_RSS_IP |
275 const uint16_t rx_rings = 1, tx_rings = 1;
276 const uint16_t rx_ring_size = 512, tx_ring_size = 512;
277 struct rte_eth_conf port_conf = port_conf_default;
280 struct rte_eth_dev_info dev_info;
281 struct rte_eth_txconf txconf;
283 if (port >= rte_eth_dev_count())
286 rte_eth_dev_info_get(port, &dev_info);
287 if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_MBUF_FAST_FREE)
288 port_conf.txmode.offloads |=
289 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
291 /* Configure the Ethernet device. */
292 retval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf);
296 /* Allocate and set up 1 RX queue per Ethernet port. */
297 for (q = 0; q < rx_rings; q++) {
298 retval = rte_eth_rx_queue_setup(port, q, rx_ring_size,
299 rte_eth_dev_socket_id(port), NULL, mbuf_pool);
304 txconf = dev_info.default_txconf;
305 txconf.txq_flags = ETH_TXQ_FLAGS_IGNORE;
306 txconf.offloads = port_conf_default.txmode.offloads;
307 /* Allocate and set up 1 TX queue per Ethernet port. */
308 for (q = 0; q < tx_rings; q++) {
309 retval = rte_eth_tx_queue_setup(port, q, tx_ring_size,
310 rte_eth_dev_socket_id(port), &txconf);
315 /* Start the Ethernet port. */
316 retval = rte_eth_dev_start(port);
320 /* Display the port MAC address. */
321 struct ether_addr addr;
322 rte_eth_macaddr_get(port, &addr);
323 printf("Port %u MAC: %02" PRIx8 " %02" PRIx8 " %02" PRIx8
324 " %02" PRIx8 " %02" PRIx8 " %02" PRIx8 "\n",
326 addr.addr_bytes[0], addr.addr_bytes[1],
327 addr.addr_bytes[2], addr.addr_bytes[3],
328 addr.addr_bytes[4], addr.addr_bytes[5]);
330 /* Enable RX in promiscuous mode for the Ethernet device. */
331 rte_eth_promiscuous_enable(port);
337 init_ports(unsigned int num_ports)
342 struct rte_mempool *mp = rte_pktmbuf_pool_create("packet_pool",
343 /* mbufs */ 16384 * num_ports,
344 /* cache_size */ 512,
346 /* data_room_size */ RTE_MBUF_DEFAULT_BUF_SIZE,
349 for (portid = 0; portid < num_ports; portid++)
350 if (port_init(portid, mp) != 0)
351 rte_exit(EXIT_FAILURE, "Cannot init port %"PRIu8 "\n",
354 for (i = 0; i < num_ports; i++) {
355 void *userdata = (void *)(uintptr_t) i;
357 rte_malloc(NULL, RTE_ETH_TX_BUFFER_SIZE(32), 0);
358 if (fdata->tx_buf[i] == NULL)
359 rte_panic("Out of memory\n");
360 rte_eth_tx_buffer_init(fdata->tx_buf[i], 32);
361 rte_eth_tx_buffer_set_err_callback(fdata->tx_buf[i],
370 do_capability_setup(uint16_t nb_ethdev, uint8_t eventdev_id)
373 uint8_t mt_unsafe = 0;
376 for (i = 0; i < nb_ethdev; i++) {
377 struct rte_eth_dev_info dev_info;
378 memset(&dev_info, 0, sizeof(struct rte_eth_dev_info));
380 rte_eth_dev_info_get(i, &dev_info);
381 /* Check if it is safe ask worker to tx. */
382 mt_unsafe |= !(dev_info.tx_offload_capa &
383 DEV_TX_OFFLOAD_MT_LOCKFREE);
386 struct rte_event_dev_info eventdev_info;
387 memset(&eventdev_info, 0, sizeof(struct rte_event_dev_info));
389 rte_event_dev_info_get(eventdev_id, &eventdev_info);
390 burst = eventdev_info.event_dev_cap & RTE_EVENT_DEV_CAP_BURST_MODE ? 1 :
394 set_worker_generic_setup_data(&fdata->cap, burst);
396 set_worker_tx_setup_data(&fdata->cap, burst);
400 signal_handler(int signum)
403 rte_exit(1, "Exiting on signal %d\n", signum);
404 if (signum == SIGINT || signum == SIGTERM) {
405 printf("\n\nSignal %d received, preparing to exit...\n",
409 if (signum == SIGTSTP)
410 rte_event_dev_dump(0, stdout);
413 static inline uint64_t
414 port_stat(int dev_id, int32_t p)
417 snprintf(statname, sizeof(statname), "port_%u_rx", p);
418 return rte_event_dev_xstats_by_name_get(dev_id, statname, NULL);
422 main(int argc, char **argv)
424 struct worker_data *worker_data;
425 unsigned int num_ports;
429 signal(SIGINT, signal_handler);
430 signal(SIGTERM, signal_handler);
431 signal(SIGTSTP, signal_handler);
433 err = rte_eal_init(argc, argv);
435 rte_panic("Invalid EAL arguments\n");
440 fdata = rte_malloc(NULL, sizeof(struct fastpath_data), 0);
442 rte_panic("Out of memory\n");
444 /* Parse cli options*/
445 parse_app_args(argc, argv);
447 num_ports = rte_eth_dev_count();
449 rte_panic("No ethernet ports found\n");
451 const unsigned int cores_needed = cdata.active_cores;
454 printf(" Config:\n");
455 printf("\tports: %u\n", num_ports);
456 printf("\tworkers: %u\n", cdata.num_workers);
457 printf("\tpackets: %"PRIi64"\n", cdata.num_packets);
458 printf("\tQueue-prio: %u\n", cdata.enable_queue_priorities);
459 if (cdata.queue_type == RTE_SCHED_TYPE_ORDERED)
460 printf("\tqid0 type: ordered\n");
461 if (cdata.queue_type == RTE_SCHED_TYPE_ATOMIC)
462 printf("\tqid0 type: atomic\n");
463 printf("\tCores available: %u\n", rte_lcore_count());
464 printf("\tCores used: %u\n", cores_needed);
467 if (rte_lcore_count() < cores_needed)
468 rte_panic("Too few cores (%d < %d)\n", rte_lcore_count(),
471 const unsigned int ndevs = rte_event_dev_count();
473 rte_panic("No dev_id devs found. Pasl in a --vdev eventdev.\n");
475 fprintf(stderr, "Warning: More than one eventdev, using idx 0");
478 do_capability_setup(num_ports, 0);
479 fdata->cap.check_opt();
481 worker_data = rte_calloc(0, cdata.num_workers,
482 sizeof(worker_data[0]), 0);
483 if (worker_data == NULL)
484 rte_panic("rte_calloc failed\n");
486 int dev_id = fdata->cap.evdev_setup(&cons_data, worker_data);
488 rte_exit(EXIT_FAILURE, "Error setting up eventdev\n");
490 init_ports(num_ports);
491 fdata->cap.adptr_setup(num_ports);
494 RTE_LCORE_FOREACH_SLAVE(lcore_id) {
495 if (lcore_id >= MAX_NUM_CORE)
498 if (!fdata->rx_core[lcore_id] &&
499 !fdata->worker_core[lcore_id] &&
500 !fdata->tx_core[lcore_id] &&
501 !fdata->sched_core[lcore_id])
504 if (fdata->rx_core[lcore_id])
506 "[%s()] lcore %d executing NIC Rx\n",
509 if (fdata->tx_core[lcore_id])
511 "[%s()] lcore %d executing NIC Tx, and using eventdev port %u\n",
512 __func__, lcore_id, cons_data.port_id);
514 if (fdata->sched_core[lcore_id])
515 printf("[%s()] lcore %d executing scheduler\n",
518 if (fdata->worker_core[lcore_id])
520 "[%s()] lcore %d executing worker, using eventdev port %u\n",
522 worker_data[worker_idx].port_id);
524 err = rte_eal_remote_launch(fdata->cap.worker,
525 &worker_data[worker_idx], lcore_id);
527 rte_panic("Failed to launch worker on core %d\n",
531 if (fdata->worker_core[lcore_id])
535 lcore_id = rte_lcore_id();
537 if (core_in_use(lcore_id))
538 fdata->cap.worker(&worker_data[worker_idx++]);
540 rte_eal_mp_wait_lcore();
543 rte_event_dev_dump(dev_id, stdout);
545 if (!cdata.quiet && (port_stat(dev_id, worker_data[0].port_id) !=
546 (uint64_t)-ENOTSUP)) {
547 printf("\nPort Workload distribution:\n");
549 uint64_t tot_pkts = 0;
550 uint64_t pkts_per_wkr[RTE_MAX_LCORE] = {0};
551 for (i = 0; i < cdata.num_workers; i++) {
553 port_stat(dev_id, worker_data[i].port_id);
554 tot_pkts += pkts_per_wkr[i];
556 for (i = 0; i < cdata.num_workers; i++) {
557 float pc = pkts_per_wkr[i] * 100 /
559 printf("worker %i :\t%.1f %% (%"PRIu64" pkts)\n",
560 i, pc, pkts_per_wkr[i]);