4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 * Inspired from FreeBSD src/sys/i386/include/atomic.h
36 * Copyright (c) 1998 Doug Rabson
37 * All rights reserved.
40 #ifndef _RTE_ATOMIC_I686_H_
41 #define _RTE_ATOMIC_I686_H_
47 #include <emmintrin.h>
48 #include "generic/rte_atomic.h"
50 #if RTE_MAX_LCORE == 1
51 #define MPLOCKED /**< No need to insert MP lock prefix. */
53 #define MPLOCKED "lock ; " /**< Insert MP lock prefix. */
56 #define rte_mb() _mm_mfence()
58 #define rte_wmb() _mm_sfence()
60 #define rte_rmb() _mm_lfence()
62 /*------------------------- 16 bit atomic operations -------------------------*/
64 #ifndef RTE_FORCE_INTRINSICS
66 rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
72 "cmpxchgw %[src], %[dst];"
74 : [res] "=a" (res), /* output */
76 : [src] "r" (src), /* input */
79 : "memory"); /* no-clobber list */
83 static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
85 return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
89 rte_atomic16_inc(rte_atomic16_t *v)
94 : [cnt] "=m" (v->cnt) /* output */
95 : "m" (v->cnt) /* input */
100 rte_atomic16_dec(rte_atomic16_t *v)
105 : [cnt] "=m" (v->cnt) /* output */
106 : "m" (v->cnt) /* input */
110 static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
118 : [cnt] "+m" (v->cnt), /* output */
124 static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
128 asm volatile(MPLOCKED
131 : [cnt] "+m" (v->cnt), /* output */
137 /*------------------------- 32 bit atomic operations -------------------------*/
140 rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
146 "cmpxchgl %[src], %[dst];"
148 : [res] "=a" (res), /* output */
150 : [src] "r" (src), /* input */
153 : "memory"); /* no-clobber list */
157 static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
159 return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
163 rte_atomic32_inc(rte_atomic32_t *v)
168 : [cnt] "=m" (v->cnt) /* output */
169 : "m" (v->cnt) /* input */
174 rte_atomic32_dec(rte_atomic32_t *v)
179 : [cnt] "=m" (v->cnt) /* output */
180 : "m" (v->cnt) /* input */
184 static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
192 : [cnt] "+m" (v->cnt), /* output */
198 static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
202 asm volatile(MPLOCKED
205 : [cnt] "+m" (v->cnt), /* output */
211 /*------------------------- 64 bit atomic operations -------------------------*/
214 rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
231 "cmpxchg8b (%[dst]);"
233 : [res] "=a" (res) /* result in eax */
234 : [dst] "S" (dst), /* esi */
235 "b" (_src.l32), /* ebx */
236 "c" (_src.h32), /* ecx */
237 "a" (_exp.l32), /* eax */
238 "d" (_exp.h32) /* edx */
239 : "memory" ); /* no-clobber list */
244 "cmpxchg8b (%[dst]);"
246 "xchgl %%ebx, %%edi;\n"
247 : [res] "=a" (res) /* result in eax */
248 : [dst] "S" (dst), /* esi */
249 "D" (_src.l32), /* ebx */
250 "c" (_src.h32), /* ecx */
251 "a" (_exp.l32), /* eax */
252 "d" (_exp.h32) /* edx */
253 : "memory" ); /* no-clobber list */
260 rte_atomic64_init(rte_atomic64_t *v)
265 while (success == 0) {
267 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
272 static inline int64_t
273 rte_atomic64_read(rte_atomic64_t *v)
278 while (success == 0) {
280 /* replace the value by itself */
281 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
288 rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
293 while (success == 0) {
295 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
301 rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
306 while (success == 0) {
308 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
314 rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
319 while (success == 0) {
321 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
327 rte_atomic64_inc(rte_atomic64_t *v)
329 rte_atomic64_add(v, 1);
333 rte_atomic64_dec(rte_atomic64_t *v)
335 rte_atomic64_sub(v, 1);
338 static inline int64_t
339 rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
344 while (success == 0) {
346 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
353 static inline int64_t
354 rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
359 while (success == 0) {
361 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
368 static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
370 return rte_atomic64_add_return(v, 1) == 0;
373 static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
375 return rte_atomic64_sub_return(v, 1) == 0;
378 static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
380 return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
383 static inline void rte_atomic64_clear(rte_atomic64_t *v)
385 rte_atomic64_set(v, 0);
393 #endif /* _RTE_ATOMIC_I686_H_ */