4 * Copyright (C) IBM Corporation 2014.
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7 * modification, are permitted provided that the following conditions
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14 * the documentation and/or other materials provided with the
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18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * Inspired from FreeBSD src/sys/powerpc/include/atomic.h
35 * Copyright (c) 2008 Marcel Moolenaar
36 * Copyright (c) 2001 Benno Rice
37 * Copyright (c) 2001 David E. O'Brien
38 * Copyright (c) 1998 Doug Rabson
39 * All rights reserved.
42 #ifndef _RTE_ATOMIC_PPC_64_H_
43 #define _RTE_ATOMIC_PPC_64_H_
50 #include "generic/rte_atomic.h"
52 #define rte_mb() asm volatile("sync" : : : "memory")
54 #define rte_wmb() asm volatile("sync" : : : "memory")
56 #define rte_rmb() asm volatile("sync" : : : "memory")
58 #define rte_smp_mb() rte_mb()
60 #define rte_smp_wmb() rte_wmb()
62 #define rte_smp_rmb() rte_rmb()
64 #define rte_io_mb() rte_mb()
66 #define rte_io_wmb() rte_wmb()
68 #define rte_io_rmb() rte_rmb()
70 #define rte_cio_wmb() rte_wmb()
72 #define rte_cio_rmb() rte_rmb()
74 /*------------------------- 16 bit atomic operations -------------------------*/
75 /* To be compatible with Power7, use GCC built-in functions for 16 bit
78 #ifndef RTE_FORCE_INTRINSICS
80 rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
82 return __atomic_compare_exchange(dst, &exp, &src, 0, __ATOMIC_ACQUIRE,
83 __ATOMIC_ACQUIRE) ? 1 : 0;
86 static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
88 return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
92 rte_atomic16_inc(rte_atomic16_t *v)
94 __atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);
98 rte_atomic16_dec(rte_atomic16_t *v)
100 __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);
103 static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
105 return __atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0;
108 static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
110 return __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0;
113 static inline uint16_t
114 rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
116 return __atomic_exchange_2(dst, val, __ATOMIC_SEQ_CST);
119 /*------------------------- 32 bit atomic operations -------------------------*/
122 rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
124 unsigned int ret = 0;
128 "1:\tlwarx %[ret], 0, %[dst]\n"
129 "cmplw %[exp], %[ret]\n"
131 "stwcx. %[src], 0, %[dst]\n"
136 "stwcx. %[ret], 0, %[dst]\n"
140 : [ret] "=&r" (ret), "=m" (*dst)
150 static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
152 return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
156 rte_atomic32_inc(rte_atomic32_t *v)
161 "1: lwarx %[t],0,%[cnt]\n"
162 "addic %[t],%[t],1\n"
163 "stwcx. %[t],0,%[cnt]\n"
165 : [t] "=&r" (t), "=m" (v->cnt)
166 : [cnt] "r" (&v->cnt), "m" (v->cnt)
167 : "cc", "xer", "memory");
171 rte_atomic32_dec(rte_atomic32_t *v)
176 "1: lwarx %[t],0,%[cnt]\n"
177 "addic %[t],%[t],-1\n"
178 "stwcx. %[t],0,%[cnt]\n"
180 : [t] "=&r" (t), "=m" (v->cnt)
181 : [cnt] "r" (&v->cnt), "m" (v->cnt)
182 : "cc", "xer", "memory");
185 static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
191 "1: lwarx %[ret],0,%[cnt]\n"
192 "addic %[ret],%[ret],1\n"
193 "stwcx. %[ret],0,%[cnt]\n"
197 : [cnt] "r" (&v->cnt)
198 : "cc", "xer", "memory");
203 static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
209 "1: lwarx %[ret],0,%[cnt]\n"
210 "addic %[ret],%[ret],-1\n"
211 "stwcx. %[ret],0,%[cnt]\n"
215 : [cnt] "r" (&v->cnt)
216 : "cc", "xer", "memory");
221 static inline uint32_t
222 rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
224 return __atomic_exchange_4(dst, val, __ATOMIC_SEQ_CST);
227 /*------------------------- 64 bit atomic operations -------------------------*/
230 rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
232 unsigned int ret = 0;
236 "1: ldarx %[ret], 0, %[dst]\n"
237 "cmpld %[exp], %[ret]\n"
239 "stdcx. %[src], 0, %[dst]\n"
244 "stdcx. %[ret], 0, %[dst]\n"
248 : [ret] "=&r" (ret), "=m" (*dst)
258 rte_atomic64_init(rte_atomic64_t *v)
263 static inline int64_t
264 rte_atomic64_read(rte_atomic64_t *v)
268 asm volatile("ld%U1%X1 %[ret],%[cnt]"
270 : [cnt] "m"(v->cnt));
276 rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
278 asm volatile("std%U0%X0 %[new_value],%[cnt]"
280 : [new_value] "r"(new_value));
284 rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
289 "1: ldarx %[t],0,%[cnt]\n"
290 "add %[t],%[inc],%[t]\n"
291 "stdcx. %[t],0,%[cnt]\n"
293 : [t] "=&r" (t), "=m" (v->cnt)
294 : [cnt] "r" (&v->cnt), [inc] "r" (inc), "m" (v->cnt)
299 rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
304 "1: ldarx %[t],0,%[cnt]\n"
305 "subf %[t],%[dec],%[t]\n"
306 "stdcx. %[t],0,%[cnt]\n"
308 : [t] "=&r" (t), "+m" (v->cnt)
309 : [cnt] "r" (&v->cnt), [dec] "r" (dec), "m" (v->cnt)
314 rte_atomic64_inc(rte_atomic64_t *v)
319 "1: ldarx %[t],0,%[cnt]\n"
320 "addic %[t],%[t],1\n"
321 "stdcx. %[t],0,%[cnt]\n"
323 : [t] "=&r" (t), "+m" (v->cnt)
324 : [cnt] "r" (&v->cnt), "m" (v->cnt)
325 : "cc", "xer", "memory");
329 rte_atomic64_dec(rte_atomic64_t *v)
334 "1: ldarx %[t],0,%[cnt]\n"
335 "addic %[t],%[t],-1\n"
336 "stdcx. %[t],0,%[cnt]\n"
338 : [t] "=&r" (t), "+m" (v->cnt)
339 : [cnt] "r" (&v->cnt), "m" (v->cnt)
340 : "cc", "xer", "memory");
343 static inline int64_t
344 rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
350 "1: ldarx %[ret],0,%[cnt]\n"
351 "add %[ret],%[inc],%[ret]\n"
352 "stdcx. %[ret],0,%[cnt]\n"
356 : [inc] "r" (inc), [cnt] "r" (&v->cnt)
362 static inline int64_t
363 rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
369 "1: ldarx %[ret],0,%[cnt]\n"
370 "subf %[ret],%[dec],%[ret]\n"
371 "stdcx. %[ret],0,%[cnt]\n"
375 : [dec] "r" (dec), [cnt] "r" (&v->cnt)
381 static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
387 "1: ldarx %[ret],0,%[cnt]\n"
388 "addic %[ret],%[ret],1\n"
389 "stdcx. %[ret],0,%[cnt]\n"
393 : [cnt] "r" (&v->cnt)
394 : "cc", "xer", "memory");
399 static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
405 "1: ldarx %[ret],0,%[cnt]\n"
406 "addic %[ret],%[ret],-1\n"
407 "stdcx. %[ret],0,%[cnt]\n"
411 : [cnt] "r" (&v->cnt)
412 : "cc", "xer", "memory");
417 static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
419 return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
422 * Atomically set a 64-bit counter to 0.
425 * A pointer to the atomic counter.
427 static inline void rte_atomic64_clear(rte_atomic64_t *v)
432 static inline uint64_t
433 rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
435 return __atomic_exchange_4(dst, val, __ATOMIC_SEQ_CST);
444 #endif /* _RTE_ATOMIC_PPC_64_H_ */