lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_82575.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /*
  29  * 82575EB Gigabit Network Connection
  30  * 82575EB Gigabit Backplane Connection
  31  * 82575GB Gigabit Network Connection
  32  * 82576 Gigabit Network Connection
  33  * 82576 Quad Port Gigabit Mezzanine Adapter
  34  */
  35
  36 #include "e1000_api.h"
  37
  38 static s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  39 static s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  40 static s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  41 static void e1000_release_phy_82575(struct e1000_hw *hw);
  42 static s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  43 static void e1000_release_nvm_82575(struct e1000_hw *hw);
  44 static s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  45 static s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  46 static s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  47                                          u16 *duplex);
  48 static s32  e1000_init_hw_82575(struct e1000_hw *hw);
  49 static s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  50 static s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  51                                            u16 *data);
  52 static s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  53 static s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  54 static s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  55                                      u32 offset, u16 *data);
  56 static s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  57                                       u32 offset, u16 data);
  58 static s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  59                                           bool active);
  60 static s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  61                                           bool active);
  62 static s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  63                                           bool active);
  64 static s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  65 static s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  66 static s32  e1000_get_media_type_82575(struct e1000_hw *hw);
  67 static s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
  68 static s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  69 static s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  70                                             u32 offset, u16 data);
  71 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  72 static s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  73 static s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  74                                                  u16 *speed, u16 *duplex);
  75 static s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  76 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  77 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  78 static s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  79 static s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  80 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  81 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  82 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  83 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  84 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  85 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  86 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  87 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  88 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
  89                                                  u16 offset);
  90 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
  91                                                    u16 offset);
  92 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
  93 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
  94 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
  95 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
  96
  97 static void e1000_i2c_start(struct e1000_hw *hw);
  98 static void e1000_i2c_stop(struct e1000_hw *hw);
  99 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
 100 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
 101 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
 102 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
 103 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
 104 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 105 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 106 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
 107 static bool e1000_get_i2c_data(u32 *i2cctl);
 108
 109 static const u16 e1000_82580_rxpbs_table[] = {
 110         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
 111 #define E1000_82580_RXPBS_TABLE_SIZE \
 112         (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
 113
 114
 115 /**
 116  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 117  *  @hw: pointer to the HW structure
 118  *
 119  *  Called to determine if the I2C pins are being used for I2C or as an
 120  *  external MDIO interface since the two options are mutually exclusive.
 121  **/
 122 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 123 {
 124         u32 reg = 0;
 125         bool ext_mdio = false;
 126
 127         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 128
 129         switch (hw->mac.type) {
 130         case e1000_82575:
 131         case e1000_82576:
 132                 reg = E1000_READ_REG(hw, E1000_MDIC);
 133                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 134                 break;
 135         case e1000_82580:
 136         case e1000_i350:
 137                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 138                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 139                 break;
 140         default:
 141                 break;
 142         }
 143         return ext_mdio;
 144 }
 145
 146 /**
 147  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 148  *  @hw: pointer to the HW structure
 149  **/
 150 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 151 {
 152         struct e1000_phy_info *phy = &hw->phy;
 153         s32 ret_val = E1000_SUCCESS;
 154         u32 ctrl_ext;
 155
 156         DEBUGFUNC("e1000_init_phy_params_82575");
 157
 158         phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
 159         phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 160
 161         if (hw->phy.media_type != e1000_media_type_copper) {
 162                 phy->type = e1000_phy_none;
 163                 goto out;
 164         }
 165
 166         phy->ops.power_up   = e1000_power_up_phy_copper;
 167         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 168
 169         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 170         phy->reset_delay_us     = 100;
 171
 172         phy->ops.acquire        = e1000_acquire_phy_82575;
 173         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 174         phy->ops.commit         = e1000_phy_sw_reset_generic;
 175         phy->ops.get_cfg_done   = e1000_get_cfg_done_82575;
 176         phy->ops.release        = e1000_release_phy_82575;
 177
 178         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 179
 180         if (e1000_sgmii_active_82575(hw)) {
 181                 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 182                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 183         } else {
 184                 phy->ops.reset = e1000_phy_hw_reset_generic;
 185                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 186         }
 187
 188         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 189         e1000_reset_mdicnfg_82580(hw);
 190
 191         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 192                 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
 193                 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 194         } else {
 195                 switch (hw->mac.type) {
 196                 case e1000_82580:
 197                 case e1000_i350:
 198                         phy->ops.read_reg = e1000_read_phy_reg_82580;
 199                         phy->ops.write_reg = e1000_write_phy_reg_82580;
 200                         break;
 201                 default:
 202                         phy->ops.read_reg = e1000_read_phy_reg_igp;
 203                         phy->ops.write_reg = e1000_write_phy_reg_igp;
 204                 }
 205         }
 206
 207         /* Set phy->phy_addr and phy->id. */
 208         ret_val = e1000_get_phy_id_82575(hw);
 209
 210         /* Verify phy id and set remaining function pointers */
 211         switch (phy->id) {
 212         case I347AT4_E_PHY_ID:
 213         case M88E1112_E_PHY_ID:
 214         case M88E1340M_E_PHY_ID:
 215         case M88E1111_I_PHY_ID:
 216                 phy->type               = e1000_phy_m88;
 217                 phy->ops.check_polarity = e1000_check_polarity_m88;
 218                 phy->ops.get_info       = e1000_get_phy_info_m88;
 219                 if (phy->id == I347AT4_E_PHY_ID ||
 220                     phy->id == M88E1112_E_PHY_ID ||
 221                     phy->id == M88E1340M_E_PHY_ID)
 222                         phy->ops.get_cable_length =
 223                                          e1000_get_cable_length_m88_gen2;
 224                 else
 225                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 226                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 227                 break;
 228         case IGP03E1000_E_PHY_ID:
 229         case IGP04E1000_E_PHY_ID:
 230                 phy->type = e1000_phy_igp_3;
 231                 phy->ops.check_polarity = e1000_check_polarity_igp;
 232                 phy->ops.get_info = e1000_get_phy_info_igp;
 233                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 234                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 235                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
 236                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 237                 break;
 238         case I82580_I_PHY_ID:
 239         case I350_I_PHY_ID:
 240                 phy->type = e1000_phy_82580;
 241                 phy->ops.check_polarity = e1000_check_polarity_82577;
 242                 phy->ops.force_speed_duplex =
 243                                          e1000_phy_force_speed_duplex_82577;
 244                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 245                 phy->ops.get_info = e1000_get_phy_info_82577;
 246                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 247                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 248                 break;
 249         default:
 250                 ret_val = -E1000_ERR_PHY;
 251                 goto out;
 252         }
 253
 254 out:
 255         return ret_val;
 256 }
 257
 258 /**
 259  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 260  *  @hw: pointer to the HW structure
 261  **/
 262 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 263 {
 264         struct e1000_nvm_info *nvm = &hw->nvm;
 265         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 266         u16 size;
 267
 268         DEBUGFUNC("e1000_init_nvm_params_82575");
 269
 270         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 271                      E1000_EECD_SIZE_EX_SHIFT);
 272         /*
 273          * Added to a constant, "size" becomes the left-shift value
 274          * for setting word_size.
 275          */
 276         size += NVM_WORD_SIZE_BASE_SHIFT;
 277
 278         /* Just in case size is out of range, cap it to the largest
 279          * EEPROM size supported
 280          */
 281         if (size > 15)
 282                 size = 15;
 283
 284         nvm->word_size = 1 << size;
 285         nvm->opcode_bits = 8;
 286         nvm->delay_usec = 1;
 287         switch (nvm->override) {
 288         case e1000_nvm_override_spi_large:
 289                 nvm->page_size = 32;
 290                 nvm->address_bits = 16;
 291                 break;
 292         case e1000_nvm_override_spi_small:
 293                 nvm->page_size = 8;
 294                 nvm->address_bits = 8;
 295                 break;
 296         default:
 297                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 298                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 299                 break;
 300         }
 301
 302         nvm->type = e1000_nvm_eeprom_spi;
 303
 304         if (nvm->word_size == (1 << 15))
 305                 nvm->page_size = 128;
 306
 307         /* Function Pointers */
 308         nvm->ops.acquire = e1000_acquire_nvm_82575;
 309         nvm->ops.release = e1000_release_nvm_82575;
 310         if (nvm->word_size < (1 << 15))
 311                 nvm->ops.read = e1000_read_nvm_eerd;
 312         else
 313                 nvm->ops.read = e1000_read_nvm_spi;
 314
 315         nvm->ops.write = e1000_write_nvm_spi;
 316         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 317         nvm->ops.update = e1000_update_nvm_checksum_generic;
 318         nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 319
 320         /* override generic family function pointers for specific descendants */
 321         switch (hw->mac.type) {
 322         case e1000_82580:
 323                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 324                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 325                 break;
 326         case e1000_i350:
 327                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 328                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 329                 break;
 330         default:
 331                 break;
 332         }
 333
 334         return E1000_SUCCESS;
 335 }
 336
 337 /**
 338  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 339  *  @hw: pointer to the HW structure
 340  **/
 341 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 342 {
 343         struct e1000_mac_info *mac = &hw->mac;
 344         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 345
 346         DEBUGFUNC("e1000_init_mac_params_82575");
 347
 348         /* Derives media type */
 349         e1000_get_media_type_82575(hw);
 350         /* Set mta register count */
 351         mac->mta_reg_count = 128;
 352         /* Set uta register count */
 353         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 354         /* Set rar entry count */
 355         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 356         if (mac->type == e1000_82576)
 357                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 358         if (mac->type == e1000_82580)
 359                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 360         if (mac->type == e1000_i350) {
 361                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 362                 /* Enable EEE default settings for i350 */
 363                 dev_spec->eee_disable = false;
 364         }
 365
 366         /* Set if part includes ASF firmware */
 367         mac->asf_firmware_present = true;
 368         /* FWSM register */
 369         mac->has_fwsm = true;
 370         /* ARC supported; valid only if manageability features are enabled. */
 371         mac->arc_subsystem_valid =
 372                 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
 373
 374         /* Function pointers */
 375
 376         /* bus type/speed/width */
 377         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 378         /* reset */
 379         if (mac->type >= e1000_82580)
 380                 mac->ops.reset_hw = e1000_reset_hw_82580;
 381         else
 382         mac->ops.reset_hw = e1000_reset_hw_82575;
 383         /* hw initialization */
 384         mac->ops.init_hw = e1000_init_hw_82575;
 385         /* link setup */
 386         mac->ops.setup_link = e1000_setup_link_generic;
 387         /* physical interface link setup */
 388         mac->ops.setup_physical_interface =
 389                 (hw->phy.media_type == e1000_media_type_copper)
 390                 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 391         /* physical interface shutdown */
 392         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 393         /* physical interface power up */
 394         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 395         /* check for link */
 396         mac->ops.check_for_link = e1000_check_for_link_82575;
 397         /* receive address register setting */
 398         mac->ops.rar_set = e1000_rar_set_generic;
 399         /* read mac address */
 400         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 401         /* configure collision distance */
 402         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 403         /* multicast address update */
 404         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 405         if (hw->mac.type == e1000_i350) {
 406                 /* writing VFTA */
 407                 mac->ops.write_vfta = e1000_write_vfta_i350;
 408                 /* clearing VFTA */
 409                 mac->ops.clear_vfta = e1000_clear_vfta_i350;
 410         } else {
 411                 /* writing VFTA */
 412                 mac->ops.write_vfta = e1000_write_vfta_generic;
 413                 /* clearing VFTA */
 414                 mac->ops.clear_vfta = e1000_clear_vfta_generic;
 415         }
 416         /* ID LED init */
 417         mac->ops.id_led_init = e1000_id_led_init_generic;
 418         /* blink LED */
 419         mac->ops.blink_led = e1000_blink_led_generic;
 420         /* setup LED */
 421         mac->ops.setup_led = e1000_setup_led_generic;
 422         /* cleanup LED */
 423         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 424         /* turn on/off LED */
 425         mac->ops.led_on = e1000_led_on_generic;
 426         mac->ops.led_off = e1000_led_off_generic;
 427         /* clear hardware counters */
 428         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 429         /* link info */
 430         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 431         /* get thermal sensor data */
 432         mac->ops.get_thermal_sensor_data =
 433                                 e1000_get_thermal_sensor_data_generic;
 434         mac->ops.init_thermal_sensor_thresh =
 435                                 e1000_init_thermal_sensor_thresh_generic;
 436         /* acquire SW_FW sync */
 437         mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
 438         mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
 439
 440         /* set lan id for port to determine which phy lock to use */
 441         hw->mac.ops.set_lan_id(hw);
 442
 443         return E1000_SUCCESS;
 444 }
 445
 446 /**
 447  *  e1000_init_function_pointers_82575 - Init func ptrs.
 448  *  @hw: pointer to the HW structure
 449  *
 450  *  Called to initialize all function pointers and parameters.
 451  **/
 452 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 453 {
 454         DEBUGFUNC("e1000_init_function_pointers_82575");
 455
 456         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 457         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 458         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 459         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 460 }
 461
 462 /**
 463  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 464  *  @hw: pointer to the HW structure
 465  *
 466  *  Acquire access rights to the correct PHY.
 467  **/
 468 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 469 {
 470         u16 mask = E1000_SWFW_PHY0_SM;
 471
 472         DEBUGFUNC("e1000_acquire_phy_82575");
 473
 474         if (hw->bus.func == E1000_FUNC_1)
 475                 mask = E1000_SWFW_PHY1_SM;
 476         else if (hw->bus.func == E1000_FUNC_2)
 477                 mask = E1000_SWFW_PHY2_SM;
 478         else if (hw->bus.func == E1000_FUNC_3)
 479                 mask = E1000_SWFW_PHY3_SM;
 480
 481         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 482 }
 483
 484 /**
 485  *  e1000_release_phy_82575 - Release rights to access PHY
 486  *  @hw: pointer to the HW structure
 487  *
 488  *  A wrapper to release access rights to the correct PHY.
 489  **/
 490 static void e1000_release_phy_82575(struct e1000_hw *hw)
 491 {
 492         u16 mask = E1000_SWFW_PHY0_SM;
 493
 494         DEBUGFUNC("e1000_release_phy_82575");
 495
 496         if (hw->bus.func == E1000_FUNC_1)
 497                 mask = E1000_SWFW_PHY1_SM;
 498         else if (hw->bus.func == E1000_FUNC_2)
 499                 mask = E1000_SWFW_PHY2_SM;
 500         else if (hw->bus.func == E1000_FUNC_3)
 501                 mask = E1000_SWFW_PHY3_SM;
 502
 503         hw->mac.ops.release_swfw_sync(hw, mask);
 504 }
 505
 506 /**
 507  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 508  *  @hw: pointer to the HW structure
 509  *  @offset: register offset to be read
 510  *  @data: pointer to the read data
 511  *
 512  *  Reads the PHY register at offset using the serial gigabit media independent
 513  *  interface and stores the retrieved information in data.
 514  **/
 515 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 516                                           u16 *data)
 517 {
 518         s32 ret_val = -E1000_ERR_PARAM;
 519
 520         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 521
 522         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 523                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 524                 goto out;
 525         }
 526
 527         ret_val = hw->phy.ops.acquire(hw);
 528         if (ret_val)
 529                 goto out;
 530
 531         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 532
 533         hw->phy.ops.release(hw);
 534
 535 out:
 536         return ret_val;
 537 }
 538
 539 /**
 540  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 541  *  @hw: pointer to the HW structure
 542  *  @offset: register offset to write to
 543  *  @data: data to write at register offset
 544  *
 545  *  Writes the data to PHY register at the offset using the serial gigabit
 546  *  media independent interface.
 547  **/
 548 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 549                                            u16 data)
 550 {
 551         s32 ret_val = -E1000_ERR_PARAM;
 552
 553         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 554
 555         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 556                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 557                 goto out;
 558         }
 559
 560         ret_val = hw->phy.ops.acquire(hw);
 561         if (ret_val)
 562                 goto out;
 563
 564         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 565
 566         hw->phy.ops.release(hw);
 567
 568 out:
 569         return ret_val;
 570 }
 571
 572 /**
 573  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 574  *  @hw: pointer to the HW structure
 575  *
 576  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 577  *  sgmi interface.
 578  **/
 579 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 580 {
 581         struct e1000_phy_info *phy = &hw->phy;
 582         s32  ret_val = E1000_SUCCESS;
 583         u16 phy_id;
 584         u32 ctrl_ext;
 585         u32 mdic;
 586
 587         DEBUGFUNC("e1000_get_phy_id_82575");
 588
 589         /*
 590          * For SGMII PHYs, we try the list of possible addresses until
 591          * we find one that works.  For non-SGMII PHYs
 592          * (e.g. integrated copper PHYs), an address of 1 should
 593          * work.  The result of this function should mean phy->phy_addr
 594          * and phy->id are set correctly.
 595          */
 596         if (!e1000_sgmii_active_82575(hw)) {
 597                 phy->addr = 1;
 598                 ret_val = e1000_get_phy_id(hw);
 599                 goto out;
 600         }
 601
 602         if (e1000_sgmii_uses_mdio_82575(hw)) {
 603                 switch (hw->mac.type) {
 604                 case e1000_82575:
 605                 case e1000_82576:
 606                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 607                         mdic &= E1000_MDIC_PHY_MASK;
 608                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 609                         break;
 610                 case e1000_82580:
 611                 case e1000_i350:
 612                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 613                         mdic &= E1000_MDICNFG_PHY_MASK;
 614                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 615                         break;
 616                 default:
 617                         ret_val = -E1000_ERR_PHY;
 618                         goto out;
 619                         break;
 620                 }
 621                 ret_val = e1000_get_phy_id(hw);
 622                 goto out;
 623         }
 624
 625         /* Power on sgmii phy if it is disabled */
 626         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 627         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 628                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 629         E1000_WRITE_FLUSH(hw);
 630         msec_delay(300);
 631
 632         /*
 633          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 634          * Therefore, we need to test 1-7
 635          */
 636         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 637                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 638                 if (ret_val == E1000_SUCCESS) {
 639                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 640                                   phy_id, phy->addr);
 641                         /*
 642                          * At the time of this writing, The M88 part is
 643                          * the only supported SGMII PHY product.
 644                          */
 645                         if (phy_id == M88_VENDOR)
 646                                 break;
 647                 } else {
 648                         DEBUGOUT1("PHY address %u was unreadable\n",
 649                                   phy->addr);
 650                 }
 651         }
 652
 653         /* A valid PHY type couldn't be found. */
 654         if (phy->addr == 8) {
 655                 phy->addr = 0;
 656                 ret_val = -E1000_ERR_PHY;
 657         } else {
 658                 ret_val = e1000_get_phy_id(hw);
 659         }
 660
 661         /* restore previous sfp cage power state */
 662         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 663
 664 out:
 665         return ret_val;
 666 }
 667
 668 /**
 669  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 670  *  @hw: pointer to the HW structure
 671  *
 672  *  Resets the PHY using the serial gigabit media independent interface.
 673  **/
 674 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 675 {
 676         s32 ret_val = E1000_SUCCESS;
 677
 678         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 679
 680         /*
 681          * This isn't a true "hard" reset, but is the only reset
 682          * available to us at this time.
 683          */
 684
 685         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 686
 687         if (!(hw->phy.ops.write_reg))
 688                 goto out;
 689
 690         /*
 691          * SFP documentation requires the following to configure the SPF module
 692          * to work on SGMII.  No further documentation is given.
 693          */
 694         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 695         if (ret_val)
 696                 goto out;
 697
 698         ret_val = hw->phy.ops.commit(hw);
 699
 700 out:
 701         return ret_val;
 702 }
 703
 704 /**
 705  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 706  *  @hw: pointer to the HW structure
 707  *  @active: true to enable LPLU, false to disable
 708  *
 709  *  Sets the LPLU D0 state according to the active flag.  When
 710  *  activating LPLU this function also disables smart speed
 711  *  and vice versa.  LPLU will not be activated unless the
 712  *  device autonegotiation advertisement meets standards of
 713  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 714  *  This is a function pointer entry point only called by
 715  *  PHY setup routines.
 716  **/
 717 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 718 {
 719         struct e1000_phy_info *phy = &hw->phy;
 720         s32 ret_val = E1000_SUCCESS;
 721         u16 data;
 722
 723         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 724
 725         if (!(hw->phy.ops.read_reg))
 726                 goto out;
 727
 728         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 729         if (ret_val)
 730                 goto out;
 731
 732         if (active) {
 733                 data |= IGP02E1000_PM_D0_LPLU;
 734                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 735                                              data);
 736                 if (ret_val)
 737                         goto out;
 738
 739                 /* When LPLU is enabled, we should disable SmartSpeed */
 740                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 741                                             &data);
 742                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 743                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 744                                              data);
 745                 if (ret_val)
 746                         goto out;
 747         } else {
 748                 data &= ~IGP02E1000_PM_D0_LPLU;
 749                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 750                                              data);
 751                 /*
 752                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 753                  * during Dx states where the power conservation is most
 754                  * important.  During driver activity we should enable
 755                  * SmartSpeed, so performance is maintained.
 756                  */
 757                 if (phy->smart_speed == e1000_smart_speed_on) {
 758                         ret_val = phy->ops.read_reg(hw,
 759                                                     IGP01E1000_PHY_PORT_CONFIG,
 760                                                     &data);
 761                         if (ret_val)
 762                                 goto out;
 763
 764                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 765                         ret_val = phy->ops.write_reg(hw,
 766                                                      IGP01E1000_PHY_PORT_CONFIG,
 767                                                      data);
 768                         if (ret_val)
 769                                 goto out;
 770                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 771                         ret_val = phy->ops.read_reg(hw,
 772                                                     IGP01E1000_PHY_PORT_CONFIG,
 773                                                     &data);
 774                         if (ret_val)
 775                                 goto out;
 776
 777                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 778                         ret_val = phy->ops.write_reg(hw,
 779                                                      IGP01E1000_PHY_PORT_CONFIG,
 780                                                      data);
 781                         if (ret_val)
 782                                 goto out;
 783                 }
 784         }
 785
 786 out:
 787         return ret_val;
 788 }
 789
 790 /**
 791  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 792  *  @hw: pointer to the HW structure
 793  *  @active: true to enable LPLU, false to disable
 794  *
 795  *  Sets the LPLU D0 state according to the active flag.  When
 796  *  activating LPLU this function also disables smart speed
 797  *  and vice versa.  LPLU will not be activated unless the
 798  *  device autonegotiation advertisement meets standards of
 799  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 800  *  This is a function pointer entry point only called by
 801  *  PHY setup routines.
 802  **/
 803 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 804 {
 805         struct e1000_phy_info *phy = &hw->phy;
 806         s32 ret_val = E1000_SUCCESS;
 807         u16 data;
 808
 809         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 810
 811         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 812
 813         if (active) {
 814                 data |= E1000_82580_PM_D0_LPLU;
 815
 816                 /* When LPLU is enabled, we should disable SmartSpeed */
 817                 data &= ~E1000_82580_PM_SPD;
 818         } else {
 819                 data &= ~E1000_82580_PM_D0_LPLU;
 820
 821                 /*
 822                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 823                  * during Dx states where the power conservation is most
 824                  * important.  During driver activity we should enable
 825                  * SmartSpeed, so performance is maintained.
 826                  */
 827                 if (phy->smart_speed == e1000_smart_speed_on)
 828                         data |= E1000_82580_PM_SPD;
 829                 else if (phy->smart_speed == e1000_smart_speed_off)
 830                         data &= ~E1000_82580_PM_SPD;
 831         }
 832
 833         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 834         return ret_val;
 835 }
 836
 837 /**
 838  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 839  *  @hw: pointer to the HW structure
 840  *  @active: boolean used to enable/disable lplu
 841  *
 842  *  Success returns 0, Failure returns 1
 843  *
 844  *  The low power link up (lplu) state is set to the power management level D3
 845  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 846  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 847  *  is used during Dx states where the power conservation is most important.
 848  *  During driver activity, SmartSpeed should be enabled so performance is
 849  *  maintained.
 850  **/
 851 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 852 {
 853         struct e1000_phy_info *phy = &hw->phy;
 854         s32 ret_val = E1000_SUCCESS;
 855         u16 data;
 856
 857         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 858
 859         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 860
 861         if (!active) {
 862                 data &= ~E1000_82580_PM_D3_LPLU;
 863                 /*
 864                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 865                  * during Dx states where the power conservation is most
 866                  * important.  During driver activity we should enable
 867                  * SmartSpeed, so performance is maintained.
 868                  */
 869                 if (phy->smart_speed == e1000_smart_speed_on)
 870                         data |= E1000_82580_PM_SPD;
 871                 else if (phy->smart_speed == e1000_smart_speed_off)
 872                         data &= ~E1000_82580_PM_SPD;
 873         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 874                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 875                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 876                 data |= E1000_82580_PM_D3_LPLU;
 877                 /* When LPLU is enabled, we should disable SmartSpeed */
 878                 data &= ~E1000_82580_PM_SPD;
 879         }
 880
 881         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 882         return ret_val;
 883 }
 884
 885 /**
 886  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 887  *  @hw: pointer to the HW structure
 888  *
 889  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 890  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 891  *  Return successful if access grant bit set, else clear the request for
 892  *  EEPROM access and return -E1000_ERR_NVM (-1).
 893  **/
 894 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 895 {
 896         s32 ret_val;
 897
 898         DEBUGFUNC("e1000_acquire_nvm_82575");
 899
 900         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 901         if (ret_val)
 902                 goto out;
 903
 904         /*
 905          * Check if there is some access
 906          * error this access may hook on
 907          */
 908         if (hw->mac.type == e1000_i350) {
 909                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 910                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
 911                     E1000_EECD_TIMEOUT)) {
 912                         /* Clear all access error flags */
 913                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 914                                         E1000_EECD_ERROR_CLR);
 915                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
 916                 }
 917         }
 918         if (hw->mac.type == e1000_82580) {
 919                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 920                 if (eecd & E1000_EECD_BLOCKED) {
 921                         /* Clear access error flag */
 922                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 923                                         E1000_EECD_BLOCKED);
 924                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
 925                 }
 926         }
 927
 928
 929         ret_val = e1000_acquire_nvm_generic(hw);
 930         if (ret_val)
 931                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 932
 933 out:
 934         return ret_val;
 935 }
 936
 937 /**
 938  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
 939  *  @hw: pointer to the HW structure
 940  *
 941  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
 942  *  then release the semaphores acquired.
 943  **/
 944 static void e1000_release_nvm_82575(struct e1000_hw *hw)
 945 {
 946         DEBUGFUNC("e1000_release_nvm_82575");
 947
 948         e1000_release_nvm_generic(hw);
 949
 950         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 951 }
 952
 953 /**
 954  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
 955  *  @hw: pointer to the HW structure
 956  *  @mask: specifies which semaphore to acquire
 957  *
 958  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 959  *  will also specify which port we're acquiring the lock for.
 960  **/
 961 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
 962 {
 963         u32 swfw_sync;
 964         u32 swmask = mask;
 965         u32 fwmask = mask << 16;
 966         s32 ret_val = E1000_SUCCESS;
 967         s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
 968
 969         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
 970
 971         while (i < timeout) {
 972                 if (e1000_get_hw_semaphore_generic(hw)) {
 973                         ret_val = -E1000_ERR_SWFW_SYNC;
 974                         goto out;
 975                 }
 976
 977                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
 978                 if (!(swfw_sync & (fwmask | swmask)))
 979                         break;
 980
 981                 /*
 982                  * Firmware currently using resource (fwmask)
 983                  * or other software thread using resource (swmask)
 984                  */
 985                 e1000_put_hw_semaphore_generic(hw);
 986                 msec_delay_irq(5);
 987                 i++;
 988         }
 989
 990         if (i == timeout) {
 991                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
 992                 ret_val = -E1000_ERR_SWFW_SYNC;
 993                 goto out;
 994         }
 995
 996         swfw_sync |= swmask;
 997         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
 998
 999         e1000_put_hw_semaphore_generic(hw);
1000
1001 out:
1002         return ret_val;
1003 }
1004
1005 /**
1006  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1007  *  @hw: pointer to the HW structure
1008  *  @mask: specifies which semaphore to acquire
1009  *
1010  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1011  *  will also specify which port we're releasing the lock for.
1012  **/
1013 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1014 {
1015         u32 swfw_sync;
1016
1017         DEBUGFUNC("e1000_release_swfw_sync_82575");
1018
1019         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1020                 ; /* Empty */
1021
1022         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1023         swfw_sync &= ~mask;
1024         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1025
1026         e1000_put_hw_semaphore_generic(hw);
1027 }
1028
1029 /**
1030  *  e1000_get_cfg_done_82575 - Read config done bit
1031  *  @hw: pointer to the HW structure
1032  *
1033  *  Read the management control register for the config done bit for
1034  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1035  *  to read the config done bit, so an error is *ONLY* logged and returns
1036  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1037  *  would not be able to be reset or change link.
1038  **/
1039 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1040 {
1041         s32 timeout = PHY_CFG_TIMEOUT;
1042         s32 ret_val = E1000_SUCCESS;
1043         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1044
1045         DEBUGFUNC("e1000_get_cfg_done_82575");
1046
1047         if (hw->bus.func == E1000_FUNC_1)
1048                 mask = E1000_NVM_CFG_DONE_PORT_1;
1049         else if (hw->bus.func == E1000_FUNC_2)
1050                 mask = E1000_NVM_CFG_DONE_PORT_2;
1051         else if (hw->bus.func == E1000_FUNC_3)
1052                 mask = E1000_NVM_CFG_DONE_PORT_3;
1053         while (timeout) {
1054                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1055                         break;
1056                 msec_delay(1);
1057                 timeout--;
1058         }
1059         if (!timeout)
1060                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1061
1062         /* If EEPROM is not marked present, init the PHY manually */
1063         if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
1064             (hw->phy.type == e1000_phy_igp_3))
1065                 e1000_phy_init_script_igp3(hw);
1066
1067         return ret_val;
1068 }
1069
1070 /**
1071  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1072  *  @hw: pointer to the HW structure
1073  *  @speed: stores the current speed
1074  *  @duplex: stores the current duplex
1075  *
1076  *  This is a wrapper function, if using the serial gigabit media independent
1077  *  interface, use PCS to retrieve the link speed and duplex information.
1078  *  Otherwise, use the generic function to get the link speed and duplex info.
1079  **/
1080 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1081                                         u16 *duplex)
1082 {
1083         s32 ret_val;
1084
1085         DEBUGFUNC("e1000_get_link_up_info_82575");
1086
1087         if (hw->phy.media_type != e1000_media_type_copper)
1088                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1089                                                                duplex);
1090         else
1091                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1092                                                                     duplex);
1093
1094         return ret_val;
1095 }
1096
1097 /**
1098  *  e1000_check_for_link_82575 - Check for link
1099  *  @hw: pointer to the HW structure
1100  *
1101  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1102  *  use the generic interface for determining link.
1103  **/
1104 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1105 {
1106         s32 ret_val;
1107         u16 speed, duplex;
1108
1109         DEBUGFUNC("e1000_check_for_link_82575");
1110
1111         if (hw->phy.media_type != e1000_media_type_copper) {
1112                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1113                                                                &duplex);
1114                 /*
1115                  * Use this flag to determine if link needs to be checked or
1116                  * not.  If we have link clear the flag so that we do not
1117                  * continue to check for link.
1118                  */
1119                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1120
1121         } else {
1122                 ret_val = e1000_check_for_copper_link_generic(hw);
1123         }
1124
1125         return ret_val;
1126 }
1127
1128 /**
1129  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1130  *  @hw: pointer to the HW structure
1131  **/
1132 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1133 {
1134         u32 reg;
1135
1136         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1137
1138         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1139             !e1000_sgmii_active_82575(hw))
1140                 return;
1141
1142         /* Enable PCS to turn on link */
1143         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1144         reg |= E1000_PCS_CFG_PCS_EN;
1145         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1146
1147         /* Power up the laser */
1148         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1149         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1150         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1151
1152         /* flush the write to verify completion */
1153         E1000_WRITE_FLUSH(hw);
1154         msec_delay(1);
1155 }
1156
1157 /**
1158  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1159  *  @hw: pointer to the HW structure
1160  *  @speed: stores the current speed
1161  *  @duplex: stores the current duplex
1162  *
1163  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1164  *  duplex, then store the values in the pointers provided.
1165  **/
1166 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1167                                                 u16 *speed, u16 *duplex)
1168 {
1169         struct e1000_mac_info *mac = &hw->mac;
1170         u32 pcs;
1171
1172         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1173
1174         /* Set up defaults for the return values of this function */
1175         mac->serdes_has_link = false;
1176         *speed = 0;
1177         *duplex = 0;
1178
1179         /*
1180          * Read the PCS Status register for link state. For non-copper mode,
1181          * the status register is not accurate. The PCS status register is
1182          * used instead.
1183          */
1184         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1185
1186         /*
1187          * The link up bit determines when link is up on autoneg.
1188          */
1189         if (pcs & E1000_PCS_LSTS_LINK_OK) {
1190                 mac->serdes_has_link = true;
1191
1192                 /* Detect and store PCS speed */
1193                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1194                         *speed = SPEED_1000;
1195                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1196                         *speed = SPEED_100;
1197                 else
1198                         *speed = SPEED_10;
1199
1200                 /* Detect and store PCS duplex */
1201                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1202                         *duplex = FULL_DUPLEX;
1203                 else
1204                         *duplex = HALF_DUPLEX;
1205         }
1206
1207         return E1000_SUCCESS;
1208 }
1209
1210 /**
1211  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1212  *  @hw: pointer to the HW structure
1213  *
1214  *  In the case of serdes shut down sfp and PCS on driver unload
1215  *  when management pass thru is not enabled.
1216  **/
1217 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1218 {
1219         u32 reg;
1220
1221         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1222
1223         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1224             !e1000_sgmii_active_82575(hw))
1225                 return;
1226
1227         if (!e1000_enable_mng_pass_thru(hw)) {
1228                 /* Disable PCS to turn off link */
1229                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1230                 reg &= ~E1000_PCS_CFG_PCS_EN;
1231                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1232
1233                 /* shutdown the laser */
1234                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1235                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1236                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1237
1238                 /* flush the write to verify completion */
1239                 E1000_WRITE_FLUSH(hw);
1240                 msec_delay(1);
1241         }
1242
1243         return;
1244 }
1245
1246 /**
1247  *  e1000_reset_hw_82575 - Reset hardware
1248  *  @hw: pointer to the HW structure
1249  *
1250  *  This resets the hardware into a known state.
1251  **/
1252 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1253 {
1254         u32 ctrl;
1255         s32 ret_val;
1256
1257         DEBUGFUNC("e1000_reset_hw_82575");
1258
1259         /*
1260          * Prevent the PCI-E bus from sticking if there is no TLP connection
1261          * on the last TLP read/write transaction when MAC is reset.
1262          */
1263         ret_val = e1000_disable_pcie_master_generic(hw);
1264         if (ret_val)
1265                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1266
1267         /* set the completion timeout for interface */
1268         ret_val = e1000_set_pcie_completion_timeout(hw);
1269         if (ret_val)
1270                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1271
1272         DEBUGOUT("Masking off all interrupts\n");
1273         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1274
1275         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1276         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1277         E1000_WRITE_FLUSH(hw);
1278
1279         msec_delay(10);
1280
1281         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1282
1283         DEBUGOUT("Issuing a global reset to MAC\n");
1284         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1285
1286         ret_val = e1000_get_auto_rd_done_generic(hw);
1287         if (ret_val) {
1288                 /*
1289                  * When auto config read does not complete, do not
1290                  * return with an error. This can happen in situations
1291                  * where there is no eeprom and prevents getting link.
1292                  */
1293                 DEBUGOUT("Auto Read Done did not complete\n");
1294         }
1295
1296         /* If EEPROM is not present, run manual init scripts */
1297         if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
1298                 e1000_reset_init_script_82575(hw);
1299
1300         /* Clear any pending interrupt events. */
1301         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1302         E1000_READ_REG(hw, E1000_ICR);
1303
1304         /* Install any alternate MAC address into RAR0 */
1305         ret_val = e1000_check_alt_mac_addr_generic(hw);
1306
1307         return ret_val;
1308 }
1309
1310 /**
1311  *  e1000_init_hw_82575 - Initialize hardware
1312  *  @hw: pointer to the HW structure
1313  *
1314  *  This inits the hardware readying it for operation.
1315  **/
1316 static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1317 {
1318         struct e1000_mac_info *mac = &hw->mac;
1319         s32 ret_val;
1320         u16 i, rar_count = mac->rar_entry_count;
1321
1322         DEBUGFUNC("e1000_init_hw_82575");
1323
1324         /* Initialize identification LED */
1325         ret_val = mac->ops.id_led_init(hw);
1326         if (ret_val) {
1327                 DEBUGOUT("Error initializing identification LED\n");
1328                 /* This is not fatal and we should not stop init due to this */
1329         }
1330
1331         /* Disabling VLAN filtering */
1332         DEBUGOUT("Initializing the IEEE VLAN\n");
1333         mac->ops.clear_vfta(hw);
1334
1335         /* Setup the receive address */
1336         e1000_init_rx_addrs_generic(hw, rar_count);
1337
1338         /* Zero out the Multicast HASH table */
1339         DEBUGOUT("Zeroing the MTA\n");
1340         for (i = 0; i < mac->mta_reg_count; i++)
1341                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1342
1343         /* Zero out the Unicast HASH table */
1344         DEBUGOUT("Zeroing the UTA\n");
1345         for (i = 0; i < mac->uta_reg_count; i++)
1346                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1347
1348         /* Setup link and flow control */
1349         ret_val = mac->ops.setup_link(hw);
1350
1351         /* Set the default MTU size */
1352         hw->dev_spec._82575.mtu = 1500;
1353
1354         /*
1355          * Clear all of the statistics registers (clear on read).  It is
1356          * important that we do this after we have tried to establish link
1357          * because the symbol error count will increment wildly if there
1358          * is no link.
1359          */
1360         e1000_clear_hw_cntrs_82575(hw);
1361
1362         return ret_val;
1363 }
1364
1365 /**
1366  *  e1000_setup_copper_link_82575 - Configure copper link settings
1367  *  @hw: pointer to the HW structure
1368  *
1369  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1370  *  for link, once link is established calls to configure collision distance
1371  *  and flow control are called.
1372  **/
1373 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1374 {
1375         u32 ctrl;
1376         s32  ret_val;
1377
1378         DEBUGFUNC("e1000_setup_copper_link_82575");
1379
1380         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1381         ctrl |= E1000_CTRL_SLU;
1382         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1383         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1384
1385         ret_val = e1000_setup_serdes_link_82575(hw);
1386         if (ret_val)
1387                 goto out;
1388
1389         if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1390                 /* allow time for SFP cage time to power up phy */
1391                 msec_delay(300);
1392
1393                 ret_val = hw->phy.ops.reset(hw);
1394                 if (ret_val) {
1395                         DEBUGOUT("Error resetting the PHY.\n");
1396                         goto out;
1397                 }
1398         }
1399         switch (hw->phy.type) {
1400         case e1000_phy_m88:
1401                 if (hw->phy.id == I347AT4_E_PHY_ID ||
1402                     hw->phy.id == M88E1112_E_PHY_ID ||
1403                     hw->phy.id == M88E1340M_E_PHY_ID)
1404                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1405                 else
1406                         ret_val = e1000_copper_link_setup_m88(hw);
1407                 break;
1408         case e1000_phy_igp_3:
1409                 ret_val = e1000_copper_link_setup_igp(hw);
1410                 break;
1411         case e1000_phy_82580:
1412                 ret_val = e1000_copper_link_setup_82577(hw);
1413                 break;
1414         default:
1415                 ret_val = -E1000_ERR_PHY;
1416                 break;
1417         }
1418
1419         if (ret_val)
1420                 goto out;
1421
1422         ret_val = e1000_setup_copper_link_generic(hw);
1423 out:
1424         return ret_val;
1425 }
1426
1427 /**
1428  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1429  *  @hw: pointer to the HW structure
1430  *
1431  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1432  *  used on copper connections where the serialized gigabit media independent
1433  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1434  *  for auto-negotiation or forces speed/duplex.
1435  **/
1436 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1437 {
1438         u32 ctrl_ext, ctrl_reg, reg;
1439         bool pcs_autoneg;
1440         s32 ret_val = E1000_SUCCESS;
1441         u16 data;
1442
1443         DEBUGFUNC("e1000_setup_serdes_link_82575");
1444
1445         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1446             !e1000_sgmii_active_82575(hw))
1447                 return ret_val;
1448
1449         /*
1450          * On the 82575, SerDes loopback mode persists until it is
1451          * explicitly turned off or a power cycle is performed.  A read to
1452          * the register does not indicate its status.  Therefore, we ensure
1453          * loopback mode is disabled during initialization.
1454          */
1455         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1456
1457         /* power on the sfp cage if present */
1458         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1459         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1460         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1461
1462         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1463         ctrl_reg |= E1000_CTRL_SLU;
1464
1465         /* set both sw defined pins on 82575/82576*/
1466         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1467                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1468
1469         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1470
1471         /* default pcs_autoneg to the same setting as mac autoneg */
1472         pcs_autoneg = hw->mac.autoneg;
1473
1474         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1475         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1476                 /* sgmii mode lets the phy handle forcing speed/duplex */
1477                 pcs_autoneg = true;
1478                 /* autoneg time out should be disabled for SGMII mode */
1479                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1480                 break;
1481         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1482                 /* disable PCS autoneg and support parallel detect only */
1483                 pcs_autoneg = false;
1484                 /* fall through to default case */
1485         default:
1486                 if (hw->mac.type == e1000_82575 ||
1487                     hw->mac.type == e1000_82576) {
1488                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1489                         if (ret_val) {
1490                                 DEBUGOUT("NVM Read Error\n");
1491                                 return ret_val;
1492                         }
1493
1494                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1495                                 pcs_autoneg = false;
1496                 }
1497
1498                 /*
1499                  * non-SGMII modes only supports a speed of 1000/Full for the
1500                  * link so it is best to just force the MAC and let the pcs
1501                  * link either autoneg or be forced to 1000/Full
1502                  */
1503                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1504                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1505
1506                 /* set speed of 1000/Full if speed/duplex is forced */
1507                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1508                 break;
1509         }
1510
1511         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1512
1513         /*
1514          * New SerDes mode allows for forcing speed or autonegotiating speed
1515          * at 1gb. Autoneg should be default set by most drivers. This is the
1516          * mode that will be compatible with older link partners and switches.
1517          * However, both are supported by the hardware and some drivers/tools.
1518          */
1519         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1520                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1521
1522         /*
1523          * We force flow control to prevent the CTRL register values from being
1524          * overwritten by the autonegotiated flow control values
1525          */
1526         reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1527
1528         if (pcs_autoneg) {
1529                 /* Set PCS register for autoneg */
1530                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1531                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1532                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1533         } else {
1534                 /* Set PCS register for forced link */
1535                 reg |= E1000_PCS_LCTL_FSD;      /* Force Speed */
1536                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1537         }
1538
1539         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1540
1541         if (!e1000_sgmii_active_82575(hw))
1542                 e1000_force_mac_fc_generic(hw);
1543
1544         return ret_val;
1545 }
1546
1547 /**
1548  *  e1000_get_media_type_82575 - derives current media type.
1549  *  @hw: pointer to the HW structure
1550  *
1551  *  The media type is chosen reflecting few settings.
1552  *  The following are taken into account:
1553  *  - link mode set in the current port Init Control Word #3
1554  *  - current link mode settings in CSR register
1555  *  - MDIO vs. I2C PHY control interface chosen
1556  *  - SFP module media type
1557  **/
1558 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1559 {
1560         u32 lan_id = 0;
1561         s32 ret_val = E1000_ERR_CONFIG;
1562         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1563         u32 ctrl_ext = 0;
1564         u32 current_link_mode = 0;
1565         u16 init_ctrl_wd_3 = 0;
1566         u8 init_ctrl_wd_3_offset = 0;
1567         u8 init_ctrl_wd_3_bit_offset = 0;
1568
1569         /* Set internal phy as default */
1570         dev_spec->sgmii_active = false;
1571         dev_spec->module_plugged = false;
1572
1573         /*
1574          * Check if NVM access method is attached already.
1575          * If it is then Init Control Word #3 is considered
1576          * otherwise runtime CSR register content is taken.
1577          */
1578
1579         /* Get CSR setting */
1580         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1581
1582         /* Get link mode setting */
1583         if ((hw->nvm.ops.read) && (hw->nvm.ops.read != e1000_null_read_nvm)) {
1584                 /* Take link mode from EEPROM */
1585
1586                 /*
1587                  * Get LAN port ID to derive its
1588                  * adequate Init Control Word #3
1589                  */
1590                 lan_id = ((E1000_READ_REG(hw, E1000_STATUS) &
1591                       E1000_STATUS_LAN_ID_MASK) >> E1000_STATUS_LAN_ID_OFFSET);
1592                 /*
1593                  * Derive Init Control Word #3 offset
1594                  * and mask to pick up link mode setting.
1595                  */
1596                 if (hw->mac.type < e1000_82580) {
1597                         init_ctrl_wd_3_offset = lan_id ?
1598                            NVM_INIT_CONTROL3_PORT_A : NVM_INIT_CONTROL3_PORT_B;
1599                         init_ctrl_wd_3_bit_offset = NVM_WORD24_LNK_MODE_OFFSET;
1600                 } else {
1601                         init_ctrl_wd_3_offset =
1602                                             NVM_82580_LAN_FUNC_OFFSET(lan_id) +
1603                                             NVM_INIT_CONTROL3_PORT_A;
1604                         init_ctrl_wd_3_bit_offset =
1605                                               NVM_WORD24_82580_LNK_MODE_OFFSET;
1606                 }
1607                 /* Read Init Control Word #3*/
1608                 hw->nvm.ops.read(hw, init_ctrl_wd_3_offset, 1, &init_ctrl_wd_3);
1609                 current_link_mode = init_ctrl_wd_3;
1610                 /*
1611                  * Switch to CSR for all but internal PHY.
1612                  */
1613                 if ((init_ctrl_wd_3 << (E1000_CTRL_EXT_LINK_MODE_OFFSET -
1614                     init_ctrl_wd_3_bit_offset)) !=
1615                     E1000_CTRL_EXT_LINK_MODE_GMII) {
1616                         current_link_mode = ctrl_ext;
1617                         init_ctrl_wd_3_bit_offset =
1618                                               E1000_CTRL_EXT_LINK_MODE_OFFSET;
1619                 }
1620         } else {
1621                 /* Take link mode from CSR */
1622                 current_link_mode = ctrl_ext;
1623                 init_ctrl_wd_3_bit_offset = E1000_CTRL_EXT_LINK_MODE_OFFSET;
1624         }
1625
1626         /*
1627          * Align link mode bits to
1628          * their CTRL_EXT location.
1629          */
1630         current_link_mode <<= (E1000_CTRL_EXT_LINK_MODE_OFFSET -
1631                                init_ctrl_wd_3_bit_offset);
1632         current_link_mode &= E1000_CTRL_EXT_LINK_MODE_MASK;
1633
1634         switch (current_link_mode) {
1635
1636         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1637                 hw->phy.media_type = e1000_media_type_internal_serdes;
1638                 current_link_mode = E1000_CTRL_EXT_LINK_MODE_1000BASE_KX;
1639                 break;
1640         case E1000_CTRL_EXT_LINK_MODE_GMII:
1641                 hw->phy.media_type = e1000_media_type_copper;
1642                 current_link_mode = E1000_CTRL_EXT_LINK_MODE_GMII;
1643                 break;
1644         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1645         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1646                 /* Get phy control interface type set (MDIO vs. I2C)*/
1647                 if (e1000_sgmii_uses_mdio_82575(hw)) {
1648                         hw->phy.media_type = e1000_media_type_copper;
1649                         dev_spec->sgmii_active = true;
1650                         current_link_mode = E1000_CTRL_EXT_LINK_MODE_SGMII;
1651                 } else {
1652                         ret_val = e1000_set_sfp_media_type_82575(hw);
1653                         if (ret_val != E1000_SUCCESS)
1654                                 goto out;
1655                         if (hw->phy.media_type ==
1656                                 e1000_media_type_internal_serdes) {
1657                                 current_link_mode =
1658                                          E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1659                         } else if (hw->phy.media_type ==
1660                                 e1000_media_type_copper) {
1661                                 current_link_mode =
1662                                                E1000_CTRL_EXT_LINK_MODE_SGMII;
1663                         }
1664                 }
1665                 break;
1666         default:
1667                 DEBUGOUT("Link mode mask doesn't fit bit field size\n");
1668                 goto out;
1669         }
1670         /*
1671          * Do not change current link mode setting
1672          * if media type is fibre or has not been
1673          * recognized.
1674          */
1675         if ((hw->phy.media_type != e1000_media_type_unknown) &&
1676             (hw->phy.media_type != e1000_media_type_fiber)) {
1677                 /* Update link mode */
1678                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1679                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext |
1680                                 current_link_mode);
1681         }
1682
1683         ret_val = E1000_SUCCESS;
1684 out:
1685         /*
1686          * If media type was not identified then return media type
1687          * defined by the CTRL_EXT settings.
1688          */
1689         if (hw->phy.media_type == e1000_media_type_unknown) {
1690                 if (current_link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII)
1691                         hw->phy.media_type = e1000_media_type_copper;
1692                 else
1693                         hw->phy.media_type = e1000_media_type_internal_serdes;
1694         }
1695
1696         return ret_val;
1697 }
1698
1699 /**
1700  *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1701  *  @hw: pointer to the HW structure
1702  *
1703  *  The media type is chosen based on SFP module.
1704  *  compatibility flags retrieved from SFP ID EEPROM.
1705  **/
1706 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1707 {
1708         s32 ret_val = E1000_ERR_CONFIG;
1709         u32 ctrl_ext = 0;
1710         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1711         struct sfp_e1000_flags eth_flags = {0};
1712         u8 tranceiver_type = 0;
1713
1714         /* Turn I2C interface ON */
1715         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1716         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1717
1718         /* Read SFP module data */
1719         ret_val = e1000_read_sfp_data_byte(hw,
1720                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1721                         &tranceiver_type);
1722         if (ret_val != E1000_SUCCESS)
1723                 goto out;
1724         ret_val = e1000_read_sfp_data_byte(hw,
1725                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1726                         (u8 *)&eth_flags);
1727         if (ret_val != E1000_SUCCESS)
1728                 goto out;
1729         /*
1730          * Check if there is some SFP
1731          * module plugged and powered
1732          */
1733         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1734             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1735                 dev_spec->module_plugged = true;
1736                 if (eth_flags.e1000_base_lx || eth_flags.e1000_base_sx) {
1737                         hw->phy.media_type = e1000_media_type_internal_serdes;
1738                 } else if (eth_flags.e1000_base_t) {
1739                         dev_spec->sgmii_active = true;
1740                         hw->phy.media_type = e1000_media_type_copper;
1741                 } else {
1742                                 hw->phy.media_type = e1000_media_type_unknown;
1743                                 DEBUGOUT("PHY module has not been recognized\n");
1744                                 goto out;
1745                 }
1746         } else {
1747                 hw->phy.media_type = e1000_media_type_unknown;
1748         }
1749         ret_val = E1000_SUCCESS;
1750 out:
1751         /* Restore I2C interface setting */
1752         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1753         return ret_val;
1754 }
1755
1756 /**
1757  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1758  *  @hw: pointer to the HW structure
1759  *  @data: pointer to the NVM (EEPROM)
1760  *
1761  *  Read the EEPROM for the current default LED configuration.  If the
1762  *  LED configuration is not valid, set to a valid LED configuration.
1763  **/
1764 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1765 {
1766         s32 ret_val;
1767
1768         DEBUGFUNC("e1000_valid_led_default_82575");
1769
1770         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1771         if (ret_val) {
1772                 DEBUGOUT("NVM Read Error\n");
1773                 goto out;
1774         }
1775
1776         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1777                 switch (hw->phy.media_type) {
1778                 case e1000_media_type_internal_serdes:
1779                         *data = ID_LED_DEFAULT_82575_SERDES;
1780                         break;
1781                 case e1000_media_type_copper:
1782                 default:
1783                         *data = ID_LED_DEFAULT;
1784                         break;
1785                 }
1786         }
1787 out:
1788         return ret_val;
1789 }
1790
1791 /**
1792  *  e1000_sgmii_active_82575 - Return sgmii state
1793  *  @hw: pointer to the HW structure
1794  *
1795  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1796  *  which can be enabled for use in the embedded applications.  Simply
1797  *  return the current state of the sgmii interface.
1798  **/
1799 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1800 {
1801         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1802         return dev_spec->sgmii_active;
1803 }
1804
1805 /**
1806  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1807  *  @hw: pointer to the HW structure
1808  *
1809  *  Inits recommended HW defaults after a reset when there is no EEPROM
1810  *  detected. This is only for the 82575.
1811  **/
1812 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1813 {
1814         DEBUGFUNC("e1000_reset_init_script_82575");
1815
1816         if (hw->mac.type == e1000_82575) {
1817                 DEBUGOUT("Running reset init script for 82575\n");
1818                 /* SerDes configuration via SERDESCTRL */
1819                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1820                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1821                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1822                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1823
1824                 /* CCM configuration via CCMCTL register */
1825                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1826                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1827
1828                 /* PCIe lanes configuration */
1829                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1830                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1831                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1832                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1833
1834                 /* PCIe PLL Configuration */
1835                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1836                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1837                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1838         }
1839
1840         return E1000_SUCCESS;
1841 }
1842
1843 /**
1844  *  e1000_read_mac_addr_82575 - Read device MAC address
1845  *  @hw: pointer to the HW structure
1846  **/
1847 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1848 {
1849         s32 ret_val = E1000_SUCCESS;
1850
1851         DEBUGFUNC("e1000_read_mac_addr_82575");
1852
1853         /*
1854          * If there's an alternate MAC address place it in RAR0
1855          * so that it will override the Si installed default perm
1856          * address.
1857          */
1858         ret_val = e1000_check_alt_mac_addr_generic(hw);
1859         if (ret_val)
1860                 goto out;
1861
1862         ret_val = e1000_read_mac_addr_generic(hw);
1863
1864 out:
1865         return ret_val;
1866 }
1867
1868 /**
1869  *  e1000_config_collision_dist_82575 - Configure collision distance
1870  *  @hw: pointer to the HW structure
1871  *
1872  *  Configures the collision distance to the default value and is used
1873  *  during link setup.
1874  **/
1875 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1876 {
1877         u32 tctl_ext;
1878
1879         DEBUGFUNC("e1000_config_collision_dist_82575");
1880
1881         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1882
1883         tctl_ext &= ~E1000_TCTL_EXT_COLD;
1884         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
1885
1886         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1887         E1000_WRITE_FLUSH(hw);
1888 }
1889
1890 /**
1891  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
1892  * @hw: pointer to the HW structure
1893  *
1894  * In the case of a PHY power down to save power, or to turn off link during a
1895  * driver unload, or wake on lan is not enabled, remove the link.
1896  **/
1897 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
1898 {
1899         struct e1000_phy_info *phy = &hw->phy;
1900
1901         if (!(phy->ops.check_reset_block))
1902                 return;
1903
1904         /* If the management interface is not enabled, then power down */
1905         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
1906                 e1000_power_down_phy_copper(hw);
1907
1908         return;
1909 }
1910
1911 /**
1912  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1913  *  @hw: pointer to the HW structure
1914  *
1915  *  Clears the hardware counters by reading the counter registers.
1916  **/
1917 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1918 {
1919         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
1920
1921         e1000_clear_hw_cntrs_base_generic(hw);
1922
1923         E1000_READ_REG(hw, E1000_PRC64);
1924         E1000_READ_REG(hw, E1000_PRC127);
1925         E1000_READ_REG(hw, E1000_PRC255);
1926         E1000_READ_REG(hw, E1000_PRC511);
1927         E1000_READ_REG(hw, E1000_PRC1023);
1928         E1000_READ_REG(hw, E1000_PRC1522);
1929         E1000_READ_REG(hw, E1000_PTC64);
1930         E1000_READ_REG(hw, E1000_PTC127);
1931         E1000_READ_REG(hw, E1000_PTC255);
1932         E1000_READ_REG(hw, E1000_PTC511);
1933         E1000_READ_REG(hw, E1000_PTC1023);
1934         E1000_READ_REG(hw, E1000_PTC1522);
1935
1936         E1000_READ_REG(hw, E1000_ALGNERRC);
1937         E1000_READ_REG(hw, E1000_RXERRC);
1938         E1000_READ_REG(hw, E1000_TNCRS);
1939         E1000_READ_REG(hw, E1000_CEXTERR);
1940         E1000_READ_REG(hw, E1000_TSCTC);
1941         E1000_READ_REG(hw, E1000_TSCTFC);
1942
1943         E1000_READ_REG(hw, E1000_MGTPRC);
1944         E1000_READ_REG(hw, E1000_MGTPDC);
1945         E1000_READ_REG(hw, E1000_MGTPTC);
1946
1947         E1000_READ_REG(hw, E1000_IAC);
1948         E1000_READ_REG(hw, E1000_ICRXOC);
1949
1950         E1000_READ_REG(hw, E1000_ICRXPTC);
1951         E1000_READ_REG(hw, E1000_ICRXATC);
1952         E1000_READ_REG(hw, E1000_ICTXPTC);
1953         E1000_READ_REG(hw, E1000_ICTXATC);
1954         E1000_READ_REG(hw, E1000_ICTXQEC);
1955         E1000_READ_REG(hw, E1000_ICTXQMTC);
1956         E1000_READ_REG(hw, E1000_ICRXDMTC);
1957
1958         E1000_READ_REG(hw, E1000_CBTMPC);
1959         E1000_READ_REG(hw, E1000_HTDPMC);
1960         E1000_READ_REG(hw, E1000_CBRMPC);
1961         E1000_READ_REG(hw, E1000_RPTHC);
1962         E1000_READ_REG(hw, E1000_HGPTC);
1963         E1000_READ_REG(hw, E1000_HTCBDPC);
1964         E1000_READ_REG(hw, E1000_HGORCL);
1965         E1000_READ_REG(hw, E1000_HGORCH);
1966         E1000_READ_REG(hw, E1000_HGOTCL);
1967         E1000_READ_REG(hw, E1000_HGOTCH);
1968         E1000_READ_REG(hw, E1000_LENERRS);
1969
1970         /* This register should not be read in copper configurations */
1971         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1972             e1000_sgmii_active_82575(hw))
1973                 E1000_READ_REG(hw, E1000_SCVPC);
1974 }
1975
1976 /**
1977  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
1978  *  @hw: pointer to the HW structure
1979  *
1980  *  After rx enable if managability is enabled then there is likely some
1981  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
1982  *  function clears the fifos and flushes any packets that came in as rx was
1983  *  being enabled.
1984  **/
1985 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
1986 {
1987         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1988         int i, ms_wait;
1989
1990         DEBUGFUNC("e1000_rx_fifo_workaround_82575");
1991         if (hw->mac.type != e1000_82575 ||
1992             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1993                 return;
1994
1995         /* Disable all Rx queues */
1996         for (i = 0; i < 4; i++) {
1997                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
1998                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
1999                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2000         }
2001         /* Poll all queues to verify they have shut down */
2002         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2003                 msec_delay(1);
2004                 rx_enabled = 0;
2005                 for (i = 0; i < 4; i++)
2006                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2007                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2008                         break;
2009         }
2010
2011         if (ms_wait == 10)
2012                 DEBUGOUT("Queue disable timed out after 10ms\n");
2013
2014         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2015          * incoming packets are rejected.  Set enable and wait 2ms so that
2016          * any packet that was coming in as RCTL.EN was set is flushed
2017          */
2018         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2019         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2020
2021         rlpml = E1000_READ_REG(hw, E1000_RLPML);
2022         E1000_WRITE_REG(hw, E1000_RLPML, 0);
2023
2024         rctl = E1000_READ_REG(hw, E1000_RCTL);
2025         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2026         temp_rctl |= E1000_RCTL_LPE;
2027
2028         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2029         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2030         E1000_WRITE_FLUSH(hw);
2031         msec_delay(2);
2032
2033         /* Enable Rx queues that were previously enabled and restore our
2034          * previous state
2035          */
2036         for (i = 0; i < 4; i++)
2037                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2038         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2039         E1000_WRITE_FLUSH(hw);
2040
2041         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2042         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2043
2044         /* Flush receive errors generated by workaround */
2045         E1000_READ_REG(hw, E1000_ROC);
2046         E1000_READ_REG(hw, E1000_RNBC);
2047         E1000_READ_REG(hw, E1000_MPC);
2048 }
2049
2050 /**
2051  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2052  *  @hw: pointer to the HW structure
2053  *
2054  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2055  *  however the hardware default for these parts is 500us to 1ms which is less
2056  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2057  *  increase the value to either 10ms to 200ms for capability version 1 config,
2058  *  or 16ms to 55ms for version 2.
2059  **/
2060 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2061 {
2062         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2063         s32 ret_val = E1000_SUCCESS;
2064         u16 pcie_devctl2;
2065
2066         /* only take action if timeout value is defaulted to 0 */
2067         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2068                 goto out;
2069
2070         /*
2071          * if capababilities version is type 1 we can write the
2072          * timeout of 10ms to 200ms through the GCR register
2073          */
2074         if (!(gcr & E1000_GCR_CAP_VER2)) {
2075                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2076                 goto out;
2077         }
2078
2079         /*
2080          * for version 2 capabilities we need to write the config space
2081          * directly in order to set the completion timeout value for
2082          * 16ms to 55ms
2083          */
2084         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2085                                           &pcie_devctl2);
2086         if (ret_val)
2087                 goto out;
2088
2089         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2090
2091         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2092                                            &pcie_devctl2);
2093 out:
2094         /* disable completion timeout resend */
2095         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2096
2097         E1000_WRITE_REG(hw, E1000_GCR, gcr);
2098         return ret_val;
2099 }
2100
2101 /**
2102  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2103  *  @hw: pointer to the hardware struct
2104  *  @enable: state to enter, either enabled or disabled
2105  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2106  *
2107  *  enables/disables L2 switch anti-spoofing functionality.
2108  **/
2109 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2110 {
2111         u32 dtxswc;
2112
2113         switch (hw->mac.type) {
2114         case e1000_82576:
2115                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2116                 if (enable) {
2117                         dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2118                                    E1000_DTXSWC_VLAN_SPOOF_MASK);
2119                         /* The PF can spoof - it has to in order to
2120                          * support emulation mode NICs */
2121                         dtxswc ^= (1 << pf | 1 << (pf +
2122                                    E1000_DTXSWC_VLAN_SPOOF_SHIFT));
2123                 } else {
2124                         dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2125                                     E1000_DTXSWC_VLAN_SPOOF_MASK);
2126                 }
2127                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2128                 break;
2129         case e1000_i350:
2130                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2131                 if (enable) {
2132                         dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2133                                    E1000_DTXSWC_VLAN_SPOOF_MASK);
2134                         /* The PF can spoof - it has to in order to
2135                          * support emulation mode NICs
2136                          */
2137                         dtxswc ^= (1 << pf | 1 << (pf +
2138                                    E1000_DTXSWC_VLAN_SPOOF_SHIFT));
2139                 } else {
2140                         dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2141                                     E1000_DTXSWC_VLAN_SPOOF_MASK);
2142                 }
2143                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2144         default:
2145                 break;
2146         }
2147 }
2148
2149 /**
2150  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2151  *  @hw: pointer to the hardware struct
2152  *  @enable: state to enter, either enabled or disabled
2153  *
2154  *  enables/disables L2 switch loopback functionality.
2155  **/
2156 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2157 {
2158         u32 dtxswc;
2159
2160         switch (hw->mac.type) {
2161         case e1000_82576:
2162                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2163                 if (enable)
2164                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2165                 else
2166                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2167                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2168                 break;
2169         case e1000_i350:
2170                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2171                 if (enable)
2172                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2173                 else
2174                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2175                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2176                 break;
2177         default:
2178                 /* Currently no other hardware supports loopback */
2179                 break;
2180         }
2181
2182
2183 }
2184
2185 /**
2186  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2187  *  @hw: pointer to the hardware struct
2188  *  @enable: state to enter, either enabled or disabled
2189  *
2190  *  enables/disables replication of packets across multiple pools.
2191  **/
2192 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2193 {
2194         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2195
2196         if (enable)
2197                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2198         else
2199                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2200
2201         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2202 }
2203
2204 /**
2205  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2206  *  @hw: pointer to the HW structure
2207  *  @offset: register offset to be read
2208  *  @data: pointer to the read data
2209  *
2210  *  Reads the MDI control register in the PHY at offset and stores the
2211  *  information read to data.
2212  **/
2213 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2214 {
2215         s32 ret_val;
2216
2217         DEBUGFUNC("e1000_read_phy_reg_82580");
2218
2219         ret_val = hw->phy.ops.acquire(hw);
2220         if (ret_val)
2221                 goto out;
2222
2223         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2224
2225         hw->phy.ops.release(hw);
2226
2227 out:
2228         return ret_val;
2229 }
2230
2231 /**
2232  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2233  *  @hw: pointer to the HW structure
2234  *  @offset: register offset to write to
2235  *  @data: data to write to register at offset
2236  *
2237  *  Writes data to MDI control register in the PHY at offset.
2238  **/
2239 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2240 {
2241         s32 ret_val;
2242
2243         DEBUGFUNC("e1000_write_phy_reg_82580");
2244
2245         ret_val = hw->phy.ops.acquire(hw);
2246         if (ret_val)
2247                 goto out;
2248
2249         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2250
2251         hw->phy.ops.release(hw);
2252
2253 out:
2254         return ret_val;
2255 }
2256
2257 /**
2258  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2259  *  @hw: pointer to the HW structure
2260  *
2261  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2262  *  the values found in the EEPROM.  This addresses an issue in which these
2263  *  bits are not restored from EEPROM after reset.
2264  **/
2265 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2266 {
2267         s32 ret_val = E1000_SUCCESS;
2268         u32 mdicnfg;
2269         u16 nvm_data = 0;
2270
2271         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2272
2273         if (hw->mac.type != e1000_82580)
2274                 goto out;
2275         if (!e1000_sgmii_active_82575(hw))
2276                 goto out;
2277
2278         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2279                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2280                                    &nvm_data);
2281         if (ret_val) {
2282                 DEBUGOUT("NVM Read Error\n");
2283                 goto out;
2284         }
2285
2286         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2287         if (nvm_data & NVM_WORD24_EXT_MDIO)
2288                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2289         if (nvm_data & NVM_WORD24_COM_MDIO)
2290                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2291         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2292 out:
2293         return ret_val;
2294 }
2295
2296 /**
2297  *  e1000_reset_hw_82580 - Reset hardware
2298  *  @hw: pointer to the HW structure
2299  *
2300  *  This resets function or entire device (all ports, etc.)
2301  *  to a known state.
2302  **/
2303 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2304 {
2305         s32 ret_val = E1000_SUCCESS;
2306         /* BH SW mailbox bit in SW_FW_SYNC */
2307         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2308         u32 ctrl;
2309         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2310
2311         DEBUGFUNC("e1000_reset_hw_82580");
2312
2313         hw->dev_spec._82575.global_device_reset = false;
2314
2315         /* Get current control state. */
2316         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2317
2318         /*
2319          * Prevent the PCI-E bus from sticking if there is no TLP connection
2320          * on the last TLP read/write transaction when MAC is reset.
2321          */
2322         ret_val = e1000_disable_pcie_master_generic(hw);
2323         if (ret_val)
2324                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2325
2326         DEBUGOUT("Masking off all interrupts\n");
2327         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2328         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2329         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2330         E1000_WRITE_FLUSH(hw);
2331
2332         msec_delay(10);
2333
2334         /* Determine whether or not a global dev reset is requested */
2335         if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2336             swmbsw_mask))
2337                         global_device_reset = false;
2338
2339         if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2340             E1000_STAT_DEV_RST_SET))
2341                 ctrl |= E1000_CTRL_DEV_RST;
2342         else
2343                 ctrl |= E1000_CTRL_RST;
2344
2345         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2346         E1000_WRITE_FLUSH(hw);
2347
2348         /* Add delay to insure DEV_RST has time to complete */
2349         if (global_device_reset)
2350                 msec_delay(5);
2351
2352         ret_val = e1000_get_auto_rd_done_generic(hw);
2353         if (ret_val) {
2354                 /*
2355                  * When auto config read does not complete, do not
2356                  * return with an error. This can happen in situations
2357                  * where there is no eeprom and prevents getting link.
2358                  */
2359                 DEBUGOUT("Auto Read Done did not complete\n");
2360         }
2361
2362         /* If EEPROM is not present, run manual init scripts */
2363         if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
2364                 e1000_reset_init_script_82575(hw);
2365
2366         /* clear global device reset status bit */
2367         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2368
2369         /* Clear any pending interrupt events. */
2370         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2371         E1000_READ_REG(hw, E1000_ICR);
2372
2373         ret_val = e1000_reset_mdicnfg_82580(hw);
2374         if (ret_val)
2375                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2376
2377         /* Install any alternate MAC address into RAR0 */
2378         ret_val = e1000_check_alt_mac_addr_generic(hw);
2379
2380         /* Release semaphore */
2381         if (global_device_reset)
2382                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2383
2384         return ret_val;
2385 }
2386
2387 /**
2388  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2389  *  @data: data received by reading RXPBS register
2390  *
2391  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2392  *  This function converts the retrieved value into the correct table value
2393  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2394  *  0x0 36  72 144   1   2   4   8  16
2395  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2396  */
2397 u16 e1000_rxpbs_adjust_82580(u32 data)
2398 {
2399         u16 ret_val = 0;
2400
2401         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2402                 ret_val = e1000_82580_rxpbs_table[data];
2403
2404         return ret_val;
2405 }
2406
2407 /**
2408  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2409  *  checksum
2410  *  @hw: pointer to the HW structure
2411  *  @offset: offset in words of the checksum protected region
2412  *
2413  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2414  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2415  **/
2416 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2417 {
2418         s32 ret_val = E1000_SUCCESS;
2419         u16 checksum = 0;
2420         u16 i, nvm_data;
2421
2422         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2423
2424         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2425                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2426                 if (ret_val) {
2427                         DEBUGOUT("NVM Read Error\n");
2428                         goto out;
2429                 }
2430                 checksum += nvm_data;
2431         }
2432
2433         if (checksum != (u16) NVM_SUM) {
2434                 DEBUGOUT("NVM Checksum Invalid\n");
2435                 ret_val = -E1000_ERR_NVM;
2436                 goto out;
2437         }
2438
2439 out:
2440         return ret_val;
2441 }
2442
2443 /**
2444  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2445  *  checksum
2446  *  @hw: pointer to the HW structure
2447  *  @offset: offset in words of the checksum protected region
2448  *
2449  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2450  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2451  *  value to the EEPROM.
2452  **/
2453 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2454 {
2455         s32 ret_val;
2456         u16 checksum = 0;
2457         u16 i, nvm_data;
2458
2459         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2460
2461         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2462                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2463                 if (ret_val) {
2464                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2465                         goto out;
2466                 }
2467                 checksum += nvm_data;
2468         }
2469         checksum = (u16) NVM_SUM - checksum;
2470         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2471                                     &checksum);
2472         if (ret_val)
2473                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2474
2475 out:
2476         return ret_val;
2477 }
2478
2479 /**
2480  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2481  *  @hw: pointer to the HW structure
2482  *
2483  *  Calculates the EEPROM section checksum by reading/adding each word of
2484  *  the EEPROM and then verifies that the sum of the EEPROM is
2485  *  equal to 0xBABA.
2486  **/
2487 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2488 {
2489         s32 ret_val = E1000_SUCCESS;
2490         u16 eeprom_regions_count = 1;
2491         u16 j, nvm_data;
2492         u16 nvm_offset;
2493
2494         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2495
2496         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2497         if (ret_val) {
2498                 DEBUGOUT("NVM Read Error\n");
2499                 goto out;
2500         }
2501
2502         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2503                 /* if chekcsums compatibility bit is set validate checksums
2504                  * for all 4 ports. */
2505                 eeprom_regions_count = 4;
2506         }
2507
2508         for (j = 0; j < eeprom_regions_count; j++) {
2509                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2510                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2511                                                                   nvm_offset);
2512                 if (ret_val != E1000_SUCCESS)
2513                         goto out;
2514         }
2515
2516 out:
2517         return ret_val;
2518 }
2519
2520 /**
2521  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2522  *  @hw: pointer to the HW structure
2523  *
2524  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2525  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2526  *  checksum and writes the value to the EEPROM.
2527  **/
2528 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2529 {
2530         s32 ret_val;
2531         u16 j, nvm_data;
2532         u16 nvm_offset;
2533
2534         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2535
2536         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2537         if (ret_val) {
2538                 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2539                 goto out;
2540         }
2541
2542         if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2543                 /* set compatibility bit to validate checksums appropriately */
2544                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2545                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2546                                             &nvm_data);
2547                 if (ret_val) {
2548                         DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2549                         goto out;
2550                 }
2551         }
2552
2553         for (j = 0; j < 4; j++) {
2554                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2555                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2556                 if (ret_val)
2557                         goto out;
2558         }
2559
2560 out:
2561         return ret_val;
2562 }
2563
2564 /**
2565  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2566  *  @hw: pointer to the HW structure
2567  *
2568  *  Calculates the EEPROM section checksum by reading/adding each word of
2569  *  the EEPROM and then verifies that the sum of the EEPROM is
2570  *  equal to 0xBABA.
2571  **/
2572 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2573 {
2574         s32 ret_val = E1000_SUCCESS;
2575         u16 j;
2576         u16 nvm_offset;
2577
2578         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2579
2580         for (j = 0; j < 4; j++) {
2581                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2582                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2583                                                                   nvm_offset);
2584                 if (ret_val != E1000_SUCCESS)
2585                         goto out;
2586         }
2587
2588 out:
2589         return ret_val;
2590 }
2591
2592 /**
2593  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2594  *  @hw: pointer to the HW structure
2595  *
2596  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2597  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2598  *  checksum and writes the value to the EEPROM.
2599  **/
2600 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2601 {
2602         s32 ret_val = E1000_SUCCESS;
2603         u16 j;
2604         u16 nvm_offset;
2605
2606         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2607
2608         for (j = 0; j < 4; j++) {
2609                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2610                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2611                 if (ret_val != E1000_SUCCESS)
2612                         goto out;
2613         }
2614
2615 out:
2616         return ret_val;
2617 }
2618
2619 /**
2620  *  e1000_set_eee_i350 - Enable/disable EEE support
2621  *  @hw: pointer to the HW structure
2622  *
2623  *  Enable/disable EEE based on setting in dev_spec structure.
2624  *
2625  **/
2626 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2627 {
2628         s32 ret_val = E1000_SUCCESS;
2629         u32 ipcnfg, eeer;
2630
2631         DEBUGFUNC("e1000_set_eee_i350");
2632
2633         if ((hw->mac.type < e1000_i350) ||
2634             (hw->phy.media_type != e1000_media_type_copper))
2635                 goto out;
2636         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2637         eeer = E1000_READ_REG(hw, E1000_EEER);
2638
2639         /* enable or disable per user setting */
2640         if (!(hw->dev_spec._82575.eee_disable)) {
2641                 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2642                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2643                          E1000_EEER_LPI_FC);
2644
2645         } else {
2646                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2647                 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2648                           E1000_EEER_LPI_FC);
2649         }
2650         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2651         E1000_WRITE_REG(hw, E1000_EEER, eeer);
2652         E1000_READ_REG(hw, E1000_IPCNFG);
2653         E1000_READ_REG(hw, E1000_EEER);
2654 out:
2655
2656         return ret_val;
2657 }
2658
2659 /* Due to a hw errata, if the host tries to  configure the VFTA register
2660  * while performing queries from the BMC or DMA, then the VFTA in some
2661  * cases won't be written.
2662  */
2663
2664 /**
2665  *  e1000_clear_vfta_i350 - Clear VLAN filter table
2666  *  @hw: pointer to the HW structure
2667  *
2668  *  Clears the register array which contains the VLAN filter table by
2669  *  setting all the values to 0.
2670  **/
2671 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2672 {
2673         u32 offset;
2674         int i;
2675
2676         DEBUGFUNC("e1000_clear_vfta_350");
2677
2678         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2679                 for (i = 0; i < 10; i++)
2680                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2681
2682                 E1000_WRITE_FLUSH(hw);
2683         }
2684 }
2685
2686 /**
2687  *  e1000_write_vfta_i350 - Write value to VLAN filter table
2688  *  @hw: pointer to the HW structure
2689  *  @offset: register offset in VLAN filter table
2690  *  @value: register value written to VLAN filter table
2691  *
2692  *  Writes value at the given offset in the register array which stores
2693  *  the VLAN filter table.
2694  **/
2695 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2696 {
2697         int i;
2698
2699         DEBUGFUNC("e1000_write_vfta_350");
2700
2701         for (i = 0; i < 10; i++)
2702                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2703
2704         E1000_WRITE_FLUSH(hw);
2705 }
2706
2707
2708 /**
2709  *  e1000_set_i2c_bb - Enable I2C bit-bang
2710  *  @hw: pointer to the HW structure
2711  *
2712  *  Enable I2C bit-bang interface
2713  *
2714  **/
2715 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
2716 {
2717         s32 ret_val = E1000_SUCCESS;
2718         u32 ctrl_ext, i2cparams;
2719
2720         DEBUGFUNC("e1000_set_i2c_bb");
2721
2722         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2723         ctrl_ext |= E1000_CTRL_I2C_ENA;
2724         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2725         E1000_WRITE_FLUSH(hw);
2726
2727         i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
2728         i2cparams |= E1000_I2CBB_EN;
2729         i2cparams |= E1000_I2C_DATA_OE_N;
2730         i2cparams |= E1000_I2C_CLK_OE_N;
2731         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
2732         E1000_WRITE_FLUSH(hw);
2733
2734         return ret_val;
2735 }
2736
2737 /**
2738  *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
2739  *  @hw: pointer to hardware structure
2740  *  @byte_offset: byte offset to read
2741  *  @dev_addr: device address
2742  *  @data: value read
2743  *
2744  *  Performs byte read operation over I2C interface at
2745  *  a specified device address.
2746  **/
2747 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2748                                 u8 dev_addr, u8 *data)
2749 {
2750         s32 status = E1000_SUCCESS;
2751         u32 max_retry = 10;
2752         u32 retry = 1;
2753         u16 swfw_mask = 0;
2754
2755         bool nack = 1;
2756
2757         DEBUGFUNC("e1000_read_i2c_byte_generic");
2758
2759         swfw_mask = E1000_SWFW_PHY0_SM;
2760
2761         do {
2762                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
2763                     != E1000_SUCCESS) {
2764                         status = E1000_ERR_SWFW_SYNC;
2765                         goto read_byte_out;
2766                 }
2767
2768                 e1000_i2c_start(hw);
2769
2770                 /* Device Address and write indication */
2771                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2772                 if (status != E1000_SUCCESS)
2773                         goto fail;
2774
2775                 status = e1000_get_i2c_ack(hw);
2776                 if (status != E1000_SUCCESS)
2777                         goto fail;
2778
2779                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2780                 if (status != E1000_SUCCESS)
2781                         goto fail;
2782
2783                 status = e1000_get_i2c_ack(hw);
2784                 if (status != E1000_SUCCESS)
2785                         goto fail;
2786
2787                 e1000_i2c_start(hw);
2788
2789                 /* Device Address and read indication */
2790                 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2791                 if (status != E1000_SUCCESS)
2792                         goto fail;
2793
2794                 status = e1000_get_i2c_ack(hw);
2795                 if (status != E1000_SUCCESS)
2796                         goto fail;
2797
2798                 status = e1000_clock_in_i2c_byte(hw, data);
2799                 if (status != E1000_SUCCESS)
2800                         goto fail;
2801
2802                 status = e1000_clock_out_i2c_bit(hw, nack);
2803                 if (status != E1000_SUCCESS)
2804                         goto fail;
2805
2806                 e1000_i2c_stop(hw);
2807                 break;
2808
2809 fail:
2810                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2811                 msec_delay(100);
2812                 e1000_i2c_bus_clear(hw);
2813                 retry++;
2814                 if (retry < max_retry)
2815                         DEBUGOUT("I2C byte read error - Retrying.\n");
2816                 else
2817                         DEBUGOUT("I2C byte read error.\n");
2818
2819         } while (retry < max_retry);
2820
2821         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2822
2823 read_byte_out:
2824
2825         return status;
2826 }
2827
2828 /**
2829  *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
2830  *  @hw: pointer to hardware structure
2831  *  @byte_offset: byte offset to write
2832  *  @dev_addr: device address
2833  *  @data: value to write
2834  *
2835  *  Performs byte write operation over I2C interface at
2836  *  a specified device address.
2837  **/
2838 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2839                                  u8 dev_addr, u8 data)
2840 {
2841         s32 status = E1000_SUCCESS;
2842         u32 max_retry = 1;
2843         u32 retry = 0;
2844         u16 swfw_mask = 0;
2845
2846         DEBUGFUNC("e1000_write_i2c_byte_generic");
2847
2848         swfw_mask = E1000_SWFW_PHY0_SM;
2849
2850         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
2851                 status = E1000_ERR_SWFW_SYNC;
2852                 goto write_byte_out;
2853         }
2854
2855         do {
2856                 e1000_i2c_start(hw);
2857
2858                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2859                 if (status != E1000_SUCCESS)
2860                         goto fail;
2861
2862                 status = e1000_get_i2c_ack(hw);
2863                 if (status != E1000_SUCCESS)
2864                         goto fail;
2865
2866                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2867                 if (status != E1000_SUCCESS)
2868                         goto fail;
2869
2870                 status = e1000_get_i2c_ack(hw);
2871                 if (status != E1000_SUCCESS)
2872                         goto fail;
2873
2874                 status = e1000_clock_out_i2c_byte(hw, data);
2875                 if (status != E1000_SUCCESS)
2876                         goto fail;
2877
2878                 status = e1000_get_i2c_ack(hw);
2879                 if (status != E1000_SUCCESS)
2880                         goto fail;
2881
2882                 e1000_i2c_stop(hw);
2883                 break;
2884
2885 fail:
2886                 e1000_i2c_bus_clear(hw);
2887                 retry++;
2888                 if (retry < max_retry)
2889                         DEBUGOUT("I2C byte write error - Retrying.\n");
2890                 else
2891                         DEBUGOUT("I2C byte write error.\n");
2892         } while (retry < max_retry);
2893
2894         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2895
2896 write_byte_out:
2897
2898         return status;
2899 }
2900
2901 /**
2902  *  e1000_i2c_start - Sets I2C start condition
2903  *  @hw: pointer to hardware structure
2904  *
2905  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2906  **/
2907 static void e1000_i2c_start(struct e1000_hw *hw)
2908 {
2909         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
2910
2911         DEBUGFUNC("e1000_i2c_start");
2912
2913         /* Start condition must begin with data and clock high */
2914         e1000_set_i2c_data(hw, &i2cctl, 1);
2915         e1000_raise_i2c_clk(hw, &i2cctl);
2916
2917         /* Setup time for start condition (4.7us) */
2918         usec_delay(E1000_I2C_T_SU_STA);
2919
2920         e1000_set_i2c_data(hw, &i2cctl, 0);
2921
2922         /* Hold time for start condition (4us) */
2923         usec_delay(E1000_I2C_T_HD_STA);
2924
2925         e1000_lower_i2c_clk(hw, &i2cctl);
2926
2927         /* Minimum low period of clock is 4.7 us */
2928         usec_delay(E1000_I2C_T_LOW);
2929
2930 }
2931
2932 /**
2933  *  e1000_i2c_stop - Sets I2C stop condition
2934  *  @hw: pointer to hardware structure
2935  *
2936  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2937  **/
2938 static void e1000_i2c_stop(struct e1000_hw *hw)
2939 {
2940         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
2941
2942         DEBUGFUNC("e1000_i2c_stop");
2943
2944         /* Stop condition must begin with data low and clock high */
2945         e1000_set_i2c_data(hw, &i2cctl, 0);
2946         e1000_raise_i2c_clk(hw, &i2cctl);
2947
2948         /* Setup time for stop condition (4us) */
2949         usec_delay(E1000_I2C_T_SU_STO);
2950
2951         e1000_set_i2c_data(hw, &i2cctl, 1);
2952
2953         /* bus free time between stop and start (4.7us)*/
2954         usec_delay(E1000_I2C_T_BUF);
2955 }
2956
2957 /**
2958  *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
2959  *  @hw: pointer to hardware structure
2960  *  @data: data byte to clock in
2961  *
2962  *  Clocks in one byte data via I2C data/clock
2963  **/
2964 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
2965 {
2966         s32 i;
2967         bool bit = 0;
2968
2969         DEBUGFUNC("e1000_clock_in_i2c_byte");
2970
2971         *data = 0;
2972         for (i = 7; i >= 0; i--) {
2973                 e1000_clock_in_i2c_bit(hw, &bit);
2974                 *data |= bit << i;
2975         }
2976
2977         return E1000_SUCCESS;
2978 }
2979
2980 /**
2981  *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
2982  *  @hw: pointer to hardware structure
2983  *  @data: data byte clocked out
2984  *
2985  *  Clocks out one byte data via I2C data/clock
2986  **/
2987 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
2988 {
2989         s32 status = E1000_SUCCESS;
2990         s32 i;
2991         u32 i2cctl;
2992         bool bit = 0;
2993
2994         DEBUGFUNC("e1000_clock_out_i2c_byte");
2995
2996         for (i = 7; i >= 0; i--) {
2997                 bit = (data >> i) & 0x1;
2998                 status = e1000_clock_out_i2c_bit(hw, bit);
2999
3000                 if (status != E1000_SUCCESS)
3001                         break;
3002         }
3003
3004         /* Release SDA line (set high) */
3005         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3006
3007         i2cctl |= E1000_I2C_DATA_OE_N;
3008         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3009         E1000_WRITE_FLUSH(hw);
3010
3011         return status;
3012 }
3013
3014 /**
3015  *  e1000_get_i2c_ack - Polls for I2C ACK
3016  *  @hw: pointer to hardware structure
3017  *
3018  *  Clocks in/out one bit via I2C data/clock
3019  **/
3020 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3021 {
3022         s32 status = E1000_SUCCESS;
3023         u32 i = 0;
3024         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3025         u32 timeout = 10;
3026         bool ack = 1;
3027
3028         DEBUGFUNC("e1000_get_i2c_ack");
3029
3030         e1000_raise_i2c_clk(hw, &i2cctl);
3031
3032         /* Minimum high period of clock is 4us */
3033         usec_delay(E1000_I2C_T_HIGH);
3034
3035         /* Wait until SCL returns high */
3036         for (i = 0; i < timeout; i++) {
3037                 usec_delay(1);
3038                 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3039                 if (i2cctl & E1000_I2C_CLK_IN)
3040                         break;
3041         }
3042         if (!(i2cctl & E1000_I2C_CLK_IN))
3043                 return E1000_ERR_I2C;
3044
3045         ack = e1000_get_i2c_data(&i2cctl);
3046         if (ack == 1) {
3047                 DEBUGOUT("I2C ack was not received.\n");
3048                 status = E1000_ERR_I2C;
3049         }
3050
3051         e1000_lower_i2c_clk(hw, &i2cctl);
3052
3053         /* Minimum low period of clock is 4.7 us */
3054         usec_delay(E1000_I2C_T_LOW);
3055
3056         return status;
3057 }
3058
3059 /**
3060  *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3061  *  @hw: pointer to hardware structure
3062  *  @data: read data value
3063  *
3064  *  Clocks in one bit via I2C data/clock
3065  **/
3066 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3067 {
3068         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3069
3070         DEBUGFUNC("e1000_clock_in_i2c_bit");
3071
3072         e1000_raise_i2c_clk(hw, &i2cctl);
3073
3074         /* Minimum high period of clock is 4us */
3075         usec_delay(E1000_I2C_T_HIGH);
3076
3077         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3078         *data = e1000_get_i2c_data(&i2cctl);
3079
3080         e1000_lower_i2c_clk(hw, &i2cctl);
3081
3082         /* Minimum low period of clock is 4.7 us */
3083         usec_delay(E1000_I2C_T_LOW);
3084
3085         return E1000_SUCCESS;
3086 }
3087
3088 /**
3089  *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3090  *  @hw: pointer to hardware structure
3091  *  @data: data value to write
3092  *
3093  *  Clocks out one bit via I2C data/clock
3094  **/
3095 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3096 {
3097         s32 status;
3098         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3099
3100         DEBUGFUNC("e1000_clock_out_i2c_bit");
3101
3102         status = e1000_set_i2c_data(hw, &i2cctl, data);
3103         if (status == E1000_SUCCESS) {
3104                 e1000_raise_i2c_clk(hw, &i2cctl);
3105
3106                 /* Minimum high period of clock is 4us */
3107                 usec_delay(E1000_I2C_T_HIGH);
3108
3109                 e1000_lower_i2c_clk(hw, &i2cctl);
3110
3111                 /* Minimum low period of clock is 4.7 us.
3112                  * This also takes care of the data hold time.
3113                  */
3114                 usec_delay(E1000_I2C_T_LOW);
3115         } else {
3116                 status = E1000_ERR_I2C;
3117                 DEBUGOUT1("I2C data was not set to %X\n", data);
3118         }
3119
3120         return status;
3121 }
3122 /**
3123  *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3124  *  @hw: pointer to hardware structure
3125  *  @i2cctl: Current value of I2CCTL register
3126  *
3127  *  Raises the I2C clock line '0'->'1'
3128  **/
3129 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3130 {
3131         DEBUGFUNC("e1000_raise_i2c_clk");
3132
3133         *i2cctl |= E1000_I2C_CLK_OUT;
3134         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3135         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3136         E1000_WRITE_FLUSH(hw);
3137
3138         /* SCL rise time (1000ns) */
3139         usec_delay(E1000_I2C_T_RISE);
3140 }
3141
3142 /**
3143  *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3144  *  @hw: pointer to hardware structure
3145  *  @i2cctl: Current value of I2CCTL register
3146  *
3147  *  Lowers the I2C clock line '1'->'0'
3148  **/
3149 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3150 {
3151
3152         DEBUGFUNC("e1000_lower_i2c_clk");
3153
3154         *i2cctl &= ~E1000_I2C_CLK_OUT;
3155         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3156         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3157         E1000_WRITE_FLUSH(hw);
3158
3159         /* SCL fall time (300ns) */
3160         usec_delay(E1000_I2C_T_FALL);
3161 }
3162
3163 /**
3164  *  e1000_set_i2c_data - Sets the I2C data bit
3165  *  @hw: pointer to hardware structure
3166  *  @i2cctl: Current value of I2CCTL register
3167  *  @data: I2C data value (0 or 1) to set
3168  *
3169  *  Sets the I2C data bit
3170  **/
3171 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3172 {
3173         s32 status = E1000_SUCCESS;
3174
3175         DEBUGFUNC("e1000_set_i2c_data");
3176
3177         if (data)
3178                 *i2cctl |= E1000_I2C_DATA_OUT;
3179         else
3180                 *i2cctl &= ~E1000_I2C_DATA_OUT;
3181
3182         *i2cctl &= ~E1000_I2C_DATA_OE_N;
3183         *i2cctl |= E1000_I2C_CLK_OE_N;
3184         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3185         E1000_WRITE_FLUSH(hw);
3186
3187         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3188         usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3189
3190         *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3191         if (data != e1000_get_i2c_data(i2cctl)) {
3192                 status = E1000_ERR_I2C;
3193                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3194         }
3195
3196         return status;
3197 }
3198
3199 /**
3200  *  e1000_get_i2c_data - Reads the I2C SDA data bit
3201  *  @hw: pointer to hardware structure
3202  *  @i2cctl: Current value of I2CCTL register
3203  *
3204  *  Returns the I2C data bit value
3205  **/
3206 static bool e1000_get_i2c_data(u32 *i2cctl)
3207 {
3208         bool data;
3209
3210         DEBUGFUNC("e1000_get_i2c_data");
3211
3212         if (*i2cctl & E1000_I2C_DATA_IN)
3213                 data = 1;
3214         else
3215                 data = 0;
3216
3217         return data;
3218 }
3219
3220 /**
3221  *  e1000_i2c_bus_clear - Clears the I2C bus
3222  *  @hw: pointer to hardware structure
3223  *
3224  *  Clears the I2C bus by sending nine clock pulses.
3225  *  Used when data line is stuck low.
3226  **/
3227 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3228 {
3229         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3230         u32 i;
3231
3232         DEBUGFUNC("e1000_i2c_bus_clear");
3233
3234         e1000_i2c_start(hw);
3235
3236         e1000_set_i2c_data(hw, &i2cctl, 1);
3237
3238         for (i = 0; i < 9; i++) {
3239                 e1000_raise_i2c_clk(hw, &i2cctl);
3240
3241                 /* Min high period of clock is 4us */
3242                 usec_delay(E1000_I2C_T_HIGH);
3243
3244                 e1000_lower_i2c_clk(hw, &i2cctl);
3245
3246                 /* Min low period of clock is 4.7us*/
3247                 usec_delay(E1000_I2C_T_LOW);
3248         }
3249
3250         e1000_i2c_start(hw);
3251
3252         /* Put the i2c bus back to default state */
3253         e1000_i2c_stop(hw);
3254 }
3255
3256 static const u8 e1000_emc_temp_data[4] = {
3257         E1000_EMC_INTERNAL_DATA,
3258         E1000_EMC_DIODE1_DATA,
3259         E1000_EMC_DIODE2_DATA,
3260         E1000_EMC_DIODE3_DATA
3261 };
3262 static const u8 e1000_emc_therm_limit[4] = {
3263         E1000_EMC_INTERNAL_THERM_LIMIT,
3264         E1000_EMC_DIODE1_THERM_LIMIT,
3265         E1000_EMC_DIODE2_THERM_LIMIT,
3266         E1000_EMC_DIODE3_THERM_LIMIT
3267 };
3268
3269 /**
3270  *  e1000_get_thermal_sensor_data_generic - Gathers thermal sensor data
3271  *  @hw: pointer to hardware structure
3272  *
3273  *  Updates the temperatures in mac.thermal_sensor_data
3274  **/
3275 s32 e1000_get_thermal_sensor_data_generic(struct e1000_hw *hw)
3276 {
3277         s32 status = E1000_SUCCESS;
3278         u16 ets_offset;
3279         u16 ets_cfg;
3280         u16 ets_sensor;
3281         u8  num_sensors;
3282         u8  sensor_index;
3283         u8  sensor_location;
3284         u8  i;
3285         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3286
3287         DEBUGFUNC("e1000_get_thermal_sensor_data_generic");
3288
3289         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
3290                 return E1000_NOT_IMPLEMENTED;
3291
3292         data->sensor[0].temp = (E1000_READ_REG(hw, E1000_THMJT) & 0xFF);
3293
3294         /* Return the internal sensor only if ETS is unsupported */
3295         e1000_read_nvm(hw, NVM_ETS_CFG, 1, &ets_offset);
3296         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
3297                 return status;
3298
3299         e1000_read_nvm(hw, ets_offset, 1, &ets_cfg);
3300         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
3301             != NVM_ETS_TYPE_EMC)
3302                 return E1000_NOT_IMPLEMENTED;
3303
3304         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
3305         if (num_sensors > E1000_MAX_SENSORS)
3306                 num_sensors = E1000_MAX_SENSORS;
3307
3308         for (i = 1; i < num_sensors; i++) {
3309                 e1000_read_nvm(hw, (ets_offset + i), 1, &ets_sensor);
3310                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
3311                                 NVM_ETS_DATA_INDEX_SHIFT);
3312                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
3313                                    NVM_ETS_DATA_LOC_SHIFT);
3314
3315                 if (sensor_location != 0)
3316                         hw->phy.ops.read_i2c_byte(hw,
3317                                         e1000_emc_temp_data[sensor_index],
3318                                         E1000_I2C_THERMAL_SENSOR_ADDR,
3319                                         &data->sensor[i].temp);
3320         }
3321         return status;
3322 }
3323
3324 /**
3325  *  e1000_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
3326  *  @hw: pointer to hardware structure
3327  *
3328  *  Sets the thermal sensor thresholds according to the NVM map
3329  *  and save off the threshold and location values into mac.thermal_sensor_data
3330  **/
3331 s32 e1000_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
3332 {
3333         s32 status = E1000_SUCCESS;
3334         u16 ets_offset;
3335         u16 ets_cfg;
3336         u16 ets_sensor;
3337         u8  low_thresh_delta;
3338         u8  num_sensors;
3339         u8  sensor_index;
3340         u8  sensor_location;
3341         u8  therm_limit;
3342         u8  i;
3343         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3344
3345         DEBUGFUNC("e1000_init_thermal_sensor_thresh_generic");
3346
3347         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
3348                 return E1000_NOT_IMPLEMENTED;
3349
3350         memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
3351
3352         data->sensor[0].location = 0x1;
3353         data->sensor[0].caution_thresh =
3354                 (E1000_READ_REG(hw, E1000_THHIGHTC) & 0xFF);
3355         data->sensor[0].max_op_thresh =
3356                 (E1000_READ_REG(hw, E1000_THLOWTC) & 0xFF);
3357
3358         /* Return the internal sensor only if ETS is unsupported */
3359         e1000_read_nvm(hw, NVM_ETS_CFG, 1, &ets_offset);
3360         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
3361                 return status;
3362
3363         e1000_read_nvm(hw, ets_offset, 1, &ets_cfg);
3364         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
3365             != NVM_ETS_TYPE_EMC)
3366                 return E1000_NOT_IMPLEMENTED;
3367
3368         low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
3369                             NVM_ETS_LTHRES_DELTA_SHIFT);
3370         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
3371
3372         for (i = 1; i <= num_sensors; i++) {
3373                 e1000_read_nvm(hw, (ets_offset + i), 1, &ets_sensor);
3374                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
3375                                 NVM_ETS_DATA_INDEX_SHIFT);
3376                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
3377                                    NVM_ETS_DATA_LOC_SHIFT);
3378                 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
3379
3380                 hw->phy.ops.write_i2c_byte(hw,
3381                         e1000_emc_therm_limit[sensor_index],
3382                         E1000_I2C_THERMAL_SENSOR_ADDR,
3383                         therm_limit);
3384
3385                 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
3386                         data->sensor[i].location = sensor_location;
3387                         data->sensor[i].caution_thresh = therm_limit;
3388                         data->sensor[i].max_op_thresh = therm_limit -
3389                                                         low_thresh_delta;
3390                 }
3391         }
3392         return status;
3393 }