lib/librte_pmd_e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 #define EM_EIAC                 0x000DC
  61
  62 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  63
  64
  65 static int eth_em_configure(struct rte_eth_dev *dev);
  66 static int eth_em_start(struct rte_eth_dev *dev);
  67 static void eth_em_stop(struct rte_eth_dev *dev);
  68 static void eth_em_close(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  70 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  72 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  73 static int eth_em_link_update(struct rte_eth_dev *dev,
  74                                 int wait_to_complete);
  75 static void eth_em_stats_get(struct rte_eth_dev *dev,
  76                                 struct rte_eth_stats *rte_stats);
  77 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  78 static void eth_em_infos_get(struct rte_eth_dev *dev,
  79                                 struct rte_eth_dev_info *dev_info);
  80 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  81                                 struct rte_eth_fc_conf *fc_conf);
  82 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  83                                 struct rte_eth_fc_conf *fc_conf);
  84 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  86 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
  87 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  88                                                         void *param);
  89
  90 static int em_hw_init(struct e1000_hw *hw);
  91 static int em_hardware_init(struct e1000_hw *hw);
  92 static void em_hw_control_acquire(struct e1000_hw *hw);
  93 static void em_hw_control_release(struct e1000_hw *hw);
  94 static void em_init_manageability(struct e1000_hw *hw);
  95 static void em_release_manageability(struct e1000_hw *hw);
  96
  97 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  98
  99 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 100                 uint16_t vlan_id, int on);
 101 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 102 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 103 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 104 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 105 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 106
 107 /*
 108 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 109                                         uint16_t vlan_id, int on);
 110 */
 111 static int eth_em_led_on(struct rte_eth_dev *dev);
 112 static int eth_em_led_off(struct rte_eth_dev *dev);
 113
 114 static void em_intr_disable(struct e1000_hw *hw);
 115 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 116 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 117                 uint32_t index, uint32_t pool);
 118 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 119
 120 #define EM_FC_PAUSE_TIME 0x0680
 121 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 122 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 123
 124 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 125
 126 /*
 127  * The set of PCI devices this driver supports
 128  */
 129 static struct rte_pci_id pci_id_em_map[] = {
 130
 131 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 132 #include "rte_pci_dev_ids.h"
 133
 134 {.device_id = 0},
 135 };
 136
 137 static struct eth_dev_ops eth_em_ops = {
 138         .dev_configure        = eth_em_configure,
 139         .dev_start            = eth_em_start,
 140         .dev_stop             = eth_em_stop,
 141         .dev_close            = eth_em_close,
 142         .promiscuous_enable   = eth_em_promiscuous_enable,
 143         .promiscuous_disable  = eth_em_promiscuous_disable,
 144         .allmulticast_enable  = eth_em_allmulticast_enable,
 145         .allmulticast_disable = eth_em_allmulticast_disable,
 146         .link_update          = eth_em_link_update,
 147         .stats_get            = eth_em_stats_get,
 148         .stats_reset          = eth_em_stats_reset,
 149         .dev_infos_get        = eth_em_infos_get,
 150         .mtu_set              = eth_em_mtu_set,
 151         .vlan_filter_set      = eth_em_vlan_filter_set,
 152         .vlan_offload_set     = eth_em_vlan_offload_set,
 153         .rx_queue_setup       = eth_em_rx_queue_setup,
 154         .rx_queue_release     = eth_em_rx_queue_release,
 155         .rx_queue_count       = eth_em_rx_queue_count,
 156         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 157         .tx_queue_setup       = eth_em_tx_queue_setup,
 158         .tx_queue_release     = eth_em_tx_queue_release,
 159         .dev_led_on           = eth_em_led_on,
 160         .dev_led_off          = eth_em_led_off,
 161         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 162         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 163         .mac_addr_add         = eth_em_rar_set,
 164         .mac_addr_remove      = eth_em_rar_clear,
 165 };
 166
 167 /**
 168  * Atomically reads the link status information from global
 169  * structure rte_eth_dev.
 170  *
 171  * @param dev
 172  *   - Pointer to the structure rte_eth_dev to read from.
 173  *   - Pointer to the buffer to be saved with the link status.
 174  *
 175  * @return
 176  *   - On success, zero.
 177  *   - On failure, negative value.
 178  */
 179 static inline int
 180 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 181                                 struct rte_eth_link *link)
 182 {
 183         struct rte_eth_link *dst = link;
 184         struct rte_eth_link *src = &(dev->data->dev_link);
 185
 186         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 187                                         *(uint64_t *)src) == 0)
 188                 return -1;
 189
 190         return 0;
 191 }
 192
 193 /**
 194  * Atomically writes the link status information into global
 195  * structure rte_eth_dev.
 196  *
 197  * @param dev
 198  *   - Pointer to the structure rte_eth_dev to read from.
 199  *   - Pointer to the buffer to be saved with the link status.
 200  *
 201  * @return
 202  *   - On success, zero.
 203  *   - On failure, negative value.
 204  */
 205 static inline int
 206 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 207                                 struct rte_eth_link *link)
 208 {
 209         struct rte_eth_link *dst = &(dev->data->dev_link);
 210         struct rte_eth_link *src = link;
 211
 212         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 213                                         *(uint64_t *)src) == 0)
 214                 return -1;
 215
 216         return 0;
 217 }
 218
 219 static int
 220 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 221 {
 222         struct rte_pci_device *pci_dev;
 223         struct e1000_hw *hw =
 224                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 225         struct e1000_vfta * shadow_vfta =
 226                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 227
 228         pci_dev = eth_dev->pci_dev;
 229         eth_dev->dev_ops = &eth_em_ops;
 230         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 231         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 232
 233         /* for secondary processes, we don't initialise any further as primary
 234          * has already done this work. Only check we don't need a different
 235          * RX function */
 236         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 237                 if (eth_dev->data->scattered_rx)
 238                         eth_dev->rx_pkt_burst =
 239                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 240                 return 0;
 241         }
 242
 243         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 244         hw->device_id = pci_dev->id.device_id;
 245
 246         /* For ICH8 support we'll need to map the flash memory BAR */
 247
 248         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 249                         em_hw_init(hw) != 0) {
 250                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 251                         "failed to init HW",
 252                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 253                         pci_dev->id.device_id);
 254                 return -(ENODEV);
 255         }
 256
 257         /* Allocate memory for storing MAC addresses */
 258         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 259                         hw->mac.rar_entry_count, 0);
 260         if (eth_dev->data->mac_addrs == NULL) {
 261                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 262                         "store MAC addresses",
 263                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 264                 return -(ENOMEM);
 265         }
 266
 267         /* Copy the permanent MAC address */
 268         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 269                 eth_dev->data->mac_addrs);
 270
 271         /* initialize the vfta */
 272         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 273
 274         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
 275                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 276                      pci_dev->id.device_id);
 277
 278         rte_intr_callback_register(&(pci_dev->intr_handle),
 279                 eth_em_interrupt_handler, (void *)eth_dev);
 280
 281         return (0);
 282 }
 283
 284 static struct eth_driver rte_em_pmd = {
 285         {
 286                 .name = "rte_em_pmd",
 287                 .id_table = pci_id_em_map,
 288                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 289         },
 290         .eth_dev_init = eth_em_dev_init,
 291         .dev_private_size = sizeof(struct e1000_adapter),
 292 };
 293
 294 static int
 295 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 296 {
 297         rte_eth_driver_register(&rte_em_pmd);
 298         return 0;
 299 }
 300
 301 static int
 302 em_hw_init(struct e1000_hw *hw)
 303 {
 304         int diag;
 305
 306         diag = hw->mac.ops.init_params(hw);
 307         if (diag != 0) {
 308                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 309                 return diag;
 310         }
 311         diag = hw->nvm.ops.init_params(hw);
 312         if (diag != 0) {
 313                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 314                 return diag;
 315         }
 316         diag = hw->phy.ops.init_params(hw);
 317         if (diag != 0) {
 318                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 319                 return diag;
 320         }
 321         (void) e1000_get_bus_info(hw);
 322
 323         hw->mac.autoneg = 1;
 324         hw->phy.autoneg_wait_to_complete = 0;
 325         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 326
 327         e1000_init_script_state_82541(hw, TRUE);
 328         e1000_set_tbi_compatibility_82543(hw, TRUE);
 329
 330         /* Copper options */
 331         if (hw->phy.media_type == e1000_media_type_copper) {
 332                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 333                 hw->phy.disable_polarity_correction = 0;
 334                 hw->phy.ms_type = e1000_ms_hw_default;
 335         }
 336
 337         /*
 338          * Start from a known state, this is important in reading the nvm
 339          * and mac from that.
 340          */
 341         e1000_reset_hw(hw);
 342
 343         /* Make sure we have a good EEPROM before we read from it */
 344         if (e1000_validate_nvm_checksum(hw) < 0) {
 345                 /*
 346                  * Some PCI-E parts fail the first check due to
 347                  * the link being in sleep state, call it again,
 348                  * if it fails a second time its a real issue.
 349                  */
 350                 diag = e1000_validate_nvm_checksum(hw);
 351                 if (diag < 0) {
 352                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 353                         goto error;
 354                 }
 355         }
 356
 357         /* Read the permanent MAC address out of the EEPROM */
 358         diag = e1000_read_mac_addr(hw);
 359         if (diag != 0) {
 360                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 361                 goto error;
 362         }
 363
 364         /* Now initialize the hardware */
 365         diag = em_hardware_init(hw);
 366         if (diag != 0) {
 367                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 368                 goto error;
 369         }
 370
 371         hw->mac.get_link_status = 1;
 372
 373         /* Indicate SOL/IDER usage */
 374         diag = e1000_check_reset_block(hw);
 375         if (diag < 0) {
 376                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 377                         "SOL/IDER session");
 378         }
 379         return (0);
 380
 381 error:
 382         em_hw_control_release(hw);
 383         return (diag);
 384 }
 385
 386 static int
 387 eth_em_configure(struct rte_eth_dev *dev)
 388 {
 389         struct e1000_interrupt *intr =
 390                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 391
 392         PMD_INIT_FUNC_TRACE();
 393         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 394         PMD_INIT_FUNC_TRACE();
 395
 396         return (0);
 397 }
 398
 399 static void
 400 em_set_pba(struct e1000_hw *hw)
 401 {
 402         uint32_t pba;
 403
 404         /*
 405          * Packet Buffer Allocation (PBA)
 406          * Writing PBA sets the receive portion of the buffer
 407          * the remainder is used for the transmit buffer.
 408          * Devices before the 82547 had a Packet Buffer of 64K.
 409          * After the 82547 the buffer was reduced to 40K.
 410          */
 411         switch (hw->mac.type) {
 412                 case e1000_82547:
 413                 case e1000_82547_rev_2:
 414                 /* 82547: Total Packet Buffer is 40K */
 415                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 416                         break;
 417                 case e1000_82571:
 418                 case e1000_82572:
 419                 case e1000_80003es2lan:
 420                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 421                         break;
 422                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 423                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 424                         break;
 425                 case e1000_82574:
 426                 case e1000_82583:
 427                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 428                         break;
 429                 case e1000_ich8lan:
 430                         pba = E1000_PBA_8K;
 431                         break;
 432                 case e1000_ich9lan:
 433                 case e1000_ich10lan:
 434                         pba = E1000_PBA_10K;
 435                         break;
 436                 case e1000_pchlan:
 437                 case e1000_pch2lan:
 438                         pba = E1000_PBA_26K;
 439                         break;
 440                 default:
 441                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 442         }
 443
 444         E1000_WRITE_REG(hw, E1000_PBA, pba);
 445 }
 446
 447 static int
 448 eth_em_start(struct rte_eth_dev *dev)
 449 {
 450         struct e1000_hw *hw =
 451                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 452         int ret, mask;
 453
 454         PMD_INIT_FUNC_TRACE();
 455
 456         eth_em_stop(dev);
 457
 458         e1000_power_up_phy(hw);
 459
 460         /* Set default PBA value */
 461         em_set_pba(hw);
 462
 463         /* Put the address into the Receive Address Array */
 464         e1000_rar_set(hw, hw->mac.addr, 0);
 465
 466         /*
 467          * With the 82571 adapter, RAR[0] may be overwritten
 468          * when the other port is reset, we make a duplicate
 469          * in RAR[14] for that eventuality, this assures
 470          * the interface continues to function.
 471          */
 472         if (hw->mac.type == e1000_82571) {
 473                 e1000_set_laa_state_82571(hw, TRUE);
 474                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 475         }
 476
 477         /* Initialize the hardware */
 478         if (em_hardware_init(hw)) {
 479                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 480                 return (-EIO);
 481         }
 482
 483         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 484
 485         /* Configure for OS presence */
 486         em_init_manageability(hw);
 487
 488         eth_em_tx_init(dev);
 489
 490         ret = eth_em_rx_init(dev);
 491         if (ret) {
 492                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 493                 em_dev_clear_queues(dev);
 494                 return ret;
 495         }
 496
 497         e1000_clear_hw_cntrs_base_generic(hw);
 498
 499         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 500                         ETH_VLAN_EXTEND_MASK;
 501         eth_em_vlan_offload_set(dev, mask);
 502
 503         /* Set Interrupt Throttling Rate to maximum allowed value. */
 504         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 505
 506         /* Setup link speed and duplex */
 507         switch (dev->data->dev_conf.link_speed) {
 508         case ETH_LINK_SPEED_AUTONEG:
 509                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 510                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 511                 else if (dev->data->dev_conf.link_duplex ==
 512                                         ETH_LINK_HALF_DUPLEX)
 513                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 514                 else if (dev->data->dev_conf.link_duplex ==
 515                                         ETH_LINK_FULL_DUPLEX)
 516                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 517                 else
 518                         goto error_invalid_config;
 519                 break;
 520         case ETH_LINK_SPEED_10:
 521                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 522                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 523                 else if (dev->data->dev_conf.link_duplex ==
 524                                         ETH_LINK_HALF_DUPLEX)
 525                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 526                 else if (dev->data->dev_conf.link_duplex ==
 527                                         ETH_LINK_FULL_DUPLEX)
 528                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 529                 else
 530                         goto error_invalid_config;
 531                 break;
 532         case ETH_LINK_SPEED_100:
 533                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 534                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 535                 else if (dev->data->dev_conf.link_duplex ==
 536                                         ETH_LINK_HALF_DUPLEX)
 537                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 538                 else if (dev->data->dev_conf.link_duplex ==
 539                                         ETH_LINK_FULL_DUPLEX)
 540                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 541                 else
 542                         goto error_invalid_config;
 543                 break;
 544         case ETH_LINK_SPEED_1000:
 545                 if ((dev->data->dev_conf.link_duplex ==
 546                                 ETH_LINK_AUTONEG_DUPLEX) ||
 547                         (dev->data->dev_conf.link_duplex ==
 548                                         ETH_LINK_FULL_DUPLEX))
 549                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 550                 else
 551                         goto error_invalid_config;
 552                 break;
 553         case ETH_LINK_SPEED_10000:
 554         default:
 555                 goto error_invalid_config;
 556         }
 557         e1000_setup_link(hw);
 558
 559         /* check if lsc interrupt feature is enabled */
 560         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 561                 ret = eth_em_interrupt_setup(dev);
 562                 if (ret) {
 563                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 564                         em_dev_clear_queues(dev);
 565                         return ret;
 566                 }
 567         }
 568
 569         PMD_INIT_LOG(DEBUG, "<<");
 570
 571         return (0);
 572
 573 error_invalid_config:
 574         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 575                      dev->data->dev_conf.link_speed,
 576                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 577         em_dev_clear_queues(dev);
 578         return (-EINVAL);
 579 }
 580
 581 /*********************************************************************
 582  *
 583  *  This routine disables all traffic on the adapter by issuing a
 584  *  global reset on the MAC.
 585  *
 586  **********************************************************************/
 587 static void
 588 eth_em_stop(struct rte_eth_dev *dev)
 589 {
 590         struct rte_eth_link link;
 591         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 592
 593         em_intr_disable(hw);
 594         e1000_reset_hw(hw);
 595         if (hw->mac.type >= e1000_82544)
 596                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 597
 598         /* Power down the phy. Needed to make the link go down */
 599         e1000_power_down_phy(hw);
 600
 601         em_dev_clear_queues(dev);
 602
 603         /* clear the recorded link status */
 604         memset(&link, 0, sizeof(link));
 605         rte_em_dev_atomic_write_link_status(dev, &link);
 606 }
 607
 608 static void
 609 eth_em_close(struct rte_eth_dev *dev)
 610 {
 611         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 612
 613         eth_em_stop(dev);
 614         e1000_phy_hw_reset(hw);
 615         em_release_manageability(hw);
 616         em_hw_control_release(hw);
 617 }
 618
 619 static int
 620 em_get_rx_buffer_size(struct e1000_hw *hw)
 621 {
 622         uint32_t rx_buf_size;
 623
 624         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 625         return rx_buf_size;
 626 }
 627
 628 /*********************************************************************
 629  *
 630  *  Initialize the hardware
 631  *
 632  **********************************************************************/
 633 static int
 634 em_hardware_init(struct e1000_hw *hw)
 635 {
 636         uint32_t rx_buf_size;
 637         int diag;
 638
 639         /* Issue a global reset */
 640         e1000_reset_hw(hw);
 641
 642         /* Let the firmware know the OS is in control */
 643         em_hw_control_acquire(hw);
 644
 645         /*
 646          * These parameters control the automatic generation (Tx) and
 647          * response (Rx) to Ethernet PAUSE frames.
 648          * - High water mark should allow for at least two standard size (1518)
 649          *   frames to be received after sending an XOFF.
 650          * - Low water mark works best when it is very near the high water mark.
 651          *   This allows the receiver to restart by sending XON when it has
 652          *   drained a bit. Here we use an arbitrary value of 1500 which will
 653          *   restart after one full frame is pulled from the buffer. There
 654          *   could be several smaller frames in the buffer and if so they will
 655          *   not trigger the XON until their total number reduces the buffer
 656          *   by 1500.
 657          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 658          */
 659         rx_buf_size = em_get_rx_buffer_size(hw);
 660
 661         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 662         hw->fc.low_water = hw->fc.high_water - 1500;
 663
 664         if (hw->mac.type == e1000_80003es2lan)
 665                 hw->fc.pause_time = UINT16_MAX;
 666         else
 667                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 668
 669         hw->fc.send_xon = 1;
 670
 671         /* Set Flow control, use the tunable location if sane */
 672         if (em_fc_setting <= e1000_fc_full)
 673                 hw->fc.requested_mode = em_fc_setting;
 674         else
 675                 hw->fc.requested_mode = e1000_fc_none;
 676
 677         /* Workaround: no TX flow ctrl for PCH */
 678         if (hw->mac.type == e1000_pchlan)
 679                 hw->fc.requested_mode = e1000_fc_rx_pause;
 680
 681         /* Override - settings for PCH2LAN, ya its magic :) */
 682         if (hw->mac.type == e1000_pch2lan) {
 683                 hw->fc.high_water = 0x5C20;
 684                 hw->fc.low_water = 0x5048;
 685                 hw->fc.pause_time = 0x0650;
 686                 hw->fc.refresh_time = 0x0400;
 687         }
 688
 689         diag = e1000_init_hw(hw);
 690         if (diag < 0)
 691                 return (diag);
 692         e1000_check_for_link(hw);
 693         return (0);
 694 }
 695
 696 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 697 static void
 698 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 699 {
 700         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 701         struct e1000_hw_stats *stats =
 702                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 703         int pause_frames;
 704
 705         if(hw->phy.media_type == e1000_media_type_copper ||
 706                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 707                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 708                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 709         }
 710
 711         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 712         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 713         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 714         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 715
 716         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 717         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 718         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 719         stats->dc += E1000_READ_REG(hw, E1000_DC);
 720         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 721         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 722         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 723
 724         /*
 725          * For watchdog management we need to know if we have been
 726          * paused during the last interval, so capture that here.
 727          */
 728         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 729         stats->xoffrxc += pause_frames;
 730         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 731         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 732         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 733         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 734         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 735         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 736         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 737         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 738         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 739         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 740         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 741         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 742
 743         /*
 744          * For the 64-bit byte counters the low dword must be read first.
 745          * Both registers clear on the read of the high dword.
 746          */
 747
 748         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 749         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 750         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 751         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 752
 753         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 754         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 755         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 756         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 757         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 758
 759         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 760         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 761
 762         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 763         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 764         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 765         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 766         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 767         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 768         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 769         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 770         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 771         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 772
 773         /* Interrupt Counts */
 774
 775         if (hw->mac.type >= e1000_82571) {
 776                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 777                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 778                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 779                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 780                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 781                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 782                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 783                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 784                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 785         }
 786
 787         if (hw->mac.type >= e1000_82543) {
 788                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 789                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 790                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 791                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 792                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 793                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 794         }
 795
 796         if (rte_stats == NULL)
 797                 return;
 798
 799         /* Rx Errors */
 800         rte_stats->ibadcrc = stats->crcerrs;
 801         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
 802         rte_stats->imissed = stats->mpc;
 803         rte_stats->ierrors = rte_stats->ibadcrc +
 804                              rte_stats->ibadlen +
 805                              rte_stats->imissed +
 806                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 807
 808         /* Tx Errors */
 809         rte_stats->oerrors = stats->ecol + stats->latecol;
 810
 811         rte_stats->ipackets = stats->gprc;
 812         rte_stats->opackets = stats->gptc;
 813         rte_stats->ibytes   = stats->gorc;
 814         rte_stats->obytes   = stats->gotc;
 815
 816         /* XON/XOFF pause frames stats registers */
 817         rte_stats->tx_pause_xon  = stats->xontxc;
 818         rte_stats->rx_pause_xon  = stats->xonrxc;
 819         rte_stats->tx_pause_xoff = stats->xofftxc;
 820         rte_stats->rx_pause_xoff = stats->xoffrxc;
 821 }
 822
 823 static void
 824 eth_em_stats_reset(struct rte_eth_dev *dev)
 825 {
 826         struct e1000_hw_stats *hw_stats =
 827                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 828
 829         /* HW registers are cleared on read */
 830         eth_em_stats_get(dev, NULL);
 831
 832         /* Reset software totals */
 833         memset(hw_stats, 0, sizeof(*hw_stats));
 834 }
 835
 836 static uint32_t
 837 em_get_max_pktlen(const struct e1000_hw *hw)
 838 {
 839         switch (hw->mac.type) {
 840         case e1000_82571:
 841         case e1000_82572:
 842         case e1000_ich9lan:
 843         case e1000_ich10lan:
 844         case e1000_pch2lan:
 845         case e1000_82574:
 846         case e1000_80003es2lan: /* 9K Jumbo Frame size */
 847                 return (0x2412);
 848         case e1000_pchlan:
 849                 return (0x1000);
 850         /* Adapters that do not support jumbo frames */
 851         case e1000_82583:
 852         case e1000_ich8lan:
 853                 return (ETHER_MAX_LEN);
 854         default:
 855                 return (MAX_JUMBO_FRAME_SIZE);
 856         }
 857 }
 858
 859 static void
 860 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 861 {
 862         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 863
 864         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
 865         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
 866         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
 867
 868         /*
 869          * Starting with 631xESB hw supports 2 TX/RX queues per port.
 870          * Unfortunatelly, all these nics have just one TX context.
 871          * So we have few choises for TX:
 872          * - Use just one TX queue.
 873          * - Allow cksum offload only for one TX queue.
 874          * - Don't allow TX cksum offload at all.
 875          * For now, option #1 was chosen.
 876          * To use second RX queue we have to use extended RX descriptor
 877          * (Multiple Receive Queues are mutually exclusive with UDP
 878          * fragmentation and are not supported when a legacy receive
 879          * descriptor format is used).
 880          * Which means separate RX routinies - as legacy nics (82540, 82545)
 881          * don't support extended RXD.
 882          * To avoid it we support just one RX queue for now (no RSS).
 883          */
 884
 885         dev_info->max_rx_queues = 1;
 886         dev_info->max_tx_queues = 1;
 887 }
 888
 889 /* return 0 means link status changed, -1 means not changed */
 890 static int
 891 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 892 {
 893         struct e1000_hw *hw =
 894                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 895         struct rte_eth_link link, old;
 896         int link_check, count;
 897
 898         link_check = 0;
 899         hw->mac.get_link_status = 1;
 900
 901         /* possible wait-to-complete in up to 9 seconds */
 902         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
 903                 /* Read the real link status */
 904                 switch (hw->phy.media_type) {
 905                 case e1000_media_type_copper:
 906                         /* Do the work to read phy */
 907                         e1000_check_for_link(hw);
 908                         link_check = !hw->mac.get_link_status;
 909                         break;
 910
 911                 case e1000_media_type_fiber:
 912                         e1000_check_for_link(hw);
 913                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
 914                                         E1000_STATUS_LU);
 915                         break;
 916
 917                 case e1000_media_type_internal_serdes:
 918                         e1000_check_for_link(hw);
 919                         link_check = hw->mac.serdes_has_link;
 920                         break;
 921
 922                 default:
 923                         break;
 924                 }
 925                 if (link_check || wait_to_complete == 0)
 926                         break;
 927                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
 928         }
 929         memset(&link, 0, sizeof(link));
 930         rte_em_dev_atomic_read_link_status(dev, &link);
 931         old = link;
 932
 933         /* Now we check if a transition has happened */
 934         if (link_check && (link.link_status == 0)) {
 935                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
 936                         &link.link_duplex);
 937                 link.link_status = 1;
 938         } else if (!link_check && (link.link_status == 1)) {
 939                 link.link_speed = 0;
 940                 link.link_duplex = 0;
 941                 link.link_status = 0;
 942         }
 943         rte_em_dev_atomic_write_link_status(dev, &link);
 944
 945         /* not changed */
 946         if (old.link_status == link.link_status)
 947                 return -1;
 948
 949         /* changed */
 950         return 0;
 951 }
 952
 953 /*
 954  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
 955  * For ASF and Pass Through versions of f/w this means
 956  * that the driver is loaded. For AMT version type f/w
 957  * this means that the network i/f is open.
 958  */
 959 static void
 960 em_hw_control_acquire(struct e1000_hw *hw)
 961 {
 962         uint32_t ctrl_ext, swsm;
 963
 964         /* Let firmware know the driver has taken over */
 965         if (hw->mac.type == e1000_82573) {
 966                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 967                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
 968
 969         } else {
 970                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 971                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 972                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 973         }
 974 }
 975
 976 /*
 977  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
 978  * For ASF and Pass Through versions of f/w this means that the
 979  * driver is no longer loaded. For AMT versions of the
 980  * f/w this means that the network i/f is closed.
 981  */
 982 static void
 983 em_hw_control_release(struct e1000_hw *hw)
 984 {
 985         uint32_t ctrl_ext, swsm;
 986
 987         /* Let firmware taken over control of h/w */
 988         if (hw->mac.type == e1000_82573) {
 989                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 990                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
 991         } else {
 992                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 993                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 994                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 995         }
 996 }
 997
 998 /*
 999  * Bit of a misnomer, what this really means is
1000  * to enable OS management of the system... aka
1001  * to disable special hardware management features.
1002  */
1003 static void
1004 em_init_manageability(struct e1000_hw *hw)
1005 {
1006         if (e1000_enable_mng_pass_thru(hw)) {
1007                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1008                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1009
1010                 /* disable hardware interception of ARP */
1011                 manc &= ~(E1000_MANC_ARP_EN);
1012
1013                 /* enable receiving management packets to the host */
1014                 manc |= E1000_MANC_EN_MNG2HOST;
1015                 manc2h |= 1 << 5;  /* Mng Port 623 */
1016                 manc2h |= 1 << 6;  /* Mng Port 664 */
1017                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1018                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1019         }
1020 }
1021
1022 /*
1023  * Give control back to hardware management
1024  * controller if there is one.
1025  */
1026 static void
1027 em_release_manageability(struct e1000_hw *hw)
1028 {
1029         uint32_t manc;
1030
1031         if (e1000_enable_mng_pass_thru(hw)) {
1032                 manc = E1000_READ_REG(hw, E1000_MANC);
1033
1034                 /* re-enable hardware interception of ARP */
1035                 manc |= E1000_MANC_ARP_EN;
1036                 manc &= ~E1000_MANC_EN_MNG2HOST;
1037
1038                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1039         }
1040 }
1041
1042 static void
1043 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1044 {
1045         struct e1000_hw *hw =
1046                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1047         uint32_t rctl;
1048
1049         rctl = E1000_READ_REG(hw, E1000_RCTL);
1050         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1051         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1052 }
1053
1054 static void
1055 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1056 {
1057         struct e1000_hw *hw =
1058                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1059         uint32_t rctl;
1060
1061         rctl = E1000_READ_REG(hw, E1000_RCTL);
1062         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1063         if (dev->data->all_multicast == 1)
1064                 rctl |= E1000_RCTL_MPE;
1065         else
1066                 rctl &= (~E1000_RCTL_MPE);
1067         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1068 }
1069
1070 static void
1071 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1072 {
1073         struct e1000_hw *hw =
1074                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1075         uint32_t rctl;
1076
1077         rctl = E1000_READ_REG(hw, E1000_RCTL);
1078         rctl |= E1000_RCTL_MPE;
1079         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1080 }
1081
1082 static void
1083 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1084 {
1085         struct e1000_hw *hw =
1086                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1087         uint32_t rctl;
1088
1089         if (dev->data->promiscuous == 1)
1090                 return; /* must remain in all_multicast mode */
1091         rctl = E1000_READ_REG(hw, E1000_RCTL);
1092         rctl &= (~E1000_RCTL_MPE);
1093         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1094 }
1095
1096 static int
1097 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1098 {
1099         struct e1000_hw *hw =
1100                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1101         struct e1000_vfta * shadow_vfta =
1102                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1103         uint32_t vfta;
1104         uint32_t vid_idx;
1105         uint32_t vid_bit;
1106
1107         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1108                               E1000_VFTA_ENTRY_MASK);
1109         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1110         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1111         if (on)
1112                 vfta |= vid_bit;
1113         else
1114                 vfta &= ~vid_bit;
1115         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1116
1117         /* update local VFTA copy */
1118         shadow_vfta->vfta[vid_idx] = vfta;
1119
1120         return 0;
1121 }
1122
1123 static void
1124 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1125 {
1126         struct e1000_hw *hw =
1127                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1128         uint32_t reg;
1129
1130         /* Filter Table Disable */
1131         reg = E1000_READ_REG(hw, E1000_RCTL);
1132         reg &= ~E1000_RCTL_CFIEN;
1133         reg &= ~E1000_RCTL_VFE;
1134         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1135 }
1136
1137 static void
1138 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1139 {
1140         struct e1000_hw *hw =
1141                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1142         struct e1000_vfta * shadow_vfta =
1143                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1144         uint32_t reg;
1145         int i;
1146
1147         /* Filter Table Enable, CFI not used for packet acceptance */
1148         reg = E1000_READ_REG(hw, E1000_RCTL);
1149         reg &= ~E1000_RCTL_CFIEN;
1150         reg |= E1000_RCTL_VFE;
1151         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1152
1153         /* restore vfta from local copy */
1154         for (i = 0; i < IGB_VFTA_SIZE; i++)
1155                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1156 }
1157
1158 static void
1159 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1160 {
1161         struct e1000_hw *hw =
1162                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1163         uint32_t reg;
1164
1165         /* VLAN Mode Disable */
1166         reg = E1000_READ_REG(hw, E1000_CTRL);
1167         reg &= ~E1000_CTRL_VME;
1168         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1169
1170 }
1171
1172 static void
1173 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1174 {
1175         struct e1000_hw *hw =
1176                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1177         uint32_t reg;
1178
1179         /* VLAN Mode Enable */
1180         reg = E1000_READ_REG(hw, E1000_CTRL);
1181         reg |= E1000_CTRL_VME;
1182         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1183 }
1184
1185 static void
1186 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1187 {
1188         if(mask & ETH_VLAN_STRIP_MASK){
1189                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1190                         em_vlan_hw_strip_enable(dev);
1191                 else
1192                         em_vlan_hw_strip_disable(dev);
1193         }
1194
1195         if(mask & ETH_VLAN_FILTER_MASK){
1196                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1197                         em_vlan_hw_filter_enable(dev);
1198                 else
1199                         em_vlan_hw_filter_disable(dev);
1200         }
1201 }
1202
1203 static void
1204 em_intr_disable(struct e1000_hw *hw)
1205 {
1206         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1207 }
1208
1209 /**
1210  * It enables the interrupt mask and then enable the interrupt.
1211  *
1212  * @param dev
1213  *  Pointer to struct rte_eth_dev.
1214  *
1215  * @return
1216  *  - On success, zero.
1217  *  - On failure, a negative value.
1218  */
1219 static int
1220 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1221 {
1222         struct e1000_hw *hw =
1223                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224
1225         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1226         rte_intr_enable(&(dev->pci_dev->intr_handle));
1227         return (0);
1228 }
1229
1230 /*
1231  * It reads ICR and gets interrupt causes, check it and set a bit flag
1232  * to update link status.
1233  *
1234  * @param dev
1235  *  Pointer to struct rte_eth_dev.
1236  *
1237  * @return
1238  *  - On success, zero.
1239  *  - On failure, a negative value.
1240  */
1241 static int
1242 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1243 {
1244         uint32_t icr;
1245         struct e1000_hw *hw =
1246                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1247         struct e1000_interrupt *intr =
1248                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1249
1250         /* read-on-clear nic registers here */
1251         icr = E1000_READ_REG(hw, E1000_ICR);
1252         if (icr & E1000_ICR_LSC) {
1253                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1254         }
1255
1256         return 0;
1257 }
1258
1259 /*
1260  * It executes link_update after knowing an interrupt is prsent.
1261  *
1262  * @param dev
1263  *  Pointer to struct rte_eth_dev.
1264  *
1265  * @return
1266  *  - On success, zero.
1267  *  - On failure, a negative value.
1268  */
1269 static int
1270 eth_em_interrupt_action(struct rte_eth_dev *dev)
1271 {
1272         struct e1000_hw *hw =
1273                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274         struct e1000_interrupt *intr =
1275                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1276         uint32_t tctl, rctl;
1277         struct rte_eth_link link;
1278         int ret;
1279
1280         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1281                 return -1;
1282
1283         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1284         rte_intr_enable(&(dev->pci_dev->intr_handle));
1285
1286         /* set get_link_status to check register later */
1287         hw->mac.get_link_status = 1;
1288         ret = eth_em_link_update(dev, 0);
1289
1290         /* check if link has changed */
1291         if (ret < 0)
1292                 return 0;
1293
1294         memset(&link, 0, sizeof(link));
1295         rte_em_dev_atomic_read_link_status(dev, &link);
1296         if (link.link_status) {
1297                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1298                              dev->data->port_id, (unsigned)link.link_speed,
1299                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1300                              "full-duplex" : "half-duplex");
1301         } else {
1302                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1303         }
1304         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1305                      dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1306                      dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1307         tctl = E1000_READ_REG(hw, E1000_TCTL);
1308         rctl = E1000_READ_REG(hw, E1000_RCTL);
1309         if (link.link_status) {
1310                 /* enable Tx/Rx */
1311                 tctl |= E1000_TCTL_EN;
1312                 rctl |= E1000_RCTL_EN;
1313         } else {
1314                 /* disable Tx/Rx */
1315                 tctl &= ~E1000_TCTL_EN;
1316                 rctl &= ~E1000_RCTL_EN;
1317         }
1318         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1319         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1320         E1000_WRITE_FLUSH(hw);
1321
1322         return 0;
1323 }
1324
1325 /**
1326  * Interrupt handler which shall be registered at first.
1327  *
1328  * @param handle
1329  *  Pointer to interrupt handle.
1330  * @param param
1331  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1332  *
1333  * @return
1334  *  void
1335  */
1336 static void
1337 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1338                                                         void *param)
1339 {
1340         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1341
1342         eth_em_interrupt_get_status(dev);
1343         eth_em_interrupt_action(dev);
1344         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1345 }
1346
1347 static int
1348 eth_em_led_on(struct rte_eth_dev *dev)
1349 {
1350         struct e1000_hw *hw;
1351
1352         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1353         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1354 }
1355
1356 static int
1357 eth_em_led_off(struct rte_eth_dev *dev)
1358 {
1359         struct e1000_hw *hw;
1360
1361         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1362         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1363 }
1364
1365 static int
1366 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1367 {
1368         struct e1000_hw *hw;
1369         uint32_t ctrl;
1370         int tx_pause;
1371         int rx_pause;
1372
1373         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1374         fc_conf->pause_time = hw->fc.pause_time;
1375         fc_conf->high_water = hw->fc.high_water;
1376         fc_conf->low_water = hw->fc.low_water;
1377         fc_conf->send_xon = hw->fc.send_xon;
1378         fc_conf->autoneg = hw->mac.autoneg;
1379
1380         /*
1381          * Return rx_pause and tx_pause status according to actual setting of
1382          * the TFCE and RFCE bits in the CTRL register.
1383          */
1384         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1385         if (ctrl & E1000_CTRL_TFCE)
1386                 tx_pause = 1;
1387         else
1388                 tx_pause = 0;
1389
1390         if (ctrl & E1000_CTRL_RFCE)
1391                 rx_pause = 1;
1392         else
1393                 rx_pause = 0;
1394
1395         if (rx_pause && tx_pause)
1396                 fc_conf->mode = RTE_FC_FULL;
1397         else if (rx_pause)
1398                 fc_conf->mode = RTE_FC_RX_PAUSE;
1399         else if (tx_pause)
1400                 fc_conf->mode = RTE_FC_TX_PAUSE;
1401         else
1402                 fc_conf->mode = RTE_FC_NONE;
1403
1404         return 0;
1405 }
1406
1407 static int
1408 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1409 {
1410         struct e1000_hw *hw;
1411         int err;
1412         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1413                 e1000_fc_none,
1414                 e1000_fc_rx_pause,
1415                 e1000_fc_tx_pause,
1416                 e1000_fc_full
1417         };
1418         uint32_t rx_buf_size;
1419         uint32_t max_high_water;
1420         uint32_t rctl;
1421
1422         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1423         if (fc_conf->autoneg != hw->mac.autoneg)
1424                 return -ENOTSUP;
1425         rx_buf_size = em_get_rx_buffer_size(hw);
1426         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1427
1428         /* At least reserve one Ethernet frame for watermark */
1429         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1430         if ((fc_conf->high_water > max_high_water) ||
1431             (fc_conf->high_water < fc_conf->low_water)) {
1432                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1433                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1434                 return (-EINVAL);
1435         }
1436
1437         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1438         hw->fc.pause_time     = fc_conf->pause_time;
1439         hw->fc.high_water     = fc_conf->high_water;
1440         hw->fc.low_water      = fc_conf->low_water;
1441         hw->fc.send_xon       = fc_conf->send_xon;
1442
1443         err = e1000_setup_link_generic(hw);
1444         if (err == E1000_SUCCESS) {
1445
1446                 /* check if we want to forward MAC frames - driver doesn't have native
1447                  * capability to do that, so we'll write the registers ourselves */
1448
1449                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1450
1451                 /* set or clear MFLCN.PMCF bit depending on configuration */
1452                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1453                         rctl |= E1000_RCTL_PMCF;
1454                 else
1455                         rctl &= ~E1000_RCTL_PMCF;
1456
1457                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1458                 E1000_WRITE_FLUSH(hw);
1459
1460                 return 0;
1461         }
1462
1463         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1464         return (-EIO);
1465 }
1466
1467 static void
1468 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1469                 uint32_t index, __rte_unused uint32_t pool)
1470 {
1471         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1472
1473         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1474 }
1475
1476 static void
1477 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1478 {
1479         uint8_t addr[ETHER_ADDR_LEN];
1480         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1481
1482         memset(addr, 0, sizeof(addr));
1483
1484         e1000_rar_set(hw, addr, index);
1485 }
1486
1487 static int
1488 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1489 {
1490         struct rte_eth_dev_info dev_info;
1491         struct e1000_hw *hw;
1492         uint32_t frame_size;
1493         uint32_t rctl;
1494
1495         eth_em_infos_get(dev, &dev_info);
1496         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1497
1498         /* check that mtu is within the allowed range */
1499         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1500                 return -EINVAL;
1501
1502         /* refuse mtu that requires the support of scattered packets when this
1503          * feature has not been enabled before. */
1504         if (!dev->data->scattered_rx &&
1505             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1506                 return -EINVAL;
1507
1508         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1509         rctl = E1000_READ_REG(hw, E1000_RCTL);
1510
1511         /* switch to jumbo mode if needed */
1512         if (frame_size > ETHER_MAX_LEN) {
1513                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1514                 rctl |= E1000_RCTL_LPE;
1515         } else {
1516                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1517                 rctl &= ~E1000_RCTL_LPE;
1518         }
1519         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1520
1521         /* update max frame size */
1522         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1523         return 0;
1524 }
1525
1526 struct rte_driver em_pmd_drv = {
1527         .type = PMD_PDEV,
1528         .init = rte_em_pmd_init,
1529 };
1530
1531 PMD_REGISTER_DRIVER(em_pmd_drv);