lib/librte_pmd_e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 #define EM_EIAC                 0x000DC
  61
  62 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  63
  64
  65 static int eth_em_configure(struct rte_eth_dev *dev);
  66 static int eth_em_start(struct rte_eth_dev *dev);
  67 static void eth_em_stop(struct rte_eth_dev *dev);
  68 static void eth_em_close(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  70 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  72 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  73 static int eth_em_link_update(struct rte_eth_dev *dev,
  74                                 int wait_to_complete);
  75 static void eth_em_stats_get(struct rte_eth_dev *dev,
  76                                 struct rte_eth_stats *rte_stats);
  77 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  78 static void eth_em_infos_get(struct rte_eth_dev *dev,
  79                                 struct rte_eth_dev_info *dev_info);
  80 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  81                                 struct rte_eth_fc_conf *fc_conf);
  82 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  83 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  84 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
  85 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  86                                                         void *param);
  87
  88 static int em_hw_init(struct e1000_hw *hw);
  89 static int em_hardware_init(struct e1000_hw *hw);
  90 static void em_hw_control_acquire(struct e1000_hw *hw);
  91 static void em_hw_control_release(struct e1000_hw *hw);
  92 static void em_init_manageability(struct e1000_hw *hw);
  93 static void em_release_manageability(struct e1000_hw *hw);
  94
  95 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  96                 uint16_t vlan_id, int on);
  97 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  98 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  99 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 100 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 101 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 102
 103 /*
 104 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 105                                         uint16_t vlan_id, int on);
 106 */
 107 static int eth_em_led_on(struct rte_eth_dev *dev);
 108 static int eth_em_led_off(struct rte_eth_dev *dev);
 109
 110 static void em_intr_disable(struct e1000_hw *hw);
 111 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 112 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 113                 uint32_t index, uint32_t pool);
 114 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 115
 116 #define EM_FC_PAUSE_TIME 0x0680
 117 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 118 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 119
 120 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 121
 122 /*
 123  * The set of PCI devices this driver supports
 124  */
 125 static struct rte_pci_id pci_id_em_map[] = {
 126
 127 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 128 #include "rte_pci_dev_ids.h"
 129
 130 {.device_id = 0},
 131 };
 132
 133 static struct eth_dev_ops eth_em_ops = {
 134         .dev_configure        = eth_em_configure,
 135         .dev_start            = eth_em_start,
 136         .dev_stop             = eth_em_stop,
 137         .dev_close            = eth_em_close,
 138         .promiscuous_enable   = eth_em_promiscuous_enable,
 139         .promiscuous_disable  = eth_em_promiscuous_disable,
 140         .allmulticast_enable  = eth_em_allmulticast_enable,
 141         .allmulticast_disable = eth_em_allmulticast_disable,
 142         .link_update          = eth_em_link_update,
 143         .stats_get            = eth_em_stats_get,
 144         .stats_reset          = eth_em_stats_reset,
 145         .dev_infos_get        = eth_em_infos_get,
 146         .vlan_filter_set      = eth_em_vlan_filter_set,
 147         .vlan_offload_set     = eth_em_vlan_offload_set,
 148         .rx_queue_setup       = eth_em_rx_queue_setup,
 149         .rx_queue_release     = eth_em_rx_queue_release,
 150         .rx_queue_count       = eth_em_rx_queue_count,
 151         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 152         .tx_queue_setup       = eth_em_tx_queue_setup,
 153         .tx_queue_release     = eth_em_tx_queue_release,
 154         .dev_led_on           = eth_em_led_on,
 155         .dev_led_off          = eth_em_led_off,
 156         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 157         .mac_addr_add         = eth_em_rar_set,
 158         .mac_addr_remove      = eth_em_rar_clear,
 159 };
 160
 161 /**
 162  * Atomically reads the link status information from global
 163  * structure rte_eth_dev.
 164  *
 165  * @param dev
 166  *   - Pointer to the structure rte_eth_dev to read from.
 167  *   - Pointer to the buffer to be saved with the link status.
 168  *
 169  * @return
 170  *   - On success, zero.
 171  *   - On failure, negative value.
 172  */
 173 static inline int
 174 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 175                                 struct rte_eth_link *link)
 176 {
 177         struct rte_eth_link *dst = link;
 178         struct rte_eth_link *src = &(dev->data->dev_link);
 179
 180         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 181                                         *(uint64_t *)src) == 0)
 182                 return -1;
 183
 184         return 0;
 185 }
 186
 187 /**
 188  * Atomically writes the link status information into global
 189  * structure rte_eth_dev.
 190  *
 191  * @param dev
 192  *   - Pointer to the structure rte_eth_dev to read from.
 193  *   - Pointer to the buffer to be saved with the link status.
 194  *
 195  * @return
 196  *   - On success, zero.
 197  *   - On failure, negative value.
 198  */
 199 static inline int
 200 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 201                                 struct rte_eth_link *link)
 202 {
 203         struct rte_eth_link *dst = &(dev->data->dev_link);
 204         struct rte_eth_link *src = link;
 205
 206         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 207                                         *(uint64_t *)src) == 0)
 208                 return -1;
 209
 210         return 0;
 211 }
 212
 213 static int
 214 eth_em_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 215                 struct rte_eth_dev *eth_dev)
 216 {
 217         struct rte_pci_device *pci_dev;
 218         struct e1000_hw *hw =
 219                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 220         struct e1000_vfta * shadow_vfta =
 221                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 222
 223         pci_dev = eth_dev->pci_dev;
 224         eth_dev->dev_ops = &eth_em_ops;
 225         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 226         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 227
 228         /* for secondary processes, we don't initialise any further as primary
 229          * has already done this work. Only check we don't need a different
 230          * RX function */
 231         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 232                 if (eth_dev->data->scattered_rx)
 233                         eth_dev->rx_pkt_burst =
 234                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 235                 return 0;
 236         }
 237
 238         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 239         hw->device_id = pci_dev->id.device_id;
 240
 241         /* For ICH8 support we'll need to map the flash memory BAR */
 242
 243         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 244                         em_hw_init(hw) != 0) {
 245                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 246                         "failed to init HW",
 247                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 248                         pci_dev->id.device_id);
 249                 return -(ENODEV);
 250         }
 251
 252         /* Allocate memory for storing MAC addresses */
 253         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 254                         hw->mac.rar_entry_count, 0);
 255         if (eth_dev->data->mac_addrs == NULL) {
 256                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 257                         "store MAC addresses",
 258                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 259                 return -(ENOMEM);
 260         }
 261
 262         /* Copy the permanent MAC address */
 263         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 264                 eth_dev->data->mac_addrs);
 265
 266         /* initialize the vfta */
 267         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 268
 269         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 270                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 271                         pci_dev->id.device_id);
 272
 273         rte_intr_callback_register(&(pci_dev->intr_handle),
 274                 eth_em_interrupt_handler, (void *)eth_dev);
 275
 276         return (0);
 277 }
 278
 279 static struct eth_driver rte_em_pmd = {
 280         {
 281                 .name = "rte_em_pmd",
 282                 .id_table = pci_id_em_map,
 283                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 284         },
 285         .eth_dev_init = eth_em_dev_init,
 286         .dev_private_size = sizeof(struct e1000_adapter),
 287 };
 288
 289 static int
 290 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 291 {
 292         rte_eth_driver_register(&rte_em_pmd);
 293         return 0;
 294 }
 295
 296 static int
 297 em_hw_init(struct e1000_hw *hw)
 298 {
 299         int diag;
 300
 301         diag = hw->mac.ops.init_params(hw);
 302         if (diag != 0) {
 303                 PMD_INIT_LOG(ERR, "MAC Initialization Error\n");
 304                 return diag;
 305         }
 306         diag = hw->nvm.ops.init_params(hw);
 307         if (diag != 0) {
 308                 PMD_INIT_LOG(ERR, "NVM Initialization Error\n");
 309                 return diag;
 310         }
 311         diag = hw->phy.ops.init_params(hw);
 312         if (diag != 0) {
 313                 PMD_INIT_LOG(ERR, "PHY Initialization Error\n");
 314                 return diag;
 315         }
 316         (void) e1000_get_bus_info(hw);
 317
 318         hw->mac.autoneg = 1;
 319         hw->phy.autoneg_wait_to_complete = 0;
 320         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 321
 322         e1000_init_script_state_82541(hw, TRUE);
 323         e1000_set_tbi_compatibility_82543(hw, TRUE);
 324
 325         /* Copper options */
 326         if (hw->phy.media_type == e1000_media_type_copper) {
 327                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 328                 hw->phy.disable_polarity_correction = 0;
 329                 hw->phy.ms_type = e1000_ms_hw_default;
 330         }
 331
 332         /*
 333          * Start from a known state, this is important in reading the nvm
 334          * and mac from that.
 335          */
 336         e1000_reset_hw(hw);
 337
 338         /* Make sure we have a good EEPROM before we read from it */
 339         if (e1000_validate_nvm_checksum(hw) < 0) {
 340                 /*
 341                  * Some PCI-E parts fail the first check due to
 342                  * the link being in sleep state, call it again,
 343                  * if it fails a second time its a real issue.
 344                  */
 345                 diag = e1000_validate_nvm_checksum(hw);
 346                 if (diag < 0) {
 347                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 348                         goto error;
 349                 }
 350         }
 351
 352         /* Read the permanent MAC address out of the EEPROM */
 353         diag = e1000_read_mac_addr(hw);
 354         if (diag != 0) {
 355                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 356                 goto error;
 357         }
 358
 359         /* Now initialize the hardware */
 360         diag = em_hardware_init(hw);
 361         if (diag != 0) {
 362                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 363                 goto error;
 364         }
 365
 366         hw->mac.get_link_status = 1;
 367
 368         /* Indicate SOL/IDER usage */
 369         diag = e1000_check_reset_block(hw);
 370         if (diag < 0) {
 371                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 372                         "SOL/IDER session");
 373         }
 374         return (0);
 375
 376 error:
 377         em_hw_control_release(hw);
 378         return (diag);
 379 }
 380
 381 static int
 382 eth_em_configure(struct rte_eth_dev *dev)
 383 {
 384         struct e1000_interrupt *intr =
 385                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 386
 387         PMD_INIT_LOG(DEBUG, ">>");
 388
 389         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 390
 391         PMD_INIT_LOG(DEBUG, "<<");
 392         return (0);
 393 }
 394
 395 static void
 396 em_set_pba(struct e1000_hw *hw)
 397 {
 398         uint32_t pba;
 399
 400         /*
 401          * Packet Buffer Allocation (PBA)
 402          * Writing PBA sets the receive portion of the buffer
 403          * the remainder is used for the transmit buffer.
 404          * Devices before the 82547 had a Packet Buffer of 64K.
 405          * After the 82547 the buffer was reduced to 40K.
 406          */
 407         switch (hw->mac.type) {
 408                 case e1000_82547:
 409                 case e1000_82547_rev_2:
 410                 /* 82547: Total Packet Buffer is 40K */
 411                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 412                         break;
 413                 case e1000_82571:
 414                 case e1000_82572:
 415                 case e1000_80003es2lan:
 416                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 417                         break;
 418                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 419                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 420                         break;
 421                 case e1000_82574:
 422                 case e1000_82583:
 423                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 424                         break;
 425                 case e1000_ich8lan:
 426                         pba = E1000_PBA_8K;
 427                         break;
 428                 case e1000_ich9lan:
 429                 case e1000_ich10lan:
 430                         pba = E1000_PBA_10K;
 431                         break;
 432                 case e1000_pchlan:
 433                 case e1000_pch2lan:
 434                         pba = E1000_PBA_26K;
 435                         break;
 436                 default:
 437                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 438         }
 439
 440         E1000_WRITE_REG(hw, E1000_PBA, pba);
 441 }
 442
 443 static int
 444 eth_em_start(struct rte_eth_dev *dev)
 445 {
 446         struct e1000_hw *hw =
 447                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 448         int ret, mask;
 449
 450         PMD_INIT_LOG(DEBUG, ">>");
 451
 452         eth_em_stop(dev);
 453
 454         e1000_power_up_phy(hw);
 455
 456         /* Set default PBA value */
 457         em_set_pba(hw);
 458
 459         /* Put the address into the Receive Address Array */
 460         e1000_rar_set(hw, hw->mac.addr, 0);
 461
 462         /*
 463          * With the 82571 adapter, RAR[0] may be overwritten
 464          * when the other port is reset, we make a duplicate
 465          * in RAR[14] for that eventuality, this assures
 466          * the interface continues to function.
 467          */
 468         if (hw->mac.type == e1000_82571) {
 469                 e1000_set_laa_state_82571(hw, TRUE);
 470                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 471         }
 472
 473         /* Initialize the hardware */
 474         if (em_hardware_init(hw)) {
 475                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 476                 return (-EIO);
 477         }
 478
 479         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 480
 481         /* Configure for OS presence */
 482         em_init_manageability(hw);
 483
 484         eth_em_tx_init(dev);
 485
 486         ret = eth_em_rx_init(dev);
 487         if (ret) {
 488                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 489                 em_dev_clear_queues(dev);
 490                 return ret;
 491         }
 492
 493         e1000_clear_hw_cntrs_base_generic(hw);
 494
 495         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 496                         ETH_VLAN_EXTEND_MASK;
 497         eth_em_vlan_offload_set(dev, mask);
 498
 499         /* Set Interrupt Throttling Rate to maximum allowed value. */
 500         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 501
 502         /* Setup link speed and duplex */
 503         switch (dev->data->dev_conf.link_speed) {
 504         case ETH_LINK_SPEED_AUTONEG:
 505                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 506                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 507                 else if (dev->data->dev_conf.link_duplex ==
 508                                         ETH_LINK_HALF_DUPLEX)
 509                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 510                 else if (dev->data->dev_conf.link_duplex ==
 511                                         ETH_LINK_FULL_DUPLEX)
 512                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 513                 else
 514                         goto error_invalid_config;
 515                 break;
 516         case ETH_LINK_SPEED_10:
 517                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 518                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 519                 else if (dev->data->dev_conf.link_duplex ==
 520                                         ETH_LINK_HALF_DUPLEX)
 521                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 522                 else if (dev->data->dev_conf.link_duplex ==
 523                                         ETH_LINK_FULL_DUPLEX)
 524                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 525                 else
 526                         goto error_invalid_config;
 527                 break;
 528         case ETH_LINK_SPEED_100:
 529                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 530                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 531                 else if (dev->data->dev_conf.link_duplex ==
 532                                         ETH_LINK_HALF_DUPLEX)
 533                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 534                 else if (dev->data->dev_conf.link_duplex ==
 535                                         ETH_LINK_FULL_DUPLEX)
 536                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 537                 else
 538                         goto error_invalid_config;
 539                 break;
 540         case ETH_LINK_SPEED_1000:
 541                 if ((dev->data->dev_conf.link_duplex ==
 542                                 ETH_LINK_AUTONEG_DUPLEX) ||
 543                         (dev->data->dev_conf.link_duplex ==
 544                                         ETH_LINK_FULL_DUPLEX))
 545                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 546                 else
 547                         goto error_invalid_config;
 548                 break;
 549         case ETH_LINK_SPEED_10000:
 550         default:
 551                 goto error_invalid_config;
 552         }
 553         e1000_setup_link(hw);
 554
 555         /* check if lsc interrupt feature is enabled */
 556         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 557                 ret = eth_em_interrupt_setup(dev);
 558                 if (ret) {
 559                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 560                         em_dev_clear_queues(dev);
 561                         return ret;
 562                 }
 563         }
 564
 565         PMD_INIT_LOG(DEBUG, "<<");
 566
 567         return (0);
 568
 569 error_invalid_config:
 570         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port "
 571                                 "%u\n", dev->data->dev_conf.link_speed,
 572                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 573         em_dev_clear_queues(dev);
 574         return (-EINVAL);
 575 }
 576
 577 /*********************************************************************
 578  *
 579  *  This routine disables all traffic on the adapter by issuing a
 580  *  global reset on the MAC.
 581  *
 582  **********************************************************************/
 583 static void
 584 eth_em_stop(struct rte_eth_dev *dev)
 585 {
 586         struct rte_eth_link link;
 587         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 588
 589         em_intr_disable(hw);
 590         e1000_reset_hw(hw);
 591         if (hw->mac.type >= e1000_82544)
 592                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 593
 594         /* Power down the phy. Needed to make the link go down */
 595         e1000_power_down_phy(hw);
 596
 597         em_dev_clear_queues(dev);
 598
 599         /* clear the recorded link status */
 600         memset(&link, 0, sizeof(link));
 601         rte_em_dev_atomic_write_link_status(dev, &link);
 602 }
 603
 604 static void
 605 eth_em_close(struct rte_eth_dev *dev)
 606 {
 607         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 608
 609         eth_em_stop(dev);
 610         e1000_phy_hw_reset(hw);
 611         em_release_manageability(hw);
 612         em_hw_control_release(hw);
 613 }
 614
 615 static int
 616 em_get_rx_buffer_size(struct e1000_hw *hw)
 617 {
 618         uint32_t rx_buf_size;
 619
 620         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 621         return rx_buf_size;
 622 }
 623
 624 /*********************************************************************
 625  *
 626  *  Initialize the hardware
 627  *
 628  **********************************************************************/
 629 static int
 630 em_hardware_init(struct e1000_hw *hw)
 631 {
 632         uint32_t rx_buf_size;
 633         int diag;
 634
 635         /* Issue a global reset */
 636         e1000_reset_hw(hw);
 637
 638         /* Let the firmware know the OS is in control */
 639         em_hw_control_acquire(hw);
 640
 641         /*
 642          * These parameters control the automatic generation (Tx) and
 643          * response (Rx) to Ethernet PAUSE frames.
 644          * - High water mark should allow for at least two standard size (1518)
 645          *   frames to be received after sending an XOFF.
 646          * - Low water mark works best when it is very near the high water mark.
 647          *   This allows the receiver to restart by sending XON when it has
 648          *   drained a bit. Here we use an arbitrary value of 1500 which will
 649          *   restart after one full frame is pulled from the buffer. There
 650          *   could be several smaller frames in the buffer and if so they will
 651          *   not trigger the XON until their total number reduces the buffer
 652          *   by 1500.
 653          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 654          */
 655         rx_buf_size = em_get_rx_buffer_size(hw);
 656
 657         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 658         hw->fc.low_water = hw->fc.high_water - 1500;
 659
 660         if (hw->mac.type == e1000_80003es2lan)
 661                 hw->fc.pause_time = UINT16_MAX;
 662         else
 663                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 664
 665         hw->fc.send_xon = 1;
 666
 667         /* Set Flow control, use the tunable location if sane */
 668         if (em_fc_setting <= e1000_fc_full)
 669                 hw->fc.requested_mode = em_fc_setting;
 670         else
 671                 hw->fc.requested_mode = e1000_fc_none;
 672
 673         /* Workaround: no TX flow ctrl for PCH */
 674         if (hw->mac.type == e1000_pchlan)
 675                 hw->fc.requested_mode = e1000_fc_rx_pause;
 676
 677         /* Override - settings for PCH2LAN, ya its magic :) */
 678         if (hw->mac.type == e1000_pch2lan) {
 679                 hw->fc.high_water = 0x5C20;
 680                 hw->fc.low_water = 0x5048;
 681                 hw->fc.pause_time = 0x0650;
 682                 hw->fc.refresh_time = 0x0400;
 683         }
 684
 685         diag = e1000_init_hw(hw);
 686         if (diag < 0)
 687                 return (diag);
 688         e1000_check_for_link(hw);
 689         return (0);
 690 }
 691
 692 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 693 static void
 694 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 695 {
 696         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 697         struct e1000_hw_stats *stats =
 698                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 699         int pause_frames;
 700
 701         if(hw->phy.media_type == e1000_media_type_copper ||
 702                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 703                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 704                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 705         }
 706
 707         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 708         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 709         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 710         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 711
 712         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 713         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 714         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 715         stats->dc += E1000_READ_REG(hw, E1000_DC);
 716         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 717         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 718         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 719
 720         /*
 721          * For watchdog management we need to know if we have been
 722          * paused during the last interval, so capture that here.
 723          */
 724         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 725         stats->xoffrxc += pause_frames;
 726         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 727         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 728         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 729         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 730         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 731         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 732         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 733         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 734         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 735         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 736         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 737         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 738
 739         /*
 740          * For the 64-bit byte counters the low dword must be read first.
 741          * Both registers clear on the read of the high dword.
 742          */
 743
 744         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 745         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 746         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 747         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 748
 749         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 750         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 751         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 752         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 753         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 754
 755         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 756         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 757
 758         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 759         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 760         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 761         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 762         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 763         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 764         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 765         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 766         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 767         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 768
 769         /* Interrupt Counts */
 770
 771         if (hw->mac.type >= e1000_82571) {
 772                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 773                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 774                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 775                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 776                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 777                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 778                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 779                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 780                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 781         }
 782
 783         if (hw->mac.type >= e1000_82543) {
 784                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 785                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 786                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 787                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 788                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 789                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 790         }
 791
 792         if (rte_stats == NULL)
 793                 return;
 794
 795         /* Rx Errors */
 796         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 797                 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 798
 799         /* Tx Errors */
 800         rte_stats->oerrors = stats->ecol + stats->latecol;
 801
 802         rte_stats->ipackets = stats->gprc;
 803         rte_stats->opackets = stats->gptc;
 804         rte_stats->ibytes   = stats->gorc;
 805         rte_stats->obytes   = stats->gotc;
 806
 807         /* XON/XOFF pause frames stats registers */
 808         rte_stats->tx_pause_xon  = stats->xontxc;
 809         rte_stats->rx_pause_xon  = stats->xonrxc;
 810         rte_stats->tx_pause_xoff = stats->xofftxc;
 811         rte_stats->rx_pause_xoff = stats->xoffrxc;
 812 }
 813
 814 static void
 815 eth_em_stats_reset(struct rte_eth_dev *dev)
 816 {
 817         struct e1000_hw_stats *hw_stats =
 818                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 819
 820         /* HW registers are cleared on read */
 821         eth_em_stats_get(dev, NULL);
 822
 823         /* Reset software totals */
 824         memset(hw_stats, 0, sizeof(*hw_stats));
 825 }
 826
 827 static uint32_t
 828 em_get_max_pktlen(const struct e1000_hw *hw)
 829 {
 830         switch (hw->mac.type) {
 831         case e1000_82571:
 832         case e1000_82572:
 833         case e1000_ich9lan:
 834         case e1000_ich10lan:
 835         case e1000_pch2lan:
 836         case e1000_82574:
 837         case e1000_80003es2lan: /* 9K Jumbo Frame size */
 838                 return (0x2412);
 839         case e1000_pchlan:
 840                 return (0x1000);
 841         /* Adapters that do not support jumbo frames */
 842         case e1000_82583:
 843         case e1000_ich8lan:
 844                 return (ETHER_MAX_LEN);
 845         default:
 846                 return (MAX_JUMBO_FRAME_SIZE);
 847         }
 848 }
 849
 850 static void
 851 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 852 {
 853         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 854
 855         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
 856         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
 857         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
 858
 859         /*
 860          * Starting with 631xESB hw supports 2 TX/RX queues per port.
 861          * Unfortunatelly, all these nics have just one TX context.
 862          * So we have few choises for TX:
 863          * - Use just one TX queue.
 864          * - Allow cksum offload only for one TX queue.
 865          * - Don't allow TX cksum offload at all.
 866          * For now, option #1 was chosen.
 867          * To use second RX queue we have to use extended RX descriptor
 868          * (Multiple Receive Queues are mutually exclusive with UDP
 869          * fragmentation and are not supported when a legacy receive
 870          * descriptor format is used).
 871          * Which means separate RX routinies - as legacy nics (82540, 82545)
 872          * don't support extended RXD.
 873          * To avoid it we support just one RX queue for now (no RSS).
 874          */
 875
 876         dev_info->max_rx_queues = 1;
 877         dev_info->max_tx_queues = 1;
 878 }
 879
 880 /* return 0 means link status changed, -1 means not changed */
 881 static int
 882 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 883 {
 884         struct e1000_hw *hw =
 885                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 886         struct rte_eth_link link, old;
 887         int link_check, count;
 888
 889         link_check = 0;
 890         hw->mac.get_link_status = 1;
 891
 892         /* possible wait-to-complete in up to 9 seconds */
 893         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
 894                 /* Read the real link status */
 895                 switch (hw->phy.media_type) {
 896                 case e1000_media_type_copper:
 897                         /* Do the work to read phy */
 898                         e1000_check_for_link(hw);
 899                         link_check = !hw->mac.get_link_status;
 900                         break;
 901
 902                 case e1000_media_type_fiber:
 903                         e1000_check_for_link(hw);
 904                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
 905                                         E1000_STATUS_LU);
 906                         break;
 907
 908                 case e1000_media_type_internal_serdes:
 909                         e1000_check_for_link(hw);
 910                         link_check = hw->mac.serdes_has_link;
 911                         break;
 912
 913                 default:
 914                         break;
 915                 }
 916                 if (link_check || wait_to_complete == 0)
 917                         break;
 918                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
 919         }
 920         memset(&link, 0, sizeof(link));
 921         rte_em_dev_atomic_read_link_status(dev, &link);
 922         old = link;
 923
 924         /* Now we check if a transition has happened */
 925         if (link_check && (link.link_status == 0)) {
 926                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
 927                         &link.link_duplex);
 928                 link.link_status = 1;
 929         } else if (!link_check && (link.link_status == 1)) {
 930                 link.link_speed = 0;
 931                 link.link_duplex = 0;
 932                 link.link_status = 0;
 933         }
 934         rte_em_dev_atomic_write_link_status(dev, &link);
 935
 936         /* not changed */
 937         if (old.link_status == link.link_status)
 938                 return -1;
 939
 940         /* changed */
 941         return 0;
 942 }
 943
 944 /*
 945  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
 946  * For ASF and Pass Through versions of f/w this means
 947  * that the driver is loaded. For AMT version type f/w
 948  * this means that the network i/f is open.
 949  */
 950 static void
 951 em_hw_control_acquire(struct e1000_hw *hw)
 952 {
 953         uint32_t ctrl_ext, swsm;
 954
 955         /* Let firmware know the driver has taken over */
 956         if (hw->mac.type == e1000_82573) {
 957                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 958                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
 959
 960         } else {
 961                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 962                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 963                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 964         }
 965 }
 966
 967 /*
 968  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
 969  * For ASF and Pass Through versions of f/w this means that the
 970  * driver is no longer loaded. For AMT versions of the
 971  * f/w this means that the network i/f is closed.
 972  */
 973 static void
 974 em_hw_control_release(struct e1000_hw *hw)
 975 {
 976         uint32_t ctrl_ext, swsm;
 977
 978         /* Let firmware taken over control of h/w */
 979         if (hw->mac.type == e1000_82573) {
 980                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 981                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
 982         } else {
 983                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 984                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 985                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 986         }
 987 }
 988
 989 /*
 990  * Bit of a misnomer, what this really means is
 991  * to enable OS management of the system... aka
 992  * to disable special hardware management features.
 993  */
 994 static void
 995 em_init_manageability(struct e1000_hw *hw)
 996 {
 997         if (e1000_enable_mng_pass_thru(hw)) {
 998                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
 999                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1000
1001                 /* disable hardware interception of ARP */
1002                 manc &= ~(E1000_MANC_ARP_EN);
1003
1004                 /* enable receiving management packets to the host */
1005                 manc |= E1000_MANC_EN_MNG2HOST;
1006                 manc2h |= 1 << 5;  /* Mng Port 623 */
1007                 manc2h |= 1 << 6;  /* Mng Port 664 */
1008                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1009                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1010         }
1011 }
1012
1013 /*
1014  * Give control back to hardware management
1015  * controller if there is one.
1016  */
1017 static void
1018 em_release_manageability(struct e1000_hw *hw)
1019 {
1020         uint32_t manc;
1021
1022         if (e1000_enable_mng_pass_thru(hw)) {
1023                 manc = E1000_READ_REG(hw, E1000_MANC);
1024
1025                 /* re-enable hardware interception of ARP */
1026                 manc |= E1000_MANC_ARP_EN;
1027                 manc &= ~E1000_MANC_EN_MNG2HOST;
1028
1029                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1030         }
1031 }
1032
1033 static void
1034 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1035 {
1036         struct e1000_hw *hw =
1037                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1038         uint32_t rctl;
1039
1040         rctl = E1000_READ_REG(hw, E1000_RCTL);
1041         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1042         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1043 }
1044
1045 static void
1046 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1047 {
1048         struct e1000_hw *hw =
1049                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1050         uint32_t rctl;
1051
1052         rctl = E1000_READ_REG(hw, E1000_RCTL);
1053         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1054         if (dev->data->all_multicast == 1)
1055                 rctl |= E1000_RCTL_MPE;
1056         else
1057                 rctl &= (~E1000_RCTL_MPE);
1058         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1059 }
1060
1061 static void
1062 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1063 {
1064         struct e1000_hw *hw =
1065                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1066         uint32_t rctl;
1067
1068         rctl = E1000_READ_REG(hw, E1000_RCTL);
1069         rctl |= E1000_RCTL_MPE;
1070         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1071 }
1072
1073 static void
1074 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1075 {
1076         struct e1000_hw *hw =
1077                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1078         uint32_t rctl;
1079
1080         if (dev->data->promiscuous == 1)
1081                 return; /* must remain in all_multicast mode */
1082         rctl = E1000_READ_REG(hw, E1000_RCTL);
1083         rctl &= (~E1000_RCTL_MPE);
1084         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1085 }
1086
1087 static int
1088 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1089 {
1090         struct e1000_hw *hw =
1091                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1092         struct e1000_vfta * shadow_vfta =
1093                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1094         uint32_t vfta;
1095         uint32_t vid_idx;
1096         uint32_t vid_bit;
1097
1098         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1099                               E1000_VFTA_ENTRY_MASK);
1100         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1101         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1102         if (on)
1103                 vfta |= vid_bit;
1104         else
1105                 vfta &= ~vid_bit;
1106         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1107
1108         /* update local VFTA copy */
1109         shadow_vfta->vfta[vid_idx] = vfta;
1110
1111         return 0;
1112 }
1113
1114 static void
1115 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1116 {
1117         struct e1000_hw *hw =
1118                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1119         uint32_t reg;
1120
1121         /* Filter Table Disable */
1122         reg = E1000_READ_REG(hw, E1000_RCTL);
1123         reg &= ~E1000_RCTL_CFIEN;
1124         reg &= ~E1000_RCTL_VFE;
1125         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1126 }
1127
1128 static void
1129 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1130 {
1131         struct e1000_hw *hw =
1132                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1133         struct e1000_vfta * shadow_vfta =
1134                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1135         uint32_t reg;
1136         int i;
1137
1138         /* Filter Table Enable, CFI not used for packet acceptance */
1139         reg = E1000_READ_REG(hw, E1000_RCTL);
1140         reg &= ~E1000_RCTL_CFIEN;
1141         reg |= E1000_RCTL_VFE;
1142         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1143
1144         /* restore vfta from local copy */
1145         for (i = 0; i < IGB_VFTA_SIZE; i++)
1146                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1147 }
1148
1149 static void
1150 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1151 {
1152         struct e1000_hw *hw =
1153                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1154         uint32_t reg;
1155
1156         /* VLAN Mode Disable */
1157         reg = E1000_READ_REG(hw, E1000_CTRL);
1158         reg &= ~E1000_CTRL_VME;
1159         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1160
1161 }
1162
1163 static void
1164 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1165 {
1166         struct e1000_hw *hw =
1167                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1168         uint32_t reg;
1169
1170         /* VLAN Mode Enable */
1171         reg = E1000_READ_REG(hw, E1000_CTRL);
1172         reg |= E1000_CTRL_VME;
1173         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1174 }
1175
1176 static void
1177 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1178 {
1179         if(mask & ETH_VLAN_STRIP_MASK){
1180                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1181                         em_vlan_hw_strip_enable(dev);
1182                 else
1183                         em_vlan_hw_strip_disable(dev);
1184         }
1185
1186         if(mask & ETH_VLAN_FILTER_MASK){
1187                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1188                         em_vlan_hw_filter_enable(dev);
1189                 else
1190                         em_vlan_hw_filter_disable(dev);
1191         }
1192 }
1193
1194 static void
1195 em_intr_disable(struct e1000_hw *hw)
1196 {
1197         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1198 }
1199
1200 /**
1201  * It enables the interrupt mask and then enable the interrupt.
1202  *
1203  * @param dev
1204  *  Pointer to struct rte_eth_dev.
1205  *
1206  * @return
1207  *  - On success, zero.
1208  *  - On failure, a negative value.
1209  */
1210 static int
1211 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1212 {
1213         struct e1000_hw *hw =
1214                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1215
1216         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1217         rte_intr_enable(&(dev->pci_dev->intr_handle));
1218         return (0);
1219 }
1220
1221 /*
1222  * It reads ICR and gets interrupt causes, check it and set a bit flag
1223  * to update link status.
1224  *
1225  * @param dev
1226  *  Pointer to struct rte_eth_dev.
1227  *
1228  * @return
1229  *  - On success, zero.
1230  *  - On failure, a negative value.
1231  */
1232 static int
1233 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1234 {
1235         uint32_t icr;
1236         struct e1000_hw *hw =
1237                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1238         struct e1000_interrupt *intr =
1239                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1240
1241         /* read-on-clear nic registers here */
1242         icr = E1000_READ_REG(hw, E1000_ICR);
1243         if (icr & E1000_ICR_LSC) {
1244                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1245         }
1246
1247         return 0;
1248 }
1249
1250 /*
1251  * It executes link_update after knowing an interrupt is prsent.
1252  *
1253  * @param dev
1254  *  Pointer to struct rte_eth_dev.
1255  *
1256  * @return
1257  *  - On success, zero.
1258  *  - On failure, a negative value.
1259  */
1260 static int
1261 eth_em_interrupt_action(struct rte_eth_dev *dev)
1262 {
1263         struct e1000_hw *hw =
1264                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1265         struct e1000_interrupt *intr =
1266                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1267         uint32_t tctl, rctl;
1268         struct rte_eth_link link;
1269         int ret;
1270
1271         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1272                 return -1;
1273
1274         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1275         rte_intr_enable(&(dev->pci_dev->intr_handle));
1276
1277         /* set get_link_status to check register later */
1278         hw->mac.get_link_status = 1;
1279         ret = eth_em_link_update(dev, 0);
1280
1281         /* check if link has changed */
1282         if (ret < 0)
1283                 return 0;
1284
1285         memset(&link, 0, sizeof(link));
1286         rte_em_dev_atomic_read_link_status(dev, &link);
1287         if (link.link_status) {
1288                 PMD_INIT_LOG(INFO,
1289                         " Port %d: Link Up - speed %u Mbps - %s\n",
1290                         dev->data->port_id, (unsigned)link.link_speed,
1291                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1292                                 "full-duplex" : "half-duplex");
1293         } else {
1294                 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1295                                         dev->data->port_id);
1296         }
1297         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1298                                 dev->pci_dev->addr.domain,
1299                                 dev->pci_dev->addr.bus,
1300                                 dev->pci_dev->addr.devid,
1301                                 dev->pci_dev->addr.function);
1302         tctl = E1000_READ_REG(hw, E1000_TCTL);
1303         rctl = E1000_READ_REG(hw, E1000_RCTL);
1304         if (link.link_status) {
1305                 /* enable Tx/Rx */
1306                 tctl |= E1000_TCTL_EN;
1307                 rctl |= E1000_RCTL_EN;
1308         } else {
1309                 /* disable Tx/Rx */
1310                 tctl &= ~E1000_TCTL_EN;
1311                 rctl &= ~E1000_RCTL_EN;
1312         }
1313         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1314         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1315         E1000_WRITE_FLUSH(hw);
1316
1317         return 0;
1318 }
1319
1320 /**
1321  * Interrupt handler which shall be registered at first.
1322  *
1323  * @param handle
1324  *  Pointer to interrupt handle.
1325  * @param param
1326  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1327  *
1328  * @return
1329  *  void
1330  */
1331 static void
1332 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1333                                                         void *param)
1334 {
1335         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1336
1337         eth_em_interrupt_get_status(dev);
1338         eth_em_interrupt_action(dev);
1339         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1340 }
1341
1342 static int
1343 eth_em_led_on(struct rte_eth_dev *dev)
1344 {
1345         struct e1000_hw *hw;
1346
1347         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1349 }
1350
1351 static int
1352 eth_em_led_off(struct rte_eth_dev *dev)
1353 {
1354         struct e1000_hw *hw;
1355
1356         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1357         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1358 }
1359
1360 static int
1361 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1362 {
1363         struct e1000_hw *hw;
1364         int err;
1365         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1366                 e1000_fc_none,
1367                 e1000_fc_rx_pause,
1368                 e1000_fc_tx_pause,
1369                 e1000_fc_full
1370         };
1371         uint32_t rx_buf_size;
1372         uint32_t max_high_water;
1373         uint32_t rctl;
1374
1375         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1376         rx_buf_size = em_get_rx_buffer_size(hw);
1377         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1378
1379         /* At least reserve one Ethernet frame for watermark */
1380         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1381         if ((fc_conf->high_water > max_high_water) ||
1382                 (fc_conf->high_water < fc_conf->low_water)) {
1383                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1384                 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1385                 return (-EINVAL);
1386         }
1387
1388         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1389         hw->fc.pause_time     = fc_conf->pause_time;
1390         hw->fc.high_water     = fc_conf->high_water;
1391         hw->fc.low_water      = fc_conf->low_water;
1392         hw->fc.send_xon       = fc_conf->send_xon;
1393
1394         err = e1000_setup_link_generic(hw);
1395         if (err == E1000_SUCCESS) {
1396
1397                 /* check if we want to forward MAC frames - driver doesn't have native
1398                  * capability to do that, so we'll write the registers ourselves */
1399
1400                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1401
1402                 /* set or clear MFLCN.PMCF bit depending on configuration */
1403                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1404                         rctl |= E1000_RCTL_PMCF;
1405                 else
1406                         rctl &= ~E1000_RCTL_PMCF;
1407
1408                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1409                 E1000_WRITE_FLUSH(hw);
1410
1411                 return 0;
1412         }
1413
1414         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1415         return (-EIO);
1416 }
1417
1418 static void
1419 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1420                 uint32_t index, __rte_unused uint32_t pool)
1421 {
1422         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1423
1424         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1425 }
1426
1427 static void
1428 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1429 {
1430         uint8_t addr[ETHER_ADDR_LEN];
1431         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1432
1433         memset(addr, 0, sizeof(addr));
1434
1435         e1000_rar_set(hw, addr, index);
1436 }
1437
1438 struct rte_driver em_pmd_drv = {
1439         .type = PMD_PDEV,
1440         .init = rte_em_pmd_init,
1441 };
1442
1443 PMD_REGISTER_DRIVER(em_pmd_drv);