lib/librte_pmd_e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #include <sys/queue.h>
  36 #include <stdio.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40
  41 #include <rte_common.h>
  42 #include <rte_interrupts.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_tailq.h>
  52 #include <rte_eal.h>
  53 #include <rte_atomic.h>
  54 #include <rte_malloc.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 #define EM_EIAC                 0x000DC
  61
  62 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  63
  64
  65 static int eth_em_configure(struct rte_eth_dev *dev);
  66 static int eth_em_start(struct rte_eth_dev *dev);
  67 static void eth_em_stop(struct rte_eth_dev *dev);
  68 static void eth_em_close(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  70 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  72 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  73 static int eth_em_link_update(struct rte_eth_dev *dev,
  74                                 int wait_to_complete);
  75 static void eth_em_stats_get(struct rte_eth_dev *dev,
  76                                 struct rte_eth_stats *rte_stats);
  77 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  78 static void eth_em_infos_get(struct rte_eth_dev *dev,
  79                                 struct rte_eth_dev_info *dev_info);
  80 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  81                                 struct rte_eth_fc_conf *fc_conf);
  82 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  83 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  84 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
  85 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  86                                                         void *param);
  87
  88 static int em_hw_init(struct e1000_hw *hw);
  89 static int em_hardware_init(struct e1000_hw *hw);
  90 static void em_hw_control_acquire(struct e1000_hw *hw);
  91 static void em_hw_control_release(struct e1000_hw *hw);
  92 static void em_init_manageability(struct e1000_hw *hw);
  93 static void em_release_manageability(struct e1000_hw *hw);
  94
  95 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  96                 uint16_t vlan_id, int on);
  97 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  98 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  99 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 100 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 101 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 102
 103 /*
 104 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 105                                         uint16_t vlan_id, int on);
 106 */
 107 static int eth_em_led_on(struct rte_eth_dev *dev);
 108 static int eth_em_led_off(struct rte_eth_dev *dev);
 109
 110 static void em_intr_disable(struct e1000_hw *hw);
 111 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 112 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 113                 uint32_t index, uint32_t pool);
 114 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 115
 116 #define EM_FC_PAUSE_TIME 0x0680
 117 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 118 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 119
 120 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 121
 122 /*
 123  * The set of PCI devices this driver supports
 124  */
 125 static struct rte_pci_id pci_id_em_map[] = {
 126
 127 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 128 #include "rte_pci_dev_ids.h"
 129
 130 {.device_id = 0},
 131 };
 132
 133 static struct eth_dev_ops eth_em_ops = {
 134         .dev_configure        = eth_em_configure,
 135         .dev_start            = eth_em_start,
 136         .dev_stop             = eth_em_stop,
 137         .dev_close            = eth_em_close,
 138         .promiscuous_enable   = eth_em_promiscuous_enable,
 139         .promiscuous_disable  = eth_em_promiscuous_disable,
 140         .allmulticast_enable  = eth_em_allmulticast_enable,
 141         .allmulticast_disable = eth_em_allmulticast_disable,
 142         .link_update          = eth_em_link_update,
 143         .stats_get            = eth_em_stats_get,
 144         .stats_reset          = eth_em_stats_reset,
 145         .dev_infos_get        = eth_em_infos_get,
 146         .vlan_filter_set      = eth_em_vlan_filter_set,
 147         .vlan_offload_set     = eth_em_vlan_offload_set,
 148         .rx_queue_setup       = eth_em_rx_queue_setup,
 149         .rx_queue_release     = eth_em_rx_queue_release,
 150         .rx_queue_count       = eth_em_rx_queue_count,
 151         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 152         .tx_queue_setup       = eth_em_tx_queue_setup,
 153         .tx_queue_release     = eth_em_tx_queue_release,
 154         .dev_led_on           = eth_em_led_on,
 155         .dev_led_off          = eth_em_led_off,
 156         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 157         .mac_addr_add         = eth_em_rar_set,
 158         .mac_addr_remove      = eth_em_rar_clear,
 159 };
 160
 161 /**
 162  * Atomically reads the link status information from global
 163  * structure rte_eth_dev.
 164  *
 165  * @param dev
 166  *   - Pointer to the structure rte_eth_dev to read from.
 167  *   - Pointer to the buffer to be saved with the link status.
 168  *
 169  * @return
 170  *   - On success, zero.
 171  *   - On failure, negative value.
 172  */
 173 static inline int
 174 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 175                                 struct rte_eth_link *link)
 176 {
 177         struct rte_eth_link *dst = link;
 178         struct rte_eth_link *src = &(dev->data->dev_link);
 179
 180         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 181                                         *(uint64_t *)src) == 0)
 182                 return -1;
 183
 184         return 0;
 185 }
 186
 187 /**
 188  * Atomically writes the link status information into global
 189  * structure rte_eth_dev.
 190  *
 191  * @param dev
 192  *   - Pointer to the structure rte_eth_dev to read from.
 193  *   - Pointer to the buffer to be saved with the link status.
 194  *
 195  * @return
 196  *   - On success, zero.
 197  *   - On failure, negative value.
 198  */
 199 static inline int
 200 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 201                                 struct rte_eth_link *link)
 202 {
 203         struct rte_eth_link *dst = &(dev->data->dev_link);
 204         struct rte_eth_link *src = link;
 205
 206         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 207                                         *(uint64_t *)src) == 0)
 208                 return -1;
 209
 210         return 0;
 211 }
 212
 213 static int
 214 eth_em_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 215                 struct rte_eth_dev *eth_dev)
 216 {
 217         struct rte_pci_device *pci_dev;
 218         struct e1000_hw *hw =
 219                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 220         struct e1000_vfta * shadow_vfta =
 221                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 222
 223         pci_dev = eth_dev->pci_dev;
 224         eth_dev->dev_ops = &eth_em_ops;
 225         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 226         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 227
 228         /* for secondary processes, we don't initialise any further as primary
 229          * has already done this work. Only check we don't need a different
 230          * RX function */
 231         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 232                 if (eth_dev->data->scattered_rx)
 233                         eth_dev->rx_pkt_burst =
 234                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 235                 return 0;
 236         }
 237
 238         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 239         hw->device_id = pci_dev->id.device_id;
 240
 241         /* For ICH8 support we'll need to map the flash memory BAR */
 242
 243         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 244                         em_hw_init(hw) != 0) {
 245                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 246                         "failed to init HW",
 247                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 248                         pci_dev->id.device_id);
 249                 return -(ENODEV);
 250         }
 251
 252         /* Allocate memory for storing MAC addresses */
 253         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 254                         hw->mac.rar_entry_count, 0);
 255         if (eth_dev->data->mac_addrs == NULL) {
 256                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 257                         "store MAC addresses",
 258                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 259                 return -(ENOMEM);
 260         }
 261
 262         /* Copy the permanent MAC address */
 263         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 264                 eth_dev->data->mac_addrs);
 265
 266         /* initialize the vfta */
 267         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 268
 269         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 270                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 271                         pci_dev->id.device_id);
 272
 273         rte_intr_callback_register(&(pci_dev->intr_handle),
 274                 eth_em_interrupt_handler, (void *)eth_dev);
 275
 276         return (0);
 277 }
 278
 279 static struct eth_driver rte_em_pmd = {
 280         {
 281                 .name = "rte_em_pmd",
 282                 .id_table = pci_id_em_map,
 283 #ifdef RTE_EAL_UNBIND_PORTS
 284                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 285 #endif
 286         },
 287         .eth_dev_init = eth_em_dev_init,
 288         .dev_private_size = sizeof(struct e1000_adapter),
 289 };
 290
 291 int
 292 rte_em_pmd_init(void)
 293 {
 294         rte_eth_driver_register(&rte_em_pmd);
 295         return 0;
 296 }
 297
 298 static int
 299 em_hw_init(struct e1000_hw *hw)
 300 {
 301         int diag;
 302
 303         diag = hw->mac.ops.init_params(hw);
 304         if (diag != 0) {
 305                 PMD_INIT_LOG(ERR, "MAC Initialization Error\n");
 306                 return diag;
 307         }
 308         diag = hw->nvm.ops.init_params(hw);
 309         if (diag != 0) {
 310                 PMD_INIT_LOG(ERR, "NVM Initialization Error\n");
 311                 return diag;
 312         }
 313         diag = hw->phy.ops.init_params(hw);
 314         if (diag != 0) {
 315                 PMD_INIT_LOG(ERR, "PHY Initialization Error\n");
 316                 return diag;
 317         }
 318         (void) e1000_get_bus_info(hw);
 319
 320         hw->mac.autoneg = 1;
 321         hw->phy.autoneg_wait_to_complete = 0;
 322         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 323
 324         e1000_init_script_state_82541(hw, TRUE);
 325         e1000_set_tbi_compatibility_82543(hw, TRUE);
 326
 327         /* Copper options */
 328         if (hw->phy.media_type == e1000_media_type_copper) {
 329                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 330                 hw->phy.disable_polarity_correction = 0;
 331                 hw->phy.ms_type = e1000_ms_hw_default;
 332         }
 333
 334         /*
 335          * Start from a known state, this is important in reading the nvm
 336          * and mac from that.
 337          */
 338         e1000_reset_hw(hw);
 339
 340         /* Make sure we have a good EEPROM before we read from it */
 341         if (e1000_validate_nvm_checksum(hw) < 0) {
 342                 /*
 343                  * Some PCI-E parts fail the first check due to
 344                  * the link being in sleep state, call it again,
 345                  * if it fails a second time its a real issue.
 346                  */
 347                 diag = e1000_validate_nvm_checksum(hw);
 348                 if (diag < 0) {
 349                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 350                         goto error;
 351                 }
 352         }
 353
 354         /* Read the permanent MAC address out of the EEPROM */
 355         diag = e1000_read_mac_addr(hw);
 356         if (diag != 0) {
 357                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 358                 goto error;
 359         }
 360
 361         /* Now initialize the hardware */
 362         diag = em_hardware_init(hw);
 363         if (diag != 0) {
 364                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 365                 goto error;
 366         }
 367
 368         hw->mac.get_link_status = 1;
 369
 370         /* Indicate SOL/IDER usage */
 371         diag = e1000_check_reset_block(hw);
 372         if (diag < 0) {
 373                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 374                         "SOL/IDER session");
 375         }
 376         return (0);
 377
 378 error:
 379         em_hw_control_release(hw);
 380         return (diag);
 381 }
 382
 383 static int
 384 eth_em_configure(struct rte_eth_dev *dev)
 385 {
 386         struct e1000_interrupt *intr =
 387                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 388
 389         PMD_INIT_LOG(DEBUG, ">>");
 390
 391         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 392
 393         PMD_INIT_LOG(DEBUG, "<<");
 394         return (0);
 395 }
 396
 397 static void
 398 em_set_pba(struct e1000_hw *hw)
 399 {
 400         uint32_t pba;
 401
 402         /*
 403          * Packet Buffer Allocation (PBA)
 404          * Writing PBA sets the receive portion of the buffer
 405          * the remainder is used for the transmit buffer.
 406          * Devices before the 82547 had a Packet Buffer of 64K.
 407          * After the 82547 the buffer was reduced to 40K.
 408          */
 409         switch (hw->mac.type) {
 410                 case e1000_82547:
 411                 case e1000_82547_rev_2:
 412                 /* 82547: Total Packet Buffer is 40K */
 413                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 414                         break;
 415                 case e1000_82571:
 416                 case e1000_82572:
 417                 case e1000_80003es2lan:
 418                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 419                         break;
 420                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 421                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 422                         break;
 423                 case e1000_82574:
 424                 case e1000_82583:
 425                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 426                         break;
 427                 case e1000_ich8lan:
 428                         pba = E1000_PBA_8K;
 429                         break;
 430                 case e1000_ich9lan:
 431                 case e1000_ich10lan:
 432                         pba = E1000_PBA_10K;
 433                         break;
 434                 case e1000_pchlan:
 435                 case e1000_pch2lan:
 436                         pba = E1000_PBA_26K;
 437                         break;
 438                 default:
 439                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 440         }
 441
 442         E1000_WRITE_REG(hw, E1000_PBA, pba);
 443 }
 444
 445 static int
 446 eth_em_start(struct rte_eth_dev *dev)
 447 {
 448         struct e1000_hw *hw =
 449                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 450         int ret, mask;
 451
 452         PMD_INIT_LOG(DEBUG, ">>");
 453
 454         eth_em_stop(dev);
 455
 456         e1000_power_up_phy(hw);
 457
 458         /* Set default PBA value */
 459         em_set_pba(hw);
 460
 461         /* Put the address into the Receive Address Array */
 462         e1000_rar_set(hw, hw->mac.addr, 0);
 463
 464         /*
 465          * With the 82571 adapter, RAR[0] may be overwritten
 466          * when the other port is reset, we make a duplicate
 467          * in RAR[14] for that eventuality, this assures
 468          * the interface continues to function.
 469          */
 470         if (hw->mac.type == e1000_82571) {
 471                 e1000_set_laa_state_82571(hw, TRUE);
 472                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 473         }
 474
 475         /* Initialize the hardware */
 476         if (em_hardware_init(hw)) {
 477                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 478                 return (-EIO);
 479         }
 480
 481         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 482
 483         /* Configure for OS presence */
 484         em_init_manageability(hw);
 485
 486         eth_em_tx_init(dev);
 487
 488         ret = eth_em_rx_init(dev);
 489         if (ret) {
 490                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 491                 em_dev_clear_queues(dev);
 492                 return ret;
 493         }
 494
 495         e1000_clear_hw_cntrs_base_generic(hw);
 496
 497         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 498                         ETH_VLAN_EXTEND_MASK;
 499         eth_em_vlan_offload_set(dev, mask);
 500
 501         /* Set Interrupt Throttling Rate to maximum allowed value. */
 502         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 503
 504         /* Setup link speed and duplex */
 505         switch (dev->data->dev_conf.link_speed) {
 506         case ETH_LINK_SPEED_AUTONEG:
 507                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 508                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 509                 else if (dev->data->dev_conf.link_duplex ==
 510                                         ETH_LINK_HALF_DUPLEX)
 511                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 512                 else if (dev->data->dev_conf.link_duplex ==
 513                                         ETH_LINK_FULL_DUPLEX)
 514                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 515                 else
 516                         goto error_invalid_config;
 517                 break;
 518         case ETH_LINK_SPEED_10:
 519                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 520                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 521                 else if (dev->data->dev_conf.link_duplex ==
 522                                         ETH_LINK_HALF_DUPLEX)
 523                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 524                 else if (dev->data->dev_conf.link_duplex ==
 525                                         ETH_LINK_FULL_DUPLEX)
 526                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 527                 else
 528                         goto error_invalid_config;
 529                 break;
 530         case ETH_LINK_SPEED_100:
 531                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 532                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 533                 else if (dev->data->dev_conf.link_duplex ==
 534                                         ETH_LINK_HALF_DUPLEX)
 535                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 536                 else if (dev->data->dev_conf.link_duplex ==
 537                                         ETH_LINK_FULL_DUPLEX)
 538                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 539                 else
 540                         goto error_invalid_config;
 541                 break;
 542         case ETH_LINK_SPEED_1000:
 543                 if ((dev->data->dev_conf.link_duplex ==
 544                                 ETH_LINK_AUTONEG_DUPLEX) ||
 545                         (dev->data->dev_conf.link_duplex ==
 546                                         ETH_LINK_FULL_DUPLEX))
 547                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 548                 else
 549                         goto error_invalid_config;
 550                 break;
 551         case ETH_LINK_SPEED_10000:
 552         default:
 553                 goto error_invalid_config;
 554         }
 555         e1000_setup_link(hw);
 556
 557         /* check if lsc interrupt feature is enabled */
 558         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 559                 ret = eth_em_interrupt_setup(dev);
 560                 if (ret) {
 561                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 562                         em_dev_clear_queues(dev);
 563                         return ret;
 564                 }
 565         }
 566
 567         PMD_INIT_LOG(DEBUG, "<<");
 568
 569         return (0);
 570
 571 error_invalid_config:
 572         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port "
 573                                 "%u\n", dev->data->dev_conf.link_speed,
 574                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 575         em_dev_clear_queues(dev);
 576         return (-EINVAL);
 577 }
 578
 579 /*********************************************************************
 580  *
 581  *  This routine disables all traffic on the adapter by issuing a
 582  *  global reset on the MAC.
 583  *
 584  **********************************************************************/
 585 static void
 586 eth_em_stop(struct rte_eth_dev *dev)
 587 {
 588         struct rte_eth_link link;
 589         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 590
 591         em_intr_disable(hw);
 592         e1000_reset_hw(hw);
 593         if (hw->mac.type >= e1000_82544)
 594                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 595
 596         /* Power down the phy. Needed to make the link go down */
 597         e1000_power_down_phy(hw);
 598
 599         em_dev_clear_queues(dev);
 600
 601         /* clear the recorded link status */
 602         memset(&link, 0, sizeof(link));
 603         rte_em_dev_atomic_write_link_status(dev, &link);
 604 }
 605
 606 static void
 607 eth_em_close(struct rte_eth_dev *dev)
 608 {
 609         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 610
 611         eth_em_stop(dev);
 612         e1000_phy_hw_reset(hw);
 613         em_release_manageability(hw);
 614         em_hw_control_release(hw);
 615 }
 616
 617 static int
 618 em_get_rx_buffer_size(struct e1000_hw *hw)
 619 {
 620         uint32_t rx_buf_size;
 621
 622         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 623         return rx_buf_size;
 624 }
 625
 626 /*********************************************************************
 627  *
 628  *  Initialize the hardware
 629  *
 630  **********************************************************************/
 631 static int
 632 em_hardware_init(struct e1000_hw *hw)
 633 {
 634         uint32_t rx_buf_size;
 635         int diag;
 636
 637         /* Issue a global reset */
 638         e1000_reset_hw(hw);
 639
 640         /* Let the firmware know the OS is in control */
 641         em_hw_control_acquire(hw);
 642
 643         /*
 644          * These parameters control the automatic generation (Tx) and
 645          * response (Rx) to Ethernet PAUSE frames.
 646          * - High water mark should allow for at least two standard size (1518)
 647          *   frames to be received after sending an XOFF.
 648          * - Low water mark works best when it is very near the high water mark.
 649          *   This allows the receiver to restart by sending XON when it has
 650          *   drained a bit. Here we use an arbitary value of 1500 which will
 651          *   restart after one full frame is pulled from the buffer. There
 652          *   could be several smaller frames in the buffer and if so they will
 653          *   not trigger the XON until their total number reduces the buffer
 654          *   by 1500.
 655          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 656          */
 657         rx_buf_size = em_get_rx_buffer_size(hw);
 658
 659         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 660         hw->fc.low_water = hw->fc.high_water - 1500;
 661
 662         if (hw->mac.type == e1000_80003es2lan)
 663                 hw->fc.pause_time = UINT16_MAX;
 664         else
 665                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 666
 667         hw->fc.send_xon = 1;
 668
 669         /* Set Flow control, use the tunable location if sane */
 670         if (em_fc_setting <= e1000_fc_full)
 671                 hw->fc.requested_mode = em_fc_setting;
 672         else
 673                 hw->fc.requested_mode = e1000_fc_none;
 674
 675         /* Workaround: no TX flow ctrl for PCH */
 676         if (hw->mac.type == e1000_pchlan)
 677                 hw->fc.requested_mode = e1000_fc_rx_pause;
 678
 679         /* Override - settings for PCH2LAN, ya its magic :) */
 680         if (hw->mac.type == e1000_pch2lan) {
 681                 hw->fc.high_water = 0x5C20;
 682                 hw->fc.low_water = 0x5048;
 683                 hw->fc.pause_time = 0x0650;
 684                 hw->fc.refresh_time = 0x0400;
 685         }
 686
 687         diag = e1000_init_hw(hw);
 688         if (diag < 0)
 689                 return (diag);
 690         e1000_check_for_link(hw);
 691         return (0);
 692 }
 693
 694 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 695 static void
 696 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 697 {
 698         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 699         struct e1000_hw_stats *stats =
 700                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 701         int pause_frames;
 702
 703         if(hw->phy.media_type == e1000_media_type_copper ||
 704                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 705                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 706                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 707         }
 708
 709         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 710         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 711         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 712         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 713
 714         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 715         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 716         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 717         stats->dc += E1000_READ_REG(hw, E1000_DC);
 718         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 719         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 720         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 721
 722         /*
 723          * For watchdog management we need to know if we have been
 724          * paused during the last interval, so capture that here.
 725          */
 726         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 727         stats->xoffrxc += pause_frames;
 728         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 729         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 730         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 731         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 732         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 733         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 734         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 735         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 736         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 737         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 738         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 739         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 740
 741         /*
 742          * For the 64-bit byte counters the low dword must be read first.
 743          * Both registers clear on the read of the high dword.
 744          */
 745
 746         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 747         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 748         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 749         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 750
 751         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 752         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 753         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 754         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 755         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 756
 757         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 758         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 759
 760         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 761         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 762         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 763         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 764         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 765         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 766         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 767         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 768         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 769         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 770
 771         /* Interrupt Counts */
 772
 773         if (hw->mac.type >= e1000_82571) {
 774                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 775                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 776                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 777                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 778                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 779                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 780                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 781                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 782                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 783         }
 784
 785         if (hw->mac.type >= e1000_82543) {
 786                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 787                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 788                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 789                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 790                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 791                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 792         }
 793
 794         if (rte_stats == NULL)
 795                 return;
 796
 797         /* Rx Errors */
 798         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 799                 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 800
 801         /* Tx Errors */
 802         rte_stats->oerrors = stats->ecol + stats->latecol;
 803
 804         rte_stats->ipackets = stats->gprc;
 805         rte_stats->opackets = stats->gptc;
 806         rte_stats->ibytes   = stats->gorc;
 807         rte_stats->obytes   = stats->gotc;
 808 }
 809
 810 static void
 811 eth_em_stats_reset(struct rte_eth_dev *dev)
 812 {
 813         struct e1000_hw_stats *hw_stats =
 814                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 815
 816         /* HW registers are cleared on read */
 817         eth_em_stats_get(dev, NULL);
 818
 819         /* Reset software totals */
 820         memset(hw_stats, 0, sizeof(*hw_stats));
 821 }
 822
 823 static uint32_t
 824 em_get_max_pktlen(const struct e1000_hw *hw)
 825 {
 826         switch (hw->mac.type) {
 827         case e1000_82571:
 828         case e1000_82572:
 829         case e1000_ich9lan:
 830         case e1000_ich10lan:
 831         case e1000_pch2lan:
 832         case e1000_82574:
 833         case e1000_80003es2lan: /* 9K Jumbo Frame size */
 834                 return (0x2412);
 835         case e1000_pchlan:
 836                 return (0x1000);
 837         /* Adapters that do not support jumbo frames */
 838         case e1000_82583:
 839         case e1000_ich8lan:
 840                 return (ETHER_MAX_LEN);
 841         default:
 842                 return (MAX_JUMBO_FRAME_SIZE);
 843         }
 844 }
 845
 846 static void
 847 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 848 {
 849         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 850
 851         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
 852         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
 853         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
 854
 855         /*
 856          * Starting with 631xESB hw supports 2 TX/RX queues per port.
 857          * Unfortunatelly, all these nics have just one TX context.
 858          * So we have few choises for TX:
 859          * - Use just one TX queue.
 860          * - Allow cksum offload only for one TX queue.
 861          * - Don't allow TX cksum offload at all.
 862          * For now, option #1 was chosen.
 863          * To use second RX queue we have to use extended RX descriptor
 864          * (Multiple Receive Queues are mutually exclusive with UDP
 865          * fragmentation and are not supported when a legacy receive
 866          * descriptor format is used).
 867          * Which means separate RX routinies - as legacy nics (82540, 82545)
 868          * don't support extended RXD.
 869          * To avoid it we support just one RX queue for now (no RSS).
 870          */
 871
 872         dev_info->max_rx_queues = 1;
 873         dev_info->max_tx_queues = 1;
 874 }
 875
 876 /* return 0 means link status changed, -1 means not changed */
 877 static int
 878 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 879 {
 880         struct e1000_hw *hw =
 881                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 882         struct rte_eth_link link, old;
 883         int link_check, count;
 884
 885         link_check = 0;
 886         hw->mac.get_link_status = 1;
 887
 888         /* possible wait-to-complete in up to 9 seconds */
 889         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
 890                 /* Read the real link status */
 891                 switch (hw->phy.media_type) {
 892                 case e1000_media_type_copper:
 893                         /* Do the work to read phy */
 894                         e1000_check_for_link(hw);
 895                         link_check = !hw->mac.get_link_status;
 896                         break;
 897
 898                 case e1000_media_type_fiber:
 899                         e1000_check_for_link(hw);
 900                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
 901                                         E1000_STATUS_LU);
 902                         break;
 903
 904                 case e1000_media_type_internal_serdes:
 905                         e1000_check_for_link(hw);
 906                         link_check = hw->mac.serdes_has_link;
 907                         break;
 908
 909                 default:
 910                         break;
 911                 }
 912                 if (link_check || wait_to_complete == 0)
 913                         break;
 914                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
 915         }
 916         memset(&link, 0, sizeof(link));
 917         rte_em_dev_atomic_read_link_status(dev, &link);
 918         old = link;
 919
 920         /* Now we check if a transition has happened */
 921         if (link_check && (link.link_status == 0)) {
 922                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
 923                         &link.link_duplex);
 924                 link.link_status = 1;
 925         } else if (!link_check && (link.link_status == 1)) {
 926                 link.link_speed = 0;
 927                 link.link_duplex = 0;
 928                 link.link_status = 0;
 929         }
 930         rte_em_dev_atomic_write_link_status(dev, &link);
 931
 932         /* not changed */
 933         if (old.link_status == link.link_status)
 934                 return -1;
 935
 936         /* changed */
 937         return 0;
 938 }
 939
 940 /*
 941  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
 942  * For ASF and Pass Through versions of f/w this means
 943  * that the driver is loaded. For AMT version type f/w
 944  * this means that the network i/f is open.
 945  */
 946 static void
 947 em_hw_control_acquire(struct e1000_hw *hw)
 948 {
 949         uint32_t ctrl_ext, swsm;
 950
 951         /* Let firmware know the driver has taken over */
 952         if (hw->mac.type == e1000_82573) {
 953                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 954                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
 955
 956         } else {
 957                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 958                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 959                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 960         }
 961 }
 962
 963 /*
 964  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
 965  * For ASF and Pass Through versions of f/w this means that the
 966  * driver is no longer loaded. For AMT versions of the
 967  * f/w this means that the network i/f is closed.
 968  */
 969 static void
 970 em_hw_control_release(struct e1000_hw *hw)
 971 {
 972         uint32_t ctrl_ext, swsm;
 973
 974         /* Let firmware taken over control of h/w */
 975         if (hw->mac.type == e1000_82573) {
 976                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 977                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
 978         } else {
 979                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 980                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 981                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 982         }
 983 }
 984
 985 /*
 986  * Bit of a misnomer, what this really means is
 987  * to enable OS management of the system... aka
 988  * to disable special hardware management features.
 989  */
 990 static void
 991 em_init_manageability(struct e1000_hw *hw)
 992 {
 993         if (e1000_enable_mng_pass_thru(hw)) {
 994                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
 995                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
 996
 997                 /* disable hardware interception of ARP */
 998                 manc &= ~(E1000_MANC_ARP_EN);
 999
1000                 /* enable receiving management packets to the host */
1001                 manc |= E1000_MANC_EN_MNG2HOST;
1002                 manc2h |= 1 << 5;  /* Mng Port 623 */
1003                 manc2h |= 1 << 6;  /* Mng Port 664 */
1004                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1005                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1006         }
1007 }
1008
1009 /*
1010  * Give control back to hardware management
1011  * controller if there is one.
1012  */
1013 static void
1014 em_release_manageability(struct e1000_hw *hw)
1015 {
1016         uint32_t manc;
1017
1018         if (e1000_enable_mng_pass_thru(hw)) {
1019                 manc = E1000_READ_REG(hw, E1000_MANC);
1020
1021                 /* re-enable hardware interception of ARP */
1022                 manc |= E1000_MANC_ARP_EN;
1023                 manc &= ~E1000_MANC_EN_MNG2HOST;
1024
1025                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1026         }
1027 }
1028
1029 static void
1030 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1031 {
1032         struct e1000_hw *hw =
1033                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1034         uint32_t rctl;
1035
1036         rctl = E1000_READ_REG(hw, E1000_RCTL);
1037         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1038         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1039 }
1040
1041 static void
1042 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1043 {
1044         struct e1000_hw *hw =
1045                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1046         uint32_t rctl;
1047
1048         rctl = E1000_READ_REG(hw, E1000_RCTL);
1049         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1050         if (dev->data->all_multicast == 1)
1051                 rctl |= E1000_RCTL_MPE;
1052         else
1053                 rctl &= (~E1000_RCTL_MPE);
1054         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1055 }
1056
1057 static void
1058 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1059 {
1060         struct e1000_hw *hw =
1061                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1062         uint32_t rctl;
1063
1064         rctl = E1000_READ_REG(hw, E1000_RCTL);
1065         rctl |= E1000_RCTL_MPE;
1066         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1067 }
1068
1069 static void
1070 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1071 {
1072         struct e1000_hw *hw =
1073                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1074         uint32_t rctl;
1075
1076         if (dev->data->promiscuous == 1)
1077                 return; /* must remain in all_multicast mode */
1078         rctl = E1000_READ_REG(hw, E1000_RCTL);
1079         rctl &= (~E1000_RCTL_MPE);
1080         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1081 }
1082
1083 static int
1084 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1085 {
1086         struct e1000_hw *hw =
1087                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1088         struct e1000_vfta * shadow_vfta =
1089                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1090         uint32_t vfta;
1091         uint32_t vid_idx;
1092         uint32_t vid_bit;
1093
1094         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1095                               E1000_VFTA_ENTRY_MASK);
1096         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1097         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1098         if (on)
1099                 vfta |= vid_bit;
1100         else
1101                 vfta &= ~vid_bit;
1102         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1103
1104         /* update local VFTA copy */
1105         shadow_vfta->vfta[vid_idx] = vfta;
1106
1107         return 0;
1108 }
1109
1110 static void
1111 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1112 {
1113         struct e1000_hw *hw =
1114                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1115         uint32_t reg;
1116
1117         /* Filter Table Disable */
1118         reg = E1000_READ_REG(hw, E1000_RCTL);
1119         reg &= ~E1000_RCTL_CFIEN;
1120         reg &= ~E1000_RCTL_VFE;
1121         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1122 }
1123
1124 static void
1125 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1126 {
1127         struct e1000_hw *hw =
1128                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1129         struct e1000_vfta * shadow_vfta =
1130                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1131         uint32_t reg;
1132         int i;
1133
1134         /* Filter Table Enable, CFI not used for packet acceptance */
1135         reg = E1000_READ_REG(hw, E1000_RCTL);
1136         reg &= ~E1000_RCTL_CFIEN;
1137         reg |= E1000_RCTL_VFE;
1138         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1139
1140         /* restore vfta from local copy */
1141         for (i = 0; i < IGB_VFTA_SIZE; i++)
1142                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1143 }
1144
1145 static void
1146 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1147 {
1148         struct e1000_hw *hw =
1149                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1150         uint32_t reg;
1151
1152         /* VLAN Mode Disable */
1153         reg = E1000_READ_REG(hw, E1000_CTRL);
1154         reg &= ~E1000_CTRL_VME;
1155         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1156
1157 }
1158
1159 static void
1160 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1161 {
1162         struct e1000_hw *hw =
1163                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1164         uint32_t reg;
1165
1166         /* VLAN Mode Enable */
1167         reg = E1000_READ_REG(hw, E1000_CTRL);
1168         reg |= E1000_CTRL_VME;
1169         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1170 }
1171
1172 static void
1173 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1174 {
1175         if(mask & ETH_VLAN_STRIP_MASK){
1176                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1177                         em_vlan_hw_strip_enable(dev);
1178                 else
1179                         em_vlan_hw_strip_disable(dev);
1180         }
1181
1182         if(mask & ETH_VLAN_FILTER_MASK){
1183                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1184                         em_vlan_hw_filter_enable(dev);
1185                 else
1186                         em_vlan_hw_filter_disable(dev);
1187         }
1188 }
1189
1190 static void
1191 em_intr_disable(struct e1000_hw *hw)
1192 {
1193         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1194 }
1195
1196 /**
1197  * It enables the interrupt mask and then enable the interrupt.
1198  *
1199  * @param dev
1200  *  Pointer to struct rte_eth_dev.
1201  *
1202  * @return
1203  *  - On success, zero.
1204  *  - On failure, a negative value.
1205  */
1206 static int
1207 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1208 {
1209         struct e1000_hw *hw =
1210                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1211
1212         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1213         rte_intr_enable(&(dev->pci_dev->intr_handle));
1214         return (0);
1215 }
1216
1217 /*
1218  * It reads ICR and gets interrupt causes, check it and set a bit flag
1219  * to update link status.
1220  *
1221  * @param dev
1222  *  Pointer to struct rte_eth_dev.
1223  *
1224  * @return
1225  *  - On success, zero.
1226  *  - On failure, a negative value.
1227  */
1228 static int
1229 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1230 {
1231         uint32_t icr;
1232         struct e1000_hw *hw =
1233                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1234         struct e1000_interrupt *intr =
1235                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1236
1237         /* read-on-clear nic registers here */
1238         icr = E1000_READ_REG(hw, E1000_ICR);
1239         if (icr & E1000_ICR_LSC) {
1240                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1241         }
1242
1243         return 0;
1244 }
1245
1246 /*
1247  * It executes link_update after knowing an interrupt is prsent.
1248  *
1249  * @param dev
1250  *  Pointer to struct rte_eth_dev.
1251  *
1252  * @return
1253  *  - On success, zero.
1254  *  - On failure, a negative value.
1255  */
1256 static int
1257 eth_em_interrupt_action(struct rte_eth_dev *dev)
1258 {
1259         struct e1000_hw *hw =
1260                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1261         struct e1000_interrupt *intr =
1262                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1263         uint32_t tctl, rctl;
1264         struct rte_eth_link link;
1265         int ret;
1266
1267         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1268                 return -1;
1269
1270         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1271         rte_intr_enable(&(dev->pci_dev->intr_handle));
1272
1273         /* set get_link_status to check register later */
1274         hw->mac.get_link_status = 1;
1275         ret = eth_em_link_update(dev, 0);
1276
1277         /* check if link has changed */
1278         if (ret < 0)
1279                 return 0;
1280
1281         memset(&link, 0, sizeof(link));
1282         rte_em_dev_atomic_read_link_status(dev, &link);
1283         if (link.link_status) {
1284                 PMD_INIT_LOG(INFO,
1285                         " Port %d: Link Up - speed %u Mbps - %s\n",
1286                         dev->data->port_id, (unsigned)link.link_speed,
1287                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1288                                 "full-duplex" : "half-duplex");
1289         } else {
1290                 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1291                                         dev->data->port_id);
1292         }
1293         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1294                                 dev->pci_dev->addr.domain,
1295                                 dev->pci_dev->addr.bus,
1296                                 dev->pci_dev->addr.devid,
1297                                 dev->pci_dev->addr.function);
1298         tctl = E1000_READ_REG(hw, E1000_TCTL);
1299         rctl = E1000_READ_REG(hw, E1000_RCTL);
1300         if (link.link_status) {
1301                 /* enable Tx/Rx */
1302                 tctl |= E1000_TCTL_EN;
1303                 rctl |= E1000_RCTL_EN;
1304         } else {
1305                 /* disable Tx/Rx */
1306                 tctl &= ~E1000_TCTL_EN;
1307                 rctl &= ~E1000_RCTL_EN;
1308         }
1309         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1310         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1311         E1000_WRITE_FLUSH(hw);
1312
1313         return 0;
1314 }
1315
1316 /**
1317  * Interrupt handler which shall be registered at first.
1318  *
1319  * @param handle
1320  *  Pointer to interrupt handle.
1321  * @param param
1322  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1323  *
1324  * @return
1325  *  void
1326  */
1327 static void
1328 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1329                                                         void *param)
1330 {
1331         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1332
1333         eth_em_interrupt_get_status(dev);
1334         eth_em_interrupt_action(dev);
1335         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1336 }
1337
1338 static int
1339 eth_em_led_on(struct rte_eth_dev *dev)
1340 {
1341         struct e1000_hw *hw;
1342
1343         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1344         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1345 }
1346
1347 static int
1348 eth_em_led_off(struct rte_eth_dev *dev)
1349 {
1350         struct e1000_hw *hw;
1351
1352         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1353         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1354 }
1355
1356 static int
1357 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1358 {
1359         struct e1000_hw *hw;
1360         int err;
1361         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1362                 e1000_fc_none,
1363                 e1000_fc_rx_pause,
1364                 e1000_fc_tx_pause,
1365                 e1000_fc_full
1366         };
1367         uint32_t rx_buf_size;
1368         uint32_t max_high_water;
1369
1370         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1371         rx_buf_size = em_get_rx_buffer_size(hw);
1372         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1373
1374         /* At least reserve one Ethernet frame for watermark */
1375         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1376         if ((fc_conf->high_water > max_high_water) ||
1377                 (fc_conf->high_water < fc_conf->low_water)) {
1378                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1379                 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1380                 return (-EINVAL);
1381         }
1382
1383         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1384         hw->fc.pause_time     = fc_conf->pause_time;
1385         hw->fc.high_water     = fc_conf->high_water;
1386         hw->fc.low_water      = fc_conf->low_water;
1387         hw->fc.send_xon       = fc_conf->send_xon;
1388
1389         err = e1000_setup_link_generic(hw);
1390         if (err == E1000_SUCCESS) {
1391                 return 0;
1392         }
1393
1394         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1395         return (-EIO);
1396 }
1397
1398 static void
1399 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1400                 uint32_t index, __rte_unused uint32_t pool)
1401 {
1402         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1403
1404         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1405 }
1406
1407 static void
1408 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1409 {
1410         uint8_t addr[ETHER_ADDR_LEN];
1411         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1412
1413         memset(addr, 0, sizeof(addr));
1414
1415         e1000_rar_set(hw, addr, index);
1416 }