lib/librte_pmd_e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54
  55 #include "e1000_logs.h"
  56 #include "e1000/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 #define EM_EIAC                 0x000DC
  60
  61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  62
  63
  64 static int eth_em_configure(struct rte_eth_dev *dev);
  65 static int eth_em_start(struct rte_eth_dev *dev);
  66 static void eth_em_stop(struct rte_eth_dev *dev);
  67 static void eth_em_close(struct rte_eth_dev *dev);
  68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  72 static int eth_em_link_update(struct rte_eth_dev *dev,
  73                                 int wait_to_complete);
  74 static void eth_em_stats_get(struct rte_eth_dev *dev,
  75                                 struct rte_eth_stats *rte_stats);
  76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  77 static void eth_em_infos_get(struct rte_eth_dev *dev,
  78                                 struct rte_eth_dev_info *dev_info);
  79 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  80                                 struct rte_eth_fc_conf *fc_conf);
  81 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  82 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  83 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
  84 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  85                                                         void *param);
  86
  87 static int em_hw_init(struct e1000_hw *hw);
  88 static int em_hardware_init(struct e1000_hw *hw);
  89 static void em_hw_control_acquire(struct e1000_hw *hw);
  90 static void em_hw_control_release(struct e1000_hw *hw);
  91 static void em_init_manageability(struct e1000_hw *hw);
  92 static void em_release_manageability(struct e1000_hw *hw);
  93
  94 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  95                 uint16_t vlan_id, int on);
  96 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  97 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  98 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  99 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 100 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 101
 102 /*
 103 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 104                                         uint16_t vlan_id, int on);
 105 */
 106 static int eth_em_led_on(struct rte_eth_dev *dev);
 107 static int eth_em_led_off(struct rte_eth_dev *dev);
 108
 109 static void em_intr_disable(struct e1000_hw *hw);
 110 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 111 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 112                 uint32_t index, uint32_t pool);
 113 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 114
 115 #define EM_FC_PAUSE_TIME 0x0680
 116 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 117 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 118
 119 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 120
 121 /*
 122  * The set of PCI devices this driver supports
 123  */
 124 static struct rte_pci_id pci_id_em_map[] = {
 125
 126 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 127 #include "rte_pci_dev_ids.h"
 128
 129 {.device_id = 0},
 130 };
 131
 132 static struct eth_dev_ops eth_em_ops = {
 133         .dev_configure        = eth_em_configure,
 134         .dev_start            = eth_em_start,
 135         .dev_stop             = eth_em_stop,
 136         .dev_close            = eth_em_close,
 137         .promiscuous_enable   = eth_em_promiscuous_enable,
 138         .promiscuous_disable  = eth_em_promiscuous_disable,
 139         .allmulticast_enable  = eth_em_allmulticast_enable,
 140         .allmulticast_disable = eth_em_allmulticast_disable,
 141         .link_update          = eth_em_link_update,
 142         .stats_get            = eth_em_stats_get,
 143         .stats_reset          = eth_em_stats_reset,
 144         .dev_infos_get        = eth_em_infos_get,
 145         .vlan_filter_set      = eth_em_vlan_filter_set,
 146         .vlan_offload_set     = eth_em_vlan_offload_set,
 147         .rx_queue_setup       = eth_em_rx_queue_setup,
 148         .rx_queue_release     = eth_em_rx_queue_release,
 149         .rx_queue_count       = eth_em_rx_queue_count,
 150         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 151         .tx_queue_setup       = eth_em_tx_queue_setup,
 152         .tx_queue_release     = eth_em_tx_queue_release,
 153         .dev_led_on           = eth_em_led_on,
 154         .dev_led_off          = eth_em_led_off,
 155         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 156         .mac_addr_add         = eth_em_rar_set,
 157         .mac_addr_remove      = eth_em_rar_clear,
 158 };
 159
 160 /**
 161  * Atomically reads the link status information from global
 162  * structure rte_eth_dev.
 163  *
 164  * @param dev
 165  *   - Pointer to the structure rte_eth_dev to read from.
 166  *   - Pointer to the buffer to be saved with the link status.
 167  *
 168  * @return
 169  *   - On success, zero.
 170  *   - On failure, negative value.
 171  */
 172 static inline int
 173 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 174                                 struct rte_eth_link *link)
 175 {
 176         struct rte_eth_link *dst = link;
 177         struct rte_eth_link *src = &(dev->data->dev_link);
 178
 179         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 180                                         *(uint64_t *)src) == 0)
 181                 return -1;
 182
 183         return 0;
 184 }
 185
 186 /**
 187  * Atomically writes the link status information into global
 188  * structure rte_eth_dev.
 189  *
 190  * @param dev
 191  *   - Pointer to the structure rte_eth_dev to read from.
 192  *   - Pointer to the buffer to be saved with the link status.
 193  *
 194  * @return
 195  *   - On success, zero.
 196  *   - On failure, negative value.
 197  */
 198 static inline int
 199 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 200                                 struct rte_eth_link *link)
 201 {
 202         struct rte_eth_link *dst = &(dev->data->dev_link);
 203         struct rte_eth_link *src = link;
 204
 205         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 206                                         *(uint64_t *)src) == 0)
 207                 return -1;
 208
 209         return 0;
 210 }
 211
 212 static int
 213 eth_em_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 214                 struct rte_eth_dev *eth_dev)
 215 {
 216         struct rte_pci_device *pci_dev;
 217         struct e1000_hw *hw =
 218                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 219         struct e1000_vfta * shadow_vfta =
 220                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 221
 222         pci_dev = eth_dev->pci_dev;
 223         eth_dev->dev_ops = &eth_em_ops;
 224         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 225         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 226
 227         /* for secondary processes, we don't initialise any further as primary
 228          * has already done this work. Only check we don't need a different
 229          * RX function */
 230         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 231                 if (eth_dev->data->scattered_rx)
 232                         eth_dev->rx_pkt_burst =
 233                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 234                 return 0;
 235         }
 236
 237         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 238         hw->device_id = pci_dev->id.device_id;
 239
 240         /* For ICH8 support we'll need to map the flash memory BAR */
 241
 242         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 243                         em_hw_init(hw) != 0) {
 244                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 245                         "failed to init HW",
 246                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 247                         pci_dev->id.device_id);
 248                 return -(ENODEV);
 249         }
 250
 251         /* Allocate memory for storing MAC addresses */
 252         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 253                         hw->mac.rar_entry_count, 0);
 254         if (eth_dev->data->mac_addrs == NULL) {
 255                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 256                         "store MAC addresses",
 257                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 258                 return -(ENOMEM);
 259         }
 260
 261         /* Copy the permanent MAC address */
 262         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 263                 eth_dev->data->mac_addrs);
 264
 265         /* initialize the vfta */
 266         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 267
 268         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 269                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 270                         pci_dev->id.device_id);
 271
 272         rte_intr_callback_register(&(pci_dev->intr_handle),
 273                 eth_em_interrupt_handler, (void *)eth_dev);
 274
 275         return (0);
 276 }
 277
 278 static struct eth_driver rte_em_pmd = {
 279         {
 280                 .name = "rte_em_pmd",
 281                 .id_table = pci_id_em_map,
 282 #ifdef RTE_EAL_UNBIND_PORTS
 283                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 284 #endif
 285         },
 286         .eth_dev_init = eth_em_dev_init,
 287         .dev_private_size = sizeof(struct e1000_adapter),
 288 };
 289
 290 int
 291 rte_em_pmd_init(void)
 292 {
 293         rte_eth_driver_register(&rte_em_pmd);
 294         return 0;
 295 }
 296
 297 static int
 298 em_hw_init(struct e1000_hw *hw)
 299 {
 300         int diag;
 301
 302         diag = hw->mac.ops.init_params(hw);
 303         if (diag != 0) {
 304                 PMD_INIT_LOG(ERR, "MAC Initialization Error\n");
 305                 return diag;
 306         }
 307         diag = hw->nvm.ops.init_params(hw);
 308         if (diag != 0) {
 309                 PMD_INIT_LOG(ERR, "NVM Initialization Error\n");
 310                 return diag;
 311         }
 312         diag = hw->phy.ops.init_params(hw);
 313         if (diag != 0) {
 314                 PMD_INIT_LOG(ERR, "PHY Initialization Error\n");
 315                 return diag;
 316         }
 317         (void) e1000_get_bus_info(hw);
 318
 319         hw->mac.autoneg = 1;
 320         hw->phy.autoneg_wait_to_complete = 0;
 321         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 322
 323         e1000_init_script_state_82541(hw, TRUE);
 324         e1000_set_tbi_compatibility_82543(hw, TRUE);
 325
 326         /* Copper options */
 327         if (hw->phy.media_type == e1000_media_type_copper) {
 328                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 329                 hw->phy.disable_polarity_correction = 0;
 330                 hw->phy.ms_type = e1000_ms_hw_default;
 331         }
 332
 333         /*
 334          * Start from a known state, this is important in reading the nvm
 335          * and mac from that.
 336          */
 337         e1000_reset_hw(hw);
 338
 339         /* Make sure we have a good EEPROM before we read from it */
 340         if (e1000_validate_nvm_checksum(hw) < 0) {
 341                 /*
 342                  * Some PCI-E parts fail the first check due to
 343                  * the link being in sleep state, call it again,
 344                  * if it fails a second time its a real issue.
 345                  */
 346                 diag = e1000_validate_nvm_checksum(hw);
 347                 if (diag < 0) {
 348                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 349                         goto error;
 350                 }
 351         }
 352
 353         /* Read the permanent MAC address out of the EEPROM */
 354         diag = e1000_read_mac_addr(hw);
 355         if (diag != 0) {
 356                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 357                 goto error;
 358         }
 359
 360         /* Now initialize the hardware */
 361         diag = em_hardware_init(hw);
 362         if (diag != 0) {
 363                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 364                 goto error;
 365         }
 366
 367         hw->mac.get_link_status = 1;
 368
 369         /* Indicate SOL/IDER usage */
 370         diag = e1000_check_reset_block(hw);
 371         if (diag < 0) {
 372                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 373                         "SOL/IDER session");
 374         }
 375         return (0);
 376
 377 error:
 378         em_hw_control_release(hw);
 379         return (diag);
 380 }
 381
 382 static int
 383 eth_em_configure(struct rte_eth_dev *dev)
 384 {
 385         struct e1000_interrupt *intr =
 386                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 387
 388         PMD_INIT_LOG(DEBUG, ">>");
 389
 390         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 391
 392         PMD_INIT_LOG(DEBUG, "<<");
 393         return (0);
 394 }
 395
 396 static void
 397 em_set_pba(struct e1000_hw *hw)
 398 {
 399         uint32_t pba;
 400
 401         /*
 402          * Packet Buffer Allocation (PBA)
 403          * Writing PBA sets the receive portion of the buffer
 404          * the remainder is used for the transmit buffer.
 405          * Devices before the 82547 had a Packet Buffer of 64K.
 406          * After the 82547 the buffer was reduced to 40K.
 407          */
 408         switch (hw->mac.type) {
 409                 case e1000_82547:
 410                 case e1000_82547_rev_2:
 411                 /* 82547: Total Packet Buffer is 40K */
 412                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 413                         break;
 414                 case e1000_82571:
 415                 case e1000_82572:
 416                 case e1000_80003es2lan:
 417                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 418                         break;
 419                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 420                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 421                         break;
 422                 case e1000_82574:
 423                 case e1000_82583:
 424                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 425                         break;
 426                 case e1000_ich8lan:
 427                         pba = E1000_PBA_8K;
 428                         break;
 429                 case e1000_ich9lan:
 430                 case e1000_ich10lan:
 431                         pba = E1000_PBA_10K;
 432                         break;
 433                 case e1000_pchlan:
 434                 case e1000_pch2lan:
 435                         pba = E1000_PBA_26K;
 436                         break;
 437                 default:
 438                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 439         }
 440
 441         E1000_WRITE_REG(hw, E1000_PBA, pba);
 442 }
 443
 444 static int
 445 eth_em_start(struct rte_eth_dev *dev)
 446 {
 447         struct e1000_hw *hw =
 448                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 449         int ret, mask;
 450
 451         PMD_INIT_LOG(DEBUG, ">>");
 452
 453         eth_em_stop(dev);
 454
 455         e1000_power_up_phy(hw);
 456
 457         /* Set default PBA value */
 458         em_set_pba(hw);
 459
 460         /* Put the address into the Receive Address Array */
 461         e1000_rar_set(hw, hw->mac.addr, 0);
 462
 463         /*
 464          * With the 82571 adapter, RAR[0] may be overwritten
 465          * when the other port is reset, we make a duplicate
 466          * in RAR[14] for that eventuality, this assures
 467          * the interface continues to function.
 468          */
 469         if (hw->mac.type == e1000_82571) {
 470                 e1000_set_laa_state_82571(hw, TRUE);
 471                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 472         }
 473
 474         /* Initialize the hardware */
 475         if (em_hardware_init(hw)) {
 476                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 477                 return (-EIO);
 478         }
 479
 480         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 481
 482         /* Configure for OS presence */
 483         em_init_manageability(hw);
 484
 485         eth_em_tx_init(dev);
 486
 487         ret = eth_em_rx_init(dev);
 488         if (ret) {
 489                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 490                 em_dev_clear_queues(dev);
 491                 return ret;
 492         }
 493
 494         e1000_clear_hw_cntrs_base_generic(hw);
 495
 496         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 497                         ETH_VLAN_EXTEND_MASK;
 498         eth_em_vlan_offload_set(dev, mask);
 499
 500         /* Set Interrupt Throttling Rate to maximum allowed value. */
 501         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 502
 503         /* Setup link speed and duplex */
 504         switch (dev->data->dev_conf.link_speed) {
 505         case ETH_LINK_SPEED_AUTONEG:
 506                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 507                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 508                 else if (dev->data->dev_conf.link_duplex ==
 509                                         ETH_LINK_HALF_DUPLEX)
 510                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 511                 else if (dev->data->dev_conf.link_duplex ==
 512                                         ETH_LINK_FULL_DUPLEX)
 513                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 514                 else
 515                         goto error_invalid_config;
 516                 break;
 517         case ETH_LINK_SPEED_10:
 518                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 519                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 520                 else if (dev->data->dev_conf.link_duplex ==
 521                                         ETH_LINK_HALF_DUPLEX)
 522                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 523                 else if (dev->data->dev_conf.link_duplex ==
 524                                         ETH_LINK_FULL_DUPLEX)
 525                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 526                 else
 527                         goto error_invalid_config;
 528                 break;
 529         case ETH_LINK_SPEED_100:
 530                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 531                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 532                 else if (dev->data->dev_conf.link_duplex ==
 533                                         ETH_LINK_HALF_DUPLEX)
 534                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 535                 else if (dev->data->dev_conf.link_duplex ==
 536                                         ETH_LINK_FULL_DUPLEX)
 537                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 538                 else
 539                         goto error_invalid_config;
 540                 break;
 541         case ETH_LINK_SPEED_1000:
 542                 if ((dev->data->dev_conf.link_duplex ==
 543                                 ETH_LINK_AUTONEG_DUPLEX) ||
 544                         (dev->data->dev_conf.link_duplex ==
 545                                         ETH_LINK_FULL_DUPLEX))
 546                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 547                 else
 548                         goto error_invalid_config;
 549                 break;
 550         case ETH_LINK_SPEED_10000:
 551         default:
 552                 goto error_invalid_config;
 553         }
 554         e1000_setup_link(hw);
 555
 556         /* check if lsc interrupt feature is enabled */
 557         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 558                 ret = eth_em_interrupt_setup(dev);
 559                 if (ret) {
 560                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 561                         em_dev_clear_queues(dev);
 562                         return ret;
 563                 }
 564         }
 565
 566         PMD_INIT_LOG(DEBUG, "<<");
 567
 568         return (0);
 569
 570 error_invalid_config:
 571         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port "
 572                                 "%u\n", dev->data->dev_conf.link_speed,
 573                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 574         em_dev_clear_queues(dev);
 575         return (-EINVAL);
 576 }
 577
 578 /*********************************************************************
 579  *
 580  *  This routine disables all traffic on the adapter by issuing a
 581  *  global reset on the MAC.
 582  *
 583  **********************************************************************/
 584 static void
 585 eth_em_stop(struct rte_eth_dev *dev)
 586 {
 587         struct rte_eth_link link;
 588         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 589
 590         em_intr_disable(hw);
 591         e1000_reset_hw(hw);
 592         if (hw->mac.type >= e1000_82544)
 593                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 594
 595         /* Power down the phy. Needed to make the link go down */
 596         e1000_power_down_phy(hw);
 597
 598         em_dev_clear_queues(dev);
 599
 600         /* clear the recorded link status */
 601         memset(&link, 0, sizeof(link));
 602         rte_em_dev_atomic_write_link_status(dev, &link);
 603 }
 604
 605 static void
 606 eth_em_close(struct rte_eth_dev *dev)
 607 {
 608         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 609
 610         eth_em_stop(dev);
 611         e1000_phy_hw_reset(hw);
 612         em_release_manageability(hw);
 613         em_hw_control_release(hw);
 614 }
 615
 616 static int
 617 em_get_rx_buffer_size(struct e1000_hw *hw)
 618 {
 619         uint32_t rx_buf_size;
 620
 621         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 622         return rx_buf_size;
 623 }
 624
 625 /*********************************************************************
 626  *
 627  *  Initialize the hardware
 628  *
 629  **********************************************************************/
 630 static int
 631 em_hardware_init(struct e1000_hw *hw)
 632 {
 633         uint32_t rx_buf_size;
 634         int diag;
 635
 636         /* Issue a global reset */
 637         e1000_reset_hw(hw);
 638
 639         /* Let the firmware know the OS is in control */
 640         em_hw_control_acquire(hw);
 641
 642         /*
 643          * These parameters control the automatic generation (Tx) and
 644          * response (Rx) to Ethernet PAUSE frames.
 645          * - High water mark should allow for at least two standard size (1518)
 646          *   frames to be received after sending an XOFF.
 647          * - Low water mark works best when it is very near the high water mark.
 648          *   This allows the receiver to restart by sending XON when it has
 649          *   drained a bit. Here we use an arbitary value of 1500 which will
 650          *   restart after one full frame is pulled from the buffer. There
 651          *   could be several smaller frames in the buffer and if so they will
 652          *   not trigger the XON until their total number reduces the buffer
 653          *   by 1500.
 654          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 655          */
 656         rx_buf_size = em_get_rx_buffer_size(hw);
 657
 658         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 659         hw->fc.low_water = hw->fc.high_water - 1500;
 660
 661         if (hw->mac.type == e1000_80003es2lan)
 662                 hw->fc.pause_time = UINT16_MAX;
 663         else
 664                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 665
 666         hw->fc.send_xon = 1;
 667
 668         /* Set Flow control, use the tunable location if sane */
 669         if (em_fc_setting <= e1000_fc_full)
 670                 hw->fc.requested_mode = em_fc_setting;
 671         else
 672                 hw->fc.requested_mode = e1000_fc_none;
 673
 674         /* Workaround: no TX flow ctrl for PCH */
 675         if (hw->mac.type == e1000_pchlan)
 676                 hw->fc.requested_mode = e1000_fc_rx_pause;
 677
 678         /* Override - settings for PCH2LAN, ya its magic :) */
 679         if (hw->mac.type == e1000_pch2lan) {
 680                 hw->fc.high_water = 0x5C20;
 681                 hw->fc.low_water = 0x5048;
 682                 hw->fc.pause_time = 0x0650;
 683                 hw->fc.refresh_time = 0x0400;
 684         }
 685
 686         diag = e1000_init_hw(hw);
 687         if (diag < 0)
 688                 return (diag);
 689         e1000_check_for_link(hw);
 690         return (0);
 691 }
 692
 693 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 694 static void
 695 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 696 {
 697         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 698         struct e1000_hw_stats *stats =
 699                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 700         int pause_frames;
 701
 702         if(hw->phy.media_type == e1000_media_type_copper ||
 703                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 704                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 705                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 706         }
 707
 708         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 709         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 710         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 711         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 712
 713         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 714         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 715         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 716         stats->dc += E1000_READ_REG(hw, E1000_DC);
 717         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 718         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 719         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 720
 721         /*
 722          * For watchdog management we need to know if we have been
 723          * paused during the last interval, so capture that here.
 724          */
 725         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 726         stats->xoffrxc += pause_frames;
 727         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 728         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 729         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 730         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 731         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 732         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 733         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 734         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 735         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 736         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 737         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 738         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 739
 740         /*
 741          * For the 64-bit byte counters the low dword must be read first.
 742          * Both registers clear on the read of the high dword.
 743          */
 744
 745         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 746         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 747         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 748         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 749
 750         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 751         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 752         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 753         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 754         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 755
 756         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 757         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 758
 759         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 760         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 761         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 762         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 763         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 764         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 765         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 766         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 767         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 768         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 769
 770         /* Interrupt Counts */
 771
 772         if (hw->mac.type >= e1000_82571) {
 773                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 774                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 775                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 776                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 777                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 778                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 779                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 780                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 781                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 782         }
 783
 784         if (hw->mac.type >= e1000_82543) {
 785                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 786                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 787                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 788                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 789                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 790                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 791         }
 792
 793         if (rte_stats == NULL)
 794                 return;
 795
 796         /* Rx Errors */
 797         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 798                 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 799
 800         /* Tx Errors */
 801         rte_stats->oerrors = stats->ecol + stats->latecol;
 802
 803         rte_stats->ipackets = stats->gprc;
 804         rte_stats->opackets = stats->gptc;
 805         rte_stats->ibytes   = stats->gorc;
 806         rte_stats->obytes   = stats->gotc;
 807 }
 808
 809 static void
 810 eth_em_stats_reset(struct rte_eth_dev *dev)
 811 {
 812         struct e1000_hw_stats *hw_stats =
 813                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 814
 815         /* HW registers are cleared on read */
 816         eth_em_stats_get(dev, NULL);
 817
 818         /* Reset software totals */
 819         memset(hw_stats, 0, sizeof(*hw_stats));
 820 }
 821
 822 static uint32_t
 823 em_get_max_pktlen(const struct e1000_hw *hw)
 824 {
 825         switch (hw->mac.type) {
 826         case e1000_82571:
 827         case e1000_82572:
 828         case e1000_ich9lan:
 829         case e1000_ich10lan:
 830         case e1000_pch2lan:
 831         case e1000_82574:
 832         case e1000_80003es2lan: /* 9K Jumbo Frame size */
 833                 return (0x2412);
 834         case e1000_pchlan:
 835                 return (0x1000);
 836         /* Adapters that do not support jumbo frames */
 837         case e1000_82583:
 838         case e1000_ich8lan:
 839                 return (ETHER_MAX_LEN);
 840         default:
 841                 return (MAX_JUMBO_FRAME_SIZE);
 842         }
 843 }
 844
 845 static void
 846 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 847 {
 848         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 849
 850         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
 851         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
 852         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
 853
 854         /*
 855          * Starting with 631xESB hw supports 2 TX/RX queues per port.
 856          * Unfortunatelly, all these nics have just one TX context.
 857          * So we have few choises for TX:
 858          * - Use just one TX queue.
 859          * - Allow cksum offload only for one TX queue.
 860          * - Don't allow TX cksum offload at all.
 861          * For now, option #1 was chosen.
 862          * To use second RX queue we have to use extended RX descriptor
 863          * (Multiple Receive Queues are mutually exclusive with UDP
 864          * fragmentation and are not supported when a legacy receive
 865          * descriptor format is used).
 866          * Which means separate RX routinies - as legacy nics (82540, 82545)
 867          * don't support extended RXD.
 868          * To avoid it we support just one RX queue for now (no RSS).
 869          */
 870
 871         dev_info->max_rx_queues = 1;
 872         dev_info->max_tx_queues = 1;
 873 }
 874
 875 /* return 0 means link status changed, -1 means not changed */
 876 static int
 877 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 878 {
 879         struct e1000_hw *hw =
 880                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 881         struct rte_eth_link link, old;
 882         int link_check, count;
 883
 884         link_check = 0;
 885         hw->mac.get_link_status = 1;
 886
 887         /* possible wait-to-complete in up to 9 seconds */
 888         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
 889                 /* Read the real link status */
 890                 switch (hw->phy.media_type) {
 891                 case e1000_media_type_copper:
 892                         /* Do the work to read phy */
 893                         e1000_check_for_link(hw);
 894                         link_check = !hw->mac.get_link_status;
 895                         break;
 896
 897                 case e1000_media_type_fiber:
 898                         e1000_check_for_link(hw);
 899                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
 900                                         E1000_STATUS_LU);
 901                         break;
 902
 903                 case e1000_media_type_internal_serdes:
 904                         e1000_check_for_link(hw);
 905                         link_check = hw->mac.serdes_has_link;
 906                         break;
 907
 908                 default:
 909                         break;
 910                 }
 911                 if (link_check || wait_to_complete == 0)
 912                         break;
 913                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
 914         }
 915         memset(&link, 0, sizeof(link));
 916         rte_em_dev_atomic_read_link_status(dev, &link);
 917         old = link;
 918
 919         /* Now we check if a transition has happened */
 920         if (link_check && (link.link_status == 0)) {
 921                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
 922                         &link.link_duplex);
 923                 link.link_status = 1;
 924         } else if (!link_check && (link.link_status == 1)) {
 925                 link.link_speed = 0;
 926                 link.link_duplex = 0;
 927                 link.link_status = 0;
 928         }
 929         rte_em_dev_atomic_write_link_status(dev, &link);
 930
 931         /* not changed */
 932         if (old.link_status == link.link_status)
 933                 return -1;
 934
 935         /* changed */
 936         return 0;
 937 }
 938
 939 /*
 940  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
 941  * For ASF and Pass Through versions of f/w this means
 942  * that the driver is loaded. For AMT version type f/w
 943  * this means that the network i/f is open.
 944  */
 945 static void
 946 em_hw_control_acquire(struct e1000_hw *hw)
 947 {
 948         uint32_t ctrl_ext, swsm;
 949
 950         /* Let firmware know the driver has taken over */
 951         if (hw->mac.type == e1000_82573) {
 952                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 953                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
 954
 955         } else {
 956                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 957                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 958                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 959         }
 960 }
 961
 962 /*
 963  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
 964  * For ASF and Pass Through versions of f/w this means that the
 965  * driver is no longer loaded. For AMT versions of the
 966  * f/w this means that the network i/f is closed.
 967  */
 968 static void
 969 em_hw_control_release(struct e1000_hw *hw)
 970 {
 971         uint32_t ctrl_ext, swsm;
 972
 973         /* Let firmware taken over control of h/w */
 974         if (hw->mac.type == e1000_82573) {
 975                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 976                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
 977         } else {
 978                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 979                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 980                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 981         }
 982 }
 983
 984 /*
 985  * Bit of a misnomer, what this really means is
 986  * to enable OS management of the system... aka
 987  * to disable special hardware management features.
 988  */
 989 static void
 990 em_init_manageability(struct e1000_hw *hw)
 991 {
 992         if (e1000_enable_mng_pass_thru(hw)) {
 993                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
 994                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
 995
 996                 /* disable hardware interception of ARP */
 997                 manc &= ~(E1000_MANC_ARP_EN);
 998
 999                 /* enable receiving management packets to the host */
1000                 manc |= E1000_MANC_EN_MNG2HOST;
1001                 manc2h |= 1 << 5;  /* Mng Port 623 */
1002                 manc2h |= 1 << 6;  /* Mng Port 664 */
1003                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1004                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1005         }
1006 }
1007
1008 /*
1009  * Give control back to hardware management
1010  * controller if there is one.
1011  */
1012 static void
1013 em_release_manageability(struct e1000_hw *hw)
1014 {
1015         uint32_t manc;
1016
1017         if (e1000_enable_mng_pass_thru(hw)) {
1018                 manc = E1000_READ_REG(hw, E1000_MANC);
1019
1020                 /* re-enable hardware interception of ARP */
1021                 manc |= E1000_MANC_ARP_EN;
1022                 manc &= ~E1000_MANC_EN_MNG2HOST;
1023
1024                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1025         }
1026 }
1027
1028 static void
1029 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1030 {
1031         struct e1000_hw *hw =
1032                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1033         uint32_t rctl;
1034
1035         rctl = E1000_READ_REG(hw, E1000_RCTL);
1036         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1037         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1038 }
1039
1040 static void
1041 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1042 {
1043         struct e1000_hw *hw =
1044                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1045         uint32_t rctl;
1046
1047         rctl = E1000_READ_REG(hw, E1000_RCTL);
1048         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1049         if (dev->data->all_multicast == 1)
1050                 rctl |= E1000_RCTL_MPE;
1051         else
1052                 rctl &= (~E1000_RCTL_MPE);
1053         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1054 }
1055
1056 static void
1057 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1058 {
1059         struct e1000_hw *hw =
1060                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1061         uint32_t rctl;
1062
1063         rctl = E1000_READ_REG(hw, E1000_RCTL);
1064         rctl |= E1000_RCTL_MPE;
1065         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1066 }
1067
1068 static void
1069 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1070 {
1071         struct e1000_hw *hw =
1072                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1073         uint32_t rctl;
1074
1075         if (dev->data->promiscuous == 1)
1076                 return; /* must remain in all_multicast mode */
1077         rctl = E1000_READ_REG(hw, E1000_RCTL);
1078         rctl &= (~E1000_RCTL_MPE);
1079         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1080 }
1081
1082 static int
1083 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1084 {
1085         struct e1000_hw *hw =
1086                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1087         struct e1000_vfta * shadow_vfta =
1088                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1089         uint32_t vfta;
1090         uint32_t vid_idx;
1091         uint32_t vid_bit;
1092
1093         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1094                               E1000_VFTA_ENTRY_MASK);
1095         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1096         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1097         if (on)
1098                 vfta |= vid_bit;
1099         else
1100                 vfta &= ~vid_bit;
1101         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1102
1103         /* update local VFTA copy */
1104         shadow_vfta->vfta[vid_idx] = vfta;
1105
1106         return 0;
1107 }
1108
1109 static void
1110 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1111 {
1112         struct e1000_hw *hw =
1113                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1114         uint32_t reg;
1115
1116         /* Filter Table Disable */
1117         reg = E1000_READ_REG(hw, E1000_RCTL);
1118         reg &= ~E1000_RCTL_CFIEN;
1119         reg &= ~E1000_RCTL_VFE;
1120         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1121 }
1122
1123 static void
1124 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1125 {
1126         struct e1000_hw *hw =
1127                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1128         struct e1000_vfta * shadow_vfta =
1129                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1130         uint32_t reg;
1131         int i;
1132
1133         /* Filter Table Enable, CFI not used for packet acceptance */
1134         reg = E1000_READ_REG(hw, E1000_RCTL);
1135         reg &= ~E1000_RCTL_CFIEN;
1136         reg |= E1000_RCTL_VFE;
1137         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1138
1139         /* restore vfta from local copy */
1140         for (i = 0; i < IGB_VFTA_SIZE; i++)
1141                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1142 }
1143
1144 static void
1145 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1146 {
1147         struct e1000_hw *hw =
1148                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1149         uint32_t reg;
1150
1151         /* VLAN Mode Disable */
1152         reg = E1000_READ_REG(hw, E1000_CTRL);
1153         reg &= ~E1000_CTRL_VME;
1154         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1155
1156 }
1157
1158 static void
1159 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1160 {
1161         struct e1000_hw *hw =
1162                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1163         uint32_t reg;
1164
1165         /* VLAN Mode Enable */
1166         reg = E1000_READ_REG(hw, E1000_CTRL);
1167         reg |= E1000_CTRL_VME;
1168         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1169 }
1170
1171 static void
1172 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1173 {
1174         if(mask & ETH_VLAN_STRIP_MASK){
1175                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1176                         em_vlan_hw_strip_enable(dev);
1177                 else
1178                         em_vlan_hw_strip_disable(dev);
1179         }
1180
1181         if(mask & ETH_VLAN_FILTER_MASK){
1182                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1183                         em_vlan_hw_filter_enable(dev);
1184                 else
1185                         em_vlan_hw_filter_disable(dev);
1186         }
1187 }
1188
1189 static void
1190 em_intr_disable(struct e1000_hw *hw)
1191 {
1192         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1193 }
1194
1195 /**
1196  * It enables the interrupt mask and then enable the interrupt.
1197  *
1198  * @param dev
1199  *  Pointer to struct rte_eth_dev.
1200  *
1201  * @return
1202  *  - On success, zero.
1203  *  - On failure, a negative value.
1204  */
1205 static int
1206 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1207 {
1208         struct e1000_hw *hw =
1209                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1210
1211         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1212         rte_intr_enable(&(dev->pci_dev->intr_handle));
1213         return (0);
1214 }
1215
1216 /*
1217  * It reads ICR and gets interrupt causes, check it and set a bit flag
1218  * to update link status.
1219  *
1220  * @param dev
1221  *  Pointer to struct rte_eth_dev.
1222  *
1223  * @return
1224  *  - On success, zero.
1225  *  - On failure, a negative value.
1226  */
1227 static int
1228 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1229 {
1230         uint32_t icr;
1231         struct e1000_hw *hw =
1232                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1233         struct e1000_interrupt *intr =
1234                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1235
1236         /* read-on-clear nic registers here */
1237         icr = E1000_READ_REG(hw, E1000_ICR);
1238         if (icr & E1000_ICR_LSC) {
1239                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1240         }
1241
1242         return 0;
1243 }
1244
1245 /*
1246  * It executes link_update after knowing an interrupt is prsent.
1247  *
1248  * @param dev
1249  *  Pointer to struct rte_eth_dev.
1250  *
1251  * @return
1252  *  - On success, zero.
1253  *  - On failure, a negative value.
1254  */
1255 static int
1256 eth_em_interrupt_action(struct rte_eth_dev *dev)
1257 {
1258         struct e1000_hw *hw =
1259                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1260         struct e1000_interrupt *intr =
1261                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1262         uint32_t tctl, rctl;
1263         struct rte_eth_link link;
1264         int ret;
1265
1266         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1267                 return -1;
1268
1269         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1270         rte_intr_enable(&(dev->pci_dev->intr_handle));
1271
1272         /* set get_link_status to check register later */
1273         hw->mac.get_link_status = 1;
1274         ret = eth_em_link_update(dev, 0);
1275
1276         /* check if link has changed */
1277         if (ret < 0)
1278                 return 0;
1279
1280         memset(&link, 0, sizeof(link));
1281         rte_em_dev_atomic_read_link_status(dev, &link);
1282         if (link.link_status) {
1283                 PMD_INIT_LOG(INFO,
1284                         " Port %d: Link Up - speed %u Mbps - %s\n",
1285                         dev->data->port_id, (unsigned)link.link_speed,
1286                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1287                                 "full-duplex" : "half-duplex");
1288         } else {
1289                 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1290                                         dev->data->port_id);
1291         }
1292         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1293                                 dev->pci_dev->addr.domain,
1294                                 dev->pci_dev->addr.bus,
1295                                 dev->pci_dev->addr.devid,
1296                                 dev->pci_dev->addr.function);
1297         tctl = E1000_READ_REG(hw, E1000_TCTL);
1298         rctl = E1000_READ_REG(hw, E1000_RCTL);
1299         if (link.link_status) {
1300                 /* enable Tx/Rx */
1301                 tctl |= E1000_TCTL_EN;
1302                 rctl |= E1000_RCTL_EN;
1303         } else {
1304                 /* disable Tx/Rx */
1305                 tctl &= ~E1000_TCTL_EN;
1306                 rctl &= ~E1000_RCTL_EN;
1307         }
1308         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1309         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1310         E1000_WRITE_FLUSH(hw);
1311
1312         return 0;
1313 }
1314
1315 /**
1316  * Interrupt handler which shall be registered at first.
1317  *
1318  * @param handle
1319  *  Pointer to interrupt handle.
1320  * @param param
1321  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1322  *
1323  * @return
1324  *  void
1325  */
1326 static void
1327 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1328                                                         void *param)
1329 {
1330         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1331
1332         eth_em_interrupt_get_status(dev);
1333         eth_em_interrupt_action(dev);
1334         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1335 }
1336
1337 static int
1338 eth_em_led_on(struct rte_eth_dev *dev)
1339 {
1340         struct e1000_hw *hw;
1341
1342         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1343         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1344 }
1345
1346 static int
1347 eth_em_led_off(struct rte_eth_dev *dev)
1348 {
1349         struct e1000_hw *hw;
1350
1351         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1353 }
1354
1355 static int
1356 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1357 {
1358         struct e1000_hw *hw;
1359         int err;
1360         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1361                 e1000_fc_none,
1362                 e1000_fc_rx_pause,
1363                 e1000_fc_tx_pause,
1364                 e1000_fc_full
1365         };
1366         uint32_t rx_buf_size;
1367         uint32_t max_high_water;
1368
1369         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1370         rx_buf_size = em_get_rx_buffer_size(hw);
1371         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1372
1373         /* At least reserve one Ethernet frame for watermark */
1374         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1375         if ((fc_conf->high_water > max_high_water) ||
1376                 (fc_conf->high_water < fc_conf->low_water)) {
1377                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1378                 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1379                 return (-EINVAL);
1380         }
1381
1382         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1383         hw->fc.pause_time     = fc_conf->pause_time;
1384         hw->fc.high_water     = fc_conf->high_water;
1385         hw->fc.low_water      = fc_conf->low_water;
1386         hw->fc.send_xon       = fc_conf->send_xon;
1387
1388         err = e1000_setup_link_generic(hw);
1389         if (err == E1000_SUCCESS) {
1390                 return 0;
1391         }
1392
1393         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1394         return (-EIO);
1395 }
1396
1397 static void
1398 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1399                 uint32_t index, __rte_unused uint32_t pool)
1400 {
1401         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1402
1403         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1404 }
1405
1406 static void
1407 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1408 {
1409         uint8_t addr[ETHER_ADDR_LEN];
1410         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1411
1412         memset(addr, 0, sizeof(addr));
1413
1414         e1000_rar_set(hw, addr, index);
1415 }