lib/librte_pmd_e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #include <sys/queue.h>
  36 #include <stdio.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40
  41 #include <rte_common.h>
  42 #include <rte_interrupts.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_tailq.h>
  52 #include <rte_eal.h>
  53 #include <rte_atomic.h>
  54 #include <rte_malloc.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 #define EM_EIAC                 0x000DC
  61
  62 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  63
  64
  65 static int eth_em_configure(struct rte_eth_dev *dev);
  66 static int eth_em_start(struct rte_eth_dev *dev);
  67 static void eth_em_stop(struct rte_eth_dev *dev);
  68 static void eth_em_close(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  70 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  72 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  73 static int eth_em_link_update(struct rte_eth_dev *dev,
  74                                 int wait_to_complete);
  75 static void eth_em_stats_get(struct rte_eth_dev *dev,
  76                                 struct rte_eth_stats *rte_stats);
  77 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  78 static void eth_em_infos_get(struct rte_eth_dev *dev,
  79                                 struct rte_eth_dev_info *dev_info);
  80 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  81                                 struct rte_eth_fc_conf *fc_conf);
  82 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  83 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  84 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
  85 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  86                                                         void *param);
  87
  88 static int em_hw_init(struct e1000_hw *hw);
  89 static int em_hardware_init(struct e1000_hw *hw);
  90 static void em_hw_control_acquire(struct e1000_hw *hw);
  91 static void em_hw_control_release(struct e1000_hw *hw);
  92 static void em_init_manageability(struct e1000_hw *hw);
  93 static void em_release_manageability(struct e1000_hw *hw);
  94
  95 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  96                 uint16_t vlan_id, int on);
  97 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  98 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  99 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 100 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 101 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 102
 103 /*
 104 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 105                                         uint16_t vlan_id, int on);
 106 */
 107 static int eth_em_led_on(struct rte_eth_dev *dev);
 108 static int eth_em_led_off(struct rte_eth_dev *dev);
 109
 110 static void em_intr_disable(struct e1000_hw *hw);
 111 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 112 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 113                 uint32_t index, uint32_t pool);
 114 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 115
 116 #define EM_FC_PAUSE_TIME 0x0680
 117 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 118 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 119
 120 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 121
 122 /*
 123  * The set of PCI devices this driver supports
 124  */
 125 static struct rte_pci_id pci_id_em_map[] = {
 126
 127 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 128 #include "rte_pci_dev_ids.h"
 129
 130 {.device_id = 0},
 131 };
 132
 133 static struct eth_dev_ops eth_em_ops = {
 134         .dev_configure        = eth_em_configure,
 135         .dev_start            = eth_em_start,
 136         .dev_stop             = eth_em_stop,
 137         .dev_close            = eth_em_close,
 138         .promiscuous_enable   = eth_em_promiscuous_enable,
 139         .promiscuous_disable  = eth_em_promiscuous_disable,
 140         .allmulticast_enable  = eth_em_allmulticast_enable,
 141         .allmulticast_disable = eth_em_allmulticast_disable,
 142         .link_update          = eth_em_link_update,
 143         .stats_get            = eth_em_stats_get,
 144         .stats_reset          = eth_em_stats_reset,
 145         .dev_infos_get        = eth_em_infos_get,
 146         .vlan_filter_set      = eth_em_vlan_filter_set,
 147         .vlan_offload_set     = eth_em_vlan_offload_set,
 148         .rx_queue_setup       = eth_em_rx_queue_setup,
 149         .rx_queue_release     = eth_em_rx_queue_release,
 150         .tx_queue_setup       = eth_em_tx_queue_setup,
 151         .tx_queue_release     = eth_em_tx_queue_release,
 152         .dev_led_on           = eth_em_led_on,
 153         .dev_led_off          = eth_em_led_off,
 154         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 155         .mac_addr_add         = eth_em_rar_set,
 156         .mac_addr_remove      = eth_em_rar_clear,
 157 };
 158
 159 /**
 160  * Atomically reads the link status information from global
 161  * structure rte_eth_dev.
 162  *
 163  * @param dev
 164  *   - Pointer to the structure rte_eth_dev to read from.
 165  *   - Pointer to the buffer to be saved with the link status.
 166  *
 167  * @return
 168  *   - On success, zero.
 169  *   - On failure, negative value.
 170  */
 171 static inline int
 172 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 173                                 struct rte_eth_link *link)
 174 {
 175         struct rte_eth_link *dst = link;
 176         struct rte_eth_link *src = &(dev->data->dev_link);
 177
 178         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 179                                         *(uint64_t *)src) == 0)
 180                 return -1;
 181
 182         return 0;
 183 }
 184
 185 /**
 186  * Atomically writes the link status information into global
 187  * structure rte_eth_dev.
 188  *
 189  * @param dev
 190  *   - Pointer to the structure rte_eth_dev to read from.
 191  *   - Pointer to the buffer to be saved with the link status.
 192  *
 193  * @return
 194  *   - On success, zero.
 195  *   - On failure, negative value.
 196  */
 197 static inline int
 198 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 199                                 struct rte_eth_link *link)
 200 {
 201         struct rte_eth_link *dst = &(dev->data->dev_link);
 202         struct rte_eth_link *src = link;
 203
 204         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 205                                         *(uint64_t *)src) == 0)
 206                 return -1;
 207
 208         return 0;
 209 }
 210
 211 static int
 212 eth_em_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 213                 struct rte_eth_dev *eth_dev)
 214 {
 215         struct rte_pci_device *pci_dev;
 216         struct e1000_hw *hw =
 217                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 218         struct e1000_vfta * shadow_vfta =
 219                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 220
 221         pci_dev = eth_dev->pci_dev;
 222         eth_dev->dev_ops = &eth_em_ops;
 223         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 224         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 225
 226         /* for secondary processes, we don't initialise any further as primary
 227          * has already done this work. Only check we don't need a different
 228          * RX function */
 229         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 230                 if (eth_dev->data->scattered_rx)
 231                         eth_dev->rx_pkt_burst =
 232                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 233                 return 0;
 234         }
 235
 236         hw->hw_addr = (void *)pci_dev->mem_resource.addr;
 237         hw->device_id = pci_dev->id.device_id;
 238
 239         /* For ICH8 support we'll need to map the flash memory BAR */
 240
 241         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 242                         em_hw_init(hw) != 0) {
 243                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 244                         "failed to init HW",
 245                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 246                         pci_dev->id.device_id);
 247                 return -(ENODEV);
 248         }
 249
 250         /* Allocate memory for storing MAC addresses */
 251         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 252                         hw->mac.rar_entry_count, 0);
 253         if (eth_dev->data->mac_addrs == NULL) {
 254                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 255                         "store MAC addresses",
 256                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 257                 return -(ENOMEM);
 258         }
 259
 260         /* Copy the permanent MAC address */
 261         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 262                 eth_dev->data->mac_addrs);
 263
 264         /* initialize the vfta */
 265         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 266
 267         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 268                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 269                         pci_dev->id.device_id);
 270
 271         rte_intr_callback_register(&(pci_dev->intr_handle),
 272                 eth_em_interrupt_handler, (void *)eth_dev);
 273
 274         return (0);
 275 }
 276
 277 static struct eth_driver rte_em_pmd = {
 278         {
 279                 .name = "rte_em_pmd",
 280                 .id_table = pci_id_em_map,
 281                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 282         },
 283         .eth_dev_init = eth_em_dev_init,
 284         .dev_private_size = sizeof(struct e1000_adapter),
 285 };
 286
 287 int
 288 rte_em_pmd_init(void)
 289 {
 290         rte_eth_driver_register(&rte_em_pmd);
 291         return 0;
 292 }
 293
 294 static int
 295 em_hw_init(struct e1000_hw *hw)
 296 {
 297         int diag;
 298
 299         diag = hw->mac.ops.init_params(hw);
 300         if (diag != 0) {
 301                 PMD_INIT_LOG(ERR, "MAC Initialization Error\n");
 302                 return diag;
 303         }
 304         diag = hw->nvm.ops.init_params(hw);
 305         if (diag != 0) {
 306                 PMD_INIT_LOG(ERR, "NVM Initialization Error\n");
 307                 return diag;
 308         }
 309         diag = hw->phy.ops.init_params(hw);
 310         if (diag != 0) {
 311                 PMD_INIT_LOG(ERR, "PHY Initialization Error\n");
 312                 return diag;
 313         }
 314         (void) e1000_get_bus_info(hw);
 315
 316         hw->mac.autoneg = 1;
 317         hw->phy.autoneg_wait_to_complete = 0;
 318         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 319
 320         e1000_init_script_state_82541(hw, TRUE);
 321         e1000_set_tbi_compatibility_82543(hw, TRUE);
 322
 323         /* Copper options */
 324         if (hw->phy.media_type == e1000_media_type_copper) {
 325                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 326                 hw->phy.disable_polarity_correction = 0;
 327                 hw->phy.ms_type = e1000_ms_hw_default;
 328         }
 329
 330         /*
 331          * Start from a known state, this is important in reading the nvm
 332          * and mac from that.
 333          */
 334         e1000_reset_hw(hw);
 335
 336         /* Make sure we have a good EEPROM before we read from it */
 337         if (e1000_validate_nvm_checksum(hw) < 0) {
 338                 /*
 339                  * Some PCI-E parts fail the first check due to
 340                  * the link being in sleep state, call it again,
 341                  * if it fails a second time its a real issue.
 342                  */
 343                 diag = e1000_validate_nvm_checksum(hw);
 344                 if (diag < 0) {
 345                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 346                         goto error;
 347                 }
 348         }
 349
 350         /* Read the permanent MAC address out of the EEPROM */
 351         diag = e1000_read_mac_addr(hw);
 352         if (diag != 0) {
 353                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 354                 goto error;
 355         }
 356
 357         /* Now initialize the hardware */
 358         diag = em_hardware_init(hw);
 359         if (diag != 0) {
 360                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 361                 goto error;
 362         }
 363
 364         hw->mac.get_link_status = 1;
 365
 366         /* Indicate SOL/IDER usage */
 367         diag = e1000_check_reset_block(hw);
 368         if (diag < 0) {
 369                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 370                         "SOL/IDER session");
 371         }
 372         return (0);
 373
 374 error:
 375         em_hw_control_release(hw);
 376         return (diag);
 377 }
 378
 379 static int
 380 eth_em_configure(struct rte_eth_dev *dev)
 381 {
 382         struct e1000_interrupt *intr =
 383                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 384
 385         PMD_INIT_LOG(DEBUG, ">>");
 386
 387         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 388
 389         PMD_INIT_LOG(DEBUG, "<<");
 390         return (0);
 391 }
 392
 393 static void
 394 em_set_pba(struct e1000_hw *hw)
 395 {
 396         uint32_t pba;
 397
 398         /*
 399          * Packet Buffer Allocation (PBA)
 400          * Writing PBA sets the receive portion of the buffer
 401          * the remainder is used for the transmit buffer.
 402          * Devices before the 82547 had a Packet Buffer of 64K.
 403          * After the 82547 the buffer was reduced to 40K.
 404          */
 405         switch (hw->mac.type) {
 406                 case e1000_82547:
 407                 case e1000_82547_rev_2:
 408                 /* 82547: Total Packet Buffer is 40K */
 409                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 410                         break;
 411                 case e1000_82571:
 412                 case e1000_82572:
 413                 case e1000_80003es2lan:
 414                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 415                         break;
 416                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 417                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 418                         break;
 419                 case e1000_82574:
 420                 case e1000_82583:
 421                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 422                         break;
 423                 case e1000_ich8lan:
 424                         pba = E1000_PBA_8K;
 425                         break;
 426                 case e1000_ich9lan:
 427                 case e1000_ich10lan:
 428                         pba = E1000_PBA_10K;
 429                         break;
 430                 case e1000_pchlan:
 431                 case e1000_pch2lan:
 432                         pba = E1000_PBA_26K;
 433                         break;
 434                 default:
 435                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 436         }
 437
 438         E1000_WRITE_REG(hw, E1000_PBA, pba);
 439 }
 440
 441 static int
 442 eth_em_start(struct rte_eth_dev *dev)
 443 {
 444         struct e1000_hw *hw =
 445                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 446         int ret, mask;
 447
 448         PMD_INIT_LOG(DEBUG, ">>");
 449
 450         eth_em_stop(dev);
 451
 452         e1000_power_up_phy(hw);
 453
 454         /* Set default PBA value */
 455         em_set_pba(hw);
 456
 457         /* Put the address into the Receive Address Array */
 458         e1000_rar_set(hw, hw->mac.addr, 0);
 459
 460         /*
 461          * With the 82571 adapter, RAR[0] may be overwritten
 462          * when the other port is reset, we make a duplicate
 463          * in RAR[14] for that eventuality, this assures
 464          * the interface continues to function.
 465          */
 466         if (hw->mac.type == e1000_82571) {
 467                 e1000_set_laa_state_82571(hw, TRUE);
 468                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 469         }
 470
 471         /* Initialize the hardware */
 472         if (em_hardware_init(hw)) {
 473                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 474                 return (-EIO);
 475         }
 476
 477         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 478
 479         /* Configure for OS presence */
 480         em_init_manageability(hw);
 481
 482         eth_em_tx_init(dev);
 483
 484         ret = eth_em_rx_init(dev);
 485         if (ret) {
 486                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 487                 em_dev_clear_queues(dev);
 488                 return ret;
 489         }
 490
 491         e1000_clear_hw_cntrs_base_generic(hw);
 492
 493         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 494                         ETH_VLAN_EXTEND_MASK;
 495         eth_em_vlan_offload_set(dev, mask);
 496
 497         /* Set Interrupt Throttling Rate to maximum allowed value. */
 498         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 499
 500         /* Setup link speed and duplex */
 501         switch (dev->data->dev_conf.link_speed) {
 502         case ETH_LINK_SPEED_AUTONEG:
 503                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 504                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 505                 else if (dev->data->dev_conf.link_duplex ==
 506                                         ETH_LINK_HALF_DUPLEX)
 507                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 508                 else if (dev->data->dev_conf.link_duplex ==
 509                                         ETH_LINK_FULL_DUPLEX)
 510                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 511                 else
 512                         goto error_invalid_config;
 513                 break;
 514         case ETH_LINK_SPEED_10:
 515                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 516                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 517                 else if (dev->data->dev_conf.link_duplex ==
 518                                         ETH_LINK_HALF_DUPLEX)
 519                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 520                 else if (dev->data->dev_conf.link_duplex ==
 521                                         ETH_LINK_FULL_DUPLEX)
 522                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 523                 else
 524                         goto error_invalid_config;
 525                 break;
 526         case ETH_LINK_SPEED_100:
 527                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 528                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 529                 else if (dev->data->dev_conf.link_duplex ==
 530                                         ETH_LINK_HALF_DUPLEX)
 531                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 532                 else if (dev->data->dev_conf.link_duplex ==
 533                                         ETH_LINK_FULL_DUPLEX)
 534                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 535                 else
 536                         goto error_invalid_config;
 537                 break;
 538         case ETH_LINK_SPEED_1000:
 539                 if ((dev->data->dev_conf.link_duplex ==
 540                                 ETH_LINK_AUTONEG_DUPLEX) ||
 541                         (dev->data->dev_conf.link_duplex ==
 542                                         ETH_LINK_FULL_DUPLEX))
 543                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 544                 else
 545                         goto error_invalid_config;
 546                 break;
 547         case ETH_LINK_SPEED_10000:
 548         default:
 549                 goto error_invalid_config;
 550         }
 551         e1000_setup_link(hw);
 552
 553         /* check if lsc interrupt feature is enabled */
 554         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 555                 ret = eth_em_interrupt_setup(dev);
 556                 if (ret) {
 557                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 558                         em_dev_clear_queues(dev);
 559                         return ret;
 560                 }
 561         }
 562
 563         PMD_INIT_LOG(DEBUG, "<<");
 564
 565         return (0);
 566
 567 error_invalid_config:
 568         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port "
 569                                 "%u\n", dev->data->dev_conf.link_speed,
 570                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 571         em_dev_clear_queues(dev);
 572         return (-EINVAL);
 573 }
 574
 575 /*********************************************************************
 576  *
 577  *  This routine disables all traffic on the adapter by issuing a
 578  *  global reset on the MAC.
 579  *
 580  **********************************************************************/
 581 static void
 582 eth_em_stop(struct rte_eth_dev *dev)
 583 {
 584         struct rte_eth_link link;
 585         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 586
 587         em_intr_disable(hw);
 588         e1000_reset_hw(hw);
 589         if (hw->mac.type >= e1000_82544)
 590                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 591
 592         /* Power down the phy. Needed to make the link go down */
 593         e1000_power_down_phy(hw);
 594
 595         em_dev_clear_queues(dev);
 596
 597         /* clear the recorded link status */
 598         memset(&link, 0, sizeof(link));
 599         rte_em_dev_atomic_write_link_status(dev, &link);
 600 }
 601
 602 static void
 603 eth_em_close(struct rte_eth_dev *dev)
 604 {
 605         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 606
 607         eth_em_stop(dev);
 608         e1000_phy_hw_reset(hw);
 609         em_release_manageability(hw);
 610         em_hw_control_release(hw);
 611 }
 612
 613 static int
 614 em_get_rx_buffer_size(struct e1000_hw *hw)
 615 {
 616         uint32_t rx_buf_size;
 617
 618         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 619         return rx_buf_size;
 620 }
 621
 622 /*********************************************************************
 623  *
 624  *  Initialize the hardware
 625  *
 626  **********************************************************************/
 627 static int
 628 em_hardware_init(struct e1000_hw *hw)
 629 {
 630         uint32_t rx_buf_size;
 631         int diag;
 632
 633         /* Issue a global reset */
 634         e1000_reset_hw(hw);
 635
 636         /* Let the firmware know the OS is in control */
 637         em_hw_control_acquire(hw);
 638
 639         /*
 640          * These parameters control the automatic generation (Tx) and
 641          * response (Rx) to Ethernet PAUSE frames.
 642          * - High water mark should allow for at least two standard size (1518)
 643          *   frames to be received after sending an XOFF.
 644          * - Low water mark works best when it is very near the high water mark.
 645          *   This allows the receiver to restart by sending XON when it has
 646          *   drained a bit. Here we use an arbitary value of 1500 which will
 647          *   restart after one full frame is pulled from the buffer. There
 648          *   could be several smaller frames in the buffer and if so they will
 649          *   not trigger the XON until their total number reduces the buffer
 650          *   by 1500.
 651          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 652          */
 653         rx_buf_size = em_get_rx_buffer_size(hw);
 654
 655         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 656         hw->fc.low_water = hw->fc.high_water - 1500;
 657
 658         if (hw->mac.type == e1000_80003es2lan)
 659                 hw->fc.pause_time = UINT16_MAX;
 660         else
 661                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 662
 663         hw->fc.send_xon = 1;
 664
 665         /* Set Flow control, use the tunable location if sane */
 666         if (em_fc_setting <= e1000_fc_full)
 667                 hw->fc.requested_mode = em_fc_setting;
 668         else
 669                 hw->fc.requested_mode = e1000_fc_none;
 670
 671         /* Workaround: no TX flow ctrl for PCH */
 672         if (hw->mac.type == e1000_pchlan)
 673                 hw->fc.requested_mode = e1000_fc_rx_pause;
 674
 675         /* Override - settings for PCH2LAN, ya its magic :) */
 676         if (hw->mac.type == e1000_pch2lan) {
 677                 hw->fc.high_water = 0x5C20;
 678                 hw->fc.low_water = 0x5048;
 679                 hw->fc.pause_time = 0x0650;
 680                 hw->fc.refresh_time = 0x0400;
 681         }
 682
 683         diag = e1000_init_hw(hw);
 684         if (diag < 0)
 685                 return (diag);
 686         e1000_check_for_link(hw);
 687         return (0);
 688 }
 689
 690 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 691 static void
 692 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 693 {
 694         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 695         struct e1000_hw_stats *stats =
 696                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 697         int pause_frames;
 698
 699         if(hw->phy.media_type == e1000_media_type_copper ||
 700                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 701                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 702                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 703         }
 704
 705         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 706         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 707         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 708         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 709
 710         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 711         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 712         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 713         stats->dc += E1000_READ_REG(hw, E1000_DC);
 714         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 715         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 716         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 717
 718         /*
 719          * For watchdog management we need to know if we have been
 720          * paused during the last interval, so capture that here.
 721          */
 722         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 723         stats->xoffrxc += pause_frames;
 724         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 725         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 726         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 727         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 728         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 729         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 730         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 731         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 732         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 733         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 734         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 735         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 736
 737         /*
 738          * For the 64-bit byte counters the low dword must be read first.
 739          * Both registers clear on the read of the high dword.
 740          */
 741
 742         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 743         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 744         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 745         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 746
 747         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 748         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 749         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 750         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 751         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 752
 753         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 754         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 755
 756         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 757         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 758         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 759         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 760         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 761         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 762         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 763         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 764         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 765         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 766
 767         /* Interrupt Counts */
 768
 769         if (hw->mac.type >= e1000_82571) {
 770                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 771                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 772                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 773                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 774                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 775                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 776                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 777                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 778                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 779         }
 780
 781         if (hw->mac.type >= e1000_82543) {
 782                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 783                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 784                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 785                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 786                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 787                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 788         }
 789
 790         if (rte_stats == NULL)
 791                 return;
 792
 793         /* Rx Errors */
 794         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 795                 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 796
 797         /* Tx Errors */
 798         rte_stats->oerrors = stats->ecol + stats->latecol;
 799
 800         rte_stats->ipackets = stats->gprc;
 801         rte_stats->opackets = stats->gptc;
 802         rte_stats->ibytes   = stats->gorc;
 803         rte_stats->obytes   = stats->gotc;
 804 }
 805
 806 static void
 807 eth_em_stats_reset(struct rte_eth_dev *dev)
 808 {
 809         struct e1000_hw_stats *hw_stats =
 810                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 811
 812         /* HW registers are cleared on read */
 813         eth_em_stats_get(dev, NULL);
 814
 815         /* Reset software totals */
 816         memset(hw_stats, 0, sizeof(*hw_stats));
 817 }
 818
 819 static uint32_t
 820 em_get_max_pktlen(const struct e1000_hw *hw)
 821 {
 822         switch (hw->mac.type) {
 823         case e1000_82571:
 824         case e1000_82572:
 825         case e1000_ich9lan:
 826         case e1000_ich10lan:
 827         case e1000_pch2lan:
 828         case e1000_82574:
 829         case e1000_80003es2lan: /* 9K Jumbo Frame size */
 830                 return (0x2412);
 831         case e1000_pchlan:
 832                 return (0x1000);
 833         /* Adapters that do not support jumbo frames */
 834         case e1000_82583:
 835         case e1000_ich8lan:
 836                 return (ETHER_MAX_LEN);
 837         default:
 838                 return (MAX_JUMBO_FRAME_SIZE);
 839         }
 840 }
 841
 842 static void
 843 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 844 {
 845         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 846
 847         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
 848         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
 849         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
 850
 851         /*
 852          * Starting with 631xESB hw supports 2 TX/RX queues per port.
 853          * Unfortunatelly, all these nics have just one TX context.
 854          * So we have few choises for TX:
 855          * - Use just one TX queue.
 856          * - Allow cksum offload only for one TX queue.
 857          * - Don't allow TX cksum offload at all.
 858          * For now, option #1 was chosen.
 859          * To use second RX queue we have to use extended RX descriptor
 860          * (Multiple Receive Queues are mutually exclusive with UDP
 861          * fragmentation and are not supported when a legacy receive
 862          * descriptor format is used).
 863          * Which means separate RX routinies - as legacy nics (82540, 82545)
 864          * don't support extended RXD.
 865          * To avoid it we support just one RX queue for now (no RSS).
 866          */
 867
 868         dev_info->max_rx_queues = 1;
 869         dev_info->max_tx_queues = 1;
 870 }
 871
 872 /* return 0 means link status changed, -1 means not changed */
 873 static int
 874 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 875 {
 876         struct e1000_hw *hw =
 877                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 878         struct rte_eth_link link, old;
 879         int link_check, count;
 880
 881         link_check = 0;
 882         hw->mac.get_link_status = 1;
 883
 884         /* possible wait-to-complete in up to 9 seconds */
 885         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
 886                 /* Read the real link status */
 887                 switch (hw->phy.media_type) {
 888                 case e1000_media_type_copper:
 889                         /* Do the work to read phy */
 890                         e1000_check_for_link(hw);
 891                         link_check = !hw->mac.get_link_status;
 892                         break;
 893
 894                 case e1000_media_type_fiber:
 895                         e1000_check_for_link(hw);
 896                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
 897                                         E1000_STATUS_LU);
 898                         break;
 899
 900                 case e1000_media_type_internal_serdes:
 901                         e1000_check_for_link(hw);
 902                         link_check = hw->mac.serdes_has_link;
 903                         break;
 904
 905                 default:
 906                         break;
 907                 }
 908                 if (link_check || wait_to_complete == 0)
 909                         break;
 910                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
 911         }
 912         memset(&link, 0, sizeof(link));
 913         rte_em_dev_atomic_read_link_status(dev, &link);
 914         old = link;
 915
 916         /* Now we check if a transition has happened */
 917         if (link_check && (link.link_status == 0)) {
 918                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
 919                         &link.link_duplex);
 920                 link.link_status = 1;
 921         } else if (!link_check && (link.link_status == 1)) {
 922                 link.link_speed = 0;
 923                 link.link_duplex = 0;
 924                 link.link_status = 0;
 925         }
 926         rte_em_dev_atomic_write_link_status(dev, &link);
 927
 928         /* not changed */
 929         if (old.link_status == link.link_status)
 930                 return -1;
 931
 932         /* changed */
 933         return 0;
 934 }
 935
 936 /*
 937  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
 938  * For ASF and Pass Through versions of f/w this means
 939  * that the driver is loaded. For AMT version type f/w
 940  * this means that the network i/f is open.
 941  */
 942 static void
 943 em_hw_control_acquire(struct e1000_hw *hw)
 944 {
 945         uint32_t ctrl_ext, swsm;
 946
 947         /* Let firmware know the driver has taken over */
 948         if (hw->mac.type == e1000_82573) {
 949                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 950                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
 951
 952         } else {
 953                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 954                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 955                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 956         }
 957 }
 958
 959 /*
 960  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
 961  * For ASF and Pass Through versions of f/w this means that the
 962  * driver is no longer loaded. For AMT versions of the
 963  * f/w this means that the network i/f is closed.
 964  */
 965 static void
 966 em_hw_control_release(struct e1000_hw *hw)
 967 {
 968         uint32_t ctrl_ext, swsm;
 969
 970         /* Let firmware taken over control of h/w */
 971         if (hw->mac.type == e1000_82573) {
 972                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 973                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
 974         } else {
 975                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 976                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 977                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 978         }
 979 }
 980
 981 /*
 982  * Bit of a misnomer, what this really means is
 983  * to enable OS management of the system... aka
 984  * to disable special hardware management features.
 985  */
 986 static void
 987 em_init_manageability(struct e1000_hw *hw)
 988 {
 989         if (e1000_enable_mng_pass_thru(hw)) {
 990                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
 991                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
 992
 993                 /* disable hardware interception of ARP */
 994                 manc &= ~(E1000_MANC_ARP_EN);
 995
 996                 /* enable receiving management packets to the host */
 997                 manc |= E1000_MANC_EN_MNG2HOST;
 998                 manc2h |= 1 << 5;  /* Mng Port 623 */
 999                 manc2h |= 1 << 6;  /* Mng Port 664 */
1000                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1001                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1002         }
1003 }
1004
1005 /*
1006  * Give control back to hardware management
1007  * controller if there is one.
1008  */
1009 static void
1010 em_release_manageability(struct e1000_hw *hw)
1011 {
1012         uint32_t manc;
1013
1014         if (e1000_enable_mng_pass_thru(hw)) {
1015                 manc = E1000_READ_REG(hw, E1000_MANC);
1016
1017                 /* re-enable hardware interception of ARP */
1018                 manc |= E1000_MANC_ARP_EN;
1019                 manc &= ~E1000_MANC_EN_MNG2HOST;
1020
1021                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1022         }
1023 }
1024
1025 static void
1026 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1027 {
1028         struct e1000_hw *hw =
1029                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030         uint32_t rctl;
1031
1032         rctl = E1000_READ_REG(hw, E1000_RCTL);
1033         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1034         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1035 }
1036
1037 static void
1038 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1039 {
1040         struct e1000_hw *hw =
1041                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1042         uint32_t rctl;
1043
1044         rctl = E1000_READ_REG(hw, E1000_RCTL);
1045         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1046         if (dev->data->all_multicast == 1)
1047                 rctl |= E1000_RCTL_MPE;
1048         else
1049                 rctl &= (~E1000_RCTL_MPE);
1050         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1051 }
1052
1053 static void
1054 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1055 {
1056         struct e1000_hw *hw =
1057                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1058         uint32_t rctl;
1059
1060         rctl = E1000_READ_REG(hw, E1000_RCTL);
1061         rctl |= E1000_RCTL_MPE;
1062         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1063 }
1064
1065 static void
1066 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1067 {
1068         struct e1000_hw *hw =
1069                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1070         uint32_t rctl;
1071
1072         if (dev->data->promiscuous == 1)
1073                 return; /* must remain in all_multicast mode */
1074         rctl = E1000_READ_REG(hw, E1000_RCTL);
1075         rctl &= (~E1000_RCTL_MPE);
1076         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1077 }
1078
1079 static int
1080 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1081 {
1082         struct e1000_hw *hw =
1083                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1084         struct e1000_vfta * shadow_vfta =
1085                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1086         uint32_t vfta;
1087         uint32_t vid_idx;
1088         uint32_t vid_bit;
1089
1090         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1091                               E1000_VFTA_ENTRY_MASK);
1092         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1093         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1094         if (on)
1095                 vfta |= vid_bit;
1096         else
1097                 vfta &= ~vid_bit;
1098         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1099
1100         /* update local VFTA copy */
1101         shadow_vfta->vfta[vid_idx] = vfta;
1102
1103         return 0;
1104 }
1105
1106 static void
1107 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1108 {
1109         struct e1000_hw *hw =
1110                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1111         uint32_t reg;
1112
1113         /* Filter Table Disable */
1114         reg = E1000_READ_REG(hw, E1000_RCTL);
1115         reg &= ~E1000_RCTL_CFIEN;
1116         reg &= ~E1000_RCTL_VFE;
1117         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1118 }
1119
1120 static void
1121 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1122 {
1123         struct e1000_hw *hw =
1124                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1125         struct e1000_vfta * shadow_vfta =
1126                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1127         uint32_t reg;
1128         int i;
1129
1130         /* Filter Table Enable, CFI not used for packet acceptance */
1131         reg = E1000_READ_REG(hw, E1000_RCTL);
1132         reg &= ~E1000_RCTL_CFIEN;
1133         reg |= E1000_RCTL_VFE;
1134         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1135
1136         /* restore vfta from local copy */
1137         for (i = 0; i < IGB_VFTA_SIZE; i++)
1138                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1139 }
1140
1141 static void
1142 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1143 {
1144         struct e1000_hw *hw =
1145                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1146         uint32_t reg;
1147
1148         /* VLAN Mode Disable */
1149         reg = E1000_READ_REG(hw, E1000_CTRL);
1150         reg &= ~E1000_CTRL_VME;
1151         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1152
1153 }
1154
1155 static void
1156 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1157 {
1158         struct e1000_hw *hw =
1159                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1160         uint32_t reg;
1161
1162         /* VLAN Mode Enable */
1163         reg = E1000_READ_REG(hw, E1000_CTRL);
1164         reg |= E1000_CTRL_VME;
1165         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1166 }
1167
1168 static void
1169 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1170 {
1171         if(mask & ETH_VLAN_STRIP_MASK){
1172                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1173                         em_vlan_hw_strip_enable(dev);
1174                 else
1175                         em_vlan_hw_strip_disable(dev);
1176         }
1177
1178         if(mask & ETH_VLAN_FILTER_MASK){
1179                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1180                         em_vlan_hw_filter_enable(dev);
1181                 else
1182                         em_vlan_hw_filter_disable(dev);
1183         }
1184 }
1185
1186 static void
1187 em_intr_disable(struct e1000_hw *hw)
1188 {
1189         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1190 }
1191
1192 /**
1193  * It enables the interrupt mask and then enable the interrupt.
1194  *
1195  * @param dev
1196  *  Pointer to struct rte_eth_dev.
1197  *
1198  * @return
1199  *  - On success, zero.
1200  *  - On failure, a negative value.
1201  */
1202 static int
1203 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1204 {
1205         struct e1000_hw *hw =
1206                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1207
1208         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1209         rte_intr_enable(&(dev->pci_dev->intr_handle));
1210         return (0);
1211 }
1212
1213 /*
1214  * It reads ICR and gets interrupt causes, check it and set a bit flag
1215  * to update link status.
1216  *
1217  * @param dev
1218  *  Pointer to struct rte_eth_dev.
1219  *
1220  * @return
1221  *  - On success, zero.
1222  *  - On failure, a negative value.
1223  */
1224 static int
1225 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1226 {
1227         uint32_t icr;
1228         struct e1000_hw *hw =
1229                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1230         struct e1000_interrupt *intr =
1231                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1232
1233         /* read-on-clear nic registers here */
1234         icr = E1000_READ_REG(hw, E1000_ICR);
1235         if (icr & E1000_ICR_LSC) {
1236                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1237         }
1238
1239         return 0;
1240 }
1241
1242 /*
1243  * It executes link_update after knowing an interrupt is prsent.
1244  *
1245  * @param dev
1246  *  Pointer to struct rte_eth_dev.
1247  *
1248  * @return
1249  *  - On success, zero.
1250  *  - On failure, a negative value.
1251  */
1252 static int
1253 eth_em_interrupt_action(struct rte_eth_dev *dev)
1254 {
1255         struct e1000_hw *hw =
1256                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1257         struct e1000_interrupt *intr =
1258                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1259         uint32_t tctl, rctl;
1260         struct rte_eth_link link;
1261         int ret;
1262
1263         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1264                 return -1;
1265
1266         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1267         rte_intr_enable(&(dev->pci_dev->intr_handle));
1268
1269         /* set get_link_status to check register later */
1270         hw->mac.get_link_status = 1;
1271         ret = eth_em_link_update(dev, 0);
1272
1273         /* check if link has changed */
1274         if (ret < 0)
1275                 return 0;
1276
1277         memset(&link, 0, sizeof(link));
1278         rte_em_dev_atomic_read_link_status(dev, &link);
1279         if (link.link_status) {
1280                 PMD_INIT_LOG(INFO,
1281                         " Port %d: Link Up - speed %u Mbps - %s\n",
1282                         dev->data->port_id, (unsigned)link.link_speed,
1283                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1284                                 "full-duplex" : "half-duplex");
1285         } else {
1286                 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1287                                         dev->data->port_id);
1288         }
1289         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1290                                 dev->pci_dev->addr.domain,
1291                                 dev->pci_dev->addr.bus,
1292                                 dev->pci_dev->addr.devid,
1293                                 dev->pci_dev->addr.function);
1294         tctl = E1000_READ_REG(hw, E1000_TCTL);
1295         rctl = E1000_READ_REG(hw, E1000_RCTL);
1296         if (link.link_status) {
1297                 /* enable Tx/Rx */
1298                 tctl |= E1000_TCTL_EN;
1299                 rctl |= E1000_RCTL_EN;
1300         } else {
1301                 /* disable Tx/Rx */
1302                 tctl &= ~E1000_TCTL_EN;
1303                 rctl &= ~E1000_RCTL_EN;
1304         }
1305         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1306         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1307         E1000_WRITE_FLUSH(hw);
1308
1309         return 0;
1310 }
1311
1312 /**
1313  * Interrupt handler which shall be registered at first.
1314  *
1315  * @param handle
1316  *  Pointer to interrupt handle.
1317  * @param param
1318  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1319  *
1320  * @return
1321  *  void
1322  */
1323 static void
1324 eth_em_interrupt_handler(struct rte_intr_handle *handle, void *param)
1325 {
1326         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1327
1328         eth_em_interrupt_get_status(dev);
1329         eth_em_interrupt_action(dev);
1330         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1331 }
1332
1333 static int
1334 eth_em_led_on(struct rte_eth_dev *dev)
1335 {
1336         struct e1000_hw *hw;
1337
1338         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1339         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1340 }
1341
1342 static int
1343 eth_em_led_off(struct rte_eth_dev *dev)
1344 {
1345         struct e1000_hw *hw;
1346
1347         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1349 }
1350
1351 static int
1352 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1353 {
1354         struct e1000_hw *hw;
1355         int err;
1356         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1357                 e1000_fc_none,
1358                 e1000_fc_rx_pause,
1359                 e1000_fc_tx_pause,
1360                 e1000_fc_full
1361         };
1362         uint32_t rx_buf_size;
1363         uint32_t max_high_water;
1364
1365         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1366         rx_buf_size = em_get_rx_buffer_size(hw);
1367         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1368
1369         /* At least reserve one Ethernet frame for watermark */
1370         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1371         if ((fc_conf->high_water > max_high_water) ||
1372                 (fc_conf->high_water < fc_conf->low_water)) {
1373                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1374                 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1375                 return (-EINVAL);
1376         }
1377
1378         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1379         hw->fc.pause_time     = fc_conf->pause_time;
1380         hw->fc.high_water     = fc_conf->high_water;
1381         hw->fc.low_water      = fc_conf->low_water;
1382         hw->fc.send_xon       = fc_conf->send_xon;
1383
1384         err = e1000_setup_link_generic(hw);
1385         if (err == E1000_SUCCESS) {
1386                 return 0;
1387         }
1388
1389         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1390         return (-EIO);
1391 }
1392
1393 static void
1394 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1395                 uint32_t index, __rte_unused uint32_t pool)
1396 {
1397         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1398
1399         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1400 }
1401
1402 static void
1403 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1404 {
1405         uint8_t addr[ETHER_ADDR_LEN];
1406         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1407
1408         memset(addr, 0, sizeof(addr));
1409
1410         e1000_rar_set(hw, addr, index);
1411 }