lib/librte_pmd_e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #include <sys/queue.h>
  36 #include <stdio.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40
  41 #include <rte_common.h>
  42 #include <rte_interrupts.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_tailq.h>
  52 #include <rte_eal.h>
  53 #include <rte_atomic.h>
  54 #include <rte_malloc.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 #define EM_EIAC                 0x000DC
  61
  62 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  63
  64
  65 static int eth_em_configure(struct rte_eth_dev *dev);
  66 static int eth_em_start(struct rte_eth_dev *dev);
  67 static void eth_em_stop(struct rte_eth_dev *dev);
  68 static void eth_em_close(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  70 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  72 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  73 static int eth_em_link_update(struct rte_eth_dev *dev,
  74                                 int wait_to_complete);
  75 static void eth_em_stats_get(struct rte_eth_dev *dev,
  76                                 struct rte_eth_stats *rte_stats);
  77 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  78 static void eth_em_infos_get(struct rte_eth_dev *dev,
  79                                 struct rte_eth_dev_info *dev_info);
  80 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  81                                 struct rte_eth_fc_conf *fc_conf);
  82 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  83 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  84 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
  85 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  86                                                         void *param);
  87
  88 static int em_hw_init(struct e1000_hw *hw);
  89 static int em_hardware_init(struct e1000_hw *hw);
  90 static void em_hw_control_acquire(struct e1000_hw *hw);
  91 static void em_hw_control_release(struct e1000_hw *hw);
  92 static void em_init_manageability(struct e1000_hw *hw);
  93 static void em_release_manageability(struct e1000_hw *hw);
  94
  95 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  96                 uint16_t vlan_id, int on);
  97 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  98 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  99 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 100 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 101 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 102
 103 /*
 104 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 105                                         uint16_t vlan_id, int on);
 106 */
 107 static int eth_em_led_on(struct rte_eth_dev *dev);
 108 static int eth_em_led_off(struct rte_eth_dev *dev);
 109
 110 static void em_intr_disable(struct e1000_hw *hw);
 111 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 112 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 113                 uint32_t index, uint32_t pool);
 114 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 115
 116 #define EM_FC_PAUSE_TIME 0x0680
 117 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 118 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 119
 120 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 121
 122 /*
 123  * The set of PCI devices this driver supports
 124  */
 125 static struct rte_pci_id pci_id_em_map[] = {
 126
 127 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 128 #include "rte_pci_dev_ids.h"
 129
 130 {.device_id = 0},
 131 };
 132
 133 static struct eth_dev_ops eth_em_ops = {
 134         .dev_configure        = eth_em_configure,
 135         .dev_start            = eth_em_start,
 136         .dev_stop             = eth_em_stop,
 137         .dev_close            = eth_em_close,
 138         .promiscuous_enable   = eth_em_promiscuous_enable,
 139         .promiscuous_disable  = eth_em_promiscuous_disable,
 140         .allmulticast_enable  = eth_em_allmulticast_enable,
 141         .allmulticast_disable = eth_em_allmulticast_disable,
 142         .link_update          = eth_em_link_update,
 143         .stats_get            = eth_em_stats_get,
 144         .stats_reset          = eth_em_stats_reset,
 145         .dev_infos_get        = eth_em_infos_get,
 146         .vlan_filter_set      = eth_em_vlan_filter_set,
 147         .vlan_offload_set     = eth_em_vlan_offload_set,
 148         .rx_queue_setup       = eth_em_rx_queue_setup,
 149         .rx_queue_release     = eth_em_rx_queue_release,
 150         .tx_queue_setup       = eth_em_tx_queue_setup,
 151         .tx_queue_release     = eth_em_tx_queue_release,
 152         .dev_led_on           = eth_em_led_on,
 153         .dev_led_off          = eth_em_led_off,
 154         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 155         .mac_addr_add         = eth_em_rar_set,
 156         .mac_addr_remove      = eth_em_rar_clear,
 157 };
 158
 159 /**
 160  * Atomically reads the link status information from global
 161  * structure rte_eth_dev.
 162  *
 163  * @param dev
 164  *   - Pointer to the structure rte_eth_dev to read from.
 165  *   - Pointer to the buffer to be saved with the link status.
 166  *
 167  * @return
 168  *   - On success, zero.
 169  *   - On failure, negative value.
 170  */
 171 static inline int
 172 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 173                                 struct rte_eth_link *link)
 174 {
 175         struct rte_eth_link *dst = link;
 176         struct rte_eth_link *src = &(dev->data->dev_link);
 177
 178         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 179                                         *(uint64_t *)src) == 0)
 180                 return -1;
 181
 182         return 0;
 183 }
 184
 185 /**
 186  * Atomically writes the link status information into global
 187  * structure rte_eth_dev.
 188  *
 189  * @param dev
 190  *   - Pointer to the structure rte_eth_dev to read from.
 191  *   - Pointer to the buffer to be saved with the link status.
 192  *
 193  * @return
 194  *   - On success, zero.
 195  *   - On failure, negative value.
 196  */
 197 static inline int
 198 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 199                                 struct rte_eth_link *link)
 200 {
 201         struct rte_eth_link *dst = &(dev->data->dev_link);
 202         struct rte_eth_link *src = link;
 203
 204         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 205                                         *(uint64_t *)src) == 0)
 206                 return -1;
 207
 208         return 0;
 209 }
 210
 211 static int
 212 eth_em_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 213                 struct rte_eth_dev *eth_dev)
 214 {
 215         struct rte_pci_device *pci_dev;
 216         struct e1000_hw *hw =
 217                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 218         struct e1000_vfta * shadow_vfta =
 219                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 220
 221         pci_dev = eth_dev->pci_dev;
 222         eth_dev->dev_ops = &eth_em_ops;
 223         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 224         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 225
 226         /* for secondary processes, we don't initialise any further as primary
 227          * has already done this work. Only check we don't need a different
 228          * RX function */
 229         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 230                 if (eth_dev->data->scattered_rx)
 231                         eth_dev->rx_pkt_burst =
 232                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 233                 return 0;
 234         }
 235
 236         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 237         hw->device_id = pci_dev->id.device_id;
 238
 239         /* For ICH8 support we'll need to map the flash memory BAR */
 240
 241         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 242                         em_hw_init(hw) != 0) {
 243                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 244                         "failed to init HW",
 245                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 246                         pci_dev->id.device_id);
 247                 return -(ENODEV);
 248         }
 249
 250         /* Allocate memory for storing MAC addresses */
 251         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 252                         hw->mac.rar_entry_count, 0);
 253         if (eth_dev->data->mac_addrs == NULL) {
 254                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 255                         "store MAC addresses",
 256                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 257                 return -(ENOMEM);
 258         }
 259
 260         /* Copy the permanent MAC address */
 261         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 262                 eth_dev->data->mac_addrs);
 263
 264         /* initialize the vfta */
 265         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 266
 267         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 268                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 269                         pci_dev->id.device_id);
 270
 271         rte_intr_callback_register(&(pci_dev->intr_handle),
 272                 eth_em_interrupt_handler, (void *)eth_dev);
 273
 274         return (0);
 275 }
 276
 277 static struct eth_driver rte_em_pmd = {
 278         {
 279                 .name = "rte_em_pmd",
 280                 .id_table = pci_id_em_map,
 281 #ifdef RTE_EAL_UNBIND_PORTS
 282                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 283 #endif
 284         },
 285         .eth_dev_init = eth_em_dev_init,
 286         .dev_private_size = sizeof(struct e1000_adapter),
 287 };
 288
 289 int
 290 rte_em_pmd_init(void)
 291 {
 292         rte_eth_driver_register(&rte_em_pmd);
 293         return 0;
 294 }
 295
 296 static int
 297 em_hw_init(struct e1000_hw *hw)
 298 {
 299         int diag;
 300
 301         diag = hw->mac.ops.init_params(hw);
 302         if (diag != 0) {
 303                 PMD_INIT_LOG(ERR, "MAC Initialization Error\n");
 304                 return diag;
 305         }
 306         diag = hw->nvm.ops.init_params(hw);
 307         if (diag != 0) {
 308                 PMD_INIT_LOG(ERR, "NVM Initialization Error\n");
 309                 return diag;
 310         }
 311         diag = hw->phy.ops.init_params(hw);
 312         if (diag != 0) {
 313                 PMD_INIT_LOG(ERR, "PHY Initialization Error\n");
 314                 return diag;
 315         }
 316         (void) e1000_get_bus_info(hw);
 317
 318         hw->mac.autoneg = 1;
 319         hw->phy.autoneg_wait_to_complete = 0;
 320         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 321
 322         e1000_init_script_state_82541(hw, TRUE);
 323         e1000_set_tbi_compatibility_82543(hw, TRUE);
 324
 325         /* Copper options */
 326         if (hw->phy.media_type == e1000_media_type_copper) {
 327                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 328                 hw->phy.disable_polarity_correction = 0;
 329                 hw->phy.ms_type = e1000_ms_hw_default;
 330         }
 331
 332         /*
 333          * Start from a known state, this is important in reading the nvm
 334          * and mac from that.
 335          */
 336         e1000_reset_hw(hw);
 337
 338         /* Make sure we have a good EEPROM before we read from it */
 339         if (e1000_validate_nvm_checksum(hw) < 0) {
 340                 /*
 341                  * Some PCI-E parts fail the first check due to
 342                  * the link being in sleep state, call it again,
 343                  * if it fails a second time its a real issue.
 344                  */
 345                 diag = e1000_validate_nvm_checksum(hw);
 346                 if (diag < 0) {
 347                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 348                         goto error;
 349                 }
 350         }
 351
 352         /* Read the permanent MAC address out of the EEPROM */
 353         diag = e1000_read_mac_addr(hw);
 354         if (diag != 0) {
 355                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 356                 goto error;
 357         }
 358
 359         /* Now initialize the hardware */
 360         diag = em_hardware_init(hw);
 361         if (diag != 0) {
 362                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 363                 goto error;
 364         }
 365
 366         hw->mac.get_link_status = 1;
 367
 368         /* Indicate SOL/IDER usage */
 369         diag = e1000_check_reset_block(hw);
 370         if (diag < 0) {
 371                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 372                         "SOL/IDER session");
 373         }
 374         return (0);
 375
 376 error:
 377         em_hw_control_release(hw);
 378         return (diag);
 379 }
 380
 381 static int
 382 eth_em_configure(struct rte_eth_dev *dev)
 383 {
 384         struct e1000_interrupt *intr =
 385                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 386
 387         PMD_INIT_LOG(DEBUG, ">>");
 388
 389         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 390
 391         PMD_INIT_LOG(DEBUG, "<<");
 392         return (0);
 393 }
 394
 395 static void
 396 em_set_pba(struct e1000_hw *hw)
 397 {
 398         uint32_t pba;
 399
 400         /*
 401          * Packet Buffer Allocation (PBA)
 402          * Writing PBA sets the receive portion of the buffer
 403          * the remainder is used for the transmit buffer.
 404          * Devices before the 82547 had a Packet Buffer of 64K.
 405          * After the 82547 the buffer was reduced to 40K.
 406          */
 407         switch (hw->mac.type) {
 408                 case e1000_82547:
 409                 case e1000_82547_rev_2:
 410                 /* 82547: Total Packet Buffer is 40K */
 411                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 412                         break;
 413                 case e1000_82571:
 414                 case e1000_82572:
 415                 case e1000_80003es2lan:
 416                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 417                         break;
 418                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 419                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 420                         break;
 421                 case e1000_82574:
 422                 case e1000_82583:
 423                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 424                         break;
 425                 case e1000_ich8lan:
 426                         pba = E1000_PBA_8K;
 427                         break;
 428                 case e1000_ich9lan:
 429                 case e1000_ich10lan:
 430                         pba = E1000_PBA_10K;
 431                         break;
 432                 case e1000_pchlan:
 433                 case e1000_pch2lan:
 434                         pba = E1000_PBA_26K;
 435                         break;
 436                 default:
 437                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 438         }
 439
 440         E1000_WRITE_REG(hw, E1000_PBA, pba);
 441 }
 442
 443 static int
 444 eth_em_start(struct rte_eth_dev *dev)
 445 {
 446         struct e1000_hw *hw =
 447                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 448         int ret, mask;
 449
 450         PMD_INIT_LOG(DEBUG, ">>");
 451
 452         eth_em_stop(dev);
 453
 454         e1000_power_up_phy(hw);
 455
 456         /* Set default PBA value */
 457         em_set_pba(hw);
 458
 459         /* Put the address into the Receive Address Array */
 460         e1000_rar_set(hw, hw->mac.addr, 0);
 461
 462         /*
 463          * With the 82571 adapter, RAR[0] may be overwritten
 464          * when the other port is reset, we make a duplicate
 465          * in RAR[14] for that eventuality, this assures
 466          * the interface continues to function.
 467          */
 468         if (hw->mac.type == e1000_82571) {
 469                 e1000_set_laa_state_82571(hw, TRUE);
 470                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 471         }
 472
 473         /* Initialize the hardware */
 474         if (em_hardware_init(hw)) {
 475                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 476                 return (-EIO);
 477         }
 478
 479         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 480
 481         /* Configure for OS presence */
 482         em_init_manageability(hw);
 483
 484         eth_em_tx_init(dev);
 485
 486         ret = eth_em_rx_init(dev);
 487         if (ret) {
 488                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 489                 em_dev_clear_queues(dev);
 490                 return ret;
 491         }
 492
 493         e1000_clear_hw_cntrs_base_generic(hw);
 494
 495         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 496                         ETH_VLAN_EXTEND_MASK;
 497         eth_em_vlan_offload_set(dev, mask);
 498
 499         /* Set Interrupt Throttling Rate to maximum allowed value. */
 500         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 501
 502         /* Setup link speed and duplex */
 503         switch (dev->data->dev_conf.link_speed) {
 504         case ETH_LINK_SPEED_AUTONEG:
 505                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 506                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 507                 else if (dev->data->dev_conf.link_duplex ==
 508                                         ETH_LINK_HALF_DUPLEX)
 509                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 510                 else if (dev->data->dev_conf.link_duplex ==
 511                                         ETH_LINK_FULL_DUPLEX)
 512                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 513                 else
 514                         goto error_invalid_config;
 515                 break;
 516         case ETH_LINK_SPEED_10:
 517                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 518                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 519                 else if (dev->data->dev_conf.link_duplex ==
 520                                         ETH_LINK_HALF_DUPLEX)
 521                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 522                 else if (dev->data->dev_conf.link_duplex ==
 523                                         ETH_LINK_FULL_DUPLEX)
 524                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 525                 else
 526                         goto error_invalid_config;
 527                 break;
 528         case ETH_LINK_SPEED_100:
 529                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 530                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 531                 else if (dev->data->dev_conf.link_duplex ==
 532                                         ETH_LINK_HALF_DUPLEX)
 533                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 534                 else if (dev->data->dev_conf.link_duplex ==
 535                                         ETH_LINK_FULL_DUPLEX)
 536                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 537                 else
 538                         goto error_invalid_config;
 539                 break;
 540         case ETH_LINK_SPEED_1000:
 541                 if ((dev->data->dev_conf.link_duplex ==
 542                                 ETH_LINK_AUTONEG_DUPLEX) ||
 543                         (dev->data->dev_conf.link_duplex ==
 544                                         ETH_LINK_FULL_DUPLEX))
 545                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 546                 else
 547                         goto error_invalid_config;
 548                 break;
 549         case ETH_LINK_SPEED_10000:
 550         default:
 551                 goto error_invalid_config;
 552         }
 553         e1000_setup_link(hw);
 554
 555         /* check if lsc interrupt feature is enabled */
 556         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 557                 ret = eth_em_interrupt_setup(dev);
 558                 if (ret) {
 559                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 560                         em_dev_clear_queues(dev);
 561                         return ret;
 562                 }
 563         }
 564
 565         PMD_INIT_LOG(DEBUG, "<<");
 566
 567         return (0);
 568
 569 error_invalid_config:
 570         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port "
 571                                 "%u\n", dev->data->dev_conf.link_speed,
 572                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 573         em_dev_clear_queues(dev);
 574         return (-EINVAL);
 575 }
 576
 577 /*********************************************************************
 578  *
 579  *  This routine disables all traffic on the adapter by issuing a
 580  *  global reset on the MAC.
 581  *
 582  **********************************************************************/
 583 static void
 584 eth_em_stop(struct rte_eth_dev *dev)
 585 {
 586         struct rte_eth_link link;
 587         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 588
 589         em_intr_disable(hw);
 590         e1000_reset_hw(hw);
 591         if (hw->mac.type >= e1000_82544)
 592                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 593
 594         /* Power down the phy. Needed to make the link go down */
 595         e1000_power_down_phy(hw);
 596
 597         em_dev_clear_queues(dev);
 598
 599         /* clear the recorded link status */
 600         memset(&link, 0, sizeof(link));
 601         rte_em_dev_atomic_write_link_status(dev, &link);
 602 }
 603
 604 static void
 605 eth_em_close(struct rte_eth_dev *dev)
 606 {
 607         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 608
 609         eth_em_stop(dev);
 610         e1000_phy_hw_reset(hw);
 611         em_release_manageability(hw);
 612         em_hw_control_release(hw);
 613 }
 614
 615 static int
 616 em_get_rx_buffer_size(struct e1000_hw *hw)
 617 {
 618         uint32_t rx_buf_size;
 619
 620         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 621         return rx_buf_size;
 622 }
 623
 624 /*********************************************************************
 625  *
 626  *  Initialize the hardware
 627  *
 628  **********************************************************************/
 629 static int
 630 em_hardware_init(struct e1000_hw *hw)
 631 {
 632         uint32_t rx_buf_size;
 633         int diag;
 634
 635         /* Issue a global reset */
 636         e1000_reset_hw(hw);
 637
 638         /* Let the firmware know the OS is in control */
 639         em_hw_control_acquire(hw);
 640
 641         /*
 642          * These parameters control the automatic generation (Tx) and
 643          * response (Rx) to Ethernet PAUSE frames.
 644          * - High water mark should allow for at least two standard size (1518)
 645          *   frames to be received after sending an XOFF.
 646          * - Low water mark works best when it is very near the high water mark.
 647          *   This allows the receiver to restart by sending XON when it has
 648          *   drained a bit. Here we use an arbitary value of 1500 which will
 649          *   restart after one full frame is pulled from the buffer. There
 650          *   could be several smaller frames in the buffer and if so they will
 651          *   not trigger the XON until their total number reduces the buffer
 652          *   by 1500.
 653          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 654          */
 655         rx_buf_size = em_get_rx_buffer_size(hw);
 656
 657         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 658         hw->fc.low_water = hw->fc.high_water - 1500;
 659
 660         if (hw->mac.type == e1000_80003es2lan)
 661                 hw->fc.pause_time = UINT16_MAX;
 662         else
 663                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 664
 665         hw->fc.send_xon = 1;
 666
 667         /* Set Flow control, use the tunable location if sane */
 668         if (em_fc_setting <= e1000_fc_full)
 669                 hw->fc.requested_mode = em_fc_setting;
 670         else
 671                 hw->fc.requested_mode = e1000_fc_none;
 672
 673         /* Workaround: no TX flow ctrl for PCH */
 674         if (hw->mac.type == e1000_pchlan)
 675                 hw->fc.requested_mode = e1000_fc_rx_pause;
 676
 677         /* Override - settings for PCH2LAN, ya its magic :) */
 678         if (hw->mac.type == e1000_pch2lan) {
 679                 hw->fc.high_water = 0x5C20;
 680                 hw->fc.low_water = 0x5048;
 681                 hw->fc.pause_time = 0x0650;
 682                 hw->fc.refresh_time = 0x0400;
 683         }
 684
 685         diag = e1000_init_hw(hw);
 686         if (diag < 0)
 687                 return (diag);
 688         e1000_check_for_link(hw);
 689         return (0);
 690 }
 691
 692 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 693 static void
 694 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 695 {
 696         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 697         struct e1000_hw_stats *stats =
 698                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 699         int pause_frames;
 700
 701         if(hw->phy.media_type == e1000_media_type_copper ||
 702                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 703                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 704                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 705         }
 706
 707         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 708         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 709         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 710         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 711
 712         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 713         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 714         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 715         stats->dc += E1000_READ_REG(hw, E1000_DC);
 716         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 717         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 718         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 719
 720         /*
 721          * For watchdog management we need to know if we have been
 722          * paused during the last interval, so capture that here.
 723          */
 724         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 725         stats->xoffrxc += pause_frames;
 726         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 727         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 728         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 729         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 730         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 731         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 732         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 733         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 734         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 735         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 736         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 737         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 738
 739         /*
 740          * For the 64-bit byte counters the low dword must be read first.
 741          * Both registers clear on the read of the high dword.
 742          */
 743
 744         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 745         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 746         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 747         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 748
 749         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 750         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 751         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 752         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 753         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 754
 755         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 756         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 757
 758         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 759         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 760         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 761         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 762         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 763         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 764         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 765         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 766         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 767         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 768
 769         /* Interrupt Counts */
 770
 771         if (hw->mac.type >= e1000_82571) {
 772                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 773                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 774                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 775                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 776                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 777                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 778                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 779                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 780                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 781         }
 782
 783         if (hw->mac.type >= e1000_82543) {
 784                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 785                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 786                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 787                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 788                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 789                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 790         }
 791
 792         if (rte_stats == NULL)
 793                 return;
 794
 795         /* Rx Errors */
 796         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 797                 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 798
 799         /* Tx Errors */
 800         rte_stats->oerrors = stats->ecol + stats->latecol;
 801
 802         rte_stats->ipackets = stats->gprc;
 803         rte_stats->opackets = stats->gptc;
 804         rte_stats->ibytes   = stats->gorc;
 805         rte_stats->obytes   = stats->gotc;
 806 }
 807
 808 static void
 809 eth_em_stats_reset(struct rte_eth_dev *dev)
 810 {
 811         struct e1000_hw_stats *hw_stats =
 812                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 813
 814         /* HW registers are cleared on read */
 815         eth_em_stats_get(dev, NULL);
 816
 817         /* Reset software totals */
 818         memset(hw_stats, 0, sizeof(*hw_stats));
 819 }
 820
 821 static uint32_t
 822 em_get_max_pktlen(const struct e1000_hw *hw)
 823 {
 824         switch (hw->mac.type) {
 825         case e1000_82571:
 826         case e1000_82572:
 827         case e1000_ich9lan:
 828         case e1000_ich10lan:
 829         case e1000_pch2lan:
 830         case e1000_82574:
 831         case e1000_80003es2lan: /* 9K Jumbo Frame size */
 832                 return (0x2412);
 833         case e1000_pchlan:
 834                 return (0x1000);
 835         /* Adapters that do not support jumbo frames */
 836         case e1000_82583:
 837         case e1000_ich8lan:
 838                 return (ETHER_MAX_LEN);
 839         default:
 840                 return (MAX_JUMBO_FRAME_SIZE);
 841         }
 842 }
 843
 844 static void
 845 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 846 {
 847         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 848
 849         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
 850         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
 851         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
 852
 853         /*
 854          * Starting with 631xESB hw supports 2 TX/RX queues per port.
 855          * Unfortunatelly, all these nics have just one TX context.
 856          * So we have few choises for TX:
 857          * - Use just one TX queue.
 858          * - Allow cksum offload only for one TX queue.
 859          * - Don't allow TX cksum offload at all.
 860          * For now, option #1 was chosen.
 861          * To use second RX queue we have to use extended RX descriptor
 862          * (Multiple Receive Queues are mutually exclusive with UDP
 863          * fragmentation and are not supported when a legacy receive
 864          * descriptor format is used).
 865          * Which means separate RX routinies - as legacy nics (82540, 82545)
 866          * don't support extended RXD.
 867          * To avoid it we support just one RX queue for now (no RSS).
 868          */
 869
 870         dev_info->max_rx_queues = 1;
 871         dev_info->max_tx_queues = 1;
 872 }
 873
 874 /* return 0 means link status changed, -1 means not changed */
 875 static int
 876 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 877 {
 878         struct e1000_hw *hw =
 879                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 880         struct rte_eth_link link, old;
 881         int link_check, count;
 882
 883         link_check = 0;
 884         hw->mac.get_link_status = 1;
 885
 886         /* possible wait-to-complete in up to 9 seconds */
 887         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
 888                 /* Read the real link status */
 889                 switch (hw->phy.media_type) {
 890                 case e1000_media_type_copper:
 891                         /* Do the work to read phy */
 892                         e1000_check_for_link(hw);
 893                         link_check = !hw->mac.get_link_status;
 894                         break;
 895
 896                 case e1000_media_type_fiber:
 897                         e1000_check_for_link(hw);
 898                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
 899                                         E1000_STATUS_LU);
 900                         break;
 901
 902                 case e1000_media_type_internal_serdes:
 903                         e1000_check_for_link(hw);
 904                         link_check = hw->mac.serdes_has_link;
 905                         break;
 906
 907                 default:
 908                         break;
 909                 }
 910                 if (link_check || wait_to_complete == 0)
 911                         break;
 912                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
 913         }
 914         memset(&link, 0, sizeof(link));
 915         rte_em_dev_atomic_read_link_status(dev, &link);
 916         old = link;
 917
 918         /* Now we check if a transition has happened */
 919         if (link_check && (link.link_status == 0)) {
 920                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
 921                         &link.link_duplex);
 922                 link.link_status = 1;
 923         } else if (!link_check && (link.link_status == 1)) {
 924                 link.link_speed = 0;
 925                 link.link_duplex = 0;
 926                 link.link_status = 0;
 927         }
 928         rte_em_dev_atomic_write_link_status(dev, &link);
 929
 930         /* not changed */
 931         if (old.link_status == link.link_status)
 932                 return -1;
 933
 934         /* changed */
 935         return 0;
 936 }
 937
 938 /*
 939  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
 940  * For ASF and Pass Through versions of f/w this means
 941  * that the driver is loaded. For AMT version type f/w
 942  * this means that the network i/f is open.
 943  */
 944 static void
 945 em_hw_control_acquire(struct e1000_hw *hw)
 946 {
 947         uint32_t ctrl_ext, swsm;
 948
 949         /* Let firmware know the driver has taken over */
 950         if (hw->mac.type == e1000_82573) {
 951                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 952                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
 953
 954         } else {
 955                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 956                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 957                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 958         }
 959 }
 960
 961 /*
 962  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
 963  * For ASF and Pass Through versions of f/w this means that the
 964  * driver is no longer loaded. For AMT versions of the
 965  * f/w this means that the network i/f is closed.
 966  */
 967 static void
 968 em_hw_control_release(struct e1000_hw *hw)
 969 {
 970         uint32_t ctrl_ext, swsm;
 971
 972         /* Let firmware taken over control of h/w */
 973         if (hw->mac.type == e1000_82573) {
 974                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 975                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
 976         } else {
 977                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 978                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 979                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 980         }
 981 }
 982
 983 /*
 984  * Bit of a misnomer, what this really means is
 985  * to enable OS management of the system... aka
 986  * to disable special hardware management features.
 987  */
 988 static void
 989 em_init_manageability(struct e1000_hw *hw)
 990 {
 991         if (e1000_enable_mng_pass_thru(hw)) {
 992                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
 993                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
 994
 995                 /* disable hardware interception of ARP */
 996                 manc &= ~(E1000_MANC_ARP_EN);
 997
 998                 /* enable receiving management packets to the host */
 999                 manc |= E1000_MANC_EN_MNG2HOST;
1000                 manc2h |= 1 << 5;  /* Mng Port 623 */
1001                 manc2h |= 1 << 6;  /* Mng Port 664 */
1002                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1003                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1004         }
1005 }
1006
1007 /*
1008  * Give control back to hardware management
1009  * controller if there is one.
1010  */
1011 static void
1012 em_release_manageability(struct e1000_hw *hw)
1013 {
1014         uint32_t manc;
1015
1016         if (e1000_enable_mng_pass_thru(hw)) {
1017                 manc = E1000_READ_REG(hw, E1000_MANC);
1018
1019                 /* re-enable hardware interception of ARP */
1020                 manc |= E1000_MANC_ARP_EN;
1021                 manc &= ~E1000_MANC_EN_MNG2HOST;
1022
1023                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1024         }
1025 }
1026
1027 static void
1028 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1029 {
1030         struct e1000_hw *hw =
1031                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032         uint32_t rctl;
1033
1034         rctl = E1000_READ_REG(hw, E1000_RCTL);
1035         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1036         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1037 }
1038
1039 static void
1040 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1041 {
1042         struct e1000_hw *hw =
1043                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044         uint32_t rctl;
1045
1046         rctl = E1000_READ_REG(hw, E1000_RCTL);
1047         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1048         if (dev->data->all_multicast == 1)
1049                 rctl |= E1000_RCTL_MPE;
1050         else
1051                 rctl &= (~E1000_RCTL_MPE);
1052         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1053 }
1054
1055 static void
1056 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1057 {
1058         struct e1000_hw *hw =
1059                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1060         uint32_t rctl;
1061
1062         rctl = E1000_READ_REG(hw, E1000_RCTL);
1063         rctl |= E1000_RCTL_MPE;
1064         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1065 }
1066
1067 static void
1068 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1069 {
1070         struct e1000_hw *hw =
1071                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1072         uint32_t rctl;
1073
1074         if (dev->data->promiscuous == 1)
1075                 return; /* must remain in all_multicast mode */
1076         rctl = E1000_READ_REG(hw, E1000_RCTL);
1077         rctl &= (~E1000_RCTL_MPE);
1078         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1079 }
1080
1081 static int
1082 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1083 {
1084         struct e1000_hw *hw =
1085                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1086         struct e1000_vfta * shadow_vfta =
1087                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1088         uint32_t vfta;
1089         uint32_t vid_idx;
1090         uint32_t vid_bit;
1091
1092         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1093                               E1000_VFTA_ENTRY_MASK);
1094         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1095         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1096         if (on)
1097                 vfta |= vid_bit;
1098         else
1099                 vfta &= ~vid_bit;
1100         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1101
1102         /* update local VFTA copy */
1103         shadow_vfta->vfta[vid_idx] = vfta;
1104
1105         return 0;
1106 }
1107
1108 static void
1109 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1110 {
1111         struct e1000_hw *hw =
1112                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1113         uint32_t reg;
1114
1115         /* Filter Table Disable */
1116         reg = E1000_READ_REG(hw, E1000_RCTL);
1117         reg &= ~E1000_RCTL_CFIEN;
1118         reg &= ~E1000_RCTL_VFE;
1119         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1120 }
1121
1122 static void
1123 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1124 {
1125         struct e1000_hw *hw =
1126                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1127         struct e1000_vfta * shadow_vfta =
1128                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1129         uint32_t reg;
1130         int i;
1131
1132         /* Filter Table Enable, CFI not used for packet acceptance */
1133         reg = E1000_READ_REG(hw, E1000_RCTL);
1134         reg &= ~E1000_RCTL_CFIEN;
1135         reg |= E1000_RCTL_VFE;
1136         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1137
1138         /* restore vfta from local copy */
1139         for (i = 0; i < IGB_VFTA_SIZE; i++)
1140                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1141 }
1142
1143 static void
1144 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1145 {
1146         struct e1000_hw *hw =
1147                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1148         uint32_t reg;
1149
1150         /* VLAN Mode Disable */
1151         reg = E1000_READ_REG(hw, E1000_CTRL);
1152         reg &= ~E1000_CTRL_VME;
1153         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1154
1155 }
1156
1157 static void
1158 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1159 {
1160         struct e1000_hw *hw =
1161                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1162         uint32_t reg;
1163
1164         /* VLAN Mode Enable */
1165         reg = E1000_READ_REG(hw, E1000_CTRL);
1166         reg |= E1000_CTRL_VME;
1167         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1168 }
1169
1170 static void
1171 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1172 {
1173         if(mask & ETH_VLAN_STRIP_MASK){
1174                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1175                         em_vlan_hw_strip_enable(dev);
1176                 else
1177                         em_vlan_hw_strip_disable(dev);
1178         }
1179
1180         if(mask & ETH_VLAN_FILTER_MASK){
1181                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1182                         em_vlan_hw_filter_enable(dev);
1183                 else
1184                         em_vlan_hw_filter_disable(dev);
1185         }
1186 }
1187
1188 static void
1189 em_intr_disable(struct e1000_hw *hw)
1190 {
1191         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1192 }
1193
1194 /**
1195  * It enables the interrupt mask and then enable the interrupt.
1196  *
1197  * @param dev
1198  *  Pointer to struct rte_eth_dev.
1199  *
1200  * @return
1201  *  - On success, zero.
1202  *  - On failure, a negative value.
1203  */
1204 static int
1205 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1206 {
1207         struct e1000_hw *hw =
1208                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1209
1210         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1211         rte_intr_enable(&(dev->pci_dev->intr_handle));
1212         return (0);
1213 }
1214
1215 /*
1216  * It reads ICR and gets interrupt causes, check it and set a bit flag
1217  * to update link status.
1218  *
1219  * @param dev
1220  *  Pointer to struct rte_eth_dev.
1221  *
1222  * @return
1223  *  - On success, zero.
1224  *  - On failure, a negative value.
1225  */
1226 static int
1227 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1228 {
1229         uint32_t icr;
1230         struct e1000_hw *hw =
1231                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1232         struct e1000_interrupt *intr =
1233                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1234
1235         /* read-on-clear nic registers here */
1236         icr = E1000_READ_REG(hw, E1000_ICR);
1237         if (icr & E1000_ICR_LSC) {
1238                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1239         }
1240
1241         return 0;
1242 }
1243
1244 /*
1245  * It executes link_update after knowing an interrupt is prsent.
1246  *
1247  * @param dev
1248  *  Pointer to struct rte_eth_dev.
1249  *
1250  * @return
1251  *  - On success, zero.
1252  *  - On failure, a negative value.
1253  */
1254 static int
1255 eth_em_interrupt_action(struct rte_eth_dev *dev)
1256 {
1257         struct e1000_hw *hw =
1258                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1259         struct e1000_interrupt *intr =
1260                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1261         uint32_t tctl, rctl;
1262         struct rte_eth_link link;
1263         int ret;
1264
1265         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1266                 return -1;
1267
1268         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1269         rte_intr_enable(&(dev->pci_dev->intr_handle));
1270
1271         /* set get_link_status to check register later */
1272         hw->mac.get_link_status = 1;
1273         ret = eth_em_link_update(dev, 0);
1274
1275         /* check if link has changed */
1276         if (ret < 0)
1277                 return 0;
1278
1279         memset(&link, 0, sizeof(link));
1280         rte_em_dev_atomic_read_link_status(dev, &link);
1281         if (link.link_status) {
1282                 PMD_INIT_LOG(INFO,
1283                         " Port %d: Link Up - speed %u Mbps - %s\n",
1284                         dev->data->port_id, (unsigned)link.link_speed,
1285                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1286                                 "full-duplex" : "half-duplex");
1287         } else {
1288                 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1289                                         dev->data->port_id);
1290         }
1291         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1292                                 dev->pci_dev->addr.domain,
1293                                 dev->pci_dev->addr.bus,
1294                                 dev->pci_dev->addr.devid,
1295                                 dev->pci_dev->addr.function);
1296         tctl = E1000_READ_REG(hw, E1000_TCTL);
1297         rctl = E1000_READ_REG(hw, E1000_RCTL);
1298         if (link.link_status) {
1299                 /* enable Tx/Rx */
1300                 tctl |= E1000_TCTL_EN;
1301                 rctl |= E1000_RCTL_EN;
1302         } else {
1303                 /* disable Tx/Rx */
1304                 tctl &= ~E1000_TCTL_EN;
1305                 rctl &= ~E1000_RCTL_EN;
1306         }
1307         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1308         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1309         E1000_WRITE_FLUSH(hw);
1310
1311         return 0;
1312 }
1313
1314 /**
1315  * Interrupt handler which shall be registered at first.
1316  *
1317  * @param handle
1318  *  Pointer to interrupt handle.
1319  * @param param
1320  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1321  *
1322  * @return
1323  *  void
1324  */
1325 static void
1326 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1327                                                         void *param)
1328 {
1329         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1330
1331         eth_em_interrupt_get_status(dev);
1332         eth_em_interrupt_action(dev);
1333         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1334 }
1335
1336 static int
1337 eth_em_led_on(struct rte_eth_dev *dev)
1338 {
1339         struct e1000_hw *hw;
1340
1341         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1342         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1343 }
1344
1345 static int
1346 eth_em_led_off(struct rte_eth_dev *dev)
1347 {
1348         struct e1000_hw *hw;
1349
1350         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1351         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1352 }
1353
1354 static int
1355 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1356 {
1357         struct e1000_hw *hw;
1358         int err;
1359         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1360                 e1000_fc_none,
1361                 e1000_fc_rx_pause,
1362                 e1000_fc_tx_pause,
1363                 e1000_fc_full
1364         };
1365         uint32_t rx_buf_size;
1366         uint32_t max_high_water;
1367
1368         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1369         rx_buf_size = em_get_rx_buffer_size(hw);
1370         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1371
1372         /* At least reserve one Ethernet frame for watermark */
1373         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1374         if ((fc_conf->high_water > max_high_water) ||
1375                 (fc_conf->high_water < fc_conf->low_water)) {
1376                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1377                 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1378                 return (-EINVAL);
1379         }
1380
1381         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1382         hw->fc.pause_time     = fc_conf->pause_time;
1383         hw->fc.high_water     = fc_conf->high_water;
1384         hw->fc.low_water      = fc_conf->low_water;
1385         hw->fc.send_xon       = fc_conf->send_xon;
1386
1387         err = e1000_setup_link_generic(hw);
1388         if (err == E1000_SUCCESS) {
1389                 return 0;
1390         }
1391
1392         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1393         return (-EIO);
1394 }
1395
1396 static void
1397 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1398                 uint32_t index, __rte_unused uint32_t pool)
1399 {
1400         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1401
1402         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1403 }
1404
1405 static void
1406 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1407 {
1408         uint8_t addr[ETHER_ADDR_LEN];
1409         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1410
1411         memset(addr, 0, sizeof(addr));
1412
1413         e1000_rar_set(hw, addr, index);
1414 }