lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #include <sys/queue.h>
  36 #include <stdio.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40
  41 #include <rte_common.h>
  42 #include <rte_interrupts.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_tailq.h>
  52 #include <rte_eal.h>
  53 #include <rte_atomic.h>
  54 #include <rte_malloc.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 static int  eth_igb_configure(struct rte_eth_dev *dev);
  61 static int  eth_igb_start(struct rte_eth_dev *dev);
  62 static void eth_igb_stop(struct rte_eth_dev *dev);
  63 static void eth_igb_close(struct rte_eth_dev *dev);
  64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  68 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  69                                 int wait_to_complete);
  70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  71                                 struct rte_eth_stats *rte_stats);
  72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  74                                 struct rte_eth_dev_info *dev_info);
  75 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  76                                 struct rte_eth_fc_conf *fc_conf);
  77 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  78 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  79 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  80 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  81                                                         void *param);
  82 static int  igb_hardware_init(struct e1000_hw *hw);
  83 static void igb_hw_control_acquire(struct e1000_hw *hw);
  84 static void igb_hw_control_release(struct e1000_hw *hw);
  85 static void igb_init_manageability(struct e1000_hw *hw);
  86 static void igb_release_manageability(struct e1000_hw *hw);
  87
  88 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  89                 uint16_t vlan_id, int on);
  90 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
  91 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  92
  93 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  94 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  95 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  96 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  97 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
  98 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
  99
 100 static int eth_igb_led_on(struct rte_eth_dev *dev);
 101 static int eth_igb_led_off(struct rte_eth_dev *dev);
 102
 103 static void igb_intr_disable(struct e1000_hw *hw);
 104 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 105 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 106                 struct ether_addr *mac_addr,
 107                 uint32_t index, uint32_t pool);
 108 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 109
 110 static void igbvf_intr_disable(struct e1000_hw *hw);
 111 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 112 static int igbvf_dev_start(struct rte_eth_dev *dev);
 113 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 114 static void igbvf_dev_close(struct rte_eth_dev *dev);
 115 static int eth_igbvf_link_update(struct e1000_hw *hw);
 116 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 117 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 118 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 119                 uint16_t vlan_id, int on);
 120 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 121 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 122 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 123                  struct rte_eth_rss_reta *reta_conf);
 124 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 125                 struct rte_eth_rss_reta *reta_conf);
 126
 127 /*
 128  * Define VF Stats MACRO for Non "cleared on read" register
 129  */
 130 #define UPDATE_VF_STAT(reg, last, cur)            \
 131 {                                                 \
 132         u32 latest = E1000_READ_REG(hw, reg);     \
 133         cur += latest - last;                     \
 134         last = latest;                            \
 135 }
 136
 137
 138 #define IGB_FC_PAUSE_TIME 0x0680
 139 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 140 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 141
 142 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 143
 144 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 145
 146 /*
 147  * The set of PCI devices this driver supports
 148  */
 149 static struct rte_pci_id pci_id_igb_map[] = {
 150
 151 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 152 #include "rte_pci_dev_ids.h"
 153
 154 {.device_id = 0},
 155 };
 156
 157 /*
 158  * The set of PCI devices this driver supports (for 82576&I350 VF)
 159  */
 160 static struct rte_pci_id pci_id_igbvf_map[] = {
 161
 162 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 163 #include "rte_pci_dev_ids.h"
 164
 165 {.device_id = 0},
 166 };
 167
 168 static struct eth_dev_ops eth_igb_ops = {
 169         .dev_configure        = eth_igb_configure,
 170         .dev_start            = eth_igb_start,
 171         .dev_stop             = eth_igb_stop,
 172         .dev_close            = eth_igb_close,
 173         .promiscuous_enable   = eth_igb_promiscuous_enable,
 174         .promiscuous_disable  = eth_igb_promiscuous_disable,
 175         .allmulticast_enable  = eth_igb_allmulticast_enable,
 176         .allmulticast_disable = eth_igb_allmulticast_disable,
 177         .link_update          = eth_igb_link_update,
 178         .stats_get            = eth_igb_stats_get,
 179         .stats_reset          = eth_igb_stats_reset,
 180         .dev_infos_get        = eth_igb_infos_get,
 181         .vlan_filter_set      = eth_igb_vlan_filter_set,
 182         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 183         .vlan_offload_set     = eth_igb_vlan_offload_set,
 184         .rx_queue_setup       = eth_igb_rx_queue_setup,
 185         .rx_queue_release     = eth_igb_rx_queue_release,
 186         .rx_queue_count       = eth_igb_rx_queue_count,
 187         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 188         .tx_queue_setup       = eth_igb_tx_queue_setup,
 189         .tx_queue_release     = eth_igb_tx_queue_release,
 190         .dev_led_on           = eth_igb_led_on,
 191         .dev_led_off          = eth_igb_led_off,
 192         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 193         .mac_addr_add         = eth_igb_rar_set,
 194         .mac_addr_remove      = eth_igb_rar_clear,
 195         .reta_update          = eth_igb_rss_reta_update,
 196         .reta_query           = eth_igb_rss_reta_query,
 197 };
 198
 199 /*
 200  * dev_ops for virtual function, bare necessities for basic vf
 201  * operation have been implemented
 202  */
 203 static struct eth_dev_ops igbvf_eth_dev_ops = {
 204         .dev_configure        = igbvf_dev_configure,
 205         .dev_start            = igbvf_dev_start,
 206         .dev_stop             = igbvf_dev_stop,
 207         .dev_close            = igbvf_dev_close,
 208         .link_update          = eth_igb_link_update,
 209         .stats_get            = eth_igbvf_stats_get,
 210         .stats_reset          = eth_igbvf_stats_reset,
 211         .vlan_filter_set      = igbvf_vlan_filter_set,
 212         .dev_infos_get        = eth_igb_infos_get,
 213         .rx_queue_setup       = eth_igb_rx_queue_setup,
 214         .rx_queue_release     = eth_igb_rx_queue_release,
 215         .tx_queue_setup       = eth_igb_tx_queue_setup,
 216         .tx_queue_release     = eth_igb_tx_queue_release,
 217 };
 218
 219 /**
 220  * Atomically reads the link status information from global
 221  * structure rte_eth_dev.
 222  *
 223  * @param dev
 224  *   - Pointer to the structure rte_eth_dev to read from.
 225  *   - Pointer to the buffer to be saved with the link status.
 226  *
 227  * @return
 228  *   - On success, zero.
 229  *   - On failure, negative value.
 230  */
 231 static inline int
 232 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 233                                 struct rte_eth_link *link)
 234 {
 235         struct rte_eth_link *dst = link;
 236         struct rte_eth_link *src = &(dev->data->dev_link);
 237
 238         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 239                                         *(uint64_t *)src) == 0)
 240                 return -1;
 241
 242         return 0;
 243 }
 244
 245 /**
 246  * Atomically writes the link status information into global
 247  * structure rte_eth_dev.
 248  *
 249  * @param dev
 250  *   - Pointer to the structure rte_eth_dev to read from.
 251  *   - Pointer to the buffer to be saved with the link status.
 252  *
 253  * @return
 254  *   - On success, zero.
 255  *   - On failure, negative value.
 256  */
 257 static inline int
 258 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 259                                 struct rte_eth_link *link)
 260 {
 261         struct rte_eth_link *dst = &(dev->data->dev_link);
 262         struct rte_eth_link *src = link;
 263
 264         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 265                                         *(uint64_t *)src) == 0)
 266                 return -1;
 267
 268         return 0;
 269 }
 270
 271 static inline void
 272 igb_intr_enable(struct rte_eth_dev *dev)
 273 {
 274         struct e1000_interrupt *intr =
 275                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 276         struct e1000_hw *hw =
 277                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278
 279         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 280         E1000_WRITE_FLUSH(hw);
 281 }
 282
 283 static void
 284 igb_intr_disable(struct e1000_hw *hw)
 285 {
 286         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 287         E1000_WRITE_FLUSH(hw);
 288 }
 289
 290 static inline int32_t
 291 igb_pf_reset_hw(struct e1000_hw *hw)
 292 {
 293         uint32_t ctrl_ext;
 294         int32_t status;
 295
 296         status = e1000_reset_hw(hw);
 297
 298         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 299         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 300         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 301         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 302         E1000_WRITE_FLUSH(hw);
 303
 304         return status;
 305 }
 306
 307 static void
 308 igb_identify_hardware(struct rte_eth_dev *dev)
 309 {
 310         struct e1000_hw *hw =
 311                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 312
 313         hw->vendor_id = dev->pci_dev->id.vendor_id;
 314         hw->device_id = dev->pci_dev->id.device_id;
 315         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 316         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 317
 318         e1000_set_mac_type(hw);
 319
 320         /* need to check if it is a vf device below */
 321 }
 322
 323 static int
 324 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 325                    struct rte_eth_dev *eth_dev)
 326 {
 327         int error = 0;
 328         struct rte_pci_device *pci_dev;
 329         struct e1000_hw *hw =
 330                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 331         struct e1000_vfta * shadow_vfta =
 332                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 333         uint32_t ctrl_ext;
 334
 335         pci_dev = eth_dev->pci_dev;
 336         eth_dev->dev_ops = &eth_igb_ops;
 337         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 338         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 339
 340         /* for secondary processes, we don't initialise any further as primary
 341          * has already done this work. Only check we don't need a different
 342          * RX function */
 343         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 344                 if (eth_dev->data->scattered_rx)
 345                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 346                 return 0;
 347         }
 348
 349         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 350
 351         igb_identify_hardware(eth_dev);
 352         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 353                 error = -EIO;
 354                 goto err_late;
 355         }
 356
 357         e1000_get_bus_info(hw);
 358
 359         hw->mac.autoneg = 1;
 360         hw->phy.autoneg_wait_to_complete = 0;
 361         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 362
 363         /* Copper options */
 364         if (hw->phy.media_type == e1000_media_type_copper) {
 365                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 366                 hw->phy.disable_polarity_correction = 0;
 367                 hw->phy.ms_type = e1000_ms_hw_default;
 368         }
 369
 370         /*
 371          * Start from a known state, this is important in reading the nvm
 372          * and mac from that.
 373          */
 374         igb_pf_reset_hw(hw);
 375
 376         /* Make sure we have a good EEPROM before we read from it */
 377         if (e1000_validate_nvm_checksum(hw) < 0) {
 378                 /*
 379                  * Some PCI-E parts fail the first check due to
 380                  * the link being in sleep state, call it again,
 381                  * if it fails a second time its a real issue.
 382                  */
 383                 if (e1000_validate_nvm_checksum(hw) < 0) {
 384                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 385                         error = -EIO;
 386                         goto err_late;
 387                 }
 388         }
 389
 390         /* Read the permanent MAC address out of the EEPROM */
 391         if (e1000_read_mac_addr(hw) != 0) {
 392                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 393                 error = -EIO;
 394                 goto err_late;
 395         }
 396
 397         /* Allocate memory for storing MAC addresses */
 398         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 399                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 400         if (eth_dev->data->mac_addrs == NULL) {
 401                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 402                                                 "store MAC addresses",
 403                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 404                 error = -ENOMEM;
 405                 goto err_late;
 406         }
 407
 408         /* Copy the permanent MAC address */
 409         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 410
 411         /* initialize the vfta */
 412         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 413
 414         /* Now initialize the hardware */
 415         if (igb_hardware_init(hw) != 0) {
 416                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 417                 rte_free(eth_dev->data->mac_addrs);
 418                 eth_dev->data->mac_addrs = NULL;
 419                 error = -ENODEV;
 420                 goto err_late;
 421         }
 422         hw->mac.get_link_status = 1;
 423
 424         /* Indicate SOL/IDER usage */
 425         if (e1000_check_reset_block(hw) < 0) {
 426                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 427                                         "SOL/IDER session");
 428         }
 429
 430         /* initialize PF if max_vfs not zero */
 431         igb_pf_host_init(eth_dev);
 432
 433         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 434         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 435         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 436         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 437         E1000_WRITE_FLUSH(hw);
 438
 439         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 440                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 441                      pci_dev->id.device_id);
 442
 443         rte_intr_callback_register(&(pci_dev->intr_handle),
 444                 eth_igb_interrupt_handler, (void *)eth_dev);
 445
 446         /* enable uio intr after callback register */
 447         rte_intr_enable(&(pci_dev->intr_handle));
 448
 449         /* enable support intr */
 450         igb_intr_enable(eth_dev);
 451
 452         return 0;
 453
 454 err_late:
 455         igb_hw_control_release(hw);
 456
 457         return (error);
 458 }
 459
 460 /*
 461  * Virtual Function device init
 462  */
 463 static int
 464 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 465                 struct rte_eth_dev *eth_dev)
 466 {
 467         struct rte_pci_device *pci_dev;
 468         struct e1000_hw *hw =
 469                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 470         int diag;
 471
 472         PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 473
 474         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 475         pci_dev = eth_dev->pci_dev;
 476
 477         hw->device_id = pci_dev->id.device_id;
 478         hw->vendor_id = pci_dev->id.vendor_id;
 479         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 480
 481         /* Initialize the shared code */
 482         diag = e1000_setup_init_funcs(hw, TRUE);
 483         if (diag != 0) {
 484                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 485                         diag);
 486                 return -EIO;
 487         }
 488
 489         /* init_mailbox_params */
 490         hw->mbx.ops.init_params(hw);
 491
 492         /* Disable the interrupts for VF */
 493         igbvf_intr_disable(hw);
 494
 495         diag = hw->mac.ops.reset_hw(hw);
 496
 497         /* Allocate memory for storing MAC addresses */
 498         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 499                 hw->mac.rar_entry_count, 0);
 500         if (eth_dev->data->mac_addrs == NULL) {
 501                 PMD_INIT_LOG(ERR,
 502                         "Failed to allocate %d bytes needed to store MAC "
 503                         "addresses",
 504                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 505                 return -ENOMEM;
 506         }
 507
 508         /* Copy the permanent MAC address */
 509         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 510                         &eth_dev->data->mac_addrs[0]);
 511
 512         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
 513                         "mac.type=%s\n",
 514                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 515                         pci_dev->id.device_id,
 516                         "igb_mac_82576_vf");
 517
 518         return 0;
 519 }
 520
 521 static struct eth_driver rte_igb_pmd = {
 522         {
 523                 .name = "rte_igb_pmd",
 524                 .id_table = pci_id_igb_map,
 525 #ifdef RTE_EAL_UNBIND_PORTS
 526                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 527 #endif
 528         },
 529         .eth_dev_init = eth_igb_dev_init,
 530         .dev_private_size = sizeof(struct e1000_adapter),
 531 };
 532
 533 /*
 534  * virtual function driver struct
 535  */
 536 static struct eth_driver rte_igbvf_pmd = {
 537         {
 538                 .name = "rte_igbvf_pmd",
 539                 .id_table = pci_id_igbvf_map,
 540 #ifdef RTE_EAL_UNBIND_PORTS
 541                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 542 #endif
 543         },
 544         .eth_dev_init = eth_igbvf_dev_init,
 545         .dev_private_size = sizeof(struct e1000_adapter),
 546 };
 547
 548 int
 549 rte_igb_pmd_init(void)
 550 {
 551         rte_eth_driver_register(&rte_igb_pmd);
 552         return 0;
 553 }
 554
 555 /*
 556  * VF Driver initialization routine.
 557  * Invoked one at EAL init time.
 558  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 559  */
 560 int
 561 rte_igbvf_pmd_init(void)
 562 {
 563         DEBUGFUNC("rte_igbvf_pmd_init");
 564
 565         rte_eth_driver_register(&rte_igbvf_pmd);
 566         return (0);
 567 }
 568
 569 static int
 570 eth_igb_configure(struct rte_eth_dev *dev)
 571 {
 572         struct e1000_interrupt *intr =
 573                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 574
 575         PMD_INIT_LOG(DEBUG, ">>");
 576
 577         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 578
 579         PMD_INIT_LOG(DEBUG, "<<");
 580
 581         return (0);
 582 }
 583
 584 static int
 585 eth_igb_start(struct rte_eth_dev *dev)
 586 {
 587         struct e1000_hw *hw =
 588                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 589         int ret, i, mask;
 590         uint32_t ctrl_ext;
 591
 592         PMD_INIT_LOG(DEBUG, ">>");
 593
 594         /* Power up the phy. Needed to make the link go Up */
 595         e1000_power_up_phy(hw);
 596
 597         /*
 598          * Packet Buffer Allocation (PBA)
 599          * Writing PBA sets the receive portion of the buffer
 600          * the remainder is used for the transmit buffer.
 601          */
 602         if (hw->mac.type == e1000_82575) {
 603                 uint32_t pba;
 604
 605                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 606                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 607         }
 608
 609         /* Put the address into the Receive Address Array */
 610         e1000_rar_set(hw, hw->mac.addr, 0);
 611
 612         /* Initialize the hardware */
 613         if (igb_hardware_init(hw)) {
 614                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 615                 return (-EIO);
 616         }
 617
 618         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 619
 620         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 621         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 622         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 623         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 624         E1000_WRITE_FLUSH(hw);
 625
 626         /* configure PF module if SRIOV enabled */
 627         igb_pf_host_configure(dev);
 628
 629         /* Configure for OS presence */
 630         igb_init_manageability(hw);
 631
 632         eth_igb_tx_init(dev);
 633
 634         /* This can fail when allocating mbufs for descriptor rings */
 635         ret = eth_igb_rx_init(dev);
 636         if (ret) {
 637                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 638                 igb_dev_clear_queues(dev);
 639                 return ret;
 640         }
 641
 642         e1000_clear_hw_cntrs_base_generic(hw);
 643
 644         /*
 645          * VLAN Offload Settings
 646          */
 647         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 648                         ETH_VLAN_EXTEND_MASK;
 649         eth_igb_vlan_offload_set(dev, mask);
 650
 651         /*
 652          * Configure the Interrupt Moderation register (EITR) with the maximum
 653          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 654          * spurious [DMA] memory updates of RX and TX ring descriptors.
 655          *
 656          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 657          * spurious memory updates per second should be expected.
 658          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 659          *
 660          * Because interrupts are not used at all, the MSI-X is not activated
 661          * and interrupt moderation is controlled by EITR[0].
 662          *
 663          * Note that having [almost] disabled memory updates of RX and TX ring
 664          * descriptors through the Interrupt Moderation mechanism, memory
 665          * updates of ring descriptors are now moderated by the configurable
 666          * value of Write-Back Threshold registers.
 667          */
 668         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 669                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 670                 uint32_t ivar;
 671
 672                 /* Enable all RX & TX queues in the IVAR registers */
 673                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 674                 for (i = 0; i < 8; i++)
 675                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 676
 677                 /* Configure EITR with the maximum possible value (0xFFFF) */
 678                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 679         }
 680
 681         /* Setup link speed and duplex */
 682         switch (dev->data->dev_conf.link_speed) {
 683         case ETH_LINK_SPEED_AUTONEG:
 684                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 685                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 686                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 687                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 688                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 689                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 690                 else
 691                         goto error_invalid_config;
 692                 break;
 693         case ETH_LINK_SPEED_10:
 694                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 695                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 696                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 697                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 698                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 699                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 700                 else
 701                         goto error_invalid_config;
 702                 break;
 703         case ETH_LINK_SPEED_100:
 704                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 705                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 706                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 707                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 708                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 709                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 710                 else
 711                         goto error_invalid_config;
 712                 break;
 713         case ETH_LINK_SPEED_1000:
 714                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 715                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 716                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 717                 else
 718                         goto error_invalid_config;
 719                 break;
 720         case ETH_LINK_SPEED_10000:
 721         default:
 722                 goto error_invalid_config;
 723         }
 724         e1000_setup_link(hw);
 725
 726         /* check if lsc interrupt feature is enabled */
 727         if (dev->data->dev_conf.intr_conf.lsc != 0)
 728                 ret = eth_igb_lsc_interrupt_setup(dev);
 729
 730         /* resume enabled intr since hw reset */
 731         igb_intr_enable(dev);
 732
 733         PMD_INIT_LOG(DEBUG, "<<");
 734
 735         return (0);
 736
 737 error_invalid_config:
 738         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 739                         dev->data->dev_conf.link_speed,
 740                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 741         igb_dev_clear_queues(dev);
 742         return (-EINVAL);
 743 }
 744
 745 /*********************************************************************
 746  *
 747  *  This routine disables all traffic on the adapter by issuing a
 748  *  global reset on the MAC.
 749  *
 750  **********************************************************************/
 751 static void
 752 eth_igb_stop(struct rte_eth_dev *dev)
 753 {
 754         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 755         struct rte_eth_link link;
 756
 757         igb_intr_disable(hw);
 758         igb_pf_reset_hw(hw);
 759         E1000_WRITE_REG(hw, E1000_WUC, 0);
 760
 761         /* Set bit for Go Link disconnect */
 762         if (hw->mac.type >= e1000_82580) {
 763                 uint32_t phpm_reg;
 764
 765                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 766                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 767                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 768         }
 769
 770         /* Power down the phy. Needed to make the link go Down */
 771         e1000_power_down_phy(hw);
 772
 773         igb_dev_clear_queues(dev);
 774
 775         /* clear the recorded link status */
 776         memset(&link, 0, sizeof(link));
 777         rte_igb_dev_atomic_write_link_status(dev, &link);
 778 }
 779
 780 static void
 781 eth_igb_close(struct rte_eth_dev *dev)
 782 {
 783         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 784         struct rte_eth_link link;
 785
 786         eth_igb_stop(dev);
 787         e1000_phy_hw_reset(hw);
 788         igb_release_manageability(hw);
 789         igb_hw_control_release(hw);
 790
 791         /* Clear bit for Go Link disconnect */
 792         if (hw->mac.type >= e1000_82580) {
 793                 uint32_t phpm_reg;
 794
 795                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 796                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
 797                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 798         }
 799
 800         igb_dev_clear_queues(dev);
 801
 802         memset(&link, 0, sizeof(link));
 803         rte_igb_dev_atomic_write_link_status(dev, &link);
 804 }
 805
 806 static int
 807 igb_get_rx_buffer_size(struct e1000_hw *hw)
 808 {
 809         uint32_t rx_buf_size;
 810         if (hw->mac.type == e1000_82576) {
 811                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 812         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 813                 /* PBS needs to be translated according to a lookup table */
 814                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 815                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 816                 rx_buf_size = (rx_buf_size << 10);
 817         } else if (hw->mac.type == e1000_i210) {
 818                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 819         } else {
 820                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 821         }
 822
 823         return rx_buf_size;
 824 }
 825
 826 /*********************************************************************
 827  *
 828  *  Initialize the hardware
 829  *
 830  **********************************************************************/
 831 static int
 832 igb_hardware_init(struct e1000_hw *hw)
 833 {
 834         uint32_t rx_buf_size;
 835         int diag;
 836
 837         /* Let the firmware know the OS is in control */
 838         igb_hw_control_acquire(hw);
 839
 840         /*
 841          * These parameters control the automatic generation (Tx) and
 842          * response (Rx) to Ethernet PAUSE frames.
 843          * - High water mark should allow for at least two standard size (1518)
 844          *   frames to be received after sending an XOFF.
 845          * - Low water mark works best when it is very near the high water mark.
 846          *   This allows the receiver to restart by sending XON when it has
 847          *   drained a bit. Here we use an arbitary value of 1500 which will
 848          *   restart after one full frame is pulled from the buffer. There
 849          *   could be several smaller frames in the buffer and if so they will
 850          *   not trigger the XON until their total number reduces the buffer
 851          *   by 1500.
 852          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 853          */
 854         rx_buf_size = igb_get_rx_buffer_size(hw);
 855
 856         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
 857         hw->fc.low_water = hw->fc.high_water - 1500;
 858         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
 859         hw->fc.send_xon = 1;
 860
 861         /* Set Flow control, use the tunable location if sane */
 862         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
 863                 hw->fc.requested_mode = igb_fc_setting;
 864         else
 865                 hw->fc.requested_mode = e1000_fc_none;
 866
 867         /* Issue a global reset */
 868         igb_pf_reset_hw(hw);
 869         E1000_WRITE_REG(hw, E1000_WUC, 0);
 870
 871         diag = e1000_init_hw(hw);
 872         if (diag < 0)
 873                 return (diag);
 874
 875         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 876         e1000_get_phy_info(hw);
 877         e1000_check_for_link(hw);
 878
 879         return (0);
 880 }
 881
 882 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
 883 static void
 884 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 885 {
 886         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 887         struct e1000_hw_stats *stats =
 888                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 889         int pause_frames;
 890
 891         if(hw->phy.media_type == e1000_media_type_copper ||
 892             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 893                 stats->symerrs +=
 894                     E1000_READ_REG(hw,E1000_SYMERRS);
 895                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 896         }
 897
 898         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 899         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 900         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 901         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 902
 903         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 904         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 905         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 906         stats->dc += E1000_READ_REG(hw, E1000_DC);
 907         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 908         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 909         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 910         /*
 911         ** For watchdog management we need to know if we have been
 912         ** paused during the last interval, so capture that here.
 913         */
 914         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 915         stats->xoffrxc += pause_frames;
 916         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 917         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 918         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 919         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 920         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 921         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 922         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 923         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 924         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 925         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 926         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 927         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 928
 929         /* For the 64-bit byte counters the low dword must be read first. */
 930         /* Both registers clear on the read of the high dword */
 931
 932         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 933         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 934         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 935         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 936
 937         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 938         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 939         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 940         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 941         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 942
 943         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 944         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 945
 946         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 947         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 948         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 949         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 950         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 951         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 952         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 953         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 954         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 955         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 956
 957         /* Interrupt Counts */
 958
 959         stats->iac += E1000_READ_REG(hw, E1000_IAC);
 960         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 961         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 962         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 963         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 964         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 965         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 966         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 967         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 968
 969         /* Host to Card Statistics */
 970
 971         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
 972         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
 973         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
 974         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
 975         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
 976         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
 977         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
 978         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
 979         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
 980         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
 981         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
 982         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
 983         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
 984         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
 985
 986         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 987         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 988         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 989         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 990         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 991         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 992
 993         if (rte_stats == NULL)
 994                 return;
 995
 996         /* Rx Errors */
 997         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 998             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 999
1000         /* Tx Errors */
1001         rte_stats->oerrors = stats->ecol + stats->latecol;
1002
1003         rte_stats->ipackets = stats->gprc;
1004         rte_stats->opackets = stats->gptc;
1005         rte_stats->ibytes   = stats->gorc;
1006         rte_stats->obytes   = stats->gotc;
1007 }
1008
1009 static void
1010 eth_igb_stats_reset(struct rte_eth_dev *dev)
1011 {
1012         struct e1000_hw_stats *hw_stats =
1013                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1014
1015         /* HW registers are cleared on read */
1016         eth_igb_stats_get(dev, NULL);
1017
1018         /* Reset software totals */
1019         memset(hw_stats, 0, sizeof(*hw_stats));
1020 }
1021
1022 static void
1023 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1024 {
1025         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1027                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1028
1029         /* Good Rx packets, include VF loopback */
1030         UPDATE_VF_STAT(E1000_VFGPRC,
1031             hw_stats->last_gprc, hw_stats->gprc);
1032
1033         /* Good Rx octets, include VF loopback */
1034         UPDATE_VF_STAT(E1000_VFGORC,
1035             hw_stats->last_gorc, hw_stats->gorc);
1036
1037         /* Good Tx packets, include VF loopback */
1038         UPDATE_VF_STAT(E1000_VFGPTC,
1039             hw_stats->last_gptc, hw_stats->gptc);
1040
1041         /* Good Tx octets, include VF loopback */
1042         UPDATE_VF_STAT(E1000_VFGOTC,
1043             hw_stats->last_gotc, hw_stats->gotc);
1044
1045         /* Rx Multicst packets */
1046         UPDATE_VF_STAT(E1000_VFMPRC,
1047             hw_stats->last_mprc, hw_stats->mprc);
1048
1049         /* Good Rx loopback packets */
1050         UPDATE_VF_STAT(E1000_VFGPRLBC,
1051             hw_stats->last_gprlbc, hw_stats->gprlbc);
1052
1053         /* Good Rx loopback octets */
1054         UPDATE_VF_STAT(E1000_VFGORLBC,
1055             hw_stats->last_gorlbc, hw_stats->gorlbc);
1056
1057         /* Good Tx loopback packets */
1058         UPDATE_VF_STAT(E1000_VFGPTLBC,
1059             hw_stats->last_gptlbc, hw_stats->gptlbc);
1060
1061         /* Good Tx loopback octets */
1062         UPDATE_VF_STAT(E1000_VFGOTLBC,
1063             hw_stats->last_gotlbc, hw_stats->gotlbc);
1064
1065         if (rte_stats == NULL)
1066                 return;
1067
1068         memset(rte_stats, 0, sizeof(*rte_stats));
1069         rte_stats->ipackets = hw_stats->gprc;
1070         rte_stats->ibytes = hw_stats->gorc;
1071         rte_stats->opackets = hw_stats->gptc;
1072         rte_stats->obytes = hw_stats->gotc;
1073         rte_stats->imcasts = hw_stats->mprc;
1074         rte_stats->ilbpackets = hw_stats->gprlbc;
1075         rte_stats->ilbbytes = hw_stats->gorlbc;
1076         rte_stats->olbpackets = hw_stats->gptlbc;
1077         rte_stats->olbbytes = hw_stats->gotlbc;
1078
1079 }
1080
1081 static void
1082 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1083 {
1084         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1085                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1086
1087         /* Sync HW register to the last stats */
1088         eth_igbvf_stats_get(dev, NULL);
1089
1090         /* reset HW current stats*/
1091         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1092                offsetof(struct e1000_vf_stats, gprc));
1093
1094 }
1095
1096 static void
1097 eth_igb_infos_get(struct rte_eth_dev *dev,
1098                     struct rte_eth_dev_info *dev_info)
1099 {
1100         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1101
1102         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1103         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1104         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1105
1106         switch (hw->mac.type) {
1107         case e1000_82575:
1108                 dev_info->max_rx_queues = 4;
1109                 dev_info->max_tx_queues = 4;
1110                 break;
1111
1112         case e1000_82576:
1113                 dev_info->max_rx_queues = 16;
1114                 dev_info->max_tx_queues = 16;
1115                 break;
1116
1117         case e1000_82580:
1118                 dev_info->max_rx_queues = 8;
1119                 dev_info->max_tx_queues = 8;
1120                 break;
1121
1122         case e1000_i350:
1123                 dev_info->max_rx_queues = 8;
1124                 dev_info->max_tx_queues = 8;
1125                 break;
1126
1127         case e1000_i210:
1128                 dev_info->max_rx_queues = 4;
1129                 dev_info->max_tx_queues = 4;
1130                 break;
1131
1132         case e1000_vfadapt:
1133                 dev_info->max_rx_queues = 2;
1134                 dev_info->max_tx_queues = 2;
1135                 break;
1136
1137         case e1000_vfadapt_i350:
1138                 dev_info->max_rx_queues = 1;
1139                 dev_info->max_tx_queues = 1;
1140                 break;
1141
1142         default:
1143                 /* Should not happen */
1144                 dev_info->max_rx_queues = 0;
1145                 dev_info->max_tx_queues = 0;
1146         }
1147 }
1148
1149 /* return 0 means link status changed, -1 means not changed */
1150 static int
1151 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1152 {
1153         struct e1000_hw *hw =
1154                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1155         struct rte_eth_link link, old;
1156         int link_check, count;
1157
1158         link_check = 0;
1159         hw->mac.get_link_status = 1;
1160
1161         /* possible wait-to-complete in up to 9 seconds */
1162         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1163                 /* Read the real link status */
1164                 switch (hw->phy.media_type) {
1165                 case e1000_media_type_copper:
1166                         /* Do the work to read phy */
1167                         e1000_check_for_link(hw);
1168                         link_check = !hw->mac.get_link_status;
1169                         break;
1170
1171                 case e1000_media_type_fiber:
1172                         e1000_check_for_link(hw);
1173                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1174                                       E1000_STATUS_LU);
1175                         break;
1176
1177                 case e1000_media_type_internal_serdes:
1178                         e1000_check_for_link(hw);
1179                         link_check = hw->mac.serdes_has_link;
1180                         break;
1181
1182                 /* VF device is type_unknown */
1183                 case e1000_media_type_unknown:
1184                         eth_igbvf_link_update(hw);
1185                         link_check = !hw->mac.get_link_status;
1186                         break;
1187
1188                 default:
1189                         break;
1190                 }
1191                 if (link_check || wait_to_complete == 0)
1192                         break;
1193                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1194         }
1195         memset(&link, 0, sizeof(link));
1196         rte_igb_dev_atomic_read_link_status(dev, &link);
1197         old = link;
1198
1199         /* Now we check if a transition has happened */
1200         if (link_check) {
1201                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1202                                           &link.link_duplex);
1203                 link.link_status = 1;
1204         } else if (!link_check) {
1205                 link.link_speed = 0;
1206                 link.link_duplex = 0;
1207                 link.link_status = 0;
1208         }
1209         rte_igb_dev_atomic_write_link_status(dev, &link);
1210
1211         /* not changed */
1212         if (old.link_status == link.link_status)
1213                 return -1;
1214
1215         /* changed */
1216         return 0;
1217 }
1218
1219 /*
1220  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1221  * For ASF and Pass Through versions of f/w this means
1222  * that the driver is loaded.
1223  */
1224 static void
1225 igb_hw_control_acquire(struct e1000_hw *hw)
1226 {
1227         uint32_t ctrl_ext;
1228
1229         /* Let firmware know the driver has taken over */
1230         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1231         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1232 }
1233
1234 /*
1235  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1236  * For ASF and Pass Through versions of f/w this means that the
1237  * driver is no longer loaded.
1238  */
1239 static void
1240 igb_hw_control_release(struct e1000_hw *hw)
1241 {
1242         uint32_t ctrl_ext;
1243
1244         /* Let firmware taken over control of h/w */
1245         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1246         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1247                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1248 }
1249
1250 /*
1251  * Bit of a misnomer, what this really means is
1252  * to enable OS management of the system... aka
1253  * to disable special hardware management features.
1254  */
1255 static void
1256 igb_init_manageability(struct e1000_hw *hw)
1257 {
1258         if (e1000_enable_mng_pass_thru(hw)) {
1259                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1260                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1261
1262                 /* disable hardware interception of ARP */
1263                 manc &= ~(E1000_MANC_ARP_EN);
1264
1265                 /* enable receiving management packets to the host */
1266                 manc |= E1000_MANC_EN_MNG2HOST;
1267                 manc2h |= 1 << 5;  /* Mng Port 623 */
1268                 manc2h |= 1 << 6;  /* Mng Port 664 */
1269                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1270                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1271         }
1272 }
1273
1274 static void
1275 igb_release_manageability(struct e1000_hw *hw)
1276 {
1277         if (e1000_enable_mng_pass_thru(hw)) {
1278                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1279
1280                 manc |= E1000_MANC_ARP_EN;
1281                 manc &= ~E1000_MANC_EN_MNG2HOST;
1282
1283                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1284         }
1285 }
1286
1287 static void
1288 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1289 {
1290         struct e1000_hw *hw =
1291                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1292         uint32_t rctl;
1293
1294         rctl = E1000_READ_REG(hw, E1000_RCTL);
1295         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1296         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1297 }
1298
1299 static void
1300 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1301 {
1302         struct e1000_hw *hw =
1303                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1304         uint32_t rctl;
1305
1306         rctl = E1000_READ_REG(hw, E1000_RCTL);
1307         rctl &= (~E1000_RCTL_UPE);
1308         if (dev->data->all_multicast == 1)
1309                 rctl |= E1000_RCTL_MPE;
1310         else
1311                 rctl &= (~E1000_RCTL_MPE);
1312         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1313 }
1314
1315 static void
1316 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1317 {
1318         struct e1000_hw *hw =
1319                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1320         uint32_t rctl;
1321
1322         rctl = E1000_READ_REG(hw, E1000_RCTL);
1323         rctl |= E1000_RCTL_MPE;
1324         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1325 }
1326
1327 static void
1328 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1329 {
1330         struct e1000_hw *hw =
1331                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1332         uint32_t rctl;
1333
1334         if (dev->data->promiscuous == 1)
1335                 return; /* must remain in all_multicast mode */
1336         rctl = E1000_READ_REG(hw, E1000_RCTL);
1337         rctl &= (~E1000_RCTL_MPE);
1338         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1339 }
1340
1341 static int
1342 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1343 {
1344         struct e1000_hw *hw =
1345                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1346         struct e1000_vfta * shadow_vfta =
1347                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1348         uint32_t vfta;
1349         uint32_t vid_idx;
1350         uint32_t vid_bit;
1351
1352         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1353                               E1000_VFTA_ENTRY_MASK);
1354         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1355         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1356         if (on)
1357                 vfta |= vid_bit;
1358         else
1359                 vfta &= ~vid_bit;
1360         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1361
1362         /* update local VFTA copy */
1363         shadow_vfta->vfta[vid_idx] = vfta;
1364
1365         return 0;
1366 }
1367
1368 static void
1369 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1370 {
1371         struct e1000_hw *hw =
1372                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1373         uint32_t reg = ETHER_TYPE_VLAN ;
1374
1375         reg |= (tpid << 16);
1376         E1000_WRITE_REG(hw, E1000_VET, reg);
1377 }
1378
1379 static void
1380 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1381 {
1382         struct e1000_hw *hw =
1383                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1384         uint32_t reg;
1385
1386         /* Filter Table Disable */
1387         reg = E1000_READ_REG(hw, E1000_RCTL);
1388         reg &= ~E1000_RCTL_CFIEN;
1389         reg &= ~E1000_RCTL_VFE;
1390         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1391 }
1392
1393 static void
1394 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1395 {
1396         struct e1000_hw *hw =
1397                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1398         struct e1000_vfta * shadow_vfta =
1399                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1400         uint32_t reg;
1401         int i;
1402
1403         /* Filter Table Enable, CFI not used for packet acceptance */
1404         reg = E1000_READ_REG(hw, E1000_RCTL);
1405         reg &= ~E1000_RCTL_CFIEN;
1406         reg |= E1000_RCTL_VFE;
1407         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1408
1409         /* restore VFTA table */
1410         for (i = 0; i < IGB_VFTA_SIZE; i++)
1411                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1412 }
1413
1414 static void
1415 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1416 {
1417         struct e1000_hw *hw =
1418                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419         uint32_t reg;
1420
1421         /* VLAN Mode Disable */
1422         reg = E1000_READ_REG(hw, E1000_CTRL);
1423         reg &= ~E1000_CTRL_VME;
1424         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1425 }
1426
1427 static void
1428 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1429 {
1430         struct e1000_hw *hw =
1431                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1432         uint32_t reg;
1433
1434         /* VLAN Mode Enable */
1435         reg = E1000_READ_REG(hw, E1000_CTRL);
1436         reg |= E1000_CTRL_VME;
1437         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1438 }
1439
1440 static void
1441 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1442 {
1443         struct e1000_hw *hw =
1444                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445         uint32_t reg;
1446
1447         /* CTRL_EXT: Extended VLAN */
1448         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1449         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1450         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1451
1452         /* Update maximum packet length */
1453         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1454                 E1000_WRITE_REG(hw, E1000_RLPML,
1455                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1456                                                 VLAN_TAG_SIZE);
1457 }
1458
1459 static void
1460 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1461 {
1462         struct e1000_hw *hw =
1463                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1464         uint32_t reg;
1465
1466         /* CTRL_EXT: Extended VLAN */
1467         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1468         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1469         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1470
1471         /* Update maximum packet length */
1472         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1473                 E1000_WRITE_REG(hw, E1000_RLPML,
1474                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1475                                                 2 * VLAN_TAG_SIZE);
1476 }
1477
1478 static void
1479 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1480 {
1481         if(mask & ETH_VLAN_STRIP_MASK){
1482                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1483                         igb_vlan_hw_strip_enable(dev);
1484                 else
1485                         igb_vlan_hw_strip_disable(dev);
1486         }
1487
1488         if(mask & ETH_VLAN_FILTER_MASK){
1489                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1490                         igb_vlan_hw_filter_enable(dev);
1491                 else
1492                         igb_vlan_hw_filter_disable(dev);
1493         }
1494
1495         if(mask & ETH_VLAN_EXTEND_MASK){
1496                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1497                         igb_vlan_hw_extend_enable(dev);
1498                 else
1499                         igb_vlan_hw_extend_disable(dev);
1500         }
1501 }
1502
1503
1504 /**
1505  * It enables the interrupt mask and then enable the interrupt.
1506  *
1507  * @param dev
1508  *  Pointer to struct rte_eth_dev.
1509  *
1510  * @return
1511  *  - On success, zero.
1512  *  - On failure, a negative value.
1513  */
1514 static int
1515 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1516 {
1517         struct e1000_interrupt *intr =
1518                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1519
1520         intr->mask |= E1000_ICR_LSC;
1521
1522         return 0;
1523 }
1524
1525 /*
1526  * It reads ICR and gets interrupt causes, check it and set a bit flag
1527  * to update link status.
1528  *
1529  * @param dev
1530  *  Pointer to struct rte_eth_dev.
1531  *
1532  * @return
1533  *  - On success, zero.
1534  *  - On failure, a negative value.
1535  */
1536 static int
1537 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1538 {
1539         uint32_t icr;
1540         struct e1000_hw *hw =
1541                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1542         struct e1000_interrupt *intr =
1543                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1544
1545         igb_intr_disable(hw);
1546
1547         /* read-on-clear nic registers here */
1548         icr = E1000_READ_REG(hw, E1000_ICR);
1549
1550         intr->flags = 0;
1551         if (icr & E1000_ICR_LSC) {
1552                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1553         }
1554
1555         if (icr & E1000_ICR_VMMB)
1556                 intr->flags |= E1000_FLAG_MAILBOX;
1557
1558         return 0;
1559 }
1560
1561 /*
1562  * It executes link_update after knowing an interrupt is prsent.
1563  *
1564  * @param dev
1565  *  Pointer to struct rte_eth_dev.
1566  *
1567  * @return
1568  *  - On success, zero.
1569  *  - On failure, a negative value.
1570  */
1571 static int
1572 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1573 {
1574         struct e1000_hw *hw =
1575                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1576         struct e1000_interrupt *intr =
1577                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1578         uint32_t tctl, rctl;
1579         struct rte_eth_link link;
1580         int ret;
1581
1582         if (intr->flags & E1000_FLAG_MAILBOX) {
1583                 igb_pf_mbx_process(dev);
1584                 intr->flags &= ~E1000_FLAG_MAILBOX;
1585         }
1586
1587         igb_intr_enable(dev);
1588         rte_intr_enable(&(dev->pci_dev->intr_handle));
1589
1590         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1591                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1592
1593                 /* set get_link_status to check register later */
1594                 hw->mac.get_link_status = 1;
1595                 ret = eth_igb_link_update(dev, 0);
1596
1597                 /* check if link has changed */
1598                 if (ret < 0)
1599                         return 0;
1600
1601                 memset(&link, 0, sizeof(link));
1602                 rte_igb_dev_atomic_read_link_status(dev, &link);
1603                 if (link.link_status) {
1604                         PMD_INIT_LOG(INFO,
1605                                 " Port %d: Link Up - speed %u Mbps - %s\n",
1606                                 dev->data->port_id, (unsigned)link.link_speed,
1607                                 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1608                                         "full-duplex" : "half-duplex");
1609                 } else {
1610                         PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1611                                                 dev->data->port_id);
1612                 }
1613                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1614                                         dev->pci_dev->addr.domain,
1615                                         dev->pci_dev->addr.bus,
1616                                         dev->pci_dev->addr.devid,
1617                                         dev->pci_dev->addr.function);
1618                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1619                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1620                 if (link.link_status) {
1621                         /* enable Tx/Rx */
1622                         tctl |= E1000_TCTL_EN;
1623                         rctl |= E1000_RCTL_EN;
1624                 } else {
1625                         /* disable Tx/Rx */
1626                         tctl &= ~E1000_TCTL_EN;
1627                         rctl &= ~E1000_RCTL_EN;
1628                 }
1629                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1630                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1631                 E1000_WRITE_FLUSH(hw);
1632                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1633         }
1634
1635         return 0;
1636 }
1637
1638 /**
1639  * Interrupt handler which shall be registered at first.
1640  *
1641  * @param handle
1642  *  Pointer to interrupt handle.
1643  * @param param
1644  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1645  *
1646  * @return
1647  *  void
1648  */
1649 static void
1650 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1651                                                         void *param)
1652 {
1653         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1654
1655         eth_igb_interrupt_get_status(dev);
1656         eth_igb_interrupt_action(dev);
1657 }
1658
1659 static int
1660 eth_igb_led_on(struct rte_eth_dev *dev)
1661 {
1662         struct e1000_hw *hw;
1663
1664         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1666 }
1667
1668 static int
1669 eth_igb_led_off(struct rte_eth_dev *dev)
1670 {
1671         struct e1000_hw *hw;
1672
1673         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1675 }
1676
1677 static int
1678 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1679 {
1680         struct e1000_hw *hw;
1681         int err;
1682         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1683                 e1000_fc_none,
1684                 e1000_fc_rx_pause,
1685                 e1000_fc_tx_pause,
1686                 e1000_fc_full
1687         };
1688         uint32_t rx_buf_size;
1689         uint32_t max_high_water;
1690
1691         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1692         rx_buf_size = igb_get_rx_buffer_size(hw);
1693         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1694
1695         /* At least reserve one Ethernet frame for watermark */
1696         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1697         if ((fc_conf->high_water > max_high_water) ||
1698                 (fc_conf->high_water < fc_conf->low_water)) {
1699                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1700                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1701                 return (-EINVAL);
1702         }
1703
1704         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1705         hw->fc.pause_time     = fc_conf->pause_time;
1706         hw->fc.high_water     = fc_conf->high_water;
1707         hw->fc.low_water      = fc_conf->low_water;
1708         hw->fc.send_xon       = fc_conf->send_xon;
1709
1710         err = e1000_setup_link_generic(hw);
1711         if (err == E1000_SUCCESS) {
1712                 return 0;
1713         }
1714
1715         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1716         return (-EIO);
1717 }
1718
1719 #define E1000_RAH_POOLSEL_SHIFT      (18)
1720 static void
1721 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1722                 uint32_t index, __rte_unused uint32_t pool)
1723 {
1724         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1725         uint32_t rah;
1726
1727         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1728         rah = E1000_READ_REG(hw, E1000_RAH(index));
1729         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
1730         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
1731 }
1732
1733 static void
1734 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1735 {
1736         uint8_t addr[ETHER_ADDR_LEN];
1737         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1738
1739         memset(addr, 0, sizeof(addr));
1740
1741         e1000_rar_set(hw, addr, index);
1742 }
1743
1744 /*
1745  * Virtual Function operations
1746  */
1747 static void
1748 igbvf_intr_disable(struct e1000_hw *hw)
1749 {
1750         PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1751
1752         /* Clear interrupt mask to stop from interrupts being generated */
1753         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
1754
1755         E1000_WRITE_FLUSH(hw);
1756 }
1757
1758 static void
1759 igbvf_stop_adapter(struct rte_eth_dev *dev)
1760 {
1761         u32 reg_val;
1762         u16 i;
1763         struct rte_eth_dev_info dev_info;
1764         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1765
1766         memset(&dev_info, 0, sizeof(dev_info));
1767         eth_igb_infos_get(dev, &dev_info);
1768
1769         /* Clear interrupt mask to stop from interrupts being generated */
1770         igbvf_intr_disable(hw);
1771
1772         /* Clear any pending interrupts, flush previous writes */
1773         E1000_READ_REG(hw, E1000_EICR);
1774
1775         /* Disable the transmit unit.  Each queue must be disabled. */
1776         for (i = 0; i < dev_info.max_tx_queues; i++)
1777                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1778
1779         /* Disable the receive unit by stopping each queue */
1780         for (i = 0; i < dev_info.max_rx_queues; i++) {
1781                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1782                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1783                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1784                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1785                         ;
1786         }
1787
1788         /* flush all queues disables */
1789         E1000_WRITE_FLUSH(hw);
1790         msec_delay(2);
1791 }
1792
1793 static int eth_igbvf_link_update(struct e1000_hw *hw)
1794 {
1795         struct e1000_mbx_info *mbx = &hw->mbx;
1796         struct e1000_mac_info *mac = &hw->mac;
1797         int ret_val = E1000_SUCCESS;
1798
1799         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1800
1801         /*
1802          * We only want to run this if there has been a rst asserted.
1803          * in this case that could mean a link change, device reset,
1804          * or a virtual function reset
1805          */
1806
1807         /* If we were hit with a reset or timeout drop the link */
1808         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1809                 mac->get_link_status = TRUE;
1810
1811         if (!mac->get_link_status)
1812                 goto out;
1813
1814         /* if link status is down no point in checking to see if pf is up */
1815         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1816                 goto out;
1817
1818         /* if we passed all the tests above then the link is up and we no
1819          * longer need to check for link */
1820         mac->get_link_status = FALSE;
1821
1822 out:
1823         return ret_val;
1824 }
1825
1826
1827 static int
1828 igbvf_dev_configure(struct rte_eth_dev *dev)
1829 {
1830         struct rte_eth_conf* conf = &dev->data->dev_conf;
1831
1832         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1833                 dev->data->port_id);
1834
1835         /*
1836          * VF has no ability to enable/disable HW CRC
1837          * Keep the persistent behavior the same as Host PF
1838          */
1839 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1840         if (!conf->rxmode.hw_strip_crc) {
1841                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1842                 conf->rxmode.hw_strip_crc = 1;
1843         }
1844 #else
1845         if (conf->rxmode.hw_strip_crc) {
1846                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1847                 conf->rxmode.hw_strip_crc = 0;
1848         }
1849 #endif
1850
1851         return 0;
1852 }
1853
1854 static int
1855 igbvf_dev_start(struct rte_eth_dev *dev)
1856 {
1857         struct e1000_hw *hw =
1858                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859         int ret;
1860
1861         PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1862
1863         hw->mac.ops.reset_hw(hw);
1864
1865         /* Set all vfta */
1866         igbvf_set_vfta_all(dev,1);
1867
1868         eth_igbvf_tx_init(dev);
1869
1870         /* This can fail when allocating mbufs for descriptor rings */
1871         ret = eth_igbvf_rx_init(dev);
1872         if (ret) {
1873                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1874                 igb_dev_clear_queues(dev);
1875                 return ret;
1876         }
1877
1878         return 0;
1879 }
1880
1881 static void
1882 igbvf_dev_stop(struct rte_eth_dev *dev)
1883 {
1884         PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1885
1886         igbvf_stop_adapter(dev);
1887
1888         /*
1889           * Clear what we set, but we still keep shadow_vfta to
1890           * restore after device starts
1891           */
1892         igbvf_set_vfta_all(dev,0);
1893
1894         igb_dev_clear_queues(dev);
1895 }
1896
1897 static void
1898 igbvf_dev_close(struct rte_eth_dev *dev)
1899 {
1900         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901
1902         PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1903
1904         e1000_reset_hw(hw);
1905
1906         igbvf_dev_stop(dev);
1907 }
1908
1909 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1910 {
1911         struct e1000_mbx_info *mbx = &hw->mbx;
1912         uint32_t msgbuf[2];
1913
1914         /* After set vlan, vlan strip will also be enabled in igb driver*/
1915         msgbuf[0] = E1000_VF_SET_VLAN;
1916         msgbuf[1] = vid;
1917         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1918         if (on)
1919                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1920
1921         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1922 }
1923
1924 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1925 {
1926         struct e1000_hw *hw =
1927                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928         struct e1000_vfta * shadow_vfta =
1929                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1930         int i = 0, j = 0, vfta = 0, mask = 1;
1931
1932         for (i = 0; i < IGB_VFTA_SIZE; i++){
1933                 vfta = shadow_vfta->vfta[i];
1934                 if(vfta){
1935                         mask = 1;
1936                         for (j = 0; j < 32; j++){
1937                                 if(vfta & mask)
1938                                         igbvf_set_vfta(hw,
1939                                                 (uint16_t)((i<<5)+j), on);
1940                                 mask<<=1;
1941                         }
1942                 }
1943         }
1944
1945 }
1946
1947 static int
1948 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1949 {
1950         struct e1000_hw *hw =
1951                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1952         struct e1000_vfta * shadow_vfta =
1953                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1954         uint32_t vid_idx = 0;
1955         uint32_t vid_bit = 0;
1956         int ret = 0;
1957
1958         PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
1959
1960         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
1961         ret = igbvf_set_vfta(hw, vlan_id, !!on);
1962         if(ret){
1963                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
1964                 return ret;
1965         }
1966         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1967         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1968
1969         /*Save what we set and retore it after device reset*/
1970         if (on)
1971                 shadow_vfta->vfta[vid_idx] |= vid_bit;
1972         else
1973                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
1974
1975         return 0;
1976 }
1977
1978 static int
1979 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
1980                                 struct rte_eth_rss_reta *reta_conf)
1981 {
1982         uint8_t i,j,mask;
1983         uint32_t reta;
1984         struct e1000_hw *hw =
1985                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1986
1987         /*
1988          * Update Redirection Table RETA[n],n=0...31,The redirection table has
1989          * 128-entries in 32 registers
1990          */
1991         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1992                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
1993                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1994                 else
1995                         mask = (uint8_t)((reta_conf->mask_hi >>
1996                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
1997                 if (mask != 0) {
1998                         reta = 0;
1999                         /* If all 4 entries were set,don't need read RETA register */
2000                         if (mask != 0xF)
2001                                 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2002
2003                         for (j = 0; j < 4; j++) {
2004                                 if (mask & (0x1 << j)) {
2005                                         if (mask != 0xF)
2006                                                 reta &= ~(0xFF << 8 * j);
2007                                         reta |= reta_conf->reta[i + j] << 8 * j;
2008                                 }
2009                         }
2010                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2011                 }
2012         }
2013
2014         return 0;
2015 }
2016
2017 static int
2018 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2019                                 struct rte_eth_rss_reta *reta_conf)
2020 {
2021         uint8_t i,j,mask;
2022         uint32_t reta;
2023         struct e1000_hw *hw =
2024                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025
2026         /*
2027          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2028          * 128-entries in 32 registers
2029          */
2030         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2031                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2032                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2033                 else
2034                         mask = (uint8_t)((reta_conf->mask_hi >>
2035                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2036
2037                 if (mask != 0) {
2038                         reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2039                         for (j = 0; j < 4; j++) {
2040                                 if (mask & (0x1 << j))
2041                                         reta_conf->reta[i + j] =
2042                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2043                         }
2044                 }
2045         }
2046
2047         return 0;
2048 }