lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 /* Bit shift and mask */
  73 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  74 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  75 #define IGB_8_BIT_WIDTH  CHAR_BIT
  76 #define IGB_8_BIT_MASK   UINT8_MAX
  77
  78 static int  eth_igb_configure(struct rte_eth_dev *dev);
  79 static int  eth_igb_start(struct rte_eth_dev *dev);
  80 static void eth_igb_stop(struct rte_eth_dev *dev);
  81 static void eth_igb_close(struct rte_eth_dev *dev);
  82 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  91 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  92                               struct rte_eth_dev_info *dev_info);
  93 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
  94                                 struct rte_eth_dev_info *dev_info);
  95 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
  96                                 struct rte_eth_fc_conf *fc_conf);
  97 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  98                                 struct rte_eth_fc_conf *fc_conf);
  99 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 100 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 101 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 102 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 103                                                         void *param);
 104 static int  igb_hardware_init(struct e1000_hw *hw);
 105 static void igb_hw_control_acquire(struct e1000_hw *hw);
 106 static void igb_hw_control_release(struct e1000_hw *hw);
 107 static void igb_init_manageability(struct e1000_hw *hw);
 108 static void igb_release_manageability(struct e1000_hw *hw);
 109
 110 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 111
 112 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 113                 uint16_t vlan_id, int on);
 114 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 115 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 116
 117 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 118 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 119 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 120 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 121 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 122 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 123
 124 static int eth_igb_led_on(struct rte_eth_dev *dev);
 125 static int eth_igb_led_off(struct rte_eth_dev *dev);
 126
 127 static void igb_intr_disable(struct e1000_hw *hw);
 128 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 129 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 130                 struct ether_addr *mac_addr,
 131                 uint32_t index, uint32_t pool);
 132 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 133
 134 static void igbvf_intr_disable(struct e1000_hw *hw);
 135 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 136 static int igbvf_dev_start(struct rte_eth_dev *dev);
 137 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 138 static void igbvf_dev_close(struct rte_eth_dev *dev);
 139 static int eth_igbvf_link_update(struct e1000_hw *hw);
 140 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 141 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 142 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 143                 uint16_t vlan_id, int on);
 144 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 145 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 146 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 147                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 148                                    uint16_t reta_size);
 149 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 150                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 151                                   uint16_t reta_size);
 152
 153 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 154                         struct rte_eth_syn_filter *filter,
 155                         bool add);
 156 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 157                         struct rte_eth_syn_filter *filter);
 158 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 159                         enum rte_filter_op filter_op,
 160                         void *arg);
 161 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 162                         struct rte_eth_ntuple_filter *ntuple_filter);
 163 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 164                         struct rte_eth_ntuple_filter *ntuple_filter);
 165 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 166                         struct rte_eth_flex_filter *filter,
 167                         bool add);
 168 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 169                         struct rte_eth_flex_filter *filter);
 170 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 171                         enum rte_filter_op filter_op,
 172                         void *arg);
 173 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 174                         struct rte_eth_ntuple_filter *ntuple_filter);
 175 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 176                         struct rte_eth_ntuple_filter *ntuple_filter);
 177 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 178                         struct rte_eth_ntuple_filter *filter,
 179                         bool add);
 180 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 181                         struct rte_eth_ntuple_filter *filter);
 182 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 183                                 enum rte_filter_op filter_op,
 184                                 void *arg);
 185 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 186                         struct rte_eth_ethertype_filter *filter,
 187                         bool add);
 188 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 189                                 enum rte_filter_op filter_op,
 190                                 void *arg);
 191 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 192                         struct rte_eth_ethertype_filter *filter);
 193 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 194                      enum rte_filter_type filter_type,
 195                      enum rte_filter_op filter_op,
 196                      void *arg);
 197
 198 /*
 199  * Define VF Stats MACRO for Non "cleared on read" register
 200  */
 201 #define UPDATE_VF_STAT(reg, last, cur)            \
 202 {                                                 \
 203         u32 latest = E1000_READ_REG(hw, reg);     \
 204         cur += latest - last;                     \
 205         last = latest;                            \
 206 }
 207
 208
 209 #define IGB_FC_PAUSE_TIME 0x0680
 210 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 211 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 212
 213 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 214
 215 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 216
 217 /*
 218  * The set of PCI devices this driver supports
 219  */
 220 static struct rte_pci_id pci_id_igb_map[] = {
 221
 222 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 223 #include "rte_pci_dev_ids.h"
 224
 225 {.device_id = 0},
 226 };
 227
 228 /*
 229  * The set of PCI devices this driver supports (for 82576&I350 VF)
 230  */
 231 static struct rte_pci_id pci_id_igbvf_map[] = {
 232
 233 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 234 #include "rte_pci_dev_ids.h"
 235
 236 {.device_id = 0},
 237 };
 238
 239 static struct eth_dev_ops eth_igb_ops = {
 240         .dev_configure        = eth_igb_configure,
 241         .dev_start            = eth_igb_start,
 242         .dev_stop             = eth_igb_stop,
 243         .dev_close            = eth_igb_close,
 244         .promiscuous_enable   = eth_igb_promiscuous_enable,
 245         .promiscuous_disable  = eth_igb_promiscuous_disable,
 246         .allmulticast_enable  = eth_igb_allmulticast_enable,
 247         .allmulticast_disable = eth_igb_allmulticast_disable,
 248         .link_update          = eth_igb_link_update,
 249         .stats_get            = eth_igb_stats_get,
 250         .stats_reset          = eth_igb_stats_reset,
 251         .dev_infos_get        = eth_igb_infos_get,
 252         .mtu_set              = eth_igb_mtu_set,
 253         .vlan_filter_set      = eth_igb_vlan_filter_set,
 254         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 255         .vlan_offload_set     = eth_igb_vlan_offload_set,
 256         .rx_queue_setup       = eth_igb_rx_queue_setup,
 257         .rx_queue_release     = eth_igb_rx_queue_release,
 258         .rx_queue_count       = eth_igb_rx_queue_count,
 259         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 260         .tx_queue_setup       = eth_igb_tx_queue_setup,
 261         .tx_queue_release     = eth_igb_tx_queue_release,
 262         .dev_led_on           = eth_igb_led_on,
 263         .dev_led_off          = eth_igb_led_off,
 264         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 265         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 266         .mac_addr_add         = eth_igb_rar_set,
 267         .mac_addr_remove      = eth_igb_rar_clear,
 268         .reta_update          = eth_igb_rss_reta_update,
 269         .reta_query           = eth_igb_rss_reta_query,
 270         .rss_hash_update      = eth_igb_rss_hash_update,
 271         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 272         .filter_ctrl          = eth_igb_filter_ctrl,
 273 };
 274
 275 /*
 276  * dev_ops for virtual function, bare necessities for basic vf
 277  * operation have been implemented
 278  */
 279 static struct eth_dev_ops igbvf_eth_dev_ops = {
 280         .dev_configure        = igbvf_dev_configure,
 281         .dev_start            = igbvf_dev_start,
 282         .dev_stop             = igbvf_dev_stop,
 283         .dev_close            = igbvf_dev_close,
 284         .link_update          = eth_igb_link_update,
 285         .stats_get            = eth_igbvf_stats_get,
 286         .stats_reset          = eth_igbvf_stats_reset,
 287         .vlan_filter_set      = igbvf_vlan_filter_set,
 288         .dev_infos_get        = eth_igbvf_infos_get,
 289         .rx_queue_setup       = eth_igb_rx_queue_setup,
 290         .rx_queue_release     = eth_igb_rx_queue_release,
 291         .tx_queue_setup       = eth_igb_tx_queue_setup,
 292         .tx_queue_release     = eth_igb_tx_queue_release,
 293 };
 294
 295 /**
 296  * Atomically reads the link status information from global
 297  * structure rte_eth_dev.
 298  *
 299  * @param dev
 300  *   - Pointer to the structure rte_eth_dev to read from.
 301  *   - Pointer to the buffer to be saved with the link status.
 302  *
 303  * @return
 304  *   - On success, zero.
 305  *   - On failure, negative value.
 306  */
 307 static inline int
 308 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 309                                 struct rte_eth_link *link)
 310 {
 311         struct rte_eth_link *dst = link;
 312         struct rte_eth_link *src = &(dev->data->dev_link);
 313
 314         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 315                                         *(uint64_t *)src) == 0)
 316                 return -1;
 317
 318         return 0;
 319 }
 320
 321 /**
 322  * Atomically writes the link status information into global
 323  * structure rte_eth_dev.
 324  *
 325  * @param dev
 326  *   - Pointer to the structure rte_eth_dev to read from.
 327  *   - Pointer to the buffer to be saved with the link status.
 328  *
 329  * @return
 330  *   - On success, zero.
 331  *   - On failure, negative value.
 332  */
 333 static inline int
 334 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 335                                 struct rte_eth_link *link)
 336 {
 337         struct rte_eth_link *dst = &(dev->data->dev_link);
 338         struct rte_eth_link *src = link;
 339
 340         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 341                                         *(uint64_t *)src) == 0)
 342                 return -1;
 343
 344         return 0;
 345 }
 346
 347 static inline void
 348 igb_intr_enable(struct rte_eth_dev *dev)
 349 {
 350         struct e1000_interrupt *intr =
 351                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 352         struct e1000_hw *hw =
 353                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 354
 355         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 356         E1000_WRITE_FLUSH(hw);
 357 }
 358
 359 static void
 360 igb_intr_disable(struct e1000_hw *hw)
 361 {
 362         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 363         E1000_WRITE_FLUSH(hw);
 364 }
 365
 366 static inline int32_t
 367 igb_pf_reset_hw(struct e1000_hw *hw)
 368 {
 369         uint32_t ctrl_ext;
 370         int32_t status;
 371
 372         status = e1000_reset_hw(hw);
 373
 374         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 375         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 376         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 377         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 378         E1000_WRITE_FLUSH(hw);
 379
 380         return status;
 381 }
 382
 383 static void
 384 igb_identify_hardware(struct rte_eth_dev *dev)
 385 {
 386         struct e1000_hw *hw =
 387                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 388
 389         hw->vendor_id = dev->pci_dev->id.vendor_id;
 390         hw->device_id = dev->pci_dev->id.device_id;
 391         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 392         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 393
 394         e1000_set_mac_type(hw);
 395
 396         /* need to check if it is a vf device below */
 397 }
 398
 399 static int
 400 igb_reset_swfw_lock(struct e1000_hw *hw)
 401 {
 402         int ret_val;
 403
 404         /*
 405          * Do mac ops initialization manually here, since we will need
 406          * some function pointers set by this call.
 407          */
 408         ret_val = e1000_init_mac_params(hw);
 409         if (ret_val)
 410                 return ret_val;
 411
 412         /*
 413          * SMBI lock should not fail in this early stage. If this is the case,
 414          * it is due to an improper exit of the application.
 415          * So force the release of the faulty lock.
 416          */
 417         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 418                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 419         }
 420         e1000_put_hw_semaphore_generic(hw);
 421
 422         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 423                 uint16_t mask;
 424
 425                 /*
 426                  * Phy lock should not fail in this early stage. If this is the case,
 427                  * it is due to an improper exit of the application.
 428                  * So force the release of the faulty lock.
 429                  */
 430                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 431                 if (hw->bus.func > E1000_FUNC_1)
 432                         mask <<= 2;
 433                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 434                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 435                                     hw->bus.func);
 436                 }
 437                 hw->mac.ops.release_swfw_sync(hw, mask);
 438
 439                 /*
 440                  * This one is more tricky since it is common to all ports; but
 441                  * swfw_sync retries last long enough (1s) to be almost sure that if
 442                  * lock can not be taken it is due to an improper lock of the
 443                  * semaphore.
 444                  */
 445                 mask = E1000_SWFW_EEP_SM;
 446                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 447                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 448                 }
 449                 hw->mac.ops.release_swfw_sync(hw, mask);
 450         }
 451
 452         return E1000_SUCCESS;
 453 }
 454
 455 static int
 456 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 457 {
 458         int error = 0;
 459         struct rte_pci_device *pci_dev;
 460         struct e1000_hw *hw =
 461                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 462         struct e1000_vfta * shadow_vfta =
 463                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 464         struct e1000_filter_info *filter_info =
 465                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 466         uint32_t ctrl_ext;
 467
 468         pci_dev = eth_dev->pci_dev;
 469         eth_dev->dev_ops = &eth_igb_ops;
 470         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 471         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 472
 473         /* for secondary processes, we don't initialise any further as primary
 474          * has already done this work. Only check we don't need a different
 475          * RX function */
 476         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 477                 if (eth_dev->data->scattered_rx)
 478                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 479                 return 0;
 480         }
 481
 482         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 483
 484         igb_identify_hardware(eth_dev);
 485         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 486                 error = -EIO;
 487                 goto err_late;
 488         }
 489
 490         e1000_get_bus_info(hw);
 491
 492         /* Reset any pending lock */
 493         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 494                 error = -EIO;
 495                 goto err_late;
 496         }
 497
 498         /* Finish initialization */
 499         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 500                 error = -EIO;
 501                 goto err_late;
 502         }
 503
 504         hw->mac.autoneg = 1;
 505         hw->phy.autoneg_wait_to_complete = 0;
 506         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 507
 508         /* Copper options */
 509         if (hw->phy.media_type == e1000_media_type_copper) {
 510                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 511                 hw->phy.disable_polarity_correction = 0;
 512                 hw->phy.ms_type = e1000_ms_hw_default;
 513         }
 514
 515         /*
 516          * Start from a known state, this is important in reading the nvm
 517          * and mac from that.
 518          */
 519         igb_pf_reset_hw(hw);
 520
 521         /* Make sure we have a good EEPROM before we read from it */
 522         if (e1000_validate_nvm_checksum(hw) < 0) {
 523                 /*
 524                  * Some PCI-E parts fail the first check due to
 525                  * the link being in sleep state, call it again,
 526                  * if it fails a second time its a real issue.
 527                  */
 528                 if (e1000_validate_nvm_checksum(hw) < 0) {
 529                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 530                         error = -EIO;
 531                         goto err_late;
 532                 }
 533         }
 534
 535         /* Read the permanent MAC address out of the EEPROM */
 536         if (e1000_read_mac_addr(hw) != 0) {
 537                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 538                 error = -EIO;
 539                 goto err_late;
 540         }
 541
 542         /* Allocate memory for storing MAC addresses */
 543         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 544                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 545         if (eth_dev->data->mac_addrs == NULL) {
 546                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 547                                                 "store MAC addresses",
 548                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 549                 error = -ENOMEM;
 550                 goto err_late;
 551         }
 552
 553         /* Copy the permanent MAC address */
 554         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 555
 556         /* initialize the vfta */
 557         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 558
 559         /* Now initialize the hardware */
 560         if (igb_hardware_init(hw) != 0) {
 561                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 562                 rte_free(eth_dev->data->mac_addrs);
 563                 eth_dev->data->mac_addrs = NULL;
 564                 error = -ENODEV;
 565                 goto err_late;
 566         }
 567         hw->mac.get_link_status = 1;
 568
 569         /* Indicate SOL/IDER usage */
 570         if (e1000_check_reset_block(hw) < 0) {
 571                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 572                                         "SOL/IDER session");
 573         }
 574
 575         /* initialize PF if max_vfs not zero */
 576         igb_pf_host_init(eth_dev);
 577
 578         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 579         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 580         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 581         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 582         E1000_WRITE_FLUSH(hw);
 583
 584         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
 585                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 586                      pci_dev->id.device_id);
 587
 588         rte_intr_callback_register(&(pci_dev->intr_handle),
 589                 eth_igb_interrupt_handler, (void *)eth_dev);
 590
 591         /* enable uio intr after callback register */
 592         rte_intr_enable(&(pci_dev->intr_handle));
 593
 594         /* enable support intr */
 595         igb_intr_enable(eth_dev);
 596
 597         TAILQ_INIT(&filter_info->flex_list);
 598         filter_info->flex_mask = 0;
 599         TAILQ_INIT(&filter_info->twotuple_list);
 600         filter_info->twotuple_mask = 0;
 601         TAILQ_INIT(&filter_info->fivetuple_list);
 602         filter_info->fivetuple_mask = 0;
 603
 604         return 0;
 605
 606 err_late:
 607         igb_hw_control_release(hw);
 608
 609         return (error);
 610 }
 611
 612 /*
 613  * Virtual Function device init
 614  */
 615 static int
 616 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 617 {
 618         struct rte_pci_device *pci_dev;
 619         struct e1000_hw *hw =
 620                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 621         int diag;
 622
 623         PMD_INIT_FUNC_TRACE();
 624
 625         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 626         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 627         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 628
 629         /* for secondary processes, we don't initialise any further as primary
 630          * has already done this work. Only check we don't need a different
 631          * RX function */
 632         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 633                 if (eth_dev->data->scattered_rx)
 634                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 635                 return 0;
 636         }
 637
 638         pci_dev = eth_dev->pci_dev;
 639
 640         hw->device_id = pci_dev->id.device_id;
 641         hw->vendor_id = pci_dev->id.vendor_id;
 642         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 643
 644         /* Initialize the shared code (base driver) */
 645         diag = e1000_setup_init_funcs(hw, TRUE);
 646         if (diag != 0) {
 647                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 648                         diag);
 649                 return -EIO;
 650         }
 651
 652         /* init_mailbox_params */
 653         hw->mbx.ops.init_params(hw);
 654
 655         /* Disable the interrupts for VF */
 656         igbvf_intr_disable(hw);
 657
 658         diag = hw->mac.ops.reset_hw(hw);
 659
 660         /* Allocate memory for storing MAC addresses */
 661         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 662                 hw->mac.rar_entry_count, 0);
 663         if (eth_dev->data->mac_addrs == NULL) {
 664                 PMD_INIT_LOG(ERR,
 665                         "Failed to allocate %d bytes needed to store MAC "
 666                         "addresses",
 667                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 668                 return -ENOMEM;
 669         }
 670
 671         /* Copy the permanent MAC address */
 672         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 673                         &eth_dev->data->mac_addrs[0]);
 674
 675         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 676                      "mac.type=%s",
 677                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 678                      pci_dev->id.device_id, "igb_mac_82576_vf");
 679
 680         return 0;
 681 }
 682
 683 static struct eth_driver rte_igb_pmd = {
 684         {
 685                 .name = "rte_igb_pmd",
 686                 .id_table = pci_id_igb_map,
 687                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 688         },
 689         .eth_dev_init = eth_igb_dev_init,
 690         .dev_private_size = sizeof(struct e1000_adapter),
 691 };
 692
 693 /*
 694  * virtual function driver struct
 695  */
 696 static struct eth_driver rte_igbvf_pmd = {
 697         {
 698                 .name = "rte_igbvf_pmd",
 699                 .id_table = pci_id_igbvf_map,
 700                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 701         },
 702         .eth_dev_init = eth_igbvf_dev_init,
 703         .dev_private_size = sizeof(struct e1000_adapter),
 704 };
 705
 706 static int
 707 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 708 {
 709         rte_eth_driver_register(&rte_igb_pmd);
 710         return 0;
 711 }
 712
 713 static void
 714 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 715 {
 716         struct e1000_hw *hw =
 717                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 718         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 719         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 720         rctl |= E1000_RCTL_VFE;
 721         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 722 }
 723
 724 /*
 725  * VF Driver initialization routine.
 726  * Invoked one at EAL init time.
 727  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 728  */
 729 static int
 730 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 731 {
 732         PMD_INIT_FUNC_TRACE();
 733
 734         rte_eth_driver_register(&rte_igbvf_pmd);
 735         return (0);
 736 }
 737
 738 static int
 739 eth_igb_configure(struct rte_eth_dev *dev)
 740 {
 741         struct e1000_interrupt *intr =
 742                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 743
 744         PMD_INIT_FUNC_TRACE();
 745         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 746         PMD_INIT_FUNC_TRACE();
 747
 748         return (0);
 749 }
 750
 751 static int
 752 eth_igb_start(struct rte_eth_dev *dev)
 753 {
 754         struct e1000_hw *hw =
 755                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 756         int ret, i, mask;
 757         uint32_t ctrl_ext;
 758
 759         PMD_INIT_FUNC_TRACE();
 760
 761         /* Power up the phy. Needed to make the link go Up */
 762         e1000_power_up_phy(hw);
 763
 764         /*
 765          * Packet Buffer Allocation (PBA)
 766          * Writing PBA sets the receive portion of the buffer
 767          * the remainder is used for the transmit buffer.
 768          */
 769         if (hw->mac.type == e1000_82575) {
 770                 uint32_t pba;
 771
 772                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 773                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 774         }
 775
 776         /* Put the address into the Receive Address Array */
 777         e1000_rar_set(hw, hw->mac.addr, 0);
 778
 779         /* Initialize the hardware */
 780         if (igb_hardware_init(hw)) {
 781                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 782                 return (-EIO);
 783         }
 784
 785         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 786
 787         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 788         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 789         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 790         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 791         E1000_WRITE_FLUSH(hw);
 792
 793         /* configure PF module if SRIOV enabled */
 794         igb_pf_host_configure(dev);
 795
 796         /* Configure for OS presence */
 797         igb_init_manageability(hw);
 798
 799         eth_igb_tx_init(dev);
 800
 801         /* This can fail when allocating mbufs for descriptor rings */
 802         ret = eth_igb_rx_init(dev);
 803         if (ret) {
 804                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 805                 igb_dev_clear_queues(dev);
 806                 return ret;
 807         }
 808
 809         e1000_clear_hw_cntrs_base_generic(hw);
 810
 811         /*
 812          * VLAN Offload Settings
 813          */
 814         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 815                         ETH_VLAN_EXTEND_MASK;
 816         eth_igb_vlan_offload_set(dev, mask);
 817
 818         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 819                 /* Enable VLAN filter since VMDq always use VLAN filter */
 820                 igb_vmdq_vlan_hw_filter_enable(dev);
 821         }
 822
 823         /*
 824          * Configure the Interrupt Moderation register (EITR) with the maximum
 825          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 826          * spurious [DMA] memory updates of RX and TX ring descriptors.
 827          *
 828          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 829          * spurious memory updates per second should be expected.
 830          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 831          *
 832          * Because interrupts are not used at all, the MSI-X is not activated
 833          * and interrupt moderation is controlled by EITR[0].
 834          *
 835          * Note that having [almost] disabled memory updates of RX and TX ring
 836          * descriptors through the Interrupt Moderation mechanism, memory
 837          * updates of ring descriptors are now moderated by the configurable
 838          * value of Write-Back Threshold registers.
 839          */
 840         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 841                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
 842                 (hw->mac.type == e1000_i211)) {
 843                 uint32_t ivar;
 844
 845                 /* Enable all RX & TX queues in the IVAR registers */
 846                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 847                 for (i = 0; i < 8; i++)
 848                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 849
 850                 /* Configure EITR with the maximum possible value (0xFFFF) */
 851                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 852         }
 853
 854         /* Setup link speed and duplex */
 855         switch (dev->data->dev_conf.link_speed) {
 856         case ETH_LINK_SPEED_AUTONEG:
 857                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 858                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 859                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 860                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 861                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 862                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 863                 else
 864                         goto error_invalid_config;
 865                 break;
 866         case ETH_LINK_SPEED_10:
 867                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 868                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 869                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 870                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 871                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 872                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 873                 else
 874                         goto error_invalid_config;
 875                 break;
 876         case ETH_LINK_SPEED_100:
 877                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 878                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 879                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 880                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 881                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 882                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 883                 else
 884                         goto error_invalid_config;
 885                 break;
 886         case ETH_LINK_SPEED_1000:
 887                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 888                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 889                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 890                 else
 891                         goto error_invalid_config;
 892                 break;
 893         case ETH_LINK_SPEED_10000:
 894         default:
 895                 goto error_invalid_config;
 896         }
 897         e1000_setup_link(hw);
 898
 899         /* check if lsc interrupt feature is enabled */
 900         if (dev->data->dev_conf.intr_conf.lsc != 0)
 901                 ret = eth_igb_lsc_interrupt_setup(dev);
 902
 903         /* resume enabled intr since hw reset */
 904         igb_intr_enable(dev);
 905
 906         PMD_INIT_LOG(DEBUG, "<<");
 907
 908         return (0);
 909
 910 error_invalid_config:
 911         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 912                      dev->data->dev_conf.link_speed,
 913                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 914         igb_dev_clear_queues(dev);
 915         return (-EINVAL);
 916 }
 917
 918 /*********************************************************************
 919  *
 920  *  This routine disables all traffic on the adapter by issuing a
 921  *  global reset on the MAC.
 922  *
 923  **********************************************************************/
 924 static void
 925 eth_igb_stop(struct rte_eth_dev *dev)
 926 {
 927         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 928         struct e1000_filter_info *filter_info =
 929                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
 930         struct rte_eth_link link;
 931         struct e1000_flex_filter *p_flex;
 932         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
 933         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
 934
 935         igb_intr_disable(hw);
 936         igb_pf_reset_hw(hw);
 937         E1000_WRITE_REG(hw, E1000_WUC, 0);
 938
 939         /* Set bit for Go Link disconnect */
 940         if (hw->mac.type >= e1000_82580) {
 941                 uint32_t phpm_reg;
 942
 943                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 944                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 945                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 946         }
 947
 948         /* Power down the phy. Needed to make the link go Down */
 949         e1000_power_down_phy(hw);
 950
 951         igb_dev_clear_queues(dev);
 952
 953         /* clear the recorded link status */
 954         memset(&link, 0, sizeof(link));
 955         rte_igb_dev_atomic_write_link_status(dev, &link);
 956
 957         /* Remove all flex filters of the device */
 958         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 959                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 960                 rte_free(p_flex);
 961         }
 962         filter_info->flex_mask = 0;
 963
 964         /* Remove all ntuple filters of the device */
 965         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
 966              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
 967                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
 968                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 969                              p_5tuple, entries);
 970                 rte_free(p_5tuple);
 971         }
 972         filter_info->fivetuple_mask = 0;
 973         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
 974              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
 975                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
 976                 TAILQ_REMOVE(&filter_info->twotuple_list,
 977                              p_2tuple, entries);
 978                 rte_free(p_2tuple);
 979         }
 980         filter_info->twotuple_mask = 0;
 981 }
 982
 983 static void
 984 eth_igb_close(struct rte_eth_dev *dev)
 985 {
 986         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 987         struct rte_eth_link link;
 988
 989         eth_igb_stop(dev);
 990         e1000_phy_hw_reset(hw);
 991         igb_release_manageability(hw);
 992         igb_hw_control_release(hw);
 993
 994         /* Clear bit for Go Link disconnect */
 995         if (hw->mac.type >= e1000_82580) {
 996                 uint32_t phpm_reg;
 997
 998                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 999                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1000                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1001         }
1002
1003         igb_dev_clear_queues(dev);
1004
1005         memset(&link, 0, sizeof(link));
1006         rte_igb_dev_atomic_write_link_status(dev, &link);
1007 }
1008
1009 static int
1010 igb_get_rx_buffer_size(struct e1000_hw *hw)
1011 {
1012         uint32_t rx_buf_size;
1013         if (hw->mac.type == e1000_82576) {
1014                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1015         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1016                 /* PBS needs to be translated according to a lookup table */
1017                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1018                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1019                 rx_buf_size = (rx_buf_size << 10);
1020         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1021                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1022         } else {
1023                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1024         }
1025
1026         return rx_buf_size;
1027 }
1028
1029 /*********************************************************************
1030  *
1031  *  Initialize the hardware
1032  *
1033  **********************************************************************/
1034 static int
1035 igb_hardware_init(struct e1000_hw *hw)
1036 {
1037         uint32_t rx_buf_size;
1038         int diag;
1039
1040         /* Let the firmware know the OS is in control */
1041         igb_hw_control_acquire(hw);
1042
1043         /*
1044          * These parameters control the automatic generation (Tx) and
1045          * response (Rx) to Ethernet PAUSE frames.
1046          * - High water mark should allow for at least two standard size (1518)
1047          *   frames to be received after sending an XOFF.
1048          * - Low water mark works best when it is very near the high water mark.
1049          *   This allows the receiver to restart by sending XON when it has
1050          *   drained a bit. Here we use an arbitrary value of 1500 which will
1051          *   restart after one full frame is pulled from the buffer. There
1052          *   could be several smaller frames in the buffer and if so they will
1053          *   not trigger the XON until their total number reduces the buffer
1054          *   by 1500.
1055          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1056          */
1057         rx_buf_size = igb_get_rx_buffer_size(hw);
1058
1059         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1060         hw->fc.low_water = hw->fc.high_water - 1500;
1061         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1062         hw->fc.send_xon = 1;
1063
1064         /* Set Flow control, use the tunable location if sane */
1065         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1066                 hw->fc.requested_mode = igb_fc_setting;
1067         else
1068                 hw->fc.requested_mode = e1000_fc_none;
1069
1070         /* Issue a global reset */
1071         igb_pf_reset_hw(hw);
1072         E1000_WRITE_REG(hw, E1000_WUC, 0);
1073
1074         diag = e1000_init_hw(hw);
1075         if (diag < 0)
1076                 return (diag);
1077
1078         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1079         e1000_get_phy_info(hw);
1080         e1000_check_for_link(hw);
1081
1082         return (0);
1083 }
1084
1085 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1086 static void
1087 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1088 {
1089         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1090         struct e1000_hw_stats *stats =
1091                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1092         int pause_frames;
1093
1094         if(hw->phy.media_type == e1000_media_type_copper ||
1095             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1096                 stats->symerrs +=
1097                     E1000_READ_REG(hw,E1000_SYMERRS);
1098                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1099         }
1100
1101         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1102         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1103         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1104         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1105
1106         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1107         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1108         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1109         stats->dc += E1000_READ_REG(hw, E1000_DC);
1110         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1111         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1112         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1113         /*
1114         ** For watchdog management we need to know if we have been
1115         ** paused during the last interval, so capture that here.
1116         */
1117         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1118         stats->xoffrxc += pause_frames;
1119         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1120         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1121         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1122         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1123         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1124         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1125         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1126         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1127         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1128         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1129         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1130         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1131
1132         /* For the 64-bit byte counters the low dword must be read first. */
1133         /* Both registers clear on the read of the high dword */
1134
1135         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1136         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1137         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1138         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1139
1140         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1141         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1142         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1143         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1144         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1145
1146         stats->tor += E1000_READ_REG(hw, E1000_TORH);
1147         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1148
1149         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1150         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1151         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1152         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1153         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1154         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1155         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1156         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1157         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1158         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1159
1160         /* Interrupt Counts */
1161
1162         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1163         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1164         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1165         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1166         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1167         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1168         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1169         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1170         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1171
1172         /* Host to Card Statistics */
1173
1174         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1175         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1176         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1177         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1178         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1179         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1180         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1181         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1182         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1183         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1184         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1185         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1186         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1187         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1188
1189         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1190         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1191         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1192         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1193         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1194         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1195
1196         if (rte_stats == NULL)
1197                 return;
1198
1199         /* Rx Errors */
1200         rte_stats->ibadcrc = stats->crcerrs;
1201         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1202         rte_stats->imissed = stats->mpc;
1203         rte_stats->ierrors = rte_stats->ibadcrc +
1204                              rte_stats->ibadlen +
1205                              rte_stats->imissed +
1206                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1207
1208         /* Tx Errors */
1209         rte_stats->oerrors = stats->ecol + stats->latecol;
1210
1211         /* XON/XOFF pause frames */
1212         rte_stats->tx_pause_xon  = stats->xontxc;
1213         rte_stats->rx_pause_xon  = stats->xonrxc;
1214         rte_stats->tx_pause_xoff = stats->xofftxc;
1215         rte_stats->rx_pause_xoff = stats->xoffrxc;
1216
1217         rte_stats->ipackets = stats->gprc;
1218         rte_stats->opackets = stats->gptc;
1219         rte_stats->ibytes   = stats->gorc;
1220         rte_stats->obytes   = stats->gotc;
1221 }
1222
1223 static void
1224 eth_igb_stats_reset(struct rte_eth_dev *dev)
1225 {
1226         struct e1000_hw_stats *hw_stats =
1227                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1228
1229         /* HW registers are cleared on read */
1230         eth_igb_stats_get(dev, NULL);
1231
1232         /* Reset software totals */
1233         memset(hw_stats, 0, sizeof(*hw_stats));
1234 }
1235
1236 static void
1237 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1238 {
1239         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1240         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1241                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1242
1243         /* Good Rx packets, include VF loopback */
1244         UPDATE_VF_STAT(E1000_VFGPRC,
1245             hw_stats->last_gprc, hw_stats->gprc);
1246
1247         /* Good Rx octets, include VF loopback */
1248         UPDATE_VF_STAT(E1000_VFGORC,
1249             hw_stats->last_gorc, hw_stats->gorc);
1250
1251         /* Good Tx packets, include VF loopback */
1252         UPDATE_VF_STAT(E1000_VFGPTC,
1253             hw_stats->last_gptc, hw_stats->gptc);
1254
1255         /* Good Tx octets, include VF loopback */
1256         UPDATE_VF_STAT(E1000_VFGOTC,
1257             hw_stats->last_gotc, hw_stats->gotc);
1258
1259         /* Rx Multicst packets */
1260         UPDATE_VF_STAT(E1000_VFMPRC,
1261             hw_stats->last_mprc, hw_stats->mprc);
1262
1263         /* Good Rx loopback packets */
1264         UPDATE_VF_STAT(E1000_VFGPRLBC,
1265             hw_stats->last_gprlbc, hw_stats->gprlbc);
1266
1267         /* Good Rx loopback octets */
1268         UPDATE_VF_STAT(E1000_VFGORLBC,
1269             hw_stats->last_gorlbc, hw_stats->gorlbc);
1270
1271         /* Good Tx loopback packets */
1272         UPDATE_VF_STAT(E1000_VFGPTLBC,
1273             hw_stats->last_gptlbc, hw_stats->gptlbc);
1274
1275         /* Good Tx loopback octets */
1276         UPDATE_VF_STAT(E1000_VFGOTLBC,
1277             hw_stats->last_gotlbc, hw_stats->gotlbc);
1278
1279         if (rte_stats == NULL)
1280                 return;
1281
1282         rte_stats->ipackets = hw_stats->gprc;
1283         rte_stats->ibytes = hw_stats->gorc;
1284         rte_stats->opackets = hw_stats->gptc;
1285         rte_stats->obytes = hw_stats->gotc;
1286         rte_stats->imcasts = hw_stats->mprc;
1287         rte_stats->ilbpackets = hw_stats->gprlbc;
1288         rte_stats->ilbbytes = hw_stats->gorlbc;
1289         rte_stats->olbpackets = hw_stats->gptlbc;
1290         rte_stats->olbbytes = hw_stats->gotlbc;
1291
1292 }
1293
1294 static void
1295 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1296 {
1297         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1298                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1299
1300         /* Sync HW register to the last stats */
1301         eth_igbvf_stats_get(dev, NULL);
1302
1303         /* reset HW current stats*/
1304         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1305                offsetof(struct e1000_vf_stats, gprc));
1306
1307 }
1308
1309 static void
1310 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1311 {
1312         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1313
1314         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1315         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1316         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1317         dev_info->rx_offload_capa =
1318                 DEV_RX_OFFLOAD_VLAN_STRIP |
1319                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1320                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1321                 DEV_RX_OFFLOAD_TCP_CKSUM;
1322         dev_info->tx_offload_capa =
1323                 DEV_TX_OFFLOAD_VLAN_INSERT |
1324                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1325                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1326                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1327                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1328
1329         switch (hw->mac.type) {
1330         case e1000_82575:
1331                 dev_info->max_rx_queues = 4;
1332                 dev_info->max_tx_queues = 4;
1333                 dev_info->max_vmdq_pools = 0;
1334                 break;
1335
1336         case e1000_82576:
1337                 dev_info->max_rx_queues = 16;
1338                 dev_info->max_tx_queues = 16;
1339                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1340                 dev_info->vmdq_queue_num = 16;
1341                 break;
1342
1343         case e1000_82580:
1344                 dev_info->max_rx_queues = 8;
1345                 dev_info->max_tx_queues = 8;
1346                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1347                 dev_info->vmdq_queue_num = 8;
1348                 break;
1349
1350         case e1000_i350:
1351                 dev_info->max_rx_queues = 8;
1352                 dev_info->max_tx_queues = 8;
1353                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1354                 dev_info->vmdq_queue_num = 8;
1355                 break;
1356
1357         case e1000_i354:
1358                 dev_info->max_rx_queues = 8;
1359                 dev_info->max_tx_queues = 8;
1360                 break;
1361
1362         case e1000_i210:
1363                 dev_info->max_rx_queues = 4;
1364                 dev_info->max_tx_queues = 4;
1365                 dev_info->max_vmdq_pools = 0;
1366                 break;
1367
1368         case e1000_i211:
1369                 dev_info->max_rx_queues = 2;
1370                 dev_info->max_tx_queues = 2;
1371                 dev_info->max_vmdq_pools = 0;
1372                 break;
1373
1374         default:
1375                 /* Should not happen */
1376                 break;
1377         }
1378         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1379         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1380
1381         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1382                 .rx_thresh = {
1383                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1384                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1385                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1386                 },
1387                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1388                 .rx_drop_en = 0,
1389         };
1390
1391         dev_info->default_txconf = (struct rte_eth_txconf) {
1392                 .tx_thresh = {
1393                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1394                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1395                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1396                 },
1397                 .txq_flags = 0,
1398         };
1399 }
1400
1401 static void
1402 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1403 {
1404         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1405
1406         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1407         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1408         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1409         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1410                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1411                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1412                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1413         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1414                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1415                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1416                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1417                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1418         switch (hw->mac.type) {
1419         case e1000_vfadapt:
1420                 dev_info->max_rx_queues = 2;
1421                 dev_info->max_tx_queues = 2;
1422                 break;
1423         case e1000_vfadapt_i350:
1424                 dev_info->max_rx_queues = 1;
1425                 dev_info->max_tx_queues = 1;
1426                 break;
1427         default:
1428                 /* Should not happen */
1429                 break;
1430         }
1431
1432         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1433                 .rx_thresh = {
1434                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1435                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1436                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1437                 },
1438                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1439                 .rx_drop_en = 0,
1440         };
1441
1442         dev_info->default_txconf = (struct rte_eth_txconf) {
1443                 .tx_thresh = {
1444                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1445                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1446                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1447                 },
1448                 .txq_flags = 0,
1449         };
1450 }
1451
1452 /* return 0 means link status changed, -1 means not changed */
1453 static int
1454 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1455 {
1456         struct e1000_hw *hw =
1457                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1458         struct rte_eth_link link, old;
1459         int link_check, count;
1460
1461         link_check = 0;
1462         hw->mac.get_link_status = 1;
1463
1464         /* possible wait-to-complete in up to 9 seconds */
1465         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1466                 /* Read the real link status */
1467                 switch (hw->phy.media_type) {
1468                 case e1000_media_type_copper:
1469                         /* Do the work to read phy */
1470                         e1000_check_for_link(hw);
1471                         link_check = !hw->mac.get_link_status;
1472                         break;
1473
1474                 case e1000_media_type_fiber:
1475                         e1000_check_for_link(hw);
1476                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1477                                       E1000_STATUS_LU);
1478                         break;
1479
1480                 case e1000_media_type_internal_serdes:
1481                         e1000_check_for_link(hw);
1482                         link_check = hw->mac.serdes_has_link;
1483                         break;
1484
1485                 /* VF device is type_unknown */
1486                 case e1000_media_type_unknown:
1487                         eth_igbvf_link_update(hw);
1488                         link_check = !hw->mac.get_link_status;
1489                         break;
1490
1491                 default:
1492                         break;
1493                 }
1494                 if (link_check || wait_to_complete == 0)
1495                         break;
1496                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1497         }
1498         memset(&link, 0, sizeof(link));
1499         rte_igb_dev_atomic_read_link_status(dev, &link);
1500         old = link;
1501
1502         /* Now we check if a transition has happened */
1503         if (link_check) {
1504                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1505                                           &link.link_duplex);
1506                 link.link_status = 1;
1507         } else if (!link_check) {
1508                 link.link_speed = 0;
1509                 link.link_duplex = 0;
1510                 link.link_status = 0;
1511         }
1512         rte_igb_dev_atomic_write_link_status(dev, &link);
1513
1514         /* not changed */
1515         if (old.link_status == link.link_status)
1516                 return -1;
1517
1518         /* changed */
1519         return 0;
1520 }
1521
1522 /*
1523  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1524  * For ASF and Pass Through versions of f/w this means
1525  * that the driver is loaded.
1526  */
1527 static void
1528 igb_hw_control_acquire(struct e1000_hw *hw)
1529 {
1530         uint32_t ctrl_ext;
1531
1532         /* Let firmware know the driver has taken over */
1533         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1534         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1535 }
1536
1537 /*
1538  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1539  * For ASF and Pass Through versions of f/w this means that the
1540  * driver is no longer loaded.
1541  */
1542 static void
1543 igb_hw_control_release(struct e1000_hw *hw)
1544 {
1545         uint32_t ctrl_ext;
1546
1547         /* Let firmware taken over control of h/w */
1548         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1549         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1550                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1551 }
1552
1553 /*
1554  * Bit of a misnomer, what this really means is
1555  * to enable OS management of the system... aka
1556  * to disable special hardware management features.
1557  */
1558 static void
1559 igb_init_manageability(struct e1000_hw *hw)
1560 {
1561         if (e1000_enable_mng_pass_thru(hw)) {
1562                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1563                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1564
1565                 /* disable hardware interception of ARP */
1566                 manc &= ~(E1000_MANC_ARP_EN);
1567
1568                 /* enable receiving management packets to the host */
1569                 manc |= E1000_MANC_EN_MNG2HOST;
1570                 manc2h |= 1 << 5;  /* Mng Port 623 */
1571                 manc2h |= 1 << 6;  /* Mng Port 664 */
1572                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1573                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1574         }
1575 }
1576
1577 static void
1578 igb_release_manageability(struct e1000_hw *hw)
1579 {
1580         if (e1000_enable_mng_pass_thru(hw)) {
1581                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1582
1583                 manc |= E1000_MANC_ARP_EN;
1584                 manc &= ~E1000_MANC_EN_MNG2HOST;
1585
1586                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1587         }
1588 }
1589
1590 static void
1591 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1592 {
1593         struct e1000_hw *hw =
1594                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595         uint32_t rctl;
1596
1597         rctl = E1000_READ_REG(hw, E1000_RCTL);
1598         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1599         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1600 }
1601
1602 static void
1603 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1604 {
1605         struct e1000_hw *hw =
1606                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1607         uint32_t rctl;
1608
1609         rctl = E1000_READ_REG(hw, E1000_RCTL);
1610         rctl &= (~E1000_RCTL_UPE);
1611         if (dev->data->all_multicast == 1)
1612                 rctl |= E1000_RCTL_MPE;
1613         else
1614                 rctl &= (~E1000_RCTL_MPE);
1615         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1616 }
1617
1618 static void
1619 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1620 {
1621         struct e1000_hw *hw =
1622                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623         uint32_t rctl;
1624
1625         rctl = E1000_READ_REG(hw, E1000_RCTL);
1626         rctl |= E1000_RCTL_MPE;
1627         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1628 }
1629
1630 static void
1631 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1632 {
1633         struct e1000_hw *hw =
1634                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1635         uint32_t rctl;
1636
1637         if (dev->data->promiscuous == 1)
1638                 return; /* must remain in all_multicast mode */
1639         rctl = E1000_READ_REG(hw, E1000_RCTL);
1640         rctl &= (~E1000_RCTL_MPE);
1641         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1642 }
1643
1644 static int
1645 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1646 {
1647         struct e1000_hw *hw =
1648                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1649         struct e1000_vfta * shadow_vfta =
1650                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1651         uint32_t vfta;
1652         uint32_t vid_idx;
1653         uint32_t vid_bit;
1654
1655         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1656                               E1000_VFTA_ENTRY_MASK);
1657         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1658         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1659         if (on)
1660                 vfta |= vid_bit;
1661         else
1662                 vfta &= ~vid_bit;
1663         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1664
1665         /* update local VFTA copy */
1666         shadow_vfta->vfta[vid_idx] = vfta;
1667
1668         return 0;
1669 }
1670
1671 static void
1672 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1673 {
1674         struct e1000_hw *hw =
1675                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1676         uint32_t reg = ETHER_TYPE_VLAN ;
1677
1678         reg |= (tpid << 16);
1679         E1000_WRITE_REG(hw, E1000_VET, reg);
1680 }
1681
1682 static void
1683 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1684 {
1685         struct e1000_hw *hw =
1686                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687         uint32_t reg;
1688
1689         /* Filter Table Disable */
1690         reg = E1000_READ_REG(hw, E1000_RCTL);
1691         reg &= ~E1000_RCTL_CFIEN;
1692         reg &= ~E1000_RCTL_VFE;
1693         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1694 }
1695
1696 static void
1697 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1698 {
1699         struct e1000_hw *hw =
1700                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1701         struct e1000_vfta * shadow_vfta =
1702                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1703         uint32_t reg;
1704         int i;
1705
1706         /* Filter Table Enable, CFI not used for packet acceptance */
1707         reg = E1000_READ_REG(hw, E1000_RCTL);
1708         reg &= ~E1000_RCTL_CFIEN;
1709         reg |= E1000_RCTL_VFE;
1710         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1711
1712         /* restore VFTA table */
1713         for (i = 0; i < IGB_VFTA_SIZE; i++)
1714                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1715 }
1716
1717 static void
1718 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1719 {
1720         struct e1000_hw *hw =
1721                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1722         uint32_t reg;
1723
1724         /* VLAN Mode Disable */
1725         reg = E1000_READ_REG(hw, E1000_CTRL);
1726         reg &= ~E1000_CTRL_VME;
1727         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1728 }
1729
1730 static void
1731 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1732 {
1733         struct e1000_hw *hw =
1734                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1735         uint32_t reg;
1736
1737         /* VLAN Mode Enable */
1738         reg = E1000_READ_REG(hw, E1000_CTRL);
1739         reg |= E1000_CTRL_VME;
1740         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1741 }
1742
1743 static void
1744 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1745 {
1746         struct e1000_hw *hw =
1747                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1748         uint32_t reg;
1749
1750         /* CTRL_EXT: Extended VLAN */
1751         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1752         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1753         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1754
1755         /* Update maximum packet length */
1756         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1757                 E1000_WRITE_REG(hw, E1000_RLPML,
1758                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1759                                                 VLAN_TAG_SIZE);
1760 }
1761
1762 static void
1763 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1764 {
1765         struct e1000_hw *hw =
1766                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1767         uint32_t reg;
1768
1769         /* CTRL_EXT: Extended VLAN */
1770         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1771         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1772         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1773
1774         /* Update maximum packet length */
1775         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1776                 E1000_WRITE_REG(hw, E1000_RLPML,
1777                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1778                                                 2 * VLAN_TAG_SIZE);
1779 }
1780
1781 static void
1782 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1783 {
1784         if(mask & ETH_VLAN_STRIP_MASK){
1785                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1786                         igb_vlan_hw_strip_enable(dev);
1787                 else
1788                         igb_vlan_hw_strip_disable(dev);
1789         }
1790
1791         if(mask & ETH_VLAN_FILTER_MASK){
1792                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1793                         igb_vlan_hw_filter_enable(dev);
1794                 else
1795                         igb_vlan_hw_filter_disable(dev);
1796         }
1797
1798         if(mask & ETH_VLAN_EXTEND_MASK){
1799                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1800                         igb_vlan_hw_extend_enable(dev);
1801                 else
1802                         igb_vlan_hw_extend_disable(dev);
1803         }
1804 }
1805
1806
1807 /**
1808  * It enables the interrupt mask and then enable the interrupt.
1809  *
1810  * @param dev
1811  *  Pointer to struct rte_eth_dev.
1812  *
1813  * @return
1814  *  - On success, zero.
1815  *  - On failure, a negative value.
1816  */
1817 static int
1818 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1819 {
1820         struct e1000_interrupt *intr =
1821                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1822
1823         intr->mask |= E1000_ICR_LSC;
1824
1825         return 0;
1826 }
1827
1828 /*
1829  * It reads ICR and gets interrupt causes, check it and set a bit flag
1830  * to update link status.
1831  *
1832  * @param dev
1833  *  Pointer to struct rte_eth_dev.
1834  *
1835  * @return
1836  *  - On success, zero.
1837  *  - On failure, a negative value.
1838  */
1839 static int
1840 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1841 {
1842         uint32_t icr;
1843         struct e1000_hw *hw =
1844                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct e1000_interrupt *intr =
1846                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1847
1848         igb_intr_disable(hw);
1849
1850         /* read-on-clear nic registers here */
1851         icr = E1000_READ_REG(hw, E1000_ICR);
1852
1853         intr->flags = 0;
1854         if (icr & E1000_ICR_LSC) {
1855                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1856         }
1857
1858         if (icr & E1000_ICR_VMMB)
1859                 intr->flags |= E1000_FLAG_MAILBOX;
1860
1861         return 0;
1862 }
1863
1864 /*
1865  * It executes link_update after knowing an interrupt is prsent.
1866  *
1867  * @param dev
1868  *  Pointer to struct rte_eth_dev.
1869  *
1870  * @return
1871  *  - On success, zero.
1872  *  - On failure, a negative value.
1873  */
1874 static int
1875 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1876 {
1877         struct e1000_hw *hw =
1878                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879         struct e1000_interrupt *intr =
1880                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1881         uint32_t tctl, rctl;
1882         struct rte_eth_link link;
1883         int ret;
1884
1885         if (intr->flags & E1000_FLAG_MAILBOX) {
1886                 igb_pf_mbx_process(dev);
1887                 intr->flags &= ~E1000_FLAG_MAILBOX;
1888         }
1889
1890         igb_intr_enable(dev);
1891         rte_intr_enable(&(dev->pci_dev->intr_handle));
1892
1893         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1894                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1895
1896                 /* set get_link_status to check register later */
1897                 hw->mac.get_link_status = 1;
1898                 ret = eth_igb_link_update(dev, 0);
1899
1900                 /* check if link has changed */
1901                 if (ret < 0)
1902                         return 0;
1903
1904                 memset(&link, 0, sizeof(link));
1905                 rte_igb_dev_atomic_read_link_status(dev, &link);
1906                 if (link.link_status) {
1907                         PMD_INIT_LOG(INFO,
1908                                      " Port %d: Link Up - speed %u Mbps - %s",
1909                                      dev->data->port_id,
1910                                      (unsigned)link.link_speed,
1911                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1912                                      "full-duplex" : "half-duplex");
1913                 } else {
1914                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
1915                                      dev->data->port_id);
1916                 }
1917                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1918                              dev->pci_dev->addr.domain,
1919                              dev->pci_dev->addr.bus,
1920                              dev->pci_dev->addr.devid,
1921                              dev->pci_dev->addr.function);
1922                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1923                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1924                 if (link.link_status) {
1925                         /* enable Tx/Rx */
1926                         tctl |= E1000_TCTL_EN;
1927                         rctl |= E1000_RCTL_EN;
1928                 } else {
1929                         /* disable Tx/Rx */
1930                         tctl &= ~E1000_TCTL_EN;
1931                         rctl &= ~E1000_RCTL_EN;
1932                 }
1933                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1934                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1935                 E1000_WRITE_FLUSH(hw);
1936                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1937         }
1938
1939         return 0;
1940 }
1941
1942 /**
1943  * Interrupt handler which shall be registered at first.
1944  *
1945  * @param handle
1946  *  Pointer to interrupt handle.
1947  * @param param
1948  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1949  *
1950  * @return
1951  *  void
1952  */
1953 static void
1954 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1955                                                         void *param)
1956 {
1957         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1958
1959         eth_igb_interrupt_get_status(dev);
1960         eth_igb_interrupt_action(dev);
1961 }
1962
1963 static int
1964 eth_igb_led_on(struct rte_eth_dev *dev)
1965 {
1966         struct e1000_hw *hw;
1967
1968         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1969         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1970 }
1971
1972 static int
1973 eth_igb_led_off(struct rte_eth_dev *dev)
1974 {
1975         struct e1000_hw *hw;
1976
1977         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1978         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1979 }
1980
1981 static int
1982 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1983 {
1984         struct e1000_hw *hw;
1985         uint32_t ctrl;
1986         int tx_pause;
1987         int rx_pause;
1988
1989         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1990         fc_conf->pause_time = hw->fc.pause_time;
1991         fc_conf->high_water = hw->fc.high_water;
1992         fc_conf->low_water = hw->fc.low_water;
1993         fc_conf->send_xon = hw->fc.send_xon;
1994         fc_conf->autoneg = hw->mac.autoneg;
1995
1996         /*
1997          * Return rx_pause and tx_pause status according to actual setting of
1998          * the TFCE and RFCE bits in the CTRL register.
1999          */
2000         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2001         if (ctrl & E1000_CTRL_TFCE)
2002                 tx_pause = 1;
2003         else
2004                 tx_pause = 0;
2005
2006         if (ctrl & E1000_CTRL_RFCE)
2007                 rx_pause = 1;
2008         else
2009                 rx_pause = 0;
2010
2011         if (rx_pause && tx_pause)
2012                 fc_conf->mode = RTE_FC_FULL;
2013         else if (rx_pause)
2014                 fc_conf->mode = RTE_FC_RX_PAUSE;
2015         else if (tx_pause)
2016                 fc_conf->mode = RTE_FC_TX_PAUSE;
2017         else
2018                 fc_conf->mode = RTE_FC_NONE;
2019
2020         return 0;
2021 }
2022
2023 static int
2024 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2025 {
2026         struct e1000_hw *hw;
2027         int err;
2028         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2029                 e1000_fc_none,
2030                 e1000_fc_rx_pause,
2031                 e1000_fc_tx_pause,
2032                 e1000_fc_full
2033         };
2034         uint32_t rx_buf_size;
2035         uint32_t max_high_water;
2036         uint32_t rctl;
2037
2038         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2039         if (fc_conf->autoneg != hw->mac.autoneg)
2040                 return -ENOTSUP;
2041         rx_buf_size = igb_get_rx_buffer_size(hw);
2042         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2043
2044         /* At least reserve one Ethernet frame for watermark */
2045         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2046         if ((fc_conf->high_water > max_high_water) ||
2047             (fc_conf->high_water < fc_conf->low_water)) {
2048                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2049                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2050                 return (-EINVAL);
2051         }
2052
2053         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2054         hw->fc.pause_time     = fc_conf->pause_time;
2055         hw->fc.high_water     = fc_conf->high_water;
2056         hw->fc.low_water      = fc_conf->low_water;
2057         hw->fc.send_xon       = fc_conf->send_xon;
2058
2059         err = e1000_setup_link_generic(hw);
2060         if (err == E1000_SUCCESS) {
2061
2062                 /* check if we want to forward MAC frames - driver doesn't have native
2063                  * capability to do that, so we'll write the registers ourselves */
2064
2065                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2066
2067                 /* set or clear MFLCN.PMCF bit depending on configuration */
2068                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2069                         rctl |= E1000_RCTL_PMCF;
2070                 else
2071                         rctl &= ~E1000_RCTL_PMCF;
2072
2073                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2074                 E1000_WRITE_FLUSH(hw);
2075
2076                 return 0;
2077         }
2078
2079         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2080         return (-EIO);
2081 }
2082
2083 #define E1000_RAH_POOLSEL_SHIFT      (18)
2084 static void
2085 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2086                 uint32_t index, __rte_unused uint32_t pool)
2087 {
2088         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2089         uint32_t rah;
2090
2091         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2092         rah = E1000_READ_REG(hw, E1000_RAH(index));
2093         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2094         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2095 }
2096
2097 static void
2098 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2099 {
2100         uint8_t addr[ETHER_ADDR_LEN];
2101         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2102
2103         memset(addr, 0, sizeof(addr));
2104
2105         e1000_rar_set(hw, addr, index);
2106 }
2107
2108 /*
2109  * Virtual Function operations
2110  */
2111 static void
2112 igbvf_intr_disable(struct e1000_hw *hw)
2113 {
2114         PMD_INIT_FUNC_TRACE();
2115
2116         /* Clear interrupt mask to stop from interrupts being generated */
2117         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2118
2119         E1000_WRITE_FLUSH(hw);
2120 }
2121
2122 static void
2123 igbvf_stop_adapter(struct rte_eth_dev *dev)
2124 {
2125         u32 reg_val;
2126         u16 i;
2127         struct rte_eth_dev_info dev_info;
2128         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2129
2130         memset(&dev_info, 0, sizeof(dev_info));
2131         eth_igbvf_infos_get(dev, &dev_info);
2132
2133         /* Clear interrupt mask to stop from interrupts being generated */
2134         igbvf_intr_disable(hw);
2135
2136         /* Clear any pending interrupts, flush previous writes */
2137         E1000_READ_REG(hw, E1000_EICR);
2138
2139         /* Disable the transmit unit.  Each queue must be disabled. */
2140         for (i = 0; i < dev_info.max_tx_queues; i++)
2141                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2142
2143         /* Disable the receive unit by stopping each queue */
2144         for (i = 0; i < dev_info.max_rx_queues; i++) {
2145                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2146                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2147                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2148                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2149                         ;
2150         }
2151
2152         /* flush all queues disables */
2153         E1000_WRITE_FLUSH(hw);
2154         msec_delay(2);
2155 }
2156
2157 static int eth_igbvf_link_update(struct e1000_hw *hw)
2158 {
2159         struct e1000_mbx_info *mbx = &hw->mbx;
2160         struct e1000_mac_info *mac = &hw->mac;
2161         int ret_val = E1000_SUCCESS;
2162
2163         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2164
2165         /*
2166          * We only want to run this if there has been a rst asserted.
2167          * in this case that could mean a link change, device reset,
2168          * or a virtual function reset
2169          */
2170
2171         /* If we were hit with a reset or timeout drop the link */
2172         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2173                 mac->get_link_status = TRUE;
2174
2175         if (!mac->get_link_status)
2176                 goto out;
2177
2178         /* if link status is down no point in checking to see if pf is up */
2179         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2180                 goto out;
2181
2182         /* if we passed all the tests above then the link is up and we no
2183          * longer need to check for link */
2184         mac->get_link_status = FALSE;
2185
2186 out:
2187         return ret_val;
2188 }
2189
2190
2191 static int
2192 igbvf_dev_configure(struct rte_eth_dev *dev)
2193 {
2194         struct rte_eth_conf* conf = &dev->data->dev_conf;
2195
2196         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2197                      dev->data->port_id);
2198
2199         /*
2200          * VF has no ability to enable/disable HW CRC
2201          * Keep the persistent behavior the same as Host PF
2202          */
2203 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2204         if (!conf->rxmode.hw_strip_crc) {
2205                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2206                 conf->rxmode.hw_strip_crc = 1;
2207         }
2208 #else
2209         if (conf->rxmode.hw_strip_crc) {
2210                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2211                 conf->rxmode.hw_strip_crc = 0;
2212         }
2213 #endif
2214
2215         return 0;
2216 }
2217
2218 static int
2219 igbvf_dev_start(struct rte_eth_dev *dev)
2220 {
2221         struct e1000_hw *hw =
2222                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2223         int ret;
2224
2225         PMD_INIT_FUNC_TRACE();
2226
2227         hw->mac.ops.reset_hw(hw);
2228
2229         /* Set all vfta */
2230         igbvf_set_vfta_all(dev,1);
2231
2232         eth_igbvf_tx_init(dev);
2233
2234         /* This can fail when allocating mbufs for descriptor rings */
2235         ret = eth_igbvf_rx_init(dev);
2236         if (ret) {
2237                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2238                 igb_dev_clear_queues(dev);
2239                 return ret;
2240         }
2241
2242         return 0;
2243 }
2244
2245 static void
2246 igbvf_dev_stop(struct rte_eth_dev *dev)
2247 {
2248         PMD_INIT_FUNC_TRACE();
2249
2250         igbvf_stop_adapter(dev);
2251
2252         /*
2253           * Clear what we set, but we still keep shadow_vfta to
2254           * restore after device starts
2255           */
2256         igbvf_set_vfta_all(dev,0);
2257
2258         igb_dev_clear_queues(dev);
2259 }
2260
2261 static void
2262 igbvf_dev_close(struct rte_eth_dev *dev)
2263 {
2264         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2265
2266         PMD_INIT_FUNC_TRACE();
2267
2268         e1000_reset_hw(hw);
2269
2270         igbvf_dev_stop(dev);
2271 }
2272
2273 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2274 {
2275         struct e1000_mbx_info *mbx = &hw->mbx;
2276         uint32_t msgbuf[2];
2277
2278         /* After set vlan, vlan strip will also be enabled in igb driver*/
2279         msgbuf[0] = E1000_VF_SET_VLAN;
2280         msgbuf[1] = vid;
2281         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2282         if (on)
2283                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2284
2285         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2286 }
2287
2288 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2289 {
2290         struct e1000_hw *hw =
2291                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2292         struct e1000_vfta * shadow_vfta =
2293                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2294         int i = 0, j = 0, vfta = 0, mask = 1;
2295
2296         for (i = 0; i < IGB_VFTA_SIZE; i++){
2297                 vfta = shadow_vfta->vfta[i];
2298                 if(vfta){
2299                         mask = 1;
2300                         for (j = 0; j < 32; j++){
2301                                 if(vfta & mask)
2302                                         igbvf_set_vfta(hw,
2303                                                 (uint16_t)((i<<5)+j), on);
2304                                 mask<<=1;
2305                         }
2306                 }
2307         }
2308
2309 }
2310
2311 static int
2312 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2313 {
2314         struct e1000_hw *hw =
2315                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316         struct e1000_vfta * shadow_vfta =
2317                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2318         uint32_t vid_idx = 0;
2319         uint32_t vid_bit = 0;
2320         int ret = 0;
2321
2322         PMD_INIT_FUNC_TRACE();
2323
2324         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2325         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2326         if(ret){
2327                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2328                 return ret;
2329         }
2330         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2331         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2332
2333         /*Save what we set and retore it after device reset*/
2334         if (on)
2335                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2336         else
2337                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2338
2339         return 0;
2340 }
2341
2342 static int
2343 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2344                         struct rte_eth_rss_reta_entry64 *reta_conf,
2345                         uint16_t reta_size)
2346 {
2347         uint8_t i, j, mask;
2348         uint32_t reta, r;
2349         uint16_t idx, shift;
2350         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2351
2352         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2353                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2354                         "(%d) doesn't match the number hardware can supported "
2355                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2356                 return -EINVAL;
2357         }
2358
2359         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2360                 idx = i / RTE_RETA_GROUP_SIZE;
2361                 shift = i % RTE_RETA_GROUP_SIZE;
2362                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2363                                                 IGB_4_BIT_MASK);
2364                 if (!mask)
2365                         continue;
2366                 if (mask == IGB_4_BIT_MASK)
2367                         r = 0;
2368                 else
2369                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2370                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2371                         if (mask & (0x1 << j))
2372                                 reta |= reta_conf[idx].reta[shift + j] <<
2373                                                         (CHAR_BIT * j);
2374                         else
2375                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2376                 }
2377                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2378         }
2379
2380         return 0;
2381 }
2382
2383 static int
2384 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2385                        struct rte_eth_rss_reta_entry64 *reta_conf,
2386                        uint16_t reta_size)
2387 {
2388         uint8_t i, j, mask;
2389         uint32_t reta;
2390         uint16_t idx, shift;
2391         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392
2393         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2394                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2395                         "(%d) doesn't match the number hardware can supported "
2396                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2397                 return -EINVAL;
2398         }
2399
2400         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2401                 idx = i / RTE_RETA_GROUP_SIZE;
2402                 shift = i % RTE_RETA_GROUP_SIZE;
2403                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2404                                                 IGB_4_BIT_MASK);
2405                 if (!mask)
2406                         continue;
2407                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2408                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2409                         if (mask & (0x1 << j))
2410                                 reta_conf[idx].reta[shift + j] =
2411                                         ((reta >> (CHAR_BIT * j)) &
2412                                                 IGB_8_BIT_MASK);
2413                 }
2414         }
2415
2416         return 0;
2417 }
2418
2419 #define MAC_TYPE_FILTER_SUP(type)    do {\
2420         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2421                 (type) != e1000_82576)\
2422                 return -ENOTSUP;\
2423 } while (0)
2424
2425 static int
2426 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2427                         struct rte_eth_syn_filter *filter,
2428                         bool add)
2429 {
2430         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2431         uint32_t synqf, rfctl;
2432
2433         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2434                 return -EINVAL;
2435
2436         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2437
2438         if (add) {
2439                 if (synqf & E1000_SYN_FILTER_ENABLE)
2440                         return -EINVAL;
2441
2442                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2443                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2444
2445                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2446                 if (filter->hig_pri)
2447                         rfctl |= E1000_RFCTL_SYNQFP;
2448                 else
2449                         rfctl &= ~E1000_RFCTL_SYNQFP;
2450
2451                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2452         } else {
2453                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2454                         return -ENOENT;
2455                 synqf = 0;
2456         }
2457
2458         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2459         E1000_WRITE_FLUSH(hw);
2460         return 0;
2461 }
2462
2463 static int
2464 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
2465                         struct rte_eth_syn_filter *filter)
2466 {
2467         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2468         uint32_t synqf, rfctl;
2469
2470         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2471         if (synqf & E1000_SYN_FILTER_ENABLE) {
2472                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2473                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2474                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2475                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2476                 return 0;
2477         }
2478
2479         return -ENOENT;
2480 }
2481
2482 static int
2483 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
2484                         enum rte_filter_op filter_op,
2485                         void *arg)
2486 {
2487         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2488         int ret;
2489
2490         MAC_TYPE_FILTER_SUP(hw->mac.type);
2491
2492         if (filter_op == RTE_ETH_FILTER_NOP)
2493                 return 0;
2494
2495         if (arg == NULL) {
2496                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2497                             filter_op);
2498                 return -EINVAL;
2499         }
2500
2501         switch (filter_op) {
2502         case RTE_ETH_FILTER_ADD:
2503                 ret = eth_igb_syn_filter_set(dev,
2504                                 (struct rte_eth_syn_filter *)arg,
2505                                 TRUE);
2506                 break;
2507         case RTE_ETH_FILTER_DELETE:
2508                 ret = eth_igb_syn_filter_set(dev,
2509                                 (struct rte_eth_syn_filter *)arg,
2510                                 FALSE);
2511                 break;
2512         case RTE_ETH_FILTER_GET:
2513                 ret = eth_igb_syn_filter_get(dev,
2514                                 (struct rte_eth_syn_filter *)arg);
2515                 break;
2516         default:
2517                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
2518                 ret = -EINVAL;
2519                 break;
2520         }
2521
2522         return ret;
2523 }
2524
2525 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2526         if ((type) != e1000_82580 && (type) != e1000_i350)\
2527                 return -ENOSYS; \
2528 } while (0)
2529
2530 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
2531 static inline int
2532 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
2533                         struct e1000_2tuple_filter_info *filter_info)
2534 {
2535         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2536                 return -EINVAL;
2537         if (filter->priority > E1000_2TUPLE_MAX_PRI)
2538                 return -EINVAL;  /* filter index is out of range. */
2539         if (filter->tcp_flags > TCP_FLAG_ALL)
2540                 return -EINVAL;  /* flags is invalid. */
2541
2542         switch (filter->dst_port_mask) {
2543         case UINT16_MAX:
2544                 filter_info->dst_port_mask = 0;
2545                 filter_info->dst_port = filter->dst_port;
2546                 break;
2547         case 0:
2548                 filter_info->dst_port_mask = 1;
2549                 break;
2550         default:
2551                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2552                 return -EINVAL;
2553         }
2554
2555         switch (filter->proto_mask) {
2556         case UINT8_MAX:
2557                 filter_info->proto_mask = 0;
2558                 filter_info->proto = filter->proto;
2559                 break;
2560         case 0:
2561                 filter_info->proto_mask = 1;
2562                 break;
2563         default:
2564                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2565                 return -EINVAL;
2566         }
2567
2568         filter_info->priority = (uint8_t)filter->priority;
2569         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
2570                 filter_info->tcp_flags = filter->tcp_flags;
2571         else
2572                 filter_info->tcp_flags = 0;
2573
2574         return 0;
2575 }
2576
2577 static inline struct e1000_2tuple_filter *
2578 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
2579                         struct e1000_2tuple_filter_info *key)
2580 {
2581         struct e1000_2tuple_filter *it;
2582
2583         TAILQ_FOREACH(it, filter_list, entries) {
2584                 if (memcmp(key, &it->filter_info,
2585                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
2586                         return it;
2587                 }
2588         }
2589         return NULL;
2590 }
2591
2592 /*
2593  * igb_add_2tuple_filter - add a 2tuple filter
2594  *
2595  * @param
2596  * dev: Pointer to struct rte_eth_dev.
2597  * ntuple_filter: ponter to the filter that will be added.
2598  *
2599  * @return
2600  *    - On success, zero.
2601  *    - On failure, a negative value.
2602  */
2603 static int
2604 igb_add_2tuple_filter(struct rte_eth_dev *dev,
2605                         struct rte_eth_ntuple_filter *ntuple_filter)
2606 {
2607         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2608         struct e1000_filter_info *filter_info =
2609                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2610         struct e1000_2tuple_filter *filter;
2611         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
2612         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
2613         int i, ret;
2614
2615         filter = rte_zmalloc("e1000_2tuple_filter",
2616                         sizeof(struct e1000_2tuple_filter), 0);
2617         if (filter == NULL)
2618                 return -ENOMEM;
2619
2620         ret = ntuple_filter_to_2tuple(ntuple_filter,
2621                                       &filter->filter_info);
2622         if (ret < 0) {
2623                 rte_free(filter);
2624                 return ret;
2625         }
2626         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2627                                          &filter->filter_info) != NULL) {
2628                 PMD_DRV_LOG(ERR, "filter exists.");
2629                 rte_free(filter);
2630                 return -EEXIST;
2631         }
2632         filter->queue = ntuple_filter->queue;
2633
2634         /*
2635          * look for an unused 2tuple filter index,
2636          * and insert the filter to list.
2637          */
2638         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
2639                 if (!(filter_info->twotuple_mask & (1 << i))) {
2640                         filter_info->twotuple_mask |= 1 << i;
2641                         filter->index = i;
2642                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
2643                                           filter,
2644                                           entries);
2645                         break;
2646                 }
2647         }
2648         if (i >= E1000_MAX_TTQF_FILTERS) {
2649                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
2650                 rte_free(filter);
2651                 return -ENOSYS;
2652         }
2653
2654         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
2655         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
2656                 imir |= E1000_IMIR_PORT_BP;
2657         else
2658                 imir &= ~E1000_IMIR_PORT_BP;
2659
2660         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
2661
2662         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2663         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
2664         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
2665         if (filter->filter_info.proto_mask == 0)
2666                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2667
2668         /* tcp flags bits setting. */
2669         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
2670                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
2671                         imir_ext |= E1000_IMIREXT_CTRL_URG;
2672                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
2673                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
2674                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
2675                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
2676                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
2677                         imir_ext |= E1000_IMIREXT_CTRL_RST;
2678                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
2679                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
2680                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
2681                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
2682         } else
2683                 imir_ext |= E1000_IMIREXT_CTRL_BP;
2684         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
2685         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
2686         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
2687         return 0;
2688 }
2689
2690 /*
2691  * igb_remove_2tuple_filter - remove a 2tuple filter
2692  *
2693  * @param
2694  * dev: Pointer to struct rte_eth_dev.
2695  * ntuple_filter: ponter to the filter that will be removed.
2696  *
2697  * @return
2698  *    - On success, zero.
2699  *    - On failure, a negative value.
2700  */
2701 static int
2702 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2703                         struct rte_eth_ntuple_filter *ntuple_filter)
2704 {
2705         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2706         struct e1000_filter_info *filter_info =
2707                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2708         struct e1000_2tuple_filter_info filter_2tuple;
2709         struct e1000_2tuple_filter *filter;
2710         int ret;
2711
2712         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
2713         ret = ntuple_filter_to_2tuple(ntuple_filter,
2714                                       &filter_2tuple);
2715         if (ret < 0)
2716                 return ret;
2717
2718         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2719                                          &filter_2tuple);
2720         if (filter == NULL) {
2721                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2722                 return -ENOENT;
2723         }
2724
2725         filter_info->twotuple_mask &= ~(1 << filter->index);
2726         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
2727         rte_free(filter);
2728
2729         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
2730         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
2731         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
2732         return 0;
2733 }
2734
2735 static inline struct e1000_flex_filter *
2736 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
2737                         struct e1000_flex_filter_info *key)
2738 {
2739         struct e1000_flex_filter *it;
2740
2741         TAILQ_FOREACH(it, filter_list, entries) {
2742                 if (memcmp(key, &it->filter_info,
2743                         sizeof(struct e1000_flex_filter_info)) == 0)
2744                         return it;
2745         }
2746
2747         return NULL;
2748 }
2749
2750 static int
2751 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
2752                         struct rte_eth_flex_filter *filter,
2753                         bool add)
2754 {
2755         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2756         struct e1000_filter_info *filter_info =
2757                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2758         struct e1000_flex_filter *flex_filter, *it;
2759         uint32_t wufc, queueing, mask;
2760         uint32_t reg_off;
2761         uint8_t shift, i, j = 0;
2762
2763         flex_filter = rte_zmalloc("e1000_flex_filter",
2764                         sizeof(struct e1000_flex_filter), 0);
2765         if (flex_filter == NULL)
2766                 return -ENOMEM;
2767
2768         flex_filter->filter_info.len = filter->len;
2769         flex_filter->filter_info.priority = filter->priority;
2770         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
2771         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
2772                 mask = 0;
2773                 /* reverse bits in flex filter's mask*/
2774                 for (shift = 0; shift < CHAR_BIT; shift++) {
2775                         if (filter->mask[i] & (0x01 << shift))
2776                                 mask |= (0x80 >> shift);
2777                 }
2778                 flex_filter->filter_info.mask[i] = mask;
2779         }
2780
2781         wufc = E1000_READ_REG(hw, E1000_WUFC);
2782         if (flex_filter->index < E1000_MAX_FHFT)
2783                 reg_off = E1000_FHFT(flex_filter->index);
2784         else
2785                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
2786
2787         if (add) {
2788                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
2789                                 &flex_filter->filter_info) != NULL) {
2790                         PMD_DRV_LOG(ERR, "filter exists.");
2791                         rte_free(flex_filter);
2792                         return -EEXIST;
2793                 }
2794                 flex_filter->queue = filter->queue;
2795                 /*
2796                  * look for an unused flex filter index
2797                  * and insert the filter into the list.
2798                  */
2799                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
2800                         if (!(filter_info->flex_mask & (1 << i))) {
2801                                 filter_info->flex_mask |= 1 << i;
2802                                 flex_filter->index = i;
2803                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
2804                                         flex_filter,
2805                                         entries);
2806                                 break;
2807                         }
2808                 }
2809                 if (i >= E1000_MAX_FLEX_FILTERS) {
2810                         PMD_DRV_LOG(ERR, "flex filters are full.");
2811                         rte_free(flex_filter);
2812                         return -ENOSYS;
2813                 }
2814
2815                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
2816                                 (E1000_WUFC_FLX0 << flex_filter->index));
2817                 queueing = filter->len |
2818                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2819                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2820                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
2821                                 queueing);
2822                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
2823                         E1000_WRITE_REG(hw, reg_off,
2824                                         flex_filter->filter_info.dwords[j]);
2825                         reg_off += sizeof(uint32_t);
2826                         E1000_WRITE_REG(hw, reg_off,
2827                                         flex_filter->filter_info.dwords[++j]);
2828                         reg_off += sizeof(uint32_t);
2829                         E1000_WRITE_REG(hw, reg_off,
2830                                 (uint32_t)flex_filter->filter_info.mask[i]);
2831                         reg_off += sizeof(uint32_t) * 2;
2832                         ++j;
2833                 }
2834         } else {
2835                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2836                                 &flex_filter->filter_info);
2837                 if (it == NULL) {
2838                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
2839                         rte_free(flex_filter);
2840                         return -ENOENT;
2841                 }
2842
2843                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
2844                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
2845                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
2846                         (~(E1000_WUFC_FLX0 << it->index)));
2847
2848                 filter_info->flex_mask &= ~(1 << it->index);
2849                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
2850                 rte_free(it);
2851                 rte_free(flex_filter);
2852         }
2853
2854         return 0;
2855 }
2856
2857 static int
2858 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
2859                         struct rte_eth_flex_filter *filter)
2860 {
2861         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2862         struct e1000_filter_info *filter_info =
2863                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2864         struct e1000_flex_filter flex_filter, *it;
2865         uint32_t wufc, queueing, wufc_en = 0;
2866
2867         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
2868         flex_filter.filter_info.len = filter->len;
2869         flex_filter.filter_info.priority = filter->priority;
2870         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
2871         memcpy(flex_filter.filter_info.mask, filter->mask,
2872                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
2873
2874         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2875                                 &flex_filter.filter_info);
2876         if (it == NULL) {
2877                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2878                 return -ENOENT;
2879         }
2880
2881         wufc = E1000_READ_REG(hw, E1000_WUFC);
2882         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
2883
2884         if ((wufc & wufc_en) == wufc_en) {
2885                 uint32_t reg_off = 0;
2886                 if (it->index < E1000_MAX_FHFT)
2887                         reg_off = E1000_FHFT(it->index);
2888                 else
2889                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
2890
2891                 queueing = E1000_READ_REG(hw,
2892                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2893                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2894                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2895                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
2896                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2897                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2898                 return 0;
2899         }
2900         return -ENOENT;
2901 }
2902
2903 static int
2904 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
2905                         enum rte_filter_op filter_op,
2906                         void *arg)
2907 {
2908         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2909         struct rte_eth_flex_filter *filter;
2910         int ret = 0;
2911
2912         MAC_TYPE_FILTER_SUP(hw->mac.type);
2913
2914         if (filter_op == RTE_ETH_FILTER_NOP)
2915                 return ret;
2916
2917         if (arg == NULL) {
2918                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2919                             filter_op);
2920                 return -EINVAL;
2921         }
2922
2923         filter = (struct rte_eth_flex_filter *)arg;
2924         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
2925             || filter->len % sizeof(uint64_t) != 0) {
2926                 PMD_DRV_LOG(ERR, "filter's length is out of range");
2927                 return -EINVAL;
2928         }
2929         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
2930                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
2931                 return -EINVAL;
2932         }
2933
2934         switch (filter_op) {
2935         case RTE_ETH_FILTER_ADD:
2936                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
2937                 break;
2938         case RTE_ETH_FILTER_DELETE:
2939                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
2940                 break;
2941         case RTE_ETH_FILTER_GET:
2942                 ret = eth_igb_get_flex_filter(dev, filter);
2943                 break;
2944         default:
2945                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
2946                 ret = -EINVAL;
2947                 break;
2948         }
2949
2950         return ret;
2951 }
2952
2953 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
2954 static inline int
2955 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
2956                         struct e1000_5tuple_filter_info *filter_info)
2957 {
2958         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2959                 return -EINVAL;
2960         if (filter->priority > E1000_2TUPLE_MAX_PRI)
2961                 return -EINVAL;  /* filter index is out of range. */
2962         if (filter->tcp_flags > TCP_FLAG_ALL)
2963                 return -EINVAL;  /* flags is invalid. */
2964
2965         switch (filter->dst_ip_mask) {
2966         case UINT32_MAX:
2967                 filter_info->dst_ip_mask = 0;
2968                 filter_info->dst_ip = filter->dst_ip;
2969                 break;
2970         case 0:
2971                 filter_info->dst_ip_mask = 1;
2972                 break;
2973         default:
2974                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2975                 return -EINVAL;
2976         }
2977
2978         switch (filter->src_ip_mask) {
2979         case UINT32_MAX:
2980                 filter_info->src_ip_mask = 0;
2981                 filter_info->src_ip = filter->src_ip;
2982                 break;
2983         case 0:
2984                 filter_info->src_ip_mask = 1;
2985                 break;
2986         default:
2987                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2988                 return -EINVAL;
2989         }
2990
2991         switch (filter->dst_port_mask) {
2992         case UINT16_MAX:
2993                 filter_info->dst_port_mask = 0;
2994                 filter_info->dst_port = filter->dst_port;
2995                 break;
2996         case 0:
2997                 filter_info->dst_port_mask = 1;
2998                 break;
2999         default:
3000                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3001                 return -EINVAL;
3002         }
3003
3004         switch (filter->src_port_mask) {
3005         case UINT16_MAX:
3006                 filter_info->src_port_mask = 0;
3007                 filter_info->src_port = filter->src_port;
3008                 break;
3009         case 0:
3010                 filter_info->src_port_mask = 1;
3011                 break;
3012         default:
3013                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3014                 return -EINVAL;
3015         }
3016
3017         switch (filter->proto_mask) {
3018         case UINT8_MAX:
3019                 filter_info->proto_mask = 0;
3020                 filter_info->proto = filter->proto;
3021                 break;
3022         case 0:
3023                 filter_info->proto_mask = 1;
3024                 break;
3025         default:
3026                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3027                 return -EINVAL;
3028         }
3029
3030         filter_info->priority = (uint8_t)filter->priority;
3031         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3032                 filter_info->tcp_flags = filter->tcp_flags;
3033         else
3034                 filter_info->tcp_flags = 0;
3035
3036         return 0;
3037 }
3038
3039 static inline struct e1000_5tuple_filter *
3040 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3041                         struct e1000_5tuple_filter_info *key)
3042 {
3043         struct e1000_5tuple_filter *it;
3044
3045         TAILQ_FOREACH(it, filter_list, entries) {
3046                 if (memcmp(key, &it->filter_info,
3047                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3048                         return it;
3049                 }
3050         }
3051         return NULL;
3052 }
3053
3054 /*
3055  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3056  *
3057  * @param
3058  * dev: Pointer to struct rte_eth_dev.
3059  * ntuple_filter: ponter to the filter that will be added.
3060  *
3061  * @return
3062  *    - On success, zero.
3063  *    - On failure, a negative value.
3064  */
3065 static int
3066 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3067                         struct rte_eth_ntuple_filter *ntuple_filter)
3068 {
3069         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3070         struct e1000_filter_info *filter_info =
3071                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3072         struct e1000_5tuple_filter *filter;
3073         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3074         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3075         uint8_t i;
3076         int ret;
3077
3078         filter = rte_zmalloc("e1000_5tuple_filter",
3079                         sizeof(struct e1000_5tuple_filter), 0);
3080         if (filter == NULL)
3081                 return -ENOMEM;
3082
3083         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3084                                             &filter->filter_info);
3085         if (ret < 0) {
3086                 rte_free(filter);
3087                 return ret;
3088         }
3089
3090         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3091                                          &filter->filter_info) != NULL) {
3092                 PMD_DRV_LOG(ERR, "filter exists.");
3093                 rte_free(filter);
3094                 return -EEXIST;
3095         }
3096         filter->queue = ntuple_filter->queue;
3097
3098         /*
3099          * look for an unused 5tuple filter index,
3100          * and insert the filter to list.
3101          */
3102         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3103                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3104                         filter_info->fivetuple_mask |= 1 << i;
3105                         filter->index = i;
3106                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3107                                           filter,
3108                                           entries);
3109                         break;
3110                 }
3111         }
3112         if (i >= E1000_MAX_FTQF_FILTERS) {
3113                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3114                 rte_free(filter);
3115                 return -ENOSYS;
3116         }
3117
3118         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3119         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3120                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3121         if (filter->filter_info.dst_ip_mask == 0)
3122                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3123         if (filter->filter_info.src_port_mask == 0)
3124                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3125         if (filter->filter_info.proto_mask == 0)
3126                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3127         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3128                 E1000_FTQF_QUEUE_MASK;
3129         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3130         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3131         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3132         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3133
3134         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3135         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3136
3137         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3138         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3139                 imir |= E1000_IMIR_PORT_BP;
3140         else
3141                 imir &= ~E1000_IMIR_PORT_BP;
3142         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3143
3144         /* tcp flags bits setting. */
3145         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3146                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3147                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3148                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3149                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3150                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3151                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3152                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3153                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3154                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3155                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3156                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3157                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3158         } else
3159                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3160         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3161         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3162         return 0;
3163 }
3164
3165 /*
3166  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3167  *
3168  * @param
3169  * dev: Pointer to struct rte_eth_dev.
3170  * ntuple_filter: ponter to the filter that will be removed.
3171  *
3172  * @return
3173  *    - On success, zero.
3174  *    - On failure, a negative value.
3175  */
3176 static int
3177 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3178                                 struct rte_eth_ntuple_filter *ntuple_filter)
3179 {
3180         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3181         struct e1000_filter_info *filter_info =
3182                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3183         struct e1000_5tuple_filter_info filter_5tuple;
3184         struct e1000_5tuple_filter *filter;
3185         int ret;
3186
3187         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3188         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3189                                             &filter_5tuple);
3190         if (ret < 0)
3191                 return ret;
3192
3193         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3194                                          &filter_5tuple);
3195         if (filter == NULL) {
3196                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3197                 return -ENOENT;
3198         }
3199
3200         filter_info->fivetuple_mask &= ~(1 << filter->index);
3201         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3202         rte_free(filter);
3203
3204         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3205                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3206         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3207         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3208         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3209         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3210         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3211         return 0;
3212 }
3213
3214 static int
3215 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3216 {
3217         uint32_t rctl;
3218         struct e1000_hw *hw;
3219         struct rte_eth_dev_info dev_info;
3220         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3221                                      VLAN_TAG_SIZE);
3222
3223         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3224
3225 #ifdef RTE_LIBRTE_82571_SUPPORT
3226         /* XXX: not bigger than max_rx_pktlen */
3227         if (hw->mac.type == e1000_82571)
3228                 return -ENOTSUP;
3229 #endif
3230         eth_igb_infos_get(dev, &dev_info);
3231
3232         /* check that mtu is within the allowed range */
3233         if ((mtu < ETHER_MIN_MTU) ||
3234             (frame_size > dev_info.max_rx_pktlen))
3235                 return -EINVAL;
3236
3237         /* refuse mtu that requires the support of scattered packets when this
3238          * feature has not been enabled before. */
3239         if (!dev->data->scattered_rx &&
3240             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3241                 return -EINVAL;
3242
3243         rctl = E1000_READ_REG(hw, E1000_RCTL);
3244
3245         /* switch to jumbo mode if needed */
3246         if (frame_size > ETHER_MAX_LEN) {
3247                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3248                 rctl |= E1000_RCTL_LPE;
3249         } else {
3250                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3251                 rctl &= ~E1000_RCTL_LPE;
3252         }
3253         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3254
3255         /* update max frame size */
3256         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3257
3258         E1000_WRITE_REG(hw, E1000_RLPML,
3259                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3260
3261         return 0;
3262 }
3263
3264 /*
3265  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3266  *
3267  * @param
3268  * dev: Pointer to struct rte_eth_dev.
3269  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3270  * add: if true, add filter, if false, remove filter
3271  *
3272  * @return
3273  *    - On success, zero.
3274  *    - On failure, a negative value.
3275  */
3276 static int
3277 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3278                         struct rte_eth_ntuple_filter *ntuple_filter,
3279                         bool add)
3280 {
3281         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3282         int ret;
3283
3284         switch (ntuple_filter->flags) {
3285         case RTE_5TUPLE_FLAGS:
3286         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3287                 if (hw->mac.type != e1000_82576)
3288                         return -ENOTSUP;
3289                 if (add)
3290                         ret = igb_add_5tuple_filter_82576(dev,
3291                                                           ntuple_filter);
3292                 else
3293                         ret = igb_remove_5tuple_filter_82576(dev,
3294                                                              ntuple_filter);
3295                 break;
3296         case RTE_2TUPLE_FLAGS:
3297         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3298                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3299                         return -ENOTSUP;
3300                 if (add)
3301                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3302                 else
3303                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3304                 break;
3305         default:
3306                 ret = -EINVAL;
3307                 break;
3308         }
3309
3310         return ret;
3311 }
3312
3313 /*
3314  * igb_get_ntuple_filter - get a ntuple filter
3315  *
3316  * @param
3317  * dev: Pointer to struct rte_eth_dev.
3318  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3319  *
3320  * @return
3321  *    - On success, zero.
3322  *    - On failure, a negative value.
3323  */
3324 static int
3325 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3326                         struct rte_eth_ntuple_filter *ntuple_filter)
3327 {
3328         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3329         struct e1000_filter_info *filter_info =
3330                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3331         struct e1000_5tuple_filter_info filter_5tuple;
3332         struct e1000_2tuple_filter_info filter_2tuple;
3333         struct e1000_5tuple_filter *p_5tuple_filter;
3334         struct e1000_2tuple_filter *p_2tuple_filter;
3335         int ret;
3336
3337         switch (ntuple_filter->flags) {
3338         case RTE_5TUPLE_FLAGS:
3339         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3340                 if (hw->mac.type != e1000_82576)
3341                         return -ENOTSUP;
3342                 memset(&filter_5tuple,
3343                         0,
3344                         sizeof(struct e1000_5tuple_filter_info));
3345                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3346                                                     &filter_5tuple);
3347                 if (ret < 0)
3348                         return ret;
3349                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3350                                         &filter_info->fivetuple_list,
3351                                         &filter_5tuple);
3352                 if (p_5tuple_filter == NULL) {
3353                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3354                         return -ENOENT;
3355                 }
3356                 ntuple_filter->queue = p_5tuple_filter->queue;
3357                 break;
3358         case RTE_2TUPLE_FLAGS:
3359         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3360                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3361                         return -ENOTSUP;
3362                 memset(&filter_2tuple,
3363                         0,
3364                         sizeof(struct e1000_2tuple_filter_info));
3365                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3366                 if (ret < 0)
3367                         return ret;
3368                 p_2tuple_filter = igb_2tuple_filter_lookup(
3369                                         &filter_info->twotuple_list,
3370                                         &filter_2tuple);
3371                 if (p_2tuple_filter == NULL) {
3372                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3373                         return -ENOENT;
3374                 }
3375                 ntuple_filter->queue = p_2tuple_filter->queue;
3376                 break;
3377         default:
3378                 ret = -EINVAL;
3379                 break;
3380         }
3381
3382         return 0;
3383 }
3384
3385 /*
3386  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3387  * @dev: pointer to rte_eth_dev structure
3388  * @filter_op:operation will be taken.
3389  * @arg: a pointer to specific structure corresponding to the filter_op
3390  */
3391 static int
3392 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3393                                 enum rte_filter_op filter_op,
3394                                 void *arg)
3395 {
3396         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3397         int ret;
3398
3399         MAC_TYPE_FILTER_SUP(hw->mac.type);
3400
3401         if (filter_op == RTE_ETH_FILTER_NOP)
3402                 return 0;
3403
3404         if (arg == NULL) {
3405                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3406                             filter_op);
3407                 return -EINVAL;
3408         }
3409
3410         switch (filter_op) {
3411         case RTE_ETH_FILTER_ADD:
3412                 ret = igb_add_del_ntuple_filter(dev,
3413                         (struct rte_eth_ntuple_filter *)arg,
3414                         TRUE);
3415                 break;
3416         case RTE_ETH_FILTER_DELETE:
3417                 ret = igb_add_del_ntuple_filter(dev,
3418                         (struct rte_eth_ntuple_filter *)arg,
3419                         FALSE);
3420                 break;
3421         case RTE_ETH_FILTER_GET:
3422                 ret = igb_get_ntuple_filter(dev,
3423                         (struct rte_eth_ntuple_filter *)arg);
3424                 break;
3425         default:
3426                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3427                 ret = -EINVAL;
3428                 break;
3429         }
3430         return ret;
3431 }
3432
3433 static inline int
3434 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3435                         uint16_t ethertype)
3436 {
3437         int i;
3438
3439         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3440                 if (filter_info->ethertype_filters[i] == ethertype &&
3441                     (filter_info->ethertype_mask & (1 << i)))
3442                         return i;
3443         }
3444         return -1;
3445 }
3446
3447 static inline int
3448 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3449                         uint16_t ethertype)
3450 {
3451         int i;
3452
3453         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3454                 if (!(filter_info->ethertype_mask & (1 << i))) {
3455                         filter_info->ethertype_mask |= 1 << i;
3456                         filter_info->ethertype_filters[i] = ethertype;
3457                         return i;
3458                 }
3459         }
3460         return -1;
3461 }
3462
3463 static inline int
3464 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3465                         uint8_t idx)
3466 {
3467         if (idx >= E1000_MAX_ETQF_FILTERS)
3468                 return -1;
3469         filter_info->ethertype_mask &= ~(1 << idx);
3470         filter_info->ethertype_filters[idx] = 0;
3471         return idx;
3472 }
3473
3474
3475 static int
3476 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3477                         struct rte_eth_ethertype_filter *filter,
3478                         bool add)
3479 {
3480         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3481         struct e1000_filter_info *filter_info =
3482                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3483         uint32_t etqf = 0;
3484         int ret;
3485
3486         if (filter->ether_type == ETHER_TYPE_IPv4 ||
3487                 filter->ether_type == ETHER_TYPE_IPv6) {
3488                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3489                         " ethertype filter.", filter->ether_type);
3490                 return -EINVAL;
3491         }
3492
3493         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3494                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3495                 return -EINVAL;
3496         }
3497         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3498                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3499                 return -EINVAL;
3500         }
3501
3502         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3503         if (ret >= 0 && add) {
3504                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3505                             filter->ether_type);
3506                 return -EEXIST;
3507         }
3508         if (ret < 0 && !add) {
3509                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3510                             filter->ether_type);
3511                 return -ENOENT;
3512         }
3513
3514         if (add) {
3515                 ret = igb_ethertype_filter_insert(filter_info,
3516                         filter->ether_type);
3517                 if (ret < 0) {
3518                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
3519                         return -ENOSYS;
3520                 }
3521
3522                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
3523                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
3524                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
3525         } else {
3526                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
3527                 if (ret < 0)
3528                         return -ENOSYS;
3529         }
3530         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
3531         E1000_WRITE_FLUSH(hw);
3532
3533         return 0;
3534 }
3535
3536 static int
3537 igb_get_ethertype_filter(struct rte_eth_dev *dev,
3538                         struct rte_eth_ethertype_filter *filter)
3539 {
3540         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3541         struct e1000_filter_info *filter_info =
3542                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3543         uint32_t etqf;
3544         int ret;
3545
3546         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3547         if (ret < 0) {
3548                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3549                             filter->ether_type);
3550                 return -ENOENT;
3551         }
3552
3553         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
3554         if (etqf & E1000_ETQF_FILTER_ENABLE) {
3555                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
3556                 filter->flags = 0;
3557                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
3558                                 E1000_ETQF_QUEUE_SHIFT;
3559                 return 0;
3560         }
3561
3562         return -ENOENT;
3563 }
3564
3565 /*
3566  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
3567  * @dev: pointer to rte_eth_dev structure
3568  * @filter_op:operation will be taken.
3569  * @arg: a pointer to specific structure corresponding to the filter_op
3570  */
3571 static int
3572 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
3573                                 enum rte_filter_op filter_op,
3574                                 void *arg)
3575 {
3576         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3577         int ret;
3578
3579         MAC_TYPE_FILTER_SUP(hw->mac.type);
3580
3581         if (filter_op == RTE_ETH_FILTER_NOP)
3582                 return 0;
3583
3584         if (arg == NULL) {
3585                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3586                             filter_op);
3587                 return -EINVAL;
3588         }
3589
3590         switch (filter_op) {
3591         case RTE_ETH_FILTER_ADD:
3592                 ret = igb_add_del_ethertype_filter(dev,
3593                         (struct rte_eth_ethertype_filter *)arg,
3594                         TRUE);
3595                 break;
3596         case RTE_ETH_FILTER_DELETE:
3597                 ret = igb_add_del_ethertype_filter(dev,
3598                         (struct rte_eth_ethertype_filter *)arg,
3599                         FALSE);
3600                 break;
3601         case RTE_ETH_FILTER_GET:
3602                 ret = igb_get_ethertype_filter(dev,
3603                         (struct rte_eth_ethertype_filter *)arg);
3604                 break;
3605         default:
3606                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3607                 ret = -EINVAL;
3608                 break;
3609         }
3610         return ret;
3611 }
3612
3613 static int
3614 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
3615                      enum rte_filter_type filter_type,
3616                      enum rte_filter_op filter_op,
3617                      void *arg)
3618 {
3619         int ret = -EINVAL;
3620
3621         switch (filter_type) {
3622         case RTE_ETH_FILTER_NTUPLE:
3623                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
3624                 break;
3625         case RTE_ETH_FILTER_ETHERTYPE:
3626                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
3627                 break;
3628         case RTE_ETH_FILTER_SYN:
3629                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
3630                 break;
3631         case RTE_ETH_FILTER_FLEXIBLE:
3632                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
3633                 break;
3634         default:
3635                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3636                                                         filter_type);
3637                 break;
3638         }
3639
3640         return ret;
3641 }
3642
3643 static struct rte_driver pmd_igb_drv = {
3644         .type = PMD_PDEV,
3645         .init = rte_igb_pmd_init,
3646 };
3647
3648 static struct rte_driver pmd_igbvf_drv = {
3649         .type = PMD_PDEV,
3650         .init = rte_igbvf_pmd_init,
3651 };
3652
3653 PMD_REGISTER_DRIVER(pmd_igb_drv);
3654 PMD_REGISTER_DRIVER(pmd_igbvf_drv);