lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54
  55 #include "e1000_logs.h"
  56 #include "e1000/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 static int  eth_igb_configure(struct rte_eth_dev *dev);
  60 static int  eth_igb_start(struct rte_eth_dev *dev);
  61 static void eth_igb_stop(struct rte_eth_dev *dev);
  62 static void eth_igb_close(struct rte_eth_dev *dev);
  63 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  64 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  65 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  66 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  67 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  68                                 int wait_to_complete);
  69 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  70                                 struct rte_eth_stats *rte_stats);
  71 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  72 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  73                                 struct rte_eth_dev_info *dev_info);
  74 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  75                                 struct rte_eth_fc_conf *fc_conf);
  76 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  77 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  78 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  79 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  80                                                         void *param);
  81 static int  igb_hardware_init(struct e1000_hw *hw);
  82 static void igb_hw_control_acquire(struct e1000_hw *hw);
  83 static void igb_hw_control_release(struct e1000_hw *hw);
  84 static void igb_init_manageability(struct e1000_hw *hw);
  85 static void igb_release_manageability(struct e1000_hw *hw);
  86
  87 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  88                 uint16_t vlan_id, int on);
  89 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
  90 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  91
  92 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  93 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  94 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  95 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  96 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
  97 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
  98
  99 static int eth_igb_led_on(struct rte_eth_dev *dev);
 100 static int eth_igb_led_off(struct rte_eth_dev *dev);
 101
 102 static void igb_intr_disable(struct e1000_hw *hw);
 103 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 104 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 105                 struct ether_addr *mac_addr,
 106                 uint32_t index, uint32_t pool);
 107 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 108
 109 static void igbvf_intr_disable(struct e1000_hw *hw);
 110 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 111 static int igbvf_dev_start(struct rte_eth_dev *dev);
 112 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 113 static void igbvf_dev_close(struct rte_eth_dev *dev);
 114 static int eth_igbvf_link_update(struct e1000_hw *hw);
 115 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 116 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 117 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 118                 uint16_t vlan_id, int on);
 119 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 120 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 121 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 122                  struct rte_eth_rss_reta *reta_conf);
 123 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 124                 struct rte_eth_rss_reta *reta_conf);
 125
 126 /*
 127  * Define VF Stats MACRO for Non "cleared on read" register
 128  */
 129 #define UPDATE_VF_STAT(reg, last, cur)            \
 130 {                                                 \
 131         u32 latest = E1000_READ_REG(hw, reg);     \
 132         cur += latest - last;                     \
 133         last = latest;                            \
 134 }
 135
 136
 137 #define IGB_FC_PAUSE_TIME 0x0680
 138 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 139 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 140
 141 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 142
 143 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 144
 145 /*
 146  * The set of PCI devices this driver supports
 147  */
 148 static struct rte_pci_id pci_id_igb_map[] = {
 149
 150 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 151 #include "rte_pci_dev_ids.h"
 152
 153 {.device_id = 0},
 154 };
 155
 156 /*
 157  * The set of PCI devices this driver supports (for 82576&I350 VF)
 158  */
 159 static struct rte_pci_id pci_id_igbvf_map[] = {
 160
 161 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 162 #include "rte_pci_dev_ids.h"
 163
 164 {.device_id = 0},
 165 };
 166
 167 static struct eth_dev_ops eth_igb_ops = {
 168         .dev_configure        = eth_igb_configure,
 169         .dev_start            = eth_igb_start,
 170         .dev_stop             = eth_igb_stop,
 171         .dev_close            = eth_igb_close,
 172         .promiscuous_enable   = eth_igb_promiscuous_enable,
 173         .promiscuous_disable  = eth_igb_promiscuous_disable,
 174         .allmulticast_enable  = eth_igb_allmulticast_enable,
 175         .allmulticast_disable = eth_igb_allmulticast_disable,
 176         .link_update          = eth_igb_link_update,
 177         .stats_get            = eth_igb_stats_get,
 178         .stats_reset          = eth_igb_stats_reset,
 179         .dev_infos_get        = eth_igb_infos_get,
 180         .vlan_filter_set      = eth_igb_vlan_filter_set,
 181         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 182         .vlan_offload_set     = eth_igb_vlan_offload_set,
 183         .rx_queue_setup       = eth_igb_rx_queue_setup,
 184         .rx_queue_release     = eth_igb_rx_queue_release,
 185         .rx_queue_count       = eth_igb_rx_queue_count,
 186         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 187         .tx_queue_setup       = eth_igb_tx_queue_setup,
 188         .tx_queue_release     = eth_igb_tx_queue_release,
 189         .dev_led_on           = eth_igb_led_on,
 190         .dev_led_off          = eth_igb_led_off,
 191         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 192         .mac_addr_add         = eth_igb_rar_set,
 193         .mac_addr_remove      = eth_igb_rar_clear,
 194         .reta_update          = eth_igb_rss_reta_update,
 195         .reta_query           = eth_igb_rss_reta_query,
 196 };
 197
 198 /*
 199  * dev_ops for virtual function, bare necessities for basic vf
 200  * operation have been implemented
 201  */
 202 static struct eth_dev_ops igbvf_eth_dev_ops = {
 203         .dev_configure        = igbvf_dev_configure,
 204         .dev_start            = igbvf_dev_start,
 205         .dev_stop             = igbvf_dev_stop,
 206         .dev_close            = igbvf_dev_close,
 207         .link_update          = eth_igb_link_update,
 208         .stats_get            = eth_igbvf_stats_get,
 209         .stats_reset          = eth_igbvf_stats_reset,
 210         .vlan_filter_set      = igbvf_vlan_filter_set,
 211         .dev_infos_get        = eth_igb_infos_get,
 212         .rx_queue_setup       = eth_igb_rx_queue_setup,
 213         .rx_queue_release     = eth_igb_rx_queue_release,
 214         .tx_queue_setup       = eth_igb_tx_queue_setup,
 215         .tx_queue_release     = eth_igb_tx_queue_release,
 216 };
 217
 218 /**
 219  * Atomically reads the link status information from global
 220  * structure rte_eth_dev.
 221  *
 222  * @param dev
 223  *   - Pointer to the structure rte_eth_dev to read from.
 224  *   - Pointer to the buffer to be saved with the link status.
 225  *
 226  * @return
 227  *   - On success, zero.
 228  *   - On failure, negative value.
 229  */
 230 static inline int
 231 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 232                                 struct rte_eth_link *link)
 233 {
 234         struct rte_eth_link *dst = link;
 235         struct rte_eth_link *src = &(dev->data->dev_link);
 236
 237         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 238                                         *(uint64_t *)src) == 0)
 239                 return -1;
 240
 241         return 0;
 242 }
 243
 244 /**
 245  * Atomically writes the link status information into global
 246  * structure rte_eth_dev.
 247  *
 248  * @param dev
 249  *   - Pointer to the structure rte_eth_dev to read from.
 250  *   - Pointer to the buffer to be saved with the link status.
 251  *
 252  * @return
 253  *   - On success, zero.
 254  *   - On failure, negative value.
 255  */
 256 static inline int
 257 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 258                                 struct rte_eth_link *link)
 259 {
 260         struct rte_eth_link *dst = &(dev->data->dev_link);
 261         struct rte_eth_link *src = link;
 262
 263         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 264                                         *(uint64_t *)src) == 0)
 265                 return -1;
 266
 267         return 0;
 268 }
 269
 270 static inline void
 271 igb_intr_enable(struct rte_eth_dev *dev)
 272 {
 273         struct e1000_interrupt *intr =
 274                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 275         struct e1000_hw *hw =
 276                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 277
 278         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 279         E1000_WRITE_FLUSH(hw);
 280 }
 281
 282 static void
 283 igb_intr_disable(struct e1000_hw *hw)
 284 {
 285         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 286         E1000_WRITE_FLUSH(hw);
 287 }
 288
 289 static inline int32_t
 290 igb_pf_reset_hw(struct e1000_hw *hw)
 291 {
 292         uint32_t ctrl_ext;
 293         int32_t status;
 294
 295         status = e1000_reset_hw(hw);
 296
 297         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 298         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 299         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 300         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 301         E1000_WRITE_FLUSH(hw);
 302
 303         return status;
 304 }
 305
 306 static void
 307 igb_identify_hardware(struct rte_eth_dev *dev)
 308 {
 309         struct e1000_hw *hw =
 310                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 311
 312         hw->vendor_id = dev->pci_dev->id.vendor_id;
 313         hw->device_id = dev->pci_dev->id.device_id;
 314         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 315         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 316
 317         e1000_set_mac_type(hw);
 318
 319         /* need to check if it is a vf device below */
 320 }
 321
 322 static int
 323 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 324                    struct rte_eth_dev *eth_dev)
 325 {
 326         int error = 0;
 327         struct rte_pci_device *pci_dev;
 328         struct e1000_hw *hw =
 329                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 330         struct e1000_vfta * shadow_vfta =
 331                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 332         uint32_t ctrl_ext;
 333
 334         pci_dev = eth_dev->pci_dev;
 335         eth_dev->dev_ops = &eth_igb_ops;
 336         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 337         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 338
 339         /* for secondary processes, we don't initialise any further as primary
 340          * has already done this work. Only check we don't need a different
 341          * RX function */
 342         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 343                 if (eth_dev->data->scattered_rx)
 344                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 345                 return 0;
 346         }
 347
 348         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 349
 350         igb_identify_hardware(eth_dev);
 351         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 352                 error = -EIO;
 353                 goto err_late;
 354         }
 355
 356         e1000_get_bus_info(hw);
 357
 358         hw->mac.autoneg = 1;
 359         hw->phy.autoneg_wait_to_complete = 0;
 360         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 361
 362         /* Copper options */
 363         if (hw->phy.media_type == e1000_media_type_copper) {
 364                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 365                 hw->phy.disable_polarity_correction = 0;
 366                 hw->phy.ms_type = e1000_ms_hw_default;
 367         }
 368
 369         /*
 370          * Start from a known state, this is important in reading the nvm
 371          * and mac from that.
 372          */
 373         igb_pf_reset_hw(hw);
 374
 375         /* Make sure we have a good EEPROM before we read from it */
 376         if (e1000_validate_nvm_checksum(hw) < 0) {
 377                 /*
 378                  * Some PCI-E parts fail the first check due to
 379                  * the link being in sleep state, call it again,
 380                  * if it fails a second time its a real issue.
 381                  */
 382                 if (e1000_validate_nvm_checksum(hw) < 0) {
 383                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 384                         error = -EIO;
 385                         goto err_late;
 386                 }
 387         }
 388
 389         /* Read the permanent MAC address out of the EEPROM */
 390         if (e1000_read_mac_addr(hw) != 0) {
 391                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 392                 error = -EIO;
 393                 goto err_late;
 394         }
 395
 396         /* Allocate memory for storing MAC addresses */
 397         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 398                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 399         if (eth_dev->data->mac_addrs == NULL) {
 400                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 401                                                 "store MAC addresses",
 402                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 403                 error = -ENOMEM;
 404                 goto err_late;
 405         }
 406
 407         /* Copy the permanent MAC address */
 408         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 409
 410         /* initialize the vfta */
 411         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 412
 413         /* Now initialize the hardware */
 414         if (igb_hardware_init(hw) != 0) {
 415                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 416                 rte_free(eth_dev->data->mac_addrs);
 417                 eth_dev->data->mac_addrs = NULL;
 418                 error = -ENODEV;
 419                 goto err_late;
 420         }
 421         hw->mac.get_link_status = 1;
 422
 423         /* Indicate SOL/IDER usage */
 424         if (e1000_check_reset_block(hw) < 0) {
 425                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 426                                         "SOL/IDER session");
 427         }
 428
 429         /* initialize PF if max_vfs not zero */
 430         igb_pf_host_init(eth_dev);
 431
 432         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 433         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 434         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 435         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 436         E1000_WRITE_FLUSH(hw);
 437
 438         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 439                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 440                      pci_dev->id.device_id);
 441
 442         rte_intr_callback_register(&(pci_dev->intr_handle),
 443                 eth_igb_interrupt_handler, (void *)eth_dev);
 444
 445         /* enable uio intr after callback register */
 446         rte_intr_enable(&(pci_dev->intr_handle));
 447
 448         /* enable support intr */
 449         igb_intr_enable(eth_dev);
 450
 451         return 0;
 452
 453 err_late:
 454         igb_hw_control_release(hw);
 455
 456         return (error);
 457 }
 458
 459 /*
 460  * Virtual Function device init
 461  */
 462 static int
 463 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 464                 struct rte_eth_dev *eth_dev)
 465 {
 466         struct rte_pci_device *pci_dev;
 467         struct e1000_hw *hw =
 468                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 469         int diag;
 470
 471         PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 472
 473         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 474         pci_dev = eth_dev->pci_dev;
 475
 476         hw->device_id = pci_dev->id.device_id;
 477         hw->vendor_id = pci_dev->id.vendor_id;
 478         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 479
 480         /* Initialize the shared code */
 481         diag = e1000_setup_init_funcs(hw, TRUE);
 482         if (diag != 0) {
 483                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 484                         diag);
 485                 return -EIO;
 486         }
 487
 488         /* init_mailbox_params */
 489         hw->mbx.ops.init_params(hw);
 490
 491         /* Disable the interrupts for VF */
 492         igbvf_intr_disable(hw);
 493
 494         diag = hw->mac.ops.reset_hw(hw);
 495
 496         /* Allocate memory for storing MAC addresses */
 497         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 498                 hw->mac.rar_entry_count, 0);
 499         if (eth_dev->data->mac_addrs == NULL) {
 500                 PMD_INIT_LOG(ERR,
 501                         "Failed to allocate %d bytes needed to store MAC "
 502                         "addresses",
 503                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 504                 return -ENOMEM;
 505         }
 506
 507         /* Copy the permanent MAC address */
 508         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 509                         &eth_dev->data->mac_addrs[0]);
 510
 511         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
 512                         "mac.type=%s\n",
 513                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 514                         pci_dev->id.device_id,
 515                         "igb_mac_82576_vf");
 516
 517         return 0;
 518 }
 519
 520 static struct eth_driver rte_igb_pmd = {
 521         {
 522                 .name = "rte_igb_pmd",
 523                 .id_table = pci_id_igb_map,
 524 #ifdef RTE_EAL_UNBIND_PORTS
 525                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 526 #endif
 527         },
 528         .eth_dev_init = eth_igb_dev_init,
 529         .dev_private_size = sizeof(struct e1000_adapter),
 530 };
 531
 532 /*
 533  * virtual function driver struct
 534  */
 535 static struct eth_driver rte_igbvf_pmd = {
 536         {
 537                 .name = "rte_igbvf_pmd",
 538                 .id_table = pci_id_igbvf_map,
 539 #ifdef RTE_EAL_UNBIND_PORTS
 540                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 541 #endif
 542         },
 543         .eth_dev_init = eth_igbvf_dev_init,
 544         .dev_private_size = sizeof(struct e1000_adapter),
 545 };
 546
 547 int
 548 rte_igb_pmd_init(void)
 549 {
 550         rte_eth_driver_register(&rte_igb_pmd);
 551         return 0;
 552 }
 553
 554 /*
 555  * VF Driver initialization routine.
 556  * Invoked one at EAL init time.
 557  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 558  */
 559 int
 560 rte_igbvf_pmd_init(void)
 561 {
 562         DEBUGFUNC("rte_igbvf_pmd_init");
 563
 564         rte_eth_driver_register(&rte_igbvf_pmd);
 565         return (0);
 566 }
 567
 568 static int
 569 eth_igb_configure(struct rte_eth_dev *dev)
 570 {
 571         struct e1000_interrupt *intr =
 572                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 573
 574         PMD_INIT_LOG(DEBUG, ">>");
 575
 576         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 577
 578         PMD_INIT_LOG(DEBUG, "<<");
 579
 580         return (0);
 581 }
 582
 583 static int
 584 eth_igb_start(struct rte_eth_dev *dev)
 585 {
 586         struct e1000_hw *hw =
 587                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 588         int ret, i, mask;
 589         uint32_t ctrl_ext;
 590
 591         PMD_INIT_LOG(DEBUG, ">>");
 592
 593         /* Power up the phy. Needed to make the link go Up */
 594         e1000_power_up_phy(hw);
 595
 596         /*
 597          * Packet Buffer Allocation (PBA)
 598          * Writing PBA sets the receive portion of the buffer
 599          * the remainder is used for the transmit buffer.
 600          */
 601         if (hw->mac.type == e1000_82575) {
 602                 uint32_t pba;
 603
 604                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 605                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 606         }
 607
 608         /* Put the address into the Receive Address Array */
 609         e1000_rar_set(hw, hw->mac.addr, 0);
 610
 611         /* Initialize the hardware */
 612         if (igb_hardware_init(hw)) {
 613                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 614                 return (-EIO);
 615         }
 616
 617         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 618
 619         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 620         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 621         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 622         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 623         E1000_WRITE_FLUSH(hw);
 624
 625         /* configure PF module if SRIOV enabled */
 626         igb_pf_host_configure(dev);
 627
 628         /* Configure for OS presence */
 629         igb_init_manageability(hw);
 630
 631         eth_igb_tx_init(dev);
 632
 633         /* This can fail when allocating mbufs for descriptor rings */
 634         ret = eth_igb_rx_init(dev);
 635         if (ret) {
 636                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 637                 igb_dev_clear_queues(dev);
 638                 return ret;
 639         }
 640
 641         e1000_clear_hw_cntrs_base_generic(hw);
 642
 643         /*
 644          * VLAN Offload Settings
 645          */
 646         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 647                         ETH_VLAN_EXTEND_MASK;
 648         eth_igb_vlan_offload_set(dev, mask);
 649
 650         /*
 651          * Configure the Interrupt Moderation register (EITR) with the maximum
 652          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 653          * spurious [DMA] memory updates of RX and TX ring descriptors.
 654          *
 655          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 656          * spurious memory updates per second should be expected.
 657          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 658          *
 659          * Because interrupts are not used at all, the MSI-X is not activated
 660          * and interrupt moderation is controlled by EITR[0].
 661          *
 662          * Note that having [almost] disabled memory updates of RX and TX ring
 663          * descriptors through the Interrupt Moderation mechanism, memory
 664          * updates of ring descriptors are now moderated by the configurable
 665          * value of Write-Back Threshold registers.
 666          */
 667         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 668                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 669                 uint32_t ivar;
 670
 671                 /* Enable all RX & TX queues in the IVAR registers */
 672                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 673                 for (i = 0; i < 8; i++)
 674                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 675
 676                 /* Configure EITR with the maximum possible value (0xFFFF) */
 677                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 678         }
 679
 680         /* Setup link speed and duplex */
 681         switch (dev->data->dev_conf.link_speed) {
 682         case ETH_LINK_SPEED_AUTONEG:
 683                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 684                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 685                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 686                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 687                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 688                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 689                 else
 690                         goto error_invalid_config;
 691                 break;
 692         case ETH_LINK_SPEED_10:
 693                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 694                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 695                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 696                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 697                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 698                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 699                 else
 700                         goto error_invalid_config;
 701                 break;
 702         case ETH_LINK_SPEED_100:
 703                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 704                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 705                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 706                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 707                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 708                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 709                 else
 710                         goto error_invalid_config;
 711                 break;
 712         case ETH_LINK_SPEED_1000:
 713                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 714                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 715                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 716                 else
 717                         goto error_invalid_config;
 718                 break;
 719         case ETH_LINK_SPEED_10000:
 720         default:
 721                 goto error_invalid_config;
 722         }
 723         e1000_setup_link(hw);
 724
 725         /* check if lsc interrupt feature is enabled */
 726         if (dev->data->dev_conf.intr_conf.lsc != 0)
 727                 ret = eth_igb_lsc_interrupt_setup(dev);
 728
 729         /* resume enabled intr since hw reset */
 730         igb_intr_enable(dev);
 731
 732         PMD_INIT_LOG(DEBUG, "<<");
 733
 734         return (0);
 735
 736 error_invalid_config:
 737         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 738                         dev->data->dev_conf.link_speed,
 739                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 740         igb_dev_clear_queues(dev);
 741         return (-EINVAL);
 742 }
 743
 744 /*********************************************************************
 745  *
 746  *  This routine disables all traffic on the adapter by issuing a
 747  *  global reset on the MAC.
 748  *
 749  **********************************************************************/
 750 static void
 751 eth_igb_stop(struct rte_eth_dev *dev)
 752 {
 753         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 754         struct rte_eth_link link;
 755
 756         igb_intr_disable(hw);
 757         igb_pf_reset_hw(hw);
 758         E1000_WRITE_REG(hw, E1000_WUC, 0);
 759
 760         /* Set bit for Go Link disconnect */
 761         if (hw->mac.type >= e1000_82580) {
 762                 uint32_t phpm_reg;
 763
 764                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 765                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 766                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 767         }
 768
 769         /* Power down the phy. Needed to make the link go Down */
 770         e1000_power_down_phy(hw);
 771
 772         igb_dev_clear_queues(dev);
 773
 774         /* clear the recorded link status */
 775         memset(&link, 0, sizeof(link));
 776         rte_igb_dev_atomic_write_link_status(dev, &link);
 777 }
 778
 779 static void
 780 eth_igb_close(struct rte_eth_dev *dev)
 781 {
 782         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 783         struct rte_eth_link link;
 784
 785         eth_igb_stop(dev);
 786         e1000_phy_hw_reset(hw);
 787         igb_release_manageability(hw);
 788         igb_hw_control_release(hw);
 789
 790         /* Clear bit for Go Link disconnect */
 791         if (hw->mac.type >= e1000_82580) {
 792                 uint32_t phpm_reg;
 793
 794                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 795                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
 796                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 797         }
 798
 799         igb_dev_clear_queues(dev);
 800
 801         memset(&link, 0, sizeof(link));
 802         rte_igb_dev_atomic_write_link_status(dev, &link);
 803 }
 804
 805 static int
 806 igb_get_rx_buffer_size(struct e1000_hw *hw)
 807 {
 808         uint32_t rx_buf_size;
 809         if (hw->mac.type == e1000_82576) {
 810                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 811         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 812                 /* PBS needs to be translated according to a lookup table */
 813                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 814                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 815                 rx_buf_size = (rx_buf_size << 10);
 816         } else if (hw->mac.type == e1000_i210) {
 817                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 818         } else {
 819                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 820         }
 821
 822         return rx_buf_size;
 823 }
 824
 825 /*********************************************************************
 826  *
 827  *  Initialize the hardware
 828  *
 829  **********************************************************************/
 830 static int
 831 igb_hardware_init(struct e1000_hw *hw)
 832 {
 833         uint32_t rx_buf_size;
 834         int diag;
 835
 836         /* Let the firmware know the OS is in control */
 837         igb_hw_control_acquire(hw);
 838
 839         /*
 840          * These parameters control the automatic generation (Tx) and
 841          * response (Rx) to Ethernet PAUSE frames.
 842          * - High water mark should allow for at least two standard size (1518)
 843          *   frames to be received after sending an XOFF.
 844          * - Low water mark works best when it is very near the high water mark.
 845          *   This allows the receiver to restart by sending XON when it has
 846          *   drained a bit. Here we use an arbitary value of 1500 which will
 847          *   restart after one full frame is pulled from the buffer. There
 848          *   could be several smaller frames in the buffer and if so they will
 849          *   not trigger the XON until their total number reduces the buffer
 850          *   by 1500.
 851          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 852          */
 853         rx_buf_size = igb_get_rx_buffer_size(hw);
 854
 855         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
 856         hw->fc.low_water = hw->fc.high_water - 1500;
 857         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
 858         hw->fc.send_xon = 1;
 859
 860         /* Set Flow control, use the tunable location if sane */
 861         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
 862                 hw->fc.requested_mode = igb_fc_setting;
 863         else
 864                 hw->fc.requested_mode = e1000_fc_none;
 865
 866         /* Issue a global reset */
 867         igb_pf_reset_hw(hw);
 868         E1000_WRITE_REG(hw, E1000_WUC, 0);
 869
 870         diag = e1000_init_hw(hw);
 871         if (diag < 0)
 872                 return (diag);
 873
 874         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 875         e1000_get_phy_info(hw);
 876         e1000_check_for_link(hw);
 877
 878         return (0);
 879 }
 880
 881 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
 882 static void
 883 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 884 {
 885         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 886         struct e1000_hw_stats *stats =
 887                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 888         int pause_frames;
 889
 890         if(hw->phy.media_type == e1000_media_type_copper ||
 891             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 892                 stats->symerrs +=
 893                     E1000_READ_REG(hw,E1000_SYMERRS);
 894                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 895         }
 896
 897         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 898         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 899         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 900         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 901
 902         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 903         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 904         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 905         stats->dc += E1000_READ_REG(hw, E1000_DC);
 906         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 907         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 908         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 909         /*
 910         ** For watchdog management we need to know if we have been
 911         ** paused during the last interval, so capture that here.
 912         */
 913         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 914         stats->xoffrxc += pause_frames;
 915         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 916         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 917         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 918         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 919         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 920         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 921         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 922         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 923         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 924         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 925         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 926         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 927
 928         /* For the 64-bit byte counters the low dword must be read first. */
 929         /* Both registers clear on the read of the high dword */
 930
 931         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 932         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 933         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 934         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 935
 936         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 937         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 938         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 939         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 940         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 941
 942         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 943         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 944
 945         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 946         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 947         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 948         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 949         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 950         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 951         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 952         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 953         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 954         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 955
 956         /* Interrupt Counts */
 957
 958         stats->iac += E1000_READ_REG(hw, E1000_IAC);
 959         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 960         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 961         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 962         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 963         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 964         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 965         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 966         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 967
 968         /* Host to Card Statistics */
 969
 970         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
 971         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
 972         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
 973         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
 974         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
 975         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
 976         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
 977         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
 978         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
 979         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
 980         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
 981         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
 982         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
 983         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
 984
 985         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 986         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 987         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 988         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 989         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 990         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 991
 992         if (rte_stats == NULL)
 993                 return;
 994
 995         /* Rx Errors */
 996         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 997             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 998
 999         /* Tx Errors */
1000         rte_stats->oerrors = stats->ecol + stats->latecol;
1001
1002         rte_stats->ipackets = stats->gprc;
1003         rte_stats->opackets = stats->gptc;
1004         rte_stats->ibytes   = stats->gorc;
1005         rte_stats->obytes   = stats->gotc;
1006 }
1007
1008 static void
1009 eth_igb_stats_reset(struct rte_eth_dev *dev)
1010 {
1011         struct e1000_hw_stats *hw_stats =
1012                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1013
1014         /* HW registers are cleared on read */
1015         eth_igb_stats_get(dev, NULL);
1016
1017         /* Reset software totals */
1018         memset(hw_stats, 0, sizeof(*hw_stats));
1019 }
1020
1021 static void
1022 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1023 {
1024         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1025         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1026                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1027
1028         /* Good Rx packets, include VF loopback */
1029         UPDATE_VF_STAT(E1000_VFGPRC,
1030             hw_stats->last_gprc, hw_stats->gprc);
1031
1032         /* Good Rx octets, include VF loopback */
1033         UPDATE_VF_STAT(E1000_VFGORC,
1034             hw_stats->last_gorc, hw_stats->gorc);
1035
1036         /* Good Tx packets, include VF loopback */
1037         UPDATE_VF_STAT(E1000_VFGPTC,
1038             hw_stats->last_gptc, hw_stats->gptc);
1039
1040         /* Good Tx octets, include VF loopback */
1041         UPDATE_VF_STAT(E1000_VFGOTC,
1042             hw_stats->last_gotc, hw_stats->gotc);
1043
1044         /* Rx Multicst packets */
1045         UPDATE_VF_STAT(E1000_VFMPRC,
1046             hw_stats->last_mprc, hw_stats->mprc);
1047
1048         /* Good Rx loopback packets */
1049         UPDATE_VF_STAT(E1000_VFGPRLBC,
1050             hw_stats->last_gprlbc, hw_stats->gprlbc);
1051
1052         /* Good Rx loopback octets */
1053         UPDATE_VF_STAT(E1000_VFGORLBC,
1054             hw_stats->last_gorlbc, hw_stats->gorlbc);
1055
1056         /* Good Tx loopback packets */
1057         UPDATE_VF_STAT(E1000_VFGPTLBC,
1058             hw_stats->last_gptlbc, hw_stats->gptlbc);
1059
1060         /* Good Tx loopback octets */
1061         UPDATE_VF_STAT(E1000_VFGOTLBC,
1062             hw_stats->last_gotlbc, hw_stats->gotlbc);
1063
1064         if (rte_stats == NULL)
1065                 return;
1066
1067         memset(rte_stats, 0, sizeof(*rte_stats));
1068         rte_stats->ipackets = hw_stats->gprc;
1069         rte_stats->ibytes = hw_stats->gorc;
1070         rte_stats->opackets = hw_stats->gptc;
1071         rte_stats->obytes = hw_stats->gotc;
1072         rte_stats->imcasts = hw_stats->mprc;
1073         rte_stats->ilbpackets = hw_stats->gprlbc;
1074         rte_stats->ilbbytes = hw_stats->gorlbc;
1075         rte_stats->olbpackets = hw_stats->gptlbc;
1076         rte_stats->olbbytes = hw_stats->gotlbc;
1077
1078 }
1079
1080 static void
1081 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1082 {
1083         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1084                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1085
1086         /* Sync HW register to the last stats */
1087         eth_igbvf_stats_get(dev, NULL);
1088
1089         /* reset HW current stats*/
1090         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1091                offsetof(struct e1000_vf_stats, gprc));
1092
1093 }
1094
1095 static void
1096 eth_igb_infos_get(struct rte_eth_dev *dev,
1097                     struct rte_eth_dev_info *dev_info)
1098 {
1099         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1100
1101         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1102         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1103         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1104
1105         switch (hw->mac.type) {
1106         case e1000_82575:
1107                 dev_info->max_rx_queues = 4;
1108                 dev_info->max_tx_queues = 4;
1109                 break;
1110
1111         case e1000_82576:
1112                 dev_info->max_rx_queues = 16;
1113                 dev_info->max_tx_queues = 16;
1114                 break;
1115
1116         case e1000_82580:
1117                 dev_info->max_rx_queues = 8;
1118                 dev_info->max_tx_queues = 8;
1119                 break;
1120
1121         case e1000_i350:
1122                 dev_info->max_rx_queues = 8;
1123                 dev_info->max_tx_queues = 8;
1124                 break;
1125
1126         case e1000_i210:
1127                 dev_info->max_rx_queues = 4;
1128                 dev_info->max_tx_queues = 4;
1129                 break;
1130
1131         case e1000_vfadapt:
1132                 dev_info->max_rx_queues = 2;
1133                 dev_info->max_tx_queues = 2;
1134                 break;
1135
1136         case e1000_vfadapt_i350:
1137                 dev_info->max_rx_queues = 1;
1138                 dev_info->max_tx_queues = 1;
1139                 break;
1140
1141         default:
1142                 /* Should not happen */
1143                 dev_info->max_rx_queues = 0;
1144                 dev_info->max_tx_queues = 0;
1145         }
1146 }
1147
1148 /* return 0 means link status changed, -1 means not changed */
1149 static int
1150 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1151 {
1152         struct e1000_hw *hw =
1153                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1154         struct rte_eth_link link, old;
1155         int link_check, count;
1156
1157         link_check = 0;
1158         hw->mac.get_link_status = 1;
1159
1160         /* possible wait-to-complete in up to 9 seconds */
1161         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1162                 /* Read the real link status */
1163                 switch (hw->phy.media_type) {
1164                 case e1000_media_type_copper:
1165                         /* Do the work to read phy */
1166                         e1000_check_for_link(hw);
1167                         link_check = !hw->mac.get_link_status;
1168                         break;
1169
1170                 case e1000_media_type_fiber:
1171                         e1000_check_for_link(hw);
1172                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1173                                       E1000_STATUS_LU);
1174                         break;
1175
1176                 case e1000_media_type_internal_serdes:
1177                         e1000_check_for_link(hw);
1178                         link_check = hw->mac.serdes_has_link;
1179                         break;
1180
1181                 /* VF device is type_unknown */
1182                 case e1000_media_type_unknown:
1183                         eth_igbvf_link_update(hw);
1184                         link_check = !hw->mac.get_link_status;
1185                         break;
1186
1187                 default:
1188                         break;
1189                 }
1190                 if (link_check || wait_to_complete == 0)
1191                         break;
1192                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1193         }
1194         memset(&link, 0, sizeof(link));
1195         rte_igb_dev_atomic_read_link_status(dev, &link);
1196         old = link;
1197
1198         /* Now we check if a transition has happened */
1199         if (link_check) {
1200                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1201                                           &link.link_duplex);
1202                 link.link_status = 1;
1203         } else if (!link_check) {
1204                 link.link_speed = 0;
1205                 link.link_duplex = 0;
1206                 link.link_status = 0;
1207         }
1208         rte_igb_dev_atomic_write_link_status(dev, &link);
1209
1210         /* not changed */
1211         if (old.link_status == link.link_status)
1212                 return -1;
1213
1214         /* changed */
1215         return 0;
1216 }
1217
1218 /*
1219  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1220  * For ASF and Pass Through versions of f/w this means
1221  * that the driver is loaded.
1222  */
1223 static void
1224 igb_hw_control_acquire(struct e1000_hw *hw)
1225 {
1226         uint32_t ctrl_ext;
1227
1228         /* Let firmware know the driver has taken over */
1229         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1230         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1231 }
1232
1233 /*
1234  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1235  * For ASF and Pass Through versions of f/w this means that the
1236  * driver is no longer loaded.
1237  */
1238 static void
1239 igb_hw_control_release(struct e1000_hw *hw)
1240 {
1241         uint32_t ctrl_ext;
1242
1243         /* Let firmware taken over control of h/w */
1244         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1245         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1246                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1247 }
1248
1249 /*
1250  * Bit of a misnomer, what this really means is
1251  * to enable OS management of the system... aka
1252  * to disable special hardware management features.
1253  */
1254 static void
1255 igb_init_manageability(struct e1000_hw *hw)
1256 {
1257         if (e1000_enable_mng_pass_thru(hw)) {
1258                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1259                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1260
1261                 /* disable hardware interception of ARP */
1262                 manc &= ~(E1000_MANC_ARP_EN);
1263
1264                 /* enable receiving management packets to the host */
1265                 manc |= E1000_MANC_EN_MNG2HOST;
1266                 manc2h |= 1 << 5;  /* Mng Port 623 */
1267                 manc2h |= 1 << 6;  /* Mng Port 664 */
1268                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1269                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1270         }
1271 }
1272
1273 static void
1274 igb_release_manageability(struct e1000_hw *hw)
1275 {
1276         if (e1000_enable_mng_pass_thru(hw)) {
1277                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1278
1279                 manc |= E1000_MANC_ARP_EN;
1280                 manc &= ~E1000_MANC_EN_MNG2HOST;
1281
1282                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1283         }
1284 }
1285
1286 static void
1287 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1288 {
1289         struct e1000_hw *hw =
1290                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1291         uint32_t rctl;
1292
1293         rctl = E1000_READ_REG(hw, E1000_RCTL);
1294         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1295         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1296 }
1297
1298 static void
1299 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1300 {
1301         struct e1000_hw *hw =
1302                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1303         uint32_t rctl;
1304
1305         rctl = E1000_READ_REG(hw, E1000_RCTL);
1306         rctl &= (~E1000_RCTL_UPE);
1307         if (dev->data->all_multicast == 1)
1308                 rctl |= E1000_RCTL_MPE;
1309         else
1310                 rctl &= (~E1000_RCTL_MPE);
1311         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1312 }
1313
1314 static void
1315 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1316 {
1317         struct e1000_hw *hw =
1318                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1319         uint32_t rctl;
1320
1321         rctl = E1000_READ_REG(hw, E1000_RCTL);
1322         rctl |= E1000_RCTL_MPE;
1323         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1324 }
1325
1326 static void
1327 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1328 {
1329         struct e1000_hw *hw =
1330                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1331         uint32_t rctl;
1332
1333         if (dev->data->promiscuous == 1)
1334                 return; /* must remain in all_multicast mode */
1335         rctl = E1000_READ_REG(hw, E1000_RCTL);
1336         rctl &= (~E1000_RCTL_MPE);
1337         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1338 }
1339
1340 static int
1341 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1342 {
1343         struct e1000_hw *hw =
1344                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1345         struct e1000_vfta * shadow_vfta =
1346                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1347         uint32_t vfta;
1348         uint32_t vid_idx;
1349         uint32_t vid_bit;
1350
1351         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1352                               E1000_VFTA_ENTRY_MASK);
1353         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1354         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1355         if (on)
1356                 vfta |= vid_bit;
1357         else
1358                 vfta &= ~vid_bit;
1359         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1360
1361         /* update local VFTA copy */
1362         shadow_vfta->vfta[vid_idx] = vfta;
1363
1364         return 0;
1365 }
1366
1367 static void
1368 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1369 {
1370         struct e1000_hw *hw =
1371                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1372         uint32_t reg = ETHER_TYPE_VLAN ;
1373
1374         reg |= (tpid << 16);
1375         E1000_WRITE_REG(hw, E1000_VET, reg);
1376 }
1377
1378 static void
1379 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1380 {
1381         struct e1000_hw *hw =
1382                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1383         uint32_t reg;
1384
1385         /* Filter Table Disable */
1386         reg = E1000_READ_REG(hw, E1000_RCTL);
1387         reg &= ~E1000_RCTL_CFIEN;
1388         reg &= ~E1000_RCTL_VFE;
1389         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1390 }
1391
1392 static void
1393 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1394 {
1395         struct e1000_hw *hw =
1396                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397         struct e1000_vfta * shadow_vfta =
1398                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1399         uint32_t reg;
1400         int i;
1401
1402         /* Filter Table Enable, CFI not used for packet acceptance */
1403         reg = E1000_READ_REG(hw, E1000_RCTL);
1404         reg &= ~E1000_RCTL_CFIEN;
1405         reg |= E1000_RCTL_VFE;
1406         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1407
1408         /* restore VFTA table */
1409         for (i = 0; i < IGB_VFTA_SIZE; i++)
1410                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1411 }
1412
1413 static void
1414 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1415 {
1416         struct e1000_hw *hw =
1417                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1418         uint32_t reg;
1419
1420         /* VLAN Mode Disable */
1421         reg = E1000_READ_REG(hw, E1000_CTRL);
1422         reg &= ~E1000_CTRL_VME;
1423         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1424 }
1425
1426 static void
1427 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1428 {
1429         struct e1000_hw *hw =
1430                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1431         uint32_t reg;
1432
1433         /* VLAN Mode Enable */
1434         reg = E1000_READ_REG(hw, E1000_CTRL);
1435         reg |= E1000_CTRL_VME;
1436         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1437 }
1438
1439 static void
1440 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1441 {
1442         struct e1000_hw *hw =
1443                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1444         uint32_t reg;
1445
1446         /* CTRL_EXT: Extended VLAN */
1447         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1448         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1449         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1450
1451         /* Update maximum packet length */
1452         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1453                 E1000_WRITE_REG(hw, E1000_RLPML,
1454                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1455                                                 VLAN_TAG_SIZE);
1456 }
1457
1458 static void
1459 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1460 {
1461         struct e1000_hw *hw =
1462                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1463         uint32_t reg;
1464
1465         /* CTRL_EXT: Extended VLAN */
1466         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1467         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1468         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1469
1470         /* Update maximum packet length */
1471         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1472                 E1000_WRITE_REG(hw, E1000_RLPML,
1473                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1474                                                 2 * VLAN_TAG_SIZE);
1475 }
1476
1477 static void
1478 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1479 {
1480         if(mask & ETH_VLAN_STRIP_MASK){
1481                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1482                         igb_vlan_hw_strip_enable(dev);
1483                 else
1484                         igb_vlan_hw_strip_disable(dev);
1485         }
1486
1487         if(mask & ETH_VLAN_FILTER_MASK){
1488                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1489                         igb_vlan_hw_filter_enable(dev);
1490                 else
1491                         igb_vlan_hw_filter_disable(dev);
1492         }
1493
1494         if(mask & ETH_VLAN_EXTEND_MASK){
1495                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1496                         igb_vlan_hw_extend_enable(dev);
1497                 else
1498                         igb_vlan_hw_extend_disable(dev);
1499         }
1500 }
1501
1502
1503 /**
1504  * It enables the interrupt mask and then enable the interrupt.
1505  *
1506  * @param dev
1507  *  Pointer to struct rte_eth_dev.
1508  *
1509  * @return
1510  *  - On success, zero.
1511  *  - On failure, a negative value.
1512  */
1513 static int
1514 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1515 {
1516         struct e1000_interrupt *intr =
1517                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1518
1519         intr->mask |= E1000_ICR_LSC;
1520
1521         return 0;
1522 }
1523
1524 /*
1525  * It reads ICR and gets interrupt causes, check it and set a bit flag
1526  * to update link status.
1527  *
1528  * @param dev
1529  *  Pointer to struct rte_eth_dev.
1530  *
1531  * @return
1532  *  - On success, zero.
1533  *  - On failure, a negative value.
1534  */
1535 static int
1536 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1537 {
1538         uint32_t icr;
1539         struct e1000_hw *hw =
1540                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1541         struct e1000_interrupt *intr =
1542                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1543
1544         igb_intr_disable(hw);
1545
1546         /* read-on-clear nic registers here */
1547         icr = E1000_READ_REG(hw, E1000_ICR);
1548
1549         intr->flags = 0;
1550         if (icr & E1000_ICR_LSC) {
1551                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1552         }
1553
1554         if (icr & E1000_ICR_VMMB)
1555                 intr->flags |= E1000_FLAG_MAILBOX;
1556
1557         return 0;
1558 }
1559
1560 /*
1561  * It executes link_update after knowing an interrupt is prsent.
1562  *
1563  * @param dev
1564  *  Pointer to struct rte_eth_dev.
1565  *
1566  * @return
1567  *  - On success, zero.
1568  *  - On failure, a negative value.
1569  */
1570 static int
1571 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1572 {
1573         struct e1000_hw *hw =
1574                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1575         struct e1000_interrupt *intr =
1576                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1577         uint32_t tctl, rctl;
1578         struct rte_eth_link link;
1579         int ret;
1580
1581         if (intr->flags & E1000_FLAG_MAILBOX) {
1582                 igb_pf_mbx_process(dev);
1583                 intr->flags &= ~E1000_FLAG_MAILBOX;
1584         }
1585
1586         igb_intr_enable(dev);
1587         rte_intr_enable(&(dev->pci_dev->intr_handle));
1588
1589         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1590                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1591
1592                 /* set get_link_status to check register later */
1593                 hw->mac.get_link_status = 1;
1594                 ret = eth_igb_link_update(dev, 0);
1595
1596                 /* check if link has changed */
1597                 if (ret < 0)
1598                         return 0;
1599
1600                 memset(&link, 0, sizeof(link));
1601                 rte_igb_dev_atomic_read_link_status(dev, &link);
1602                 if (link.link_status) {
1603                         PMD_INIT_LOG(INFO,
1604                                 " Port %d: Link Up - speed %u Mbps - %s\n",
1605                                 dev->data->port_id, (unsigned)link.link_speed,
1606                                 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1607                                         "full-duplex" : "half-duplex");
1608                 } else {
1609                         PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1610                                                 dev->data->port_id);
1611                 }
1612                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1613                                         dev->pci_dev->addr.domain,
1614                                         dev->pci_dev->addr.bus,
1615                                         dev->pci_dev->addr.devid,
1616                                         dev->pci_dev->addr.function);
1617                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1618                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1619                 if (link.link_status) {
1620                         /* enable Tx/Rx */
1621                         tctl |= E1000_TCTL_EN;
1622                         rctl |= E1000_RCTL_EN;
1623                 } else {
1624                         /* disable Tx/Rx */
1625                         tctl &= ~E1000_TCTL_EN;
1626                         rctl &= ~E1000_RCTL_EN;
1627                 }
1628                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1629                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1630                 E1000_WRITE_FLUSH(hw);
1631                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1632         }
1633
1634         return 0;
1635 }
1636
1637 /**
1638  * Interrupt handler which shall be registered at first.
1639  *
1640  * @param handle
1641  *  Pointer to interrupt handle.
1642  * @param param
1643  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1644  *
1645  * @return
1646  *  void
1647  */
1648 static void
1649 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1650                                                         void *param)
1651 {
1652         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1653
1654         eth_igb_interrupt_get_status(dev);
1655         eth_igb_interrupt_action(dev);
1656 }
1657
1658 static int
1659 eth_igb_led_on(struct rte_eth_dev *dev)
1660 {
1661         struct e1000_hw *hw;
1662
1663         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1664         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1665 }
1666
1667 static int
1668 eth_igb_led_off(struct rte_eth_dev *dev)
1669 {
1670         struct e1000_hw *hw;
1671
1672         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1673         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1674 }
1675
1676 static int
1677 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1678 {
1679         struct e1000_hw *hw;
1680         int err;
1681         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1682                 e1000_fc_none,
1683                 e1000_fc_rx_pause,
1684                 e1000_fc_tx_pause,
1685                 e1000_fc_full
1686         };
1687         uint32_t rx_buf_size;
1688         uint32_t max_high_water;
1689
1690         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1691         rx_buf_size = igb_get_rx_buffer_size(hw);
1692         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1693
1694         /* At least reserve one Ethernet frame for watermark */
1695         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1696         if ((fc_conf->high_water > max_high_water) ||
1697                 (fc_conf->high_water < fc_conf->low_water)) {
1698                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1699                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1700                 return (-EINVAL);
1701         }
1702
1703         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1704         hw->fc.pause_time     = fc_conf->pause_time;
1705         hw->fc.high_water     = fc_conf->high_water;
1706         hw->fc.low_water      = fc_conf->low_water;
1707         hw->fc.send_xon       = fc_conf->send_xon;
1708
1709         err = e1000_setup_link_generic(hw);
1710         if (err == E1000_SUCCESS) {
1711                 return 0;
1712         }
1713
1714         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1715         return (-EIO);
1716 }
1717
1718 #define E1000_RAH_POOLSEL_SHIFT      (18)
1719 static void
1720 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1721                 uint32_t index, __rte_unused uint32_t pool)
1722 {
1723         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1724         uint32_t rah;
1725
1726         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1727         rah = E1000_READ_REG(hw, E1000_RAH(index));
1728         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
1729         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
1730 }
1731
1732 static void
1733 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1734 {
1735         uint8_t addr[ETHER_ADDR_LEN];
1736         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1737
1738         memset(addr, 0, sizeof(addr));
1739
1740         e1000_rar_set(hw, addr, index);
1741 }
1742
1743 /*
1744  * Virtual Function operations
1745  */
1746 static void
1747 igbvf_intr_disable(struct e1000_hw *hw)
1748 {
1749         PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1750
1751         /* Clear interrupt mask to stop from interrupts being generated */
1752         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
1753
1754         E1000_WRITE_FLUSH(hw);
1755 }
1756
1757 static void
1758 igbvf_stop_adapter(struct rte_eth_dev *dev)
1759 {
1760         u32 reg_val;
1761         u16 i;
1762         struct rte_eth_dev_info dev_info;
1763         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1764
1765         memset(&dev_info, 0, sizeof(dev_info));
1766         eth_igb_infos_get(dev, &dev_info);
1767
1768         /* Clear interrupt mask to stop from interrupts being generated */
1769         igbvf_intr_disable(hw);
1770
1771         /* Clear any pending interrupts, flush previous writes */
1772         E1000_READ_REG(hw, E1000_EICR);
1773
1774         /* Disable the transmit unit.  Each queue must be disabled. */
1775         for (i = 0; i < dev_info.max_tx_queues; i++)
1776                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1777
1778         /* Disable the receive unit by stopping each queue */
1779         for (i = 0; i < dev_info.max_rx_queues; i++) {
1780                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1781                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1782                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1783                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1784                         ;
1785         }
1786
1787         /* flush all queues disables */
1788         E1000_WRITE_FLUSH(hw);
1789         msec_delay(2);
1790 }
1791
1792 static int eth_igbvf_link_update(struct e1000_hw *hw)
1793 {
1794         struct e1000_mbx_info *mbx = &hw->mbx;
1795         struct e1000_mac_info *mac = &hw->mac;
1796         int ret_val = E1000_SUCCESS;
1797
1798         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1799
1800         /*
1801          * We only want to run this if there has been a rst asserted.
1802          * in this case that could mean a link change, device reset,
1803          * or a virtual function reset
1804          */
1805
1806         /* If we were hit with a reset or timeout drop the link */
1807         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1808                 mac->get_link_status = TRUE;
1809
1810         if (!mac->get_link_status)
1811                 goto out;
1812
1813         /* if link status is down no point in checking to see if pf is up */
1814         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1815                 goto out;
1816
1817         /* if we passed all the tests above then the link is up and we no
1818          * longer need to check for link */
1819         mac->get_link_status = FALSE;
1820
1821 out:
1822         return ret_val;
1823 }
1824
1825
1826 static int
1827 igbvf_dev_configure(struct rte_eth_dev *dev)
1828 {
1829         struct rte_eth_conf* conf = &dev->data->dev_conf;
1830
1831         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1832                 dev->data->port_id);
1833
1834         /*
1835          * VF has no ability to enable/disable HW CRC
1836          * Keep the persistent behavior the same as Host PF
1837          */
1838 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1839         if (!conf->rxmode.hw_strip_crc) {
1840                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1841                 conf->rxmode.hw_strip_crc = 1;
1842         }
1843 #else
1844         if (conf->rxmode.hw_strip_crc) {
1845                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1846                 conf->rxmode.hw_strip_crc = 0;
1847         }
1848 #endif
1849
1850         return 0;
1851 }
1852
1853 static int
1854 igbvf_dev_start(struct rte_eth_dev *dev)
1855 {
1856         struct e1000_hw *hw =
1857                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858         int ret;
1859
1860         PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1861
1862         hw->mac.ops.reset_hw(hw);
1863
1864         /* Set all vfta */
1865         igbvf_set_vfta_all(dev,1);
1866
1867         eth_igbvf_tx_init(dev);
1868
1869         /* This can fail when allocating mbufs for descriptor rings */
1870         ret = eth_igbvf_rx_init(dev);
1871         if (ret) {
1872                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1873                 igb_dev_clear_queues(dev);
1874                 return ret;
1875         }
1876
1877         return 0;
1878 }
1879
1880 static void
1881 igbvf_dev_stop(struct rte_eth_dev *dev)
1882 {
1883         PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1884
1885         igbvf_stop_adapter(dev);
1886
1887         /*
1888           * Clear what we set, but we still keep shadow_vfta to
1889           * restore after device starts
1890           */
1891         igbvf_set_vfta_all(dev,0);
1892
1893         igb_dev_clear_queues(dev);
1894 }
1895
1896 static void
1897 igbvf_dev_close(struct rte_eth_dev *dev)
1898 {
1899         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1900
1901         PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1902
1903         e1000_reset_hw(hw);
1904
1905         igbvf_dev_stop(dev);
1906 }
1907
1908 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1909 {
1910         struct e1000_mbx_info *mbx = &hw->mbx;
1911         uint32_t msgbuf[2];
1912
1913         /* After set vlan, vlan strip will also be enabled in igb driver*/
1914         msgbuf[0] = E1000_VF_SET_VLAN;
1915         msgbuf[1] = vid;
1916         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1917         if (on)
1918                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1919
1920         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1921 }
1922
1923 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1924 {
1925         struct e1000_hw *hw =
1926                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927         struct e1000_vfta * shadow_vfta =
1928                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1929         int i = 0, j = 0, vfta = 0, mask = 1;
1930
1931         for (i = 0; i < IGB_VFTA_SIZE; i++){
1932                 vfta = shadow_vfta->vfta[i];
1933                 if(vfta){
1934                         mask = 1;
1935                         for (j = 0; j < 32; j++){
1936                                 if(vfta & mask)
1937                                         igbvf_set_vfta(hw,
1938                                                 (uint16_t)((i<<5)+j), on);
1939                                 mask<<=1;
1940                         }
1941                 }
1942         }
1943
1944 }
1945
1946 static int
1947 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1948 {
1949         struct e1000_hw *hw =
1950                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951         struct e1000_vfta * shadow_vfta =
1952                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1953         uint32_t vid_idx = 0;
1954         uint32_t vid_bit = 0;
1955         int ret = 0;
1956
1957         PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
1958
1959         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
1960         ret = igbvf_set_vfta(hw, vlan_id, !!on);
1961         if(ret){
1962                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
1963                 return ret;
1964         }
1965         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1966         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1967
1968         /*Save what we set and retore it after device reset*/
1969         if (on)
1970                 shadow_vfta->vfta[vid_idx] |= vid_bit;
1971         else
1972                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
1973
1974         return 0;
1975 }
1976
1977 static int
1978 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
1979                                 struct rte_eth_rss_reta *reta_conf)
1980 {
1981         uint8_t i,j,mask;
1982         uint32_t reta;
1983         struct e1000_hw *hw =
1984                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985
1986         /*
1987          * Update Redirection Table RETA[n],n=0...31,The redirection table has
1988          * 128-entries in 32 registers
1989          */
1990         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1991                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
1992                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1993                 else
1994                         mask = (uint8_t)((reta_conf->mask_hi >>
1995                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
1996                 if (mask != 0) {
1997                         reta = 0;
1998                         /* If all 4 entries were set,don't need read RETA register */
1999                         if (mask != 0xF)
2000                                 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2001
2002                         for (j = 0; j < 4; j++) {
2003                                 if (mask & (0x1 << j)) {
2004                                         if (mask != 0xF)
2005                                                 reta &= ~(0xFF << 8 * j);
2006                                         reta |= reta_conf->reta[i + j] << 8 * j;
2007                                 }
2008                         }
2009                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2010                 }
2011         }
2012
2013         return 0;
2014 }
2015
2016 static int
2017 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2018                                 struct rte_eth_rss_reta *reta_conf)
2019 {
2020         uint8_t i,j,mask;
2021         uint32_t reta;
2022         struct e1000_hw *hw =
2023                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2024
2025         /*
2026          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2027          * 128-entries in 32 registers
2028          */
2029         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2030                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2031                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2032                 else
2033                         mask = (uint8_t)((reta_conf->mask_hi >>
2034                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2035
2036                 if (mask != 0) {
2037                         reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2038                         for (j = 0; j < 4; j++) {
2039                                 if (mask & (0x1 << j))
2040                                         reta_conf->reta[i + j] =
2041                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2042                         }
2043                 }
2044         }
2045
2046         return 0;
2047 }