lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #include <sys/queue.h>
  36 #include <stdio.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40
  41 #include <rte_common.h>
  42 #include <rte_interrupts.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_tailq.h>
  52 #include <rte_eal.h>
  53 #include <rte_atomic.h>
  54 #include <rte_malloc.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 static int  eth_igb_configure(struct rte_eth_dev *dev);
  61 static int  eth_igb_start(struct rte_eth_dev *dev);
  62 static void eth_igb_stop(struct rte_eth_dev *dev);
  63 static void eth_igb_close(struct rte_eth_dev *dev);
  64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  68 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  69                                 int wait_to_complete);
  70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  71                                 struct rte_eth_stats *rte_stats);
  72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  74                                 struct rte_eth_dev_info *dev_info);
  75 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  76                                 struct rte_eth_fc_conf *fc_conf);
  77 static int eth_igb_interrupt_setup(struct rte_eth_dev *dev);
  78 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  79 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  80 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  81                                                         void *param);
  82 static int  igb_hardware_init(struct e1000_hw *hw);
  83 static void igb_hw_control_acquire(struct e1000_hw *hw);
  84 static void igb_hw_control_release(struct e1000_hw *hw);
  85 static void igb_init_manageability(struct e1000_hw *hw);
  86 static void igb_release_manageability(struct e1000_hw *hw);
  87
  88 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  89                 uint16_t vlan_id, int on);
  90 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
  91 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  92
  93 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  94 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  95 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  96 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  97 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
  98 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
  99
 100 static int eth_igb_led_on(struct rte_eth_dev *dev);
 101 static int eth_igb_led_off(struct rte_eth_dev *dev);
 102
 103 static void igb_intr_disable(struct e1000_hw *hw);
 104 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 105 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 106                 struct ether_addr *mac_addr,
 107                 uint32_t index, uint32_t pool);
 108 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 109
 110 static void igbvf_intr_disable(struct e1000_hw *hw);
 111 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 112 static int igbvf_dev_start(struct rte_eth_dev *dev);
 113 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 114 static void igbvf_dev_close(struct rte_eth_dev *dev);
 115 static int eth_igbvf_link_update(struct e1000_hw *hw);
 116 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 117 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 118 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 119                 uint16_t vlan_id, int on);
 120 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 121 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 122
 123 /*
 124  * Define VF Stats MACRO for Non "cleared on read" register
 125  */
 126 #define UPDATE_VF_STAT(reg, last, cur)            \
 127 {                                                 \
 128         u32 latest = E1000_READ_REG(hw, reg);     \
 129         cur += latest - last;                     \
 130         last = latest;                            \
 131 }
 132
 133
 134 #define IGB_FC_PAUSE_TIME 0x0680
 135 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 136 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 137
 138 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 139
 140 /*
 141  * The set of PCI devices this driver supports
 142  */
 143 static struct rte_pci_id pci_id_igb_map[] = {
 144
 145 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 146 #include "rte_pci_dev_ids.h"
 147
 148 {.device_id = 0},
 149 };
 150
 151 /*
 152  * The set of PCI devices this driver supports (for 82576&I350 VF)
 153  */
 154 static struct rte_pci_id pci_id_igbvf_map[] = {
 155
 156 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 157 #include "rte_pci_dev_ids.h"
 158
 159 {.device_id = 0},
 160 };
 161
 162 static struct eth_dev_ops eth_igb_ops = {
 163         .dev_configure        = eth_igb_configure,
 164         .dev_start            = eth_igb_start,
 165         .dev_stop             = eth_igb_stop,
 166         .dev_close            = eth_igb_close,
 167         .promiscuous_enable   = eth_igb_promiscuous_enable,
 168         .promiscuous_disable  = eth_igb_promiscuous_disable,
 169         .allmulticast_enable  = eth_igb_allmulticast_enable,
 170         .allmulticast_disable = eth_igb_allmulticast_disable,
 171         .link_update          = eth_igb_link_update,
 172         .stats_get            = eth_igb_stats_get,
 173         .stats_reset          = eth_igb_stats_reset,
 174         .dev_infos_get        = eth_igb_infos_get,
 175         .vlan_filter_set      = eth_igb_vlan_filter_set,
 176         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 177         .vlan_offload_set     = eth_igb_vlan_offload_set,
 178         .rx_queue_setup       = eth_igb_rx_queue_setup,
 179         .rx_queue_release     = eth_igb_rx_queue_release,
 180         .tx_queue_setup       = eth_igb_tx_queue_setup,
 181         .tx_queue_release     = eth_igb_tx_queue_release,
 182         .dev_led_on           = eth_igb_led_on,
 183         .dev_led_off          = eth_igb_led_off,
 184         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 185         .mac_addr_add         = eth_igb_rar_set,
 186         .mac_addr_remove      = eth_igb_rar_clear,
 187 };
 188
 189 /*
 190  * dev_ops for virtual function, bare necessities for basic vf
 191  * operation have been implemented
 192  */
 193 static struct eth_dev_ops igbvf_eth_dev_ops = {
 194         .dev_configure        = igbvf_dev_configure,
 195         .dev_start            = igbvf_dev_start,
 196         .dev_stop             = igbvf_dev_stop,
 197         .dev_close            = igbvf_dev_close,
 198         .link_update          = eth_igb_link_update,
 199         .stats_get            = eth_igbvf_stats_get,
 200         .stats_reset          = eth_igbvf_stats_reset,
 201         .vlan_filter_set      = igbvf_vlan_filter_set,
 202         .dev_infos_get        = eth_igb_infos_get,
 203         .rx_queue_setup       = eth_igb_rx_queue_setup,
 204         .rx_queue_release     = eth_igb_rx_queue_release,
 205         .tx_queue_setup       = eth_igb_tx_queue_setup,
 206         .tx_queue_release     = eth_igb_tx_queue_release,
 207 };
 208
 209 /**
 210  * Atomically reads the link status information from global
 211  * structure rte_eth_dev.
 212  *
 213  * @param dev
 214  *   - Pointer to the structure rte_eth_dev to read from.
 215  *   - Pointer to the buffer to be saved with the link status.
 216  *
 217  * @return
 218  *   - On success, zero.
 219  *   - On failure, negative value.
 220  */
 221 static inline int
 222 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 223                                 struct rte_eth_link *link)
 224 {
 225         struct rte_eth_link *dst = link;
 226         struct rte_eth_link *src = &(dev->data->dev_link);
 227
 228         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 229                                         *(uint64_t *)src) == 0)
 230                 return -1;
 231
 232         return 0;
 233 }
 234
 235 /**
 236  * Atomically writes the link status information into global
 237  * structure rte_eth_dev.
 238  *
 239  * @param dev
 240  *   - Pointer to the structure rte_eth_dev to read from.
 241  *   - Pointer to the buffer to be saved with the link status.
 242  *
 243  * @return
 244  *   - On success, zero.
 245  *   - On failure, negative value.
 246  */
 247 static inline int
 248 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 249                                 struct rte_eth_link *link)
 250 {
 251         struct rte_eth_link *dst = &(dev->data->dev_link);
 252         struct rte_eth_link *src = link;
 253
 254         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 255                                         *(uint64_t *)src) == 0)
 256                 return -1;
 257
 258         return 0;
 259 }
 260
 261 static void
 262 igb_identify_hardware(struct rte_eth_dev *dev)
 263 {
 264         struct e1000_hw *hw =
 265                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 266
 267         hw->vendor_id = dev->pci_dev->id.vendor_id;
 268         hw->device_id = dev->pci_dev->id.device_id;
 269         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 270         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 271
 272         e1000_set_mac_type(hw);
 273
 274         /* need to check if it is a vf device below */
 275 }
 276
 277 static int
 278 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 279                    struct rte_eth_dev *eth_dev)
 280 {
 281         int error = 0;
 282         struct rte_pci_device *pci_dev;
 283         struct e1000_hw *hw =
 284                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 285         struct e1000_vfta * shadow_vfta =
 286                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 287
 288         pci_dev = eth_dev->pci_dev;
 289         eth_dev->dev_ops = &eth_igb_ops;
 290         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 291         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 292
 293         /* for secondary processes, we don't initialise any further as primary
 294          * has already done this work. Only check we don't need a different
 295          * RX function */
 296         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 297                 if (eth_dev->data->scattered_rx)
 298                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 299                 return 0;
 300         }
 301
 302         hw->hw_addr= (void *)pci_dev->mem_resource.addr;
 303
 304         igb_identify_hardware(eth_dev);
 305
 306         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 307                 error = -EIO;
 308                 goto err_late;
 309         }
 310
 311         e1000_get_bus_info(hw);
 312
 313         hw->mac.autoneg = 1;
 314         hw->phy.autoneg_wait_to_complete = 0;
 315         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 316
 317         /* Copper options */
 318         if (hw->phy.media_type == e1000_media_type_copper) {
 319                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 320                 hw->phy.disable_polarity_correction = 0;
 321                 hw->phy.ms_type = e1000_ms_hw_default;
 322         }
 323
 324         /*
 325          * Start from a known state, this is important in reading the nvm
 326          * and mac from that.
 327          */
 328         e1000_reset_hw(hw);
 329
 330         /* Make sure we have a good EEPROM before we read from it */
 331         if (e1000_validate_nvm_checksum(hw) < 0) {
 332                 /*
 333                  * Some PCI-E parts fail the first check due to
 334                  * the link being in sleep state, call it again,
 335                  * if it fails a second time its a real issue.
 336                  */
 337                 if (e1000_validate_nvm_checksum(hw) < 0) {
 338                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 339                         error = -EIO;
 340                         goto err_late;
 341                 }
 342         }
 343
 344         /* Read the permanent MAC address out of the EEPROM */
 345         if (e1000_read_mac_addr(hw) != 0) {
 346                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 347                 error = -EIO;
 348                 goto err_late;
 349         }
 350
 351         /* Allocate memory for storing MAC addresses */
 352         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 353                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 354         if (eth_dev->data->mac_addrs == NULL) {
 355                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 356                                                 "store MAC addresses",
 357                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 358                 error = -ENOMEM;
 359                 goto err_late;
 360         }
 361
 362         /* Copy the permanent MAC address */
 363         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 364
 365         /* initialize the vfta */
 366         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 367
 368         /* Now initialize the hardware */
 369         if (igb_hardware_init(hw) != 0) {
 370                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 371                 rte_free(eth_dev->data->mac_addrs);
 372                 eth_dev->data->mac_addrs = NULL;
 373                 error = -ENODEV;
 374                 goto err_late;
 375         }
 376         hw->mac.get_link_status = 1;
 377
 378         /* Indicate SOL/IDER usage */
 379         if (e1000_check_reset_block(hw) < 0) {
 380                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 381                                         "SOL/IDER session");
 382         }
 383
 384         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 385                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 386                      pci_dev->id.device_id);
 387
 388         rte_intr_callback_register(&(pci_dev->intr_handle),
 389                 eth_igb_interrupt_handler, (void *)eth_dev);
 390
 391         return 0;
 392
 393 err_late:
 394         igb_hw_control_release(hw);
 395
 396         return (error);
 397 }
 398
 399 /*
 400  * Virtual Function device init
 401  */
 402 static int
 403 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 404                 struct rte_eth_dev *eth_dev)
 405 {
 406         struct rte_pci_device *pci_dev;
 407         struct e1000_hw *hw =
 408                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 409         int diag;
 410
 411         PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 412
 413         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 414         pci_dev = eth_dev->pci_dev;
 415
 416         hw->device_id = pci_dev->id.device_id;
 417         hw->vendor_id = pci_dev->id.vendor_id;
 418         hw->hw_addr = (void *)pci_dev->mem_resource.addr;
 419
 420         /* Initialize the shared code */
 421         diag = e1000_setup_init_funcs(hw, TRUE);
 422         if (diag != 0) {
 423                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 424                         diag);
 425                 return -EIO;
 426         }
 427
 428         /* init_mailbox_params */
 429         hw->mbx.ops.init_params(hw);
 430
 431         /* Disable the interrupts for VF */
 432         igbvf_intr_disable(hw);
 433
 434         diag = hw->mac.ops.reset_hw(hw);
 435
 436         /* Allocate memory for storing MAC addresses */
 437         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 438                 hw->mac.rar_entry_count, 0);
 439         if (eth_dev->data->mac_addrs == NULL) {
 440                 PMD_INIT_LOG(ERR,
 441                         "Failed to allocate %d bytes needed to store MAC "
 442                         "addresses",
 443                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 444                 return -ENOMEM;
 445         }
 446         /* Copy the permanent MAC address */
 447         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 448                         &eth_dev->data->mac_addrs[0]);
 449
 450         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
 451                         "mac.type=%s\n",
 452                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 453                         pci_dev->id.device_id,
 454                         "igb_mac_82576_vf");
 455
 456         return 0;
 457 }
 458
 459 static struct eth_driver rte_igb_pmd = {
 460         {
 461                 .name = "rte_igb_pmd",
 462                 .id_table = pci_id_igb_map,
 463                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 464         },
 465         .eth_dev_init = eth_igb_dev_init,
 466         .dev_private_size = sizeof(struct e1000_adapter),
 467 };
 468
 469 /*
 470  * virtual function driver struct
 471  */
 472 static struct eth_driver rte_igbvf_pmd = {
 473         {
 474                 .name = "rte_igbvf_pmd",
 475                 .id_table = pci_id_igbvf_map,
 476                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 477         },
 478         .eth_dev_init = eth_igbvf_dev_init,
 479         .dev_private_size = sizeof(struct e1000_adapter),
 480 };
 481
 482 int
 483 rte_igb_pmd_init(void)
 484 {
 485         rte_eth_driver_register(&rte_igb_pmd);
 486         return 0;
 487 }
 488
 489 /*
 490  * VF Driver initialization routine.
 491  * Invoked one at EAL init time.
 492  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 493  */
 494 int
 495 rte_igbvf_pmd_init(void)
 496 {
 497         DEBUGFUNC("rte_igbvf_pmd_init");
 498
 499         rte_eth_driver_register(&rte_igbvf_pmd);
 500         return (0);
 501 }
 502
 503 static int
 504 eth_igb_configure(struct rte_eth_dev *dev)
 505 {
 506         struct e1000_interrupt *intr =
 507                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 508
 509         PMD_INIT_LOG(DEBUG, ">>");
 510
 511         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 512
 513         PMD_INIT_LOG(DEBUG, "<<");
 514
 515         return (0);
 516 }
 517
 518 static int
 519 eth_igb_start(struct rte_eth_dev *dev)
 520 {
 521         struct e1000_hw *hw =
 522                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 523         int ret, i, mask;
 524
 525         PMD_INIT_LOG(DEBUG, ">>");
 526
 527         igb_intr_disable(hw);
 528
 529         /* Power up the phy. Needed to make the link go Up */
 530         e1000_power_up_phy(hw);
 531
 532         /*
 533          * Packet Buffer Allocation (PBA)
 534          * Writing PBA sets the receive portion of the buffer
 535          * the remainder is used for the transmit buffer.
 536          */
 537         if (hw->mac.type == e1000_82575) {
 538                 uint32_t pba;
 539
 540                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 541                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 542         }
 543
 544         /* Put the address into the Receive Address Array */
 545         e1000_rar_set(hw, hw->mac.addr, 0);
 546
 547         /* Initialize the hardware */
 548         if (igb_hardware_init(hw)) {
 549                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 550                 return (-EIO);
 551         }
 552
 553         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 554
 555         /* Configure for OS presence */
 556         igb_init_manageability(hw);
 557
 558         eth_igb_tx_init(dev);
 559
 560         /* This can fail when allocating mbufs for descriptor rings */
 561         ret = eth_igb_rx_init(dev);
 562         if (ret) {
 563                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 564                 igb_dev_clear_queues(dev);
 565                 return ret;
 566         }
 567
 568         e1000_clear_hw_cntrs_base_generic(hw);
 569
 570         /*
 571          * VLAN Offload Settings
 572          */
 573         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 574                         ETH_VLAN_EXTEND_MASK;
 575         eth_igb_vlan_offload_set(dev, mask);
 576
 577         /*
 578          * Configure the Interrupt Moderation register (EITR) with the maximum
 579          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 580          * spurious [DMA] memory updates of RX and TX ring descriptors.
 581          *
 582          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 583          * spurious memory updates per second should be expected.
 584          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 585          *
 586          * Because interrupts are not used at all, the MSI-X is not activated
 587          * and interrupt moderation is controlled by EITR[0].
 588          *
 589          * Note that having [almost] disabled memory updates of RX and TX ring
 590          * descriptors through the Interrupt Moderation mechanism, memory
 591          * updates of ring descriptors are now moderated by the configurable
 592          * value of Write-Back Threshold registers.
 593          */
 594         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 595                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 596                 uint32_t ivar;
 597
 598                 /* Enable all RX & TX queues in the IVAR registers */
 599                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 600                 for (i = 0; i < 8; i++)
 601                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 602
 603                 /* Configure EITR with the maximum possible value (0xFFFF) */
 604                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 605         }
 606
 607         /* Setup link speed and duplex */
 608         switch (dev->data->dev_conf.link_speed) {
 609         case ETH_LINK_SPEED_AUTONEG:
 610                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 611                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 612                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 613                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 614                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 615                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 616                 else
 617                         goto error_invalid_config;
 618                 break;
 619         case ETH_LINK_SPEED_10:
 620                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 621                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 622                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 623                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 624                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 625                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 626                 else
 627                         goto error_invalid_config;
 628                 break;
 629         case ETH_LINK_SPEED_100:
 630                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 631                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 632                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 633                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 634                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 635                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 636                 else
 637                         goto error_invalid_config;
 638                 break;
 639         case ETH_LINK_SPEED_1000:
 640                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 641                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 642                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 643                 else
 644                         goto error_invalid_config;
 645                 break;
 646         case ETH_LINK_SPEED_10000:
 647         default:
 648                 goto error_invalid_config;
 649         }
 650         e1000_setup_link(hw);
 651
 652         /* check if lsc interrupt feature is enabled */
 653         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 654                 ret = eth_igb_interrupt_setup(dev);
 655                 if (ret) {
 656                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 657                         igb_dev_clear_queues(dev);
 658                         return ret;
 659                 }
 660         }
 661
 662         PMD_INIT_LOG(DEBUG, "<<");
 663
 664         return (0);
 665
 666 error_invalid_config:
 667         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 668                         dev->data->dev_conf.link_speed,
 669                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 670         igb_dev_clear_queues(dev);
 671         return (-EINVAL);
 672 }
 673
 674 /*********************************************************************
 675  *
 676  *  This routine disables all traffic on the adapter by issuing a
 677  *  global reset on the MAC.
 678  *
 679  **********************************************************************/
 680 static void
 681 eth_igb_stop(struct rte_eth_dev *dev)
 682 {
 683         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 684         struct rte_eth_link link;
 685
 686         igb_intr_disable(hw);
 687         e1000_reset_hw(hw);
 688         E1000_WRITE_REG(hw, E1000_WUC, 0);
 689
 690         /* Power down the phy. Needed to make the link go Down */
 691         e1000_power_down_phy(hw);
 692
 693         igb_dev_clear_queues(dev);
 694
 695         /* clear the recorded link status */
 696         memset(&link, 0, sizeof(link));
 697         rte_igb_dev_atomic_write_link_status(dev, &link);
 698 }
 699
 700 static void
 701 eth_igb_close(struct rte_eth_dev *dev)
 702 {
 703         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 704         struct rte_eth_link link;
 705
 706         eth_igb_stop(dev);
 707         e1000_phy_hw_reset(hw);
 708         igb_release_manageability(hw);
 709         igb_hw_control_release(hw);
 710
 711         igb_dev_clear_queues(dev);
 712
 713         memset(&link, 0, sizeof(link));
 714         rte_igb_dev_atomic_write_link_status(dev, &link);
 715 }
 716
 717 static int
 718 igb_get_rx_buffer_size(struct e1000_hw *hw)
 719 {
 720         uint32_t rx_buf_size;
 721         if (hw->mac.type == e1000_82576) {
 722                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 723         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 724                 /* PBS needs to be translated according to a lookup table */
 725                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 726                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 727                 rx_buf_size = (rx_buf_size << 10);
 728         } else if (hw->mac.type == e1000_i210) {
 729                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 730         } else {
 731                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 732         }
 733
 734         return rx_buf_size;
 735 }
 736
 737 /*********************************************************************
 738  *
 739  *  Initialize the hardware
 740  *
 741  **********************************************************************/
 742 static int
 743 igb_hardware_init(struct e1000_hw *hw)
 744 {
 745         uint32_t rx_buf_size;
 746         int diag;
 747
 748         /* Let the firmware know the OS is in control */
 749         igb_hw_control_acquire(hw);
 750
 751         /*
 752          * These parameters control the automatic generation (Tx) and
 753          * response (Rx) to Ethernet PAUSE frames.
 754          * - High water mark should allow for at least two standard size (1518)
 755          *   frames to be received after sending an XOFF.
 756          * - Low water mark works best when it is very near the high water mark.
 757          *   This allows the receiver to restart by sending XON when it has
 758          *   drained a bit. Here we use an arbitary value of 1500 which will
 759          *   restart after one full frame is pulled from the buffer. There
 760          *   could be several smaller frames in the buffer and if so they will
 761          *   not trigger the XON until their total number reduces the buffer
 762          *   by 1500.
 763          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 764          */
 765         rx_buf_size = igb_get_rx_buffer_size(hw);
 766
 767         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
 768         hw->fc.low_water = hw->fc.high_water - 1500;
 769         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
 770         hw->fc.send_xon = 1;
 771
 772         /* Set Flow control, use the tunable location if sane */
 773         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
 774                 hw->fc.requested_mode = igb_fc_setting;
 775         else
 776                 hw->fc.requested_mode = e1000_fc_none;
 777
 778         /* Issue a global reset */
 779         e1000_reset_hw(hw);
 780         E1000_WRITE_REG(hw, E1000_WUC, 0);
 781
 782         diag = e1000_init_hw(hw);
 783         if (diag < 0)
 784                 return (diag);
 785
 786         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 787         e1000_get_phy_info(hw);
 788         e1000_check_for_link(hw);
 789
 790         return (0);
 791 }
 792
 793 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
 794 static void
 795 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 796 {
 797         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 798         struct e1000_hw_stats *stats =
 799                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 800         int pause_frames;
 801
 802         if(hw->phy.media_type == e1000_media_type_copper ||
 803             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 804                 stats->symerrs +=
 805                     E1000_READ_REG(hw,E1000_SYMERRS);
 806                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 807         }
 808
 809         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 810         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 811         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 812         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 813
 814         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 815         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 816         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 817         stats->dc += E1000_READ_REG(hw, E1000_DC);
 818         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 819         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 820         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 821         /*
 822         ** For watchdog management we need to know if we have been
 823         ** paused during the last interval, so capture that here.
 824         */
 825         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 826         stats->xoffrxc += pause_frames;
 827         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 828         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 829         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 830         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 831         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 832         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 833         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 834         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 835         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 836         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 837         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 838         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 839
 840         /* For the 64-bit byte counters the low dword must be read first. */
 841         /* Both registers clear on the read of the high dword */
 842
 843         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 844         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 845         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 846         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 847
 848         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 849         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 850         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 851         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 852         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 853
 854         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 855         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 856
 857         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 858         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 859         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 860         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 861         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 862         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 863         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 864         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 865         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 866         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 867
 868         /* Interrupt Counts */
 869
 870         stats->iac += E1000_READ_REG(hw, E1000_IAC);
 871         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 872         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 873         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 874         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 875         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 876         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 877         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 878         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 879
 880         /* Host to Card Statistics */
 881
 882         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
 883         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
 884         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
 885         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
 886         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
 887         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
 888         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
 889         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
 890         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
 891         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
 892         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
 893         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
 894         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
 895         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
 896
 897         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 898         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 899         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 900         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 901         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 902         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 903
 904         if (rte_stats == NULL)
 905                 return;
 906
 907         /* Rx Errors */
 908         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 909             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 910
 911         /* Tx Errors */
 912         rte_stats->oerrors = stats->ecol + stats->latecol;
 913
 914         rte_stats->ipackets = stats->gprc;
 915         rte_stats->opackets = stats->gptc;
 916         rte_stats->ibytes   = stats->gorc;
 917         rte_stats->obytes   = stats->gotc;
 918 }
 919
 920 static void
 921 eth_igb_stats_reset(struct rte_eth_dev *dev)
 922 {
 923         struct e1000_hw_stats *hw_stats =
 924                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 925
 926         /* HW registers are cleared on read */
 927         eth_igb_stats_get(dev, NULL);
 928
 929         /* Reset software totals */
 930         memset(hw_stats, 0, sizeof(*hw_stats));
 931 }
 932
 933 static void
 934 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 935 {
 936         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 937         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
 938                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 939
 940         /* Good Rx packets, include VF loopback */
 941         UPDATE_VF_STAT(E1000_VFGPRC,
 942             hw_stats->last_gprc, hw_stats->gprc);
 943
 944         /* Good Rx octets, include VF loopback */
 945         UPDATE_VF_STAT(E1000_VFGORC,
 946             hw_stats->last_gorc, hw_stats->gorc);
 947
 948         /* Good Tx packets, include VF loopback */
 949         UPDATE_VF_STAT(E1000_VFGPTC,
 950             hw_stats->last_gptc, hw_stats->gptc);
 951
 952         /* Good Tx octets, include VF loopback */
 953         UPDATE_VF_STAT(E1000_VFGOTC,
 954             hw_stats->last_gotc, hw_stats->gotc);
 955
 956         /* Rx Multicst packets */
 957         UPDATE_VF_STAT(E1000_VFMPRC,
 958             hw_stats->last_mprc, hw_stats->mprc);
 959
 960         /* Good Rx loopback packets */
 961         UPDATE_VF_STAT(E1000_VFGPRLBC,
 962             hw_stats->last_gprlbc, hw_stats->gprlbc);
 963
 964         /* Good Rx loopback octets */
 965         UPDATE_VF_STAT(E1000_VFGORLBC,
 966             hw_stats->last_gorlbc, hw_stats->gorlbc);
 967
 968         /* Good Tx loopback packets */
 969         UPDATE_VF_STAT(E1000_VFGPTLBC,
 970             hw_stats->last_gptlbc, hw_stats->gptlbc);
 971
 972         /* Good Tx loopback octets */
 973         UPDATE_VF_STAT(E1000_VFGOTLBC,
 974             hw_stats->last_gotlbc, hw_stats->gotlbc);
 975
 976         if (rte_stats == NULL)
 977                 return;
 978
 979         memset(rte_stats, 0, sizeof(*rte_stats));
 980         rte_stats->ipackets = hw_stats->gprc;
 981         rte_stats->ibytes = hw_stats->gorc;
 982         rte_stats->opackets = hw_stats->gptc;
 983         rte_stats->obytes = hw_stats->gotc;
 984         rte_stats->imcasts = hw_stats->mprc;
 985         rte_stats->ilbpackets = hw_stats->gprlbc;
 986         rte_stats->ilbbytes = hw_stats->gorlbc;
 987         rte_stats->olbpackets = hw_stats->gptlbc;
 988         rte_stats->olbbytes = hw_stats->gotlbc;
 989
 990 }
 991
 992 static void
 993 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
 994 {
 995         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
 996                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 997
 998         /* Sync HW register to the last stats */
 999         eth_igbvf_stats_get(dev, NULL);
1000
1001         /* reset HW current stats*/
1002         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1003                offsetof(struct e1000_vf_stats, gprc));
1004
1005 }
1006
1007 static void
1008 eth_igb_infos_get(struct rte_eth_dev *dev,
1009                     struct rte_eth_dev_info *dev_info)
1010 {
1011         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1012
1013         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1014         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1015         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1016
1017         switch (hw->mac.type) {
1018         case e1000_82575:
1019                 dev_info->max_rx_queues = 4;
1020                 dev_info->max_tx_queues = 4;
1021                 break;
1022
1023         case e1000_82576:
1024                 dev_info->max_rx_queues = 16;
1025                 dev_info->max_tx_queues = 16;
1026                 break;
1027
1028         case e1000_82580:
1029                 dev_info->max_rx_queues = 8;
1030                 dev_info->max_tx_queues = 8;
1031                 break;
1032
1033         case e1000_i350:
1034                 dev_info->max_rx_queues = 8;
1035                 dev_info->max_tx_queues = 8;
1036                 break;
1037
1038         case e1000_i210:
1039                 dev_info->max_rx_queues = 4;
1040                 dev_info->max_tx_queues = 4;
1041                 break;
1042
1043         case e1000_vfadapt:
1044                 dev_info->max_rx_queues = 2;
1045                 dev_info->max_tx_queues = 2;
1046                 break;
1047
1048         case e1000_vfadapt_i350:
1049                 dev_info->max_rx_queues = 1;
1050                 dev_info->max_tx_queues = 1;
1051                 break;
1052
1053         default:
1054                 /* Should not happen */
1055                 dev_info->max_rx_queues = 0;
1056                 dev_info->max_tx_queues = 0;
1057         }
1058 }
1059
1060 /* return 0 means link status changed, -1 means not changed */
1061 static int
1062 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1063 {
1064         struct e1000_hw *hw =
1065                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1066         struct rte_eth_link link, old;
1067         int link_check, count;
1068
1069         link_check = 0;
1070         hw->mac.get_link_status = 1;
1071
1072         /* possible wait-to-complete in up to 9 seconds */
1073         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1074                 /* Read the real link status */
1075                 switch (hw->phy.media_type) {
1076                 case e1000_media_type_copper:
1077                         /* Do the work to read phy */
1078                         e1000_check_for_link(hw);
1079                         link_check = !hw->mac.get_link_status;
1080                         break;
1081
1082                 case e1000_media_type_fiber:
1083                         e1000_check_for_link(hw);
1084                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1085                                       E1000_STATUS_LU);
1086                         break;
1087
1088                 case e1000_media_type_internal_serdes:
1089                         e1000_check_for_link(hw);
1090                         link_check = hw->mac.serdes_has_link;
1091                         break;
1092
1093                 /* VF device is type_unknown */
1094                 case e1000_media_type_unknown:
1095                         eth_igbvf_link_update(hw);
1096                         link_check = !hw->mac.get_link_status;
1097                         break;
1098
1099                 default:
1100                         break;
1101                 }
1102                 if (link_check || wait_to_complete == 0)
1103                         break;
1104                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1105         }
1106         memset(&link, 0, sizeof(link));
1107         rte_igb_dev_atomic_read_link_status(dev, &link);
1108         old = link;
1109
1110         /* Now we check if a transition has happened */
1111         if (link_check) {
1112                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1113                                           &link.link_duplex);
1114                 link.link_status = 1;
1115         } else if (!link_check) {
1116                 link.link_speed = 0;
1117                 link.link_duplex = 0;
1118                 link.link_status = 0;
1119         }
1120         rte_igb_dev_atomic_write_link_status(dev, &link);
1121
1122         /* not changed */
1123         if (old.link_status == link.link_status)
1124                 return -1;
1125
1126         /* changed */
1127         return 0;
1128 }
1129
1130 /*
1131  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1132  * For ASF and Pass Through versions of f/w this means
1133  * that the driver is loaded.
1134  */
1135 static void
1136 igb_hw_control_acquire(struct e1000_hw *hw)
1137 {
1138         uint32_t ctrl_ext;
1139
1140         /* Let firmware know the driver has taken over */
1141         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1142         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1143 }
1144
1145 /*
1146  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1147  * For ASF and Pass Through versions of f/w this means that the
1148  * driver is no longer loaded.
1149  */
1150 static void
1151 igb_hw_control_release(struct e1000_hw *hw)
1152 {
1153         uint32_t ctrl_ext;
1154
1155         /* Let firmware taken over control of h/w */
1156         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1157         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1158                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1159 }
1160
1161 /*
1162  * Bit of a misnomer, what this really means is
1163  * to enable OS management of the system... aka
1164  * to disable special hardware management features.
1165  */
1166 static void
1167 igb_init_manageability(struct e1000_hw *hw)
1168 {
1169         if (e1000_enable_mng_pass_thru(hw)) {
1170                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1171                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1172
1173                 /* disable hardware interception of ARP */
1174                 manc &= ~(E1000_MANC_ARP_EN);
1175
1176                 /* enable receiving management packets to the host */
1177                 manc |= E1000_MANC_EN_MNG2HOST;
1178                 manc2h |= 1 << 5;  /* Mng Port 623 */
1179                 manc2h |= 1 << 6;  /* Mng Port 664 */
1180                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1181                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1182         }
1183 }
1184
1185 static void
1186 igb_release_manageability(struct e1000_hw *hw)
1187 {
1188         if (e1000_enable_mng_pass_thru(hw)) {
1189                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1190
1191                 manc |= E1000_MANC_ARP_EN;
1192                 manc &= ~E1000_MANC_EN_MNG2HOST;
1193
1194                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1195         }
1196 }
1197
1198 static void
1199 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1200 {
1201         struct e1000_hw *hw =
1202                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1203         uint32_t rctl;
1204
1205         rctl = E1000_READ_REG(hw, E1000_RCTL);
1206         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1207         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1208 }
1209
1210 static void
1211 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1212 {
1213         struct e1000_hw *hw =
1214                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1215         uint32_t rctl;
1216
1217         rctl = E1000_READ_REG(hw, E1000_RCTL);
1218         rctl &= (~E1000_RCTL_UPE);
1219         if (dev->data->all_multicast == 1)
1220                 rctl |= E1000_RCTL_MPE;
1221         else
1222                 rctl &= (~E1000_RCTL_MPE);
1223         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1224 }
1225
1226 static void
1227 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1228 {
1229         struct e1000_hw *hw =
1230                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1231         uint32_t rctl;
1232
1233         rctl = E1000_READ_REG(hw, E1000_RCTL);
1234         rctl |= E1000_RCTL_MPE;
1235         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1236 }
1237
1238 static void
1239 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1240 {
1241         struct e1000_hw *hw =
1242                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1243         uint32_t rctl;
1244
1245         if (dev->data->promiscuous == 1)
1246                 return; /* must remain in all_multicast mode */
1247         rctl = E1000_READ_REG(hw, E1000_RCTL);
1248         rctl &= (~E1000_RCTL_MPE);
1249         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1250 }
1251
1252 static int
1253 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1254 {
1255         struct e1000_hw *hw =
1256                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1257         struct e1000_vfta * shadow_vfta =
1258                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1259         uint32_t vfta;
1260         uint32_t vid_idx;
1261         uint32_t vid_bit;
1262
1263         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1264                               E1000_VFTA_ENTRY_MASK);
1265         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1266         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1267         if (on)
1268                 vfta |= vid_bit;
1269         else
1270                 vfta &= ~vid_bit;
1271         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1272
1273         /* update local VFTA copy */
1274         shadow_vfta->vfta[vid_idx] = vfta;
1275
1276         return 0;
1277 }
1278
1279 static void
1280 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1281 {
1282         struct e1000_hw *hw =
1283                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1284         uint32_t reg = ETHER_TYPE_VLAN ;
1285
1286         reg |= (tpid << 16);
1287         E1000_WRITE_REG(hw, E1000_VET, reg);
1288 }
1289
1290 static void
1291 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1292 {
1293         struct e1000_hw *hw =
1294                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1295         uint32_t reg;
1296
1297         /* Filter Table Disable */
1298         reg = E1000_READ_REG(hw, E1000_RCTL);
1299         reg &= ~E1000_RCTL_CFIEN;
1300         reg &= ~E1000_RCTL_VFE;
1301         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1302 }
1303
1304 static void
1305 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1306 {
1307         struct e1000_hw *hw =
1308                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1309         struct e1000_vfta * shadow_vfta =
1310                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1311         uint32_t reg;
1312         int i;
1313
1314         /* Filter Table Enable, CFI not used for packet acceptance */
1315         reg = E1000_READ_REG(hw, E1000_RCTL);
1316         reg &= ~E1000_RCTL_CFIEN;
1317         reg |= E1000_RCTL_VFE;
1318         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1319
1320         /* restore VFTA table */
1321         for (i = 0; i < IGB_VFTA_SIZE; i++)
1322                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1323 }
1324
1325 static void
1326 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1327 {
1328         struct e1000_hw *hw =
1329                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1330         uint32_t reg;
1331
1332         /* VLAN Mode Disable */
1333         reg = E1000_READ_REG(hw, E1000_CTRL);
1334         reg &= ~E1000_CTRL_VME;
1335         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1336
1337         /* Update maximum frame size */
1338         E1000_WRITE_REG(hw, E1000_RLPML,
1339                 dev->data->dev_conf.rxmode.max_rx_pkt_len + VLAN_TAG_SIZE);
1340 }
1341
1342 static void
1343 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1344 {
1345         struct e1000_hw *hw =
1346                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1347         uint32_t reg;
1348
1349         /* VLAN Mode Enable */
1350         reg = E1000_READ_REG(hw, E1000_CTRL);
1351         reg |= E1000_CTRL_VME;
1352         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1353
1354         /* Update maximum frame size */
1355         E1000_WRITE_REG(hw, E1000_RLPML,
1356                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1357
1358 }
1359
1360 static void
1361 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1362 {
1363         struct e1000_hw *hw =
1364                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1365         uint32_t reg;
1366
1367         /* CTRL_EXT: Extended VLAN */
1368         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1369         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1370         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1371
1372 }
1373
1374 static void
1375 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1376 {
1377         struct e1000_hw *hw =
1378                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1379         uint32_t reg;
1380
1381         /* CTRL_EXT: Extended VLAN */
1382         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1383         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1384         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1385 }
1386
1387 static void
1388 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1389 {
1390         if(mask & ETH_VLAN_STRIP_MASK){
1391                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1392                         igb_vlan_hw_strip_enable(dev);
1393                 else
1394                         igb_vlan_hw_strip_disable(dev);
1395         }
1396
1397         if(mask & ETH_VLAN_FILTER_MASK){
1398                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1399                         igb_vlan_hw_filter_enable(dev);
1400                 else
1401                         igb_vlan_hw_filter_disable(dev);
1402         }
1403
1404         if(mask & ETH_VLAN_EXTEND_MASK){
1405                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1406                         igb_vlan_hw_extend_enable(dev);
1407                 else
1408                         igb_vlan_hw_extend_disable(dev);
1409         }
1410 }
1411
1412 static void
1413 igb_intr_disable(struct e1000_hw *hw)
1414 {
1415         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1416         E1000_WRITE_FLUSH(hw);
1417 }
1418
1419 /**
1420  * It enables the interrupt mask and then enable the interrupt.
1421  *
1422  * @param dev
1423  *  Pointer to struct rte_eth_dev.
1424  *
1425  * @return
1426  *  - On success, zero.
1427  *  - On failure, a negative value.
1428  */
1429 static int
1430 eth_igb_interrupt_setup(struct rte_eth_dev *dev)
1431 {
1432         struct e1000_hw *hw =
1433                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1434
1435         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1436         E1000_WRITE_FLUSH(hw);
1437         rte_intr_enable(&(dev->pci_dev->intr_handle));
1438
1439         return 0;
1440 }
1441
1442 /*
1443  * It reads ICR and gets interrupt causes, check it and set a bit flag
1444  * to update link status.
1445  *
1446  * @param dev
1447  *  Pointer to struct rte_eth_dev.
1448  *
1449  * @return
1450  *  - On success, zero.
1451  *  - On failure, a negative value.
1452  */
1453 static int
1454 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1455 {
1456         uint32_t icr;
1457         struct e1000_hw *hw =
1458                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1459         struct e1000_interrupt *intr =
1460                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1461
1462         /* read-on-clear nic registers here */
1463         icr = E1000_READ_REG(hw, E1000_ICR);
1464         if (icr & E1000_ICR_LSC) {
1465                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1466         }
1467
1468         return 0;
1469 }
1470
1471 /*
1472  * It executes link_update after knowing an interrupt is prsent.
1473  *
1474  * @param dev
1475  *  Pointer to struct rte_eth_dev.
1476  *
1477  * @return
1478  *  - On success, zero.
1479  *  - On failure, a negative value.
1480  */
1481 static int
1482 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1483 {
1484         struct e1000_hw *hw =
1485                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1486         struct e1000_interrupt *intr =
1487                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1488         uint32_t tctl, rctl;
1489         struct rte_eth_link link;
1490         int ret;
1491
1492         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1493                 return -1;
1494
1495         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1496         rte_intr_enable(&(dev->pci_dev->intr_handle));
1497
1498         /* set get_link_status to check register later */
1499         hw->mac.get_link_status = 1;
1500         ret = eth_igb_link_update(dev, 0);
1501
1502         /* check if link has changed */
1503         if (ret < 0)
1504                 return 0;
1505
1506         memset(&link, 0, sizeof(link));
1507         rte_igb_dev_atomic_read_link_status(dev, &link);
1508         if (link.link_status) {
1509                 PMD_INIT_LOG(INFO,
1510                         " Port %d: Link Up - speed %u Mbps - %s\n",
1511                         dev->data->port_id, (unsigned)link.link_speed,
1512                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1513                                 "full-duplex" : "half-duplex");
1514         } else {
1515                 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1516                                         dev->data->port_id);
1517         }
1518         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1519                                 dev->pci_dev->addr.domain,
1520                                 dev->pci_dev->addr.bus,
1521                                 dev->pci_dev->addr.devid,
1522                                 dev->pci_dev->addr.function);
1523         tctl = E1000_READ_REG(hw, E1000_TCTL);
1524         rctl = E1000_READ_REG(hw, E1000_RCTL);
1525         if (link.link_status) {
1526                 /* enable Tx/Rx */
1527                 tctl |= E1000_TCTL_EN;
1528                 rctl |= E1000_RCTL_EN;
1529         } else {
1530                 /* disable Tx/Rx */
1531                 tctl &= ~E1000_TCTL_EN;
1532                 rctl &= ~E1000_RCTL_EN;
1533         }
1534         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1535         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1536         E1000_WRITE_FLUSH(hw);
1537
1538         return 0;
1539 }
1540
1541 /**
1542  * Interrupt handler which shall be registered at first.
1543  *
1544  * @param handle
1545  *  Pointer to interrupt handle.
1546  * @param param
1547  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1548  *
1549  * @return
1550  *  void
1551  */
1552 static void
1553 eth_igb_interrupt_handler(struct rte_intr_handle *handle, void *param)
1554 {
1555         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1556
1557         eth_igb_interrupt_get_status(dev);
1558         eth_igb_interrupt_action(dev);
1559         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1560 }
1561
1562 static int
1563 eth_igb_led_on(struct rte_eth_dev *dev)
1564 {
1565         struct e1000_hw *hw;
1566
1567         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1568         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1569 }
1570
1571 static int
1572 eth_igb_led_off(struct rte_eth_dev *dev)
1573 {
1574         struct e1000_hw *hw;
1575
1576         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1577         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1578 }
1579
1580 static int
1581 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1582 {
1583         struct e1000_hw *hw;
1584         int err;
1585         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1586                 e1000_fc_none,
1587                 e1000_fc_rx_pause,
1588                 e1000_fc_tx_pause,
1589                 e1000_fc_full
1590         };
1591         uint32_t rx_buf_size;
1592         uint32_t max_high_water;
1593
1594         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595         rx_buf_size = igb_get_rx_buffer_size(hw);
1596         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1597
1598         /* At least reserve one Ethernet frame for watermark */
1599         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1600         if ((fc_conf->high_water > max_high_water) ||
1601                 (fc_conf->high_water < fc_conf->low_water)) {
1602                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1603                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1604                 return (-EINVAL);
1605         }
1606
1607         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1608         hw->fc.pause_time     = fc_conf->pause_time;
1609         hw->fc.high_water     = fc_conf->high_water;
1610         hw->fc.low_water      = fc_conf->low_water;
1611         hw->fc.send_xon       = fc_conf->send_xon;
1612
1613         err = e1000_setup_link_generic(hw);
1614         if (err == E1000_SUCCESS) {
1615                 return 0;
1616         }
1617
1618         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1619         return (-EIO);
1620 }
1621
1622 static void
1623 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1624                 uint32_t index, __rte_unused uint32_t pool)
1625 {
1626         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1627
1628         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1629 }
1630
1631 static void
1632 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1633 {
1634         uint8_t addr[ETHER_ADDR_LEN];
1635         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1636
1637         memset(addr, 0, sizeof(addr));
1638
1639         e1000_rar_set(hw, addr, index);
1640 }
1641
1642 /*
1643  * Virtual Function operations
1644  */
1645 static void
1646 igbvf_intr_disable(struct e1000_hw *hw)
1647 {
1648         PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1649
1650         /* Clear interrupt mask to stop from interrupts being generated */
1651         E1000_WRITE_REG(hw, E1000_EIMC, ~0);
1652
1653         E1000_WRITE_FLUSH(hw);
1654 }
1655
1656 static void
1657 igbvf_stop_adapter(struct rte_eth_dev *dev)
1658 {
1659         u32 reg_val;
1660         u16 i;
1661         struct rte_eth_dev_info dev_info;
1662         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663
1664         memset(&dev_info, 0, sizeof(dev_info));
1665         eth_igb_infos_get(dev, &dev_info);
1666
1667         /* Clear interrupt mask to stop from interrupts being generated */
1668         E1000_WRITE_REG(hw, E1000_EIMC, ~0);
1669
1670         /* Clear any pending interrupts, flush previous writes */
1671         E1000_READ_REG(hw, E1000_EICR);
1672
1673         /* Disable the transmit unit.  Each queue must be disabled. */
1674         for (i = 0; i < dev_info.max_tx_queues; i++)
1675                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1676
1677         /* Disable the receive unit by stopping each queue */
1678         for (i = 0; i < dev_info.max_rx_queues; i++) {
1679                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1680                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1681                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1682                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1683                         ;
1684         }
1685
1686         /* flush all queues disables */
1687         E1000_WRITE_FLUSH(hw);
1688         msec_delay(2);
1689 }
1690
1691 static int eth_igbvf_link_update(struct e1000_hw *hw)
1692 {
1693         struct e1000_mbx_info *mbx = &hw->mbx;
1694         struct e1000_mac_info *mac = &hw->mac;
1695         int ret_val = E1000_SUCCESS;
1696
1697         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1698
1699         /*
1700          * We only want to run this if there has been a rst asserted.
1701          * in this case that could mean a link change, device reset,
1702          * or a virtual function reset
1703          */
1704
1705         /* If we were hit with a reset or timeout drop the link */
1706         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1707                 mac->get_link_status = TRUE;
1708
1709         if (!mac->get_link_status)
1710                 goto out;
1711
1712         /* if link status is down no point in checking to see if pf is up */
1713         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1714                 goto out;
1715
1716         /* if we passed all the tests above then the link is up and we no
1717          * longer need to check for link */
1718         mac->get_link_status = FALSE;
1719
1720 out:
1721         return ret_val;
1722 }
1723
1724
1725 static int
1726 igbvf_dev_configure(struct rte_eth_dev *dev)
1727 {
1728         struct rte_eth_conf* conf = &dev->data->dev_conf;
1729
1730         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1731                 dev->data->port_id);
1732
1733         /*
1734          * VF has no ability to enable/disable HW CRC
1735          * Keep the persistent behavior the same as Host PF
1736          */
1737 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1738         if (!conf->rxmode.hw_strip_crc) {
1739                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1740                 conf->rxmode.hw_strip_crc = 1;
1741         }
1742 #else
1743         if (conf->rxmode.hw_strip_crc) {
1744                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1745                 conf->rxmode.hw_strip_crc = 0;
1746         }
1747 #endif
1748
1749         return 0;
1750 }
1751
1752 static int
1753 igbvf_dev_start(struct rte_eth_dev *dev)
1754 {
1755         int ret;
1756
1757         PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1758
1759         /* Set all vfta */
1760         igbvf_set_vfta_all(dev,1);
1761
1762         eth_igbvf_tx_init(dev);
1763
1764         /* This can fail when allocating mbufs for descriptor rings */
1765         ret = eth_igbvf_rx_init(dev);
1766         if (ret) {
1767                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1768                 igb_dev_clear_queues(dev);
1769                 return ret;
1770         }
1771
1772         return 0;
1773 }
1774
1775 static void
1776 igbvf_dev_stop(struct rte_eth_dev *dev)
1777 {
1778         PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1779
1780         igbvf_stop_adapter(dev);
1781
1782         /*
1783           * Clear what we set, but we still keep shadow_vfta to
1784           * restore after device starts
1785           */
1786         igbvf_set_vfta_all(dev,0);
1787
1788         igb_dev_clear_queues(dev);
1789 }
1790
1791 static void
1792 igbvf_dev_close(struct rte_eth_dev *dev)
1793 {
1794         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1795
1796         PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1797
1798         e1000_reset_hw(hw);
1799
1800         igbvf_dev_stop(dev);
1801 }
1802
1803 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1804 {
1805         struct e1000_mbx_info *mbx = &hw->mbx;
1806         uint32_t msgbuf[2];
1807
1808         /* After set vlan, vlan strip will also be enabled in igb driver*/
1809         msgbuf[0] = E1000_VF_SET_VLAN;
1810         msgbuf[1] = vid;
1811         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1812         if (on)
1813                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1814
1815         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1816 }
1817
1818 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1819 {
1820         struct e1000_hw *hw =
1821                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1822         struct e1000_vfta * shadow_vfta =
1823                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1824         int i = 0, j = 0, vfta = 0, mask = 1;
1825
1826         for (i = 0; i < IGB_VFTA_SIZE; i++){
1827                 vfta = shadow_vfta->vfta[i];
1828                 if(vfta){
1829                         mask = 1;
1830                         for (j = 0; j < 32; j++){
1831                                 if(vfta & mask)
1832                                         igbvf_set_vfta(hw, (i<<5)+j, on);
1833                                 mask<<=1;
1834                         }
1835                 }
1836         }
1837
1838 }
1839
1840 static int
1841 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1842 {
1843         struct e1000_hw *hw =
1844                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct e1000_vfta * shadow_vfta =
1846                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1847         uint32_t vid_idx = 0;
1848         uint32_t vid_bit = 0;
1849         int ret = 0;
1850
1851         PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
1852
1853         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
1854         ret = igbvf_set_vfta(hw, vlan_id, !!on);
1855         if(ret){
1856                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
1857                 return ret;
1858         }
1859         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1860         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1861
1862         /*Save what we set and retore it after device reset*/
1863         if (on)
1864                 shadow_vfta->vfta[vid_idx] |= vid_bit;
1865         else
1866                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
1867
1868         return 0;
1869 }
1870