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34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_tailq.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "e1000/e1000_api.h"
58 #include "e1000_ethdev.h"
60 static int eth_igb_configure(struct rte_eth_dev *dev);
61 static int eth_igb_start(struct rte_eth_dev *dev);
62 static void eth_igb_stop(struct rte_eth_dev *dev);
63 static void eth_igb_close(struct rte_eth_dev *dev);
64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
68 static int eth_igb_link_update(struct rte_eth_dev *dev,
69 int wait_to_complete);
70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
71 struct rte_eth_stats *rte_stats);
72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
74 struct rte_eth_dev_info *dev_info);
75 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
76 struct rte_eth_fc_conf *fc_conf);
77 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
78 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
79 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
80 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
82 static int igb_hardware_init(struct e1000_hw *hw);
83 static void igb_hw_control_acquire(struct e1000_hw *hw);
84 static void igb_hw_control_release(struct e1000_hw *hw);
85 static void igb_init_manageability(struct e1000_hw *hw);
86 static void igb_release_manageability(struct e1000_hw *hw);
88 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
89 uint16_t vlan_id, int on);
90 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
91 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
94 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
95 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
96 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
97 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
98 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
100 static int eth_igb_led_on(struct rte_eth_dev *dev);
101 static int eth_igb_led_off(struct rte_eth_dev *dev);
103 static void igb_intr_disable(struct e1000_hw *hw);
104 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
105 static void eth_igb_rar_set(struct rte_eth_dev *dev,
106 struct ether_addr *mac_addr,
107 uint32_t index, uint32_t pool);
108 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
110 static void igbvf_intr_disable(struct e1000_hw *hw);
111 static int igbvf_dev_configure(struct rte_eth_dev *dev);
112 static int igbvf_dev_start(struct rte_eth_dev *dev);
113 static void igbvf_dev_stop(struct rte_eth_dev *dev);
114 static void igbvf_dev_close(struct rte_eth_dev *dev);
115 static int eth_igbvf_link_update(struct e1000_hw *hw);
116 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
117 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
118 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
119 uint16_t vlan_id, int on);
120 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
121 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
122 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
123 struct rte_eth_rss_reta *reta_conf);
124 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
125 struct rte_eth_rss_reta *reta_conf);
127 static int eth_igb_add_syn_filter(struct rte_eth_dev *dev,
128 struct rte_syn_filter *filter, uint16_t rx_queue);
129 static int eth_igb_remove_syn_filter(struct rte_eth_dev *dev);
130 static int eth_igb_get_syn_filter(struct rte_eth_dev *dev,
131 struct rte_syn_filter *filter, uint16_t *rx_queue);
132 static int eth_igb_add_ethertype_filter(struct rte_eth_dev *dev,
134 struct rte_ethertype_filter *filter, uint16_t rx_queue);
135 static int eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev,
137 static int eth_igb_get_ethertype_filter(struct rte_eth_dev *dev,
139 struct rte_ethertype_filter *filter, uint16_t *rx_queue);
140 static int eth_igb_add_2tuple_filter(struct rte_eth_dev *dev,
142 struct rte_2tuple_filter *filter, uint16_t rx_queue);
143 static int eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
145 static int eth_igb_get_2tuple_filter(struct rte_eth_dev *dev,
147 struct rte_2tuple_filter *filter, uint16_t *rx_queue);
148 static int eth_igb_add_flex_filter(struct rte_eth_dev *dev,
150 struct rte_flex_filter *filter, uint16_t rx_queue);
151 static int eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
153 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
155 struct rte_flex_filter *filter, uint16_t *rx_queue);
156 static int eth_igb_add_5tuple_filter(struct rte_eth_dev *dev,
158 struct rte_5tuple_filter *filter, uint16_t rx_queue);
159 static int eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
161 static int eth_igb_get_5tuple_filter(struct rte_eth_dev *dev,
163 struct rte_5tuple_filter *filter, uint16_t *rx_queue);
166 * Define VF Stats MACRO for Non "cleared on read" register
168 #define UPDATE_VF_STAT(reg, last, cur) \
170 u32 latest = E1000_READ_REG(hw, reg); \
171 cur += latest - last; \
176 #define IGB_FC_PAUSE_TIME 0x0680
177 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
178 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
180 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
182 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
185 * The set of PCI devices this driver supports
187 static struct rte_pci_id pci_id_igb_map[] = {
189 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
190 #include "rte_pci_dev_ids.h"
196 * The set of PCI devices this driver supports (for 82576&I350 VF)
198 static struct rte_pci_id pci_id_igbvf_map[] = {
200 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
201 #include "rte_pci_dev_ids.h"
206 static struct eth_dev_ops eth_igb_ops = {
207 .dev_configure = eth_igb_configure,
208 .dev_start = eth_igb_start,
209 .dev_stop = eth_igb_stop,
210 .dev_close = eth_igb_close,
211 .promiscuous_enable = eth_igb_promiscuous_enable,
212 .promiscuous_disable = eth_igb_promiscuous_disable,
213 .allmulticast_enable = eth_igb_allmulticast_enable,
214 .allmulticast_disable = eth_igb_allmulticast_disable,
215 .link_update = eth_igb_link_update,
216 .stats_get = eth_igb_stats_get,
217 .stats_reset = eth_igb_stats_reset,
218 .dev_infos_get = eth_igb_infos_get,
219 .vlan_filter_set = eth_igb_vlan_filter_set,
220 .vlan_tpid_set = eth_igb_vlan_tpid_set,
221 .vlan_offload_set = eth_igb_vlan_offload_set,
222 .rx_queue_setup = eth_igb_rx_queue_setup,
223 .rx_queue_release = eth_igb_rx_queue_release,
224 .rx_queue_count = eth_igb_rx_queue_count,
225 .rx_descriptor_done = eth_igb_rx_descriptor_done,
226 .tx_queue_setup = eth_igb_tx_queue_setup,
227 .tx_queue_release = eth_igb_tx_queue_release,
228 .dev_led_on = eth_igb_led_on,
229 .dev_led_off = eth_igb_led_off,
230 .flow_ctrl_set = eth_igb_flow_ctrl_set,
231 .mac_addr_add = eth_igb_rar_set,
232 .mac_addr_remove = eth_igb_rar_clear,
233 .reta_update = eth_igb_rss_reta_update,
234 .reta_query = eth_igb_rss_reta_query,
235 .rss_hash_update = eth_igb_rss_hash_update,
236 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
237 .add_syn_filter = eth_igb_add_syn_filter,
238 .remove_syn_filter = eth_igb_remove_syn_filter,
239 .get_syn_filter = eth_igb_get_syn_filter,
240 .add_ethertype_filter = eth_igb_add_ethertype_filter,
241 .remove_ethertype_filter = eth_igb_remove_ethertype_filter,
242 .get_ethertype_filter = eth_igb_get_ethertype_filter,
243 .add_2tuple_filter = eth_igb_add_2tuple_filter,
244 .remove_2tuple_filter = eth_igb_remove_2tuple_filter,
245 .get_2tuple_filter = eth_igb_get_2tuple_filter,
246 .add_flex_filter = eth_igb_add_flex_filter,
247 .remove_flex_filter = eth_igb_remove_flex_filter,
248 .get_flex_filter = eth_igb_get_flex_filter,
249 .add_5tuple_filter = eth_igb_add_5tuple_filter,
250 .remove_5tuple_filter = eth_igb_remove_5tuple_filter,
251 .get_5tuple_filter = eth_igb_get_5tuple_filter,
255 * dev_ops for virtual function, bare necessities for basic vf
256 * operation have been implemented
258 static struct eth_dev_ops igbvf_eth_dev_ops = {
259 .dev_configure = igbvf_dev_configure,
260 .dev_start = igbvf_dev_start,
261 .dev_stop = igbvf_dev_stop,
262 .dev_close = igbvf_dev_close,
263 .link_update = eth_igb_link_update,
264 .stats_get = eth_igbvf_stats_get,
265 .stats_reset = eth_igbvf_stats_reset,
266 .vlan_filter_set = igbvf_vlan_filter_set,
267 .dev_infos_get = eth_igb_infos_get,
268 .rx_queue_setup = eth_igb_rx_queue_setup,
269 .rx_queue_release = eth_igb_rx_queue_release,
270 .tx_queue_setup = eth_igb_tx_queue_setup,
271 .tx_queue_release = eth_igb_tx_queue_release,
275 * Atomically reads the link status information from global
276 * structure rte_eth_dev.
279 * - Pointer to the structure rte_eth_dev to read from.
280 * - Pointer to the buffer to be saved with the link status.
283 * - On success, zero.
284 * - On failure, negative value.
287 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
288 struct rte_eth_link *link)
290 struct rte_eth_link *dst = link;
291 struct rte_eth_link *src = &(dev->data->dev_link);
293 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
294 *(uint64_t *)src) == 0)
301 * Atomically writes the link status information into global
302 * structure rte_eth_dev.
305 * - Pointer to the structure rte_eth_dev to read from.
306 * - Pointer to the buffer to be saved with the link status.
309 * - On success, zero.
310 * - On failure, negative value.
313 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
314 struct rte_eth_link *link)
316 struct rte_eth_link *dst = &(dev->data->dev_link);
317 struct rte_eth_link *src = link;
319 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
320 *(uint64_t *)src) == 0)
327 igb_intr_enable(struct rte_eth_dev *dev)
329 struct e1000_interrupt *intr =
330 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
331 struct e1000_hw *hw =
332 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
334 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
335 E1000_WRITE_FLUSH(hw);
339 igb_intr_disable(struct e1000_hw *hw)
341 E1000_WRITE_REG(hw, E1000_IMC, ~0);
342 E1000_WRITE_FLUSH(hw);
345 static inline int32_t
346 igb_pf_reset_hw(struct e1000_hw *hw)
351 status = e1000_reset_hw(hw);
353 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
354 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
355 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
356 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
357 E1000_WRITE_FLUSH(hw);
363 igb_identify_hardware(struct rte_eth_dev *dev)
365 struct e1000_hw *hw =
366 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
368 hw->vendor_id = dev->pci_dev->id.vendor_id;
369 hw->device_id = dev->pci_dev->id.device_id;
370 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
371 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
373 e1000_set_mac_type(hw);
375 /* need to check if it is a vf device below */
379 igb_reset_swfw_lock(struct e1000_hw *hw)
384 * Do mac ops initialization manually here, since we will need
385 * some function pointers set by this call.
387 ret_val = e1000_init_mac_params(hw);
392 * SMBI lock should not fail in this early stage. If this is the case,
393 * it is due to an improper exit of the application.
394 * So force the release of the faulty lock.
396 if (e1000_get_hw_semaphore_generic(hw) < 0) {
397 DEBUGOUT("SMBI lock released");
399 e1000_put_hw_semaphore_generic(hw);
401 if (hw->mac.ops.acquire_swfw_sync != NULL) {
405 * Phy lock should not fail in this early stage. If this is the case,
406 * it is due to an improper exit of the application.
407 * So force the release of the faulty lock.
409 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
410 if (hw->bus.func > E1000_FUNC_1)
412 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
413 DEBUGOUT1("SWFW phy%d lock released", hw->bus.func);
415 hw->mac.ops.release_swfw_sync(hw, mask);
418 * This one is more tricky since it is common to all ports; but
419 * swfw_sync retries last long enough (1s) to be almost sure that if
420 * lock can not be taken it is due to an improper lock of the
423 mask = E1000_SWFW_EEP_SM;
424 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
425 DEBUGOUT("SWFW common locks released");
427 hw->mac.ops.release_swfw_sync(hw, mask);
430 return E1000_SUCCESS;
434 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
435 struct rte_eth_dev *eth_dev)
438 struct rte_pci_device *pci_dev;
439 struct e1000_hw *hw =
440 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
441 struct e1000_vfta * shadow_vfta =
442 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
445 pci_dev = eth_dev->pci_dev;
446 eth_dev->dev_ops = ð_igb_ops;
447 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
448 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
450 /* for secondary processes, we don't initialise any further as primary
451 * has already done this work. Only check we don't need a different
453 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
454 if (eth_dev->data->scattered_rx)
455 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
459 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
461 igb_identify_hardware(eth_dev);
462 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
467 e1000_get_bus_info(hw);
469 /* Reset any pending lock */
470 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
475 /* Finish initialization */
476 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
482 hw->phy.autoneg_wait_to_complete = 0;
483 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
486 if (hw->phy.media_type == e1000_media_type_copper) {
487 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
488 hw->phy.disable_polarity_correction = 0;
489 hw->phy.ms_type = e1000_ms_hw_default;
493 * Start from a known state, this is important in reading the nvm
498 /* Make sure we have a good EEPROM before we read from it */
499 if (e1000_validate_nvm_checksum(hw) < 0) {
501 * Some PCI-E parts fail the first check due to
502 * the link being in sleep state, call it again,
503 * if it fails a second time its a real issue.
505 if (e1000_validate_nvm_checksum(hw) < 0) {
506 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
512 /* Read the permanent MAC address out of the EEPROM */
513 if (e1000_read_mac_addr(hw) != 0) {
514 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
519 /* Allocate memory for storing MAC addresses */
520 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
521 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
522 if (eth_dev->data->mac_addrs == NULL) {
523 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
524 "store MAC addresses",
525 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
530 /* Copy the permanent MAC address */
531 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
533 /* initialize the vfta */
534 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
536 /* Now initialize the hardware */
537 if (igb_hardware_init(hw) != 0) {
538 PMD_INIT_LOG(ERR, "Hardware initialization failed");
539 rte_free(eth_dev->data->mac_addrs);
540 eth_dev->data->mac_addrs = NULL;
544 hw->mac.get_link_status = 1;
546 /* Indicate SOL/IDER usage */
547 if (e1000_check_reset_block(hw) < 0) {
548 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
552 /* initialize PF if max_vfs not zero */
553 igb_pf_host_init(eth_dev);
555 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
556 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
557 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
558 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
559 E1000_WRITE_FLUSH(hw);
561 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
562 eth_dev->data->port_id, pci_dev->id.vendor_id,
563 pci_dev->id.device_id);
565 rte_intr_callback_register(&(pci_dev->intr_handle),
566 eth_igb_interrupt_handler, (void *)eth_dev);
568 /* enable uio intr after callback register */
569 rte_intr_enable(&(pci_dev->intr_handle));
571 /* enable support intr */
572 igb_intr_enable(eth_dev);
577 igb_hw_control_release(hw);
583 * Virtual Function device init
586 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
587 struct rte_eth_dev *eth_dev)
589 struct rte_pci_device *pci_dev;
590 struct e1000_hw *hw =
591 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
594 PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
596 eth_dev->dev_ops = &igbvf_eth_dev_ops;
597 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
598 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
600 /* for secondary processes, we don't initialise any further as primary
601 * has already done this work. Only check we don't need a different
603 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
604 if (eth_dev->data->scattered_rx)
605 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
609 pci_dev = eth_dev->pci_dev;
611 hw->device_id = pci_dev->id.device_id;
612 hw->vendor_id = pci_dev->id.vendor_id;
613 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
615 /* Initialize the shared code */
616 diag = e1000_setup_init_funcs(hw, TRUE);
618 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
623 /* init_mailbox_params */
624 hw->mbx.ops.init_params(hw);
626 /* Disable the interrupts for VF */
627 igbvf_intr_disable(hw);
629 diag = hw->mac.ops.reset_hw(hw);
631 /* Allocate memory for storing MAC addresses */
632 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
633 hw->mac.rar_entry_count, 0);
634 if (eth_dev->data->mac_addrs == NULL) {
636 "Failed to allocate %d bytes needed to store MAC "
638 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
642 /* Copy the permanent MAC address */
643 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
644 ð_dev->data->mac_addrs[0]);
646 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
648 eth_dev->data->port_id, pci_dev->id.vendor_id,
649 pci_dev->id.device_id,
655 static struct eth_driver rte_igb_pmd = {
657 .name = "rte_igb_pmd",
658 .id_table = pci_id_igb_map,
659 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
661 .eth_dev_init = eth_igb_dev_init,
662 .dev_private_size = sizeof(struct e1000_adapter),
666 * virtual function driver struct
668 static struct eth_driver rte_igbvf_pmd = {
670 .name = "rte_igbvf_pmd",
671 .id_table = pci_id_igbvf_map,
672 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
674 .eth_dev_init = eth_igbvf_dev_init,
675 .dev_private_size = sizeof(struct e1000_adapter),
679 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
681 rte_eth_driver_register(&rte_igb_pmd);
686 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
688 struct e1000_hw *hw =
689 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
690 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
691 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
692 rctl |= E1000_RCTL_VFE;
693 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
697 * VF Driver initialization routine.
698 * Invoked one at EAL init time.
699 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
702 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
704 DEBUGFUNC("rte_igbvf_pmd_init");
706 rte_eth_driver_register(&rte_igbvf_pmd);
711 eth_igb_configure(struct rte_eth_dev *dev)
713 struct e1000_interrupt *intr =
714 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
716 PMD_INIT_LOG(DEBUG, ">>");
718 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
720 PMD_INIT_LOG(DEBUG, "<<");
726 eth_igb_start(struct rte_eth_dev *dev)
728 struct e1000_hw *hw =
729 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
733 PMD_INIT_LOG(DEBUG, ">>");
735 /* Power up the phy. Needed to make the link go Up */
736 e1000_power_up_phy(hw);
739 * Packet Buffer Allocation (PBA)
740 * Writing PBA sets the receive portion of the buffer
741 * the remainder is used for the transmit buffer.
743 if (hw->mac.type == e1000_82575) {
746 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
747 E1000_WRITE_REG(hw, E1000_PBA, pba);
750 /* Put the address into the Receive Address Array */
751 e1000_rar_set(hw, hw->mac.addr, 0);
753 /* Initialize the hardware */
754 if (igb_hardware_init(hw)) {
755 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
759 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
761 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
762 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
763 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
764 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
765 E1000_WRITE_FLUSH(hw);
767 /* configure PF module if SRIOV enabled */
768 igb_pf_host_configure(dev);
770 /* Configure for OS presence */
771 igb_init_manageability(hw);
773 eth_igb_tx_init(dev);
775 /* This can fail when allocating mbufs for descriptor rings */
776 ret = eth_igb_rx_init(dev);
778 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
779 igb_dev_clear_queues(dev);
783 e1000_clear_hw_cntrs_base_generic(hw);
786 * VLAN Offload Settings
788 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
789 ETH_VLAN_EXTEND_MASK;
790 eth_igb_vlan_offload_set(dev, mask);
792 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
793 /* Enable VLAN filter since VMDq always use VLAN filter */
794 igb_vmdq_vlan_hw_filter_enable(dev);
798 * Configure the Interrupt Moderation register (EITR) with the maximum
799 * possible value (0xFFFF) to minimize "System Partial Write" issued by
800 * spurious [DMA] memory updates of RX and TX ring descriptors.
802 * With a EITR granularity of 2 microseconds in the 82576, only 7/8
803 * spurious memory updates per second should be expected.
804 * ((65535 * 2) / 1000.1000 ~= 0.131 second).
806 * Because interrupts are not used at all, the MSI-X is not activated
807 * and interrupt moderation is controlled by EITR[0].
809 * Note that having [almost] disabled memory updates of RX and TX ring
810 * descriptors through the Interrupt Moderation mechanism, memory
811 * updates of ring descriptors are now moderated by the configurable
812 * value of Write-Back Threshold registers.
814 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
815 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
818 /* Enable all RX & TX queues in the IVAR registers */
819 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
820 for (i = 0; i < 8; i++)
821 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
823 /* Configure EITR with the maximum possible value (0xFFFF) */
824 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
827 /* Setup link speed and duplex */
828 switch (dev->data->dev_conf.link_speed) {
829 case ETH_LINK_SPEED_AUTONEG:
830 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
831 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
832 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
833 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
834 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
835 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
837 goto error_invalid_config;
839 case ETH_LINK_SPEED_10:
840 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
841 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
842 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
843 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
844 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
845 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
847 goto error_invalid_config;
849 case ETH_LINK_SPEED_100:
850 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
851 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
852 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
853 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
854 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
855 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
857 goto error_invalid_config;
859 case ETH_LINK_SPEED_1000:
860 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
861 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
862 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
864 goto error_invalid_config;
866 case ETH_LINK_SPEED_10000:
868 goto error_invalid_config;
870 e1000_setup_link(hw);
872 /* check if lsc interrupt feature is enabled */
873 if (dev->data->dev_conf.intr_conf.lsc != 0)
874 ret = eth_igb_lsc_interrupt_setup(dev);
876 /* resume enabled intr since hw reset */
877 igb_intr_enable(dev);
879 PMD_INIT_LOG(DEBUG, "<<");
883 error_invalid_config:
884 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
885 dev->data->dev_conf.link_speed,
886 dev->data->dev_conf.link_duplex, dev->data->port_id);
887 igb_dev_clear_queues(dev);
891 /*********************************************************************
893 * This routine disables all traffic on the adapter by issuing a
894 * global reset on the MAC.
896 **********************************************************************/
898 eth_igb_stop(struct rte_eth_dev *dev)
900 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
901 struct rte_eth_link link;
903 igb_intr_disable(hw);
905 E1000_WRITE_REG(hw, E1000_WUC, 0);
907 /* Set bit for Go Link disconnect */
908 if (hw->mac.type >= e1000_82580) {
911 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
912 phpm_reg |= E1000_82580_PM_GO_LINKD;
913 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
916 /* Power down the phy. Needed to make the link go Down */
917 e1000_power_down_phy(hw);
919 igb_dev_clear_queues(dev);
921 /* clear the recorded link status */
922 memset(&link, 0, sizeof(link));
923 rte_igb_dev_atomic_write_link_status(dev, &link);
927 eth_igb_close(struct rte_eth_dev *dev)
929 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
930 struct rte_eth_link link;
933 e1000_phy_hw_reset(hw);
934 igb_release_manageability(hw);
935 igb_hw_control_release(hw);
937 /* Clear bit for Go Link disconnect */
938 if (hw->mac.type >= e1000_82580) {
941 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
942 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
943 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
946 igb_dev_clear_queues(dev);
948 memset(&link, 0, sizeof(link));
949 rte_igb_dev_atomic_write_link_status(dev, &link);
953 igb_get_rx_buffer_size(struct e1000_hw *hw)
955 uint32_t rx_buf_size;
956 if (hw->mac.type == e1000_82576) {
957 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
958 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
959 /* PBS needs to be translated according to a lookup table */
960 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
961 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
962 rx_buf_size = (rx_buf_size << 10);
963 } else if (hw->mac.type == e1000_i210) {
964 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
966 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
972 /*********************************************************************
974 * Initialize the hardware
976 **********************************************************************/
978 igb_hardware_init(struct e1000_hw *hw)
980 uint32_t rx_buf_size;
983 /* Let the firmware know the OS is in control */
984 igb_hw_control_acquire(hw);
987 * These parameters control the automatic generation (Tx) and
988 * response (Rx) to Ethernet PAUSE frames.
989 * - High water mark should allow for at least two standard size (1518)
990 * frames to be received after sending an XOFF.
991 * - Low water mark works best when it is very near the high water mark.
992 * This allows the receiver to restart by sending XON when it has
993 * drained a bit. Here we use an arbitrary value of 1500 which will
994 * restart after one full frame is pulled from the buffer. There
995 * could be several smaller frames in the buffer and if so they will
996 * not trigger the XON until their total number reduces the buffer
998 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1000 rx_buf_size = igb_get_rx_buffer_size(hw);
1002 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1003 hw->fc.low_water = hw->fc.high_water - 1500;
1004 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1005 hw->fc.send_xon = 1;
1007 /* Set Flow control, use the tunable location if sane */
1008 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1009 hw->fc.requested_mode = igb_fc_setting;
1011 hw->fc.requested_mode = e1000_fc_none;
1013 /* Issue a global reset */
1014 igb_pf_reset_hw(hw);
1015 E1000_WRITE_REG(hw, E1000_WUC, 0);
1017 diag = e1000_init_hw(hw);
1021 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1022 e1000_get_phy_info(hw);
1023 e1000_check_for_link(hw);
1028 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1030 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1032 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1033 struct e1000_hw_stats *stats =
1034 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1037 if(hw->phy.media_type == e1000_media_type_copper ||
1038 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1040 E1000_READ_REG(hw,E1000_SYMERRS);
1041 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1044 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1045 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1046 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1047 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1049 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1050 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1051 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1052 stats->dc += E1000_READ_REG(hw, E1000_DC);
1053 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1054 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1055 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1057 ** For watchdog management we need to know if we have been
1058 ** paused during the last interval, so capture that here.
1060 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1061 stats->xoffrxc += pause_frames;
1062 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1063 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1064 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1065 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1066 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1067 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1068 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1069 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1070 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1071 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1072 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1073 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1075 /* For the 64-bit byte counters the low dword must be read first. */
1076 /* Both registers clear on the read of the high dword */
1078 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1079 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1080 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1081 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1083 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1084 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1085 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1086 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1087 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1089 stats->tor += E1000_READ_REG(hw, E1000_TORH);
1090 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1092 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1093 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1094 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1095 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1096 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1097 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1098 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1099 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1100 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1101 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1103 /* Interrupt Counts */
1105 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1106 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1107 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1108 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1109 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1110 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1111 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1112 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1113 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1115 /* Host to Card Statistics */
1117 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1118 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1119 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1120 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1121 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1122 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1123 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1124 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1125 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1126 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1127 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1128 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1129 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1130 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1132 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1133 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1134 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1135 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1136 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1137 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1139 if (rte_stats == NULL)
1143 rte_stats->ibadcrc = stats->crcerrs;
1144 rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1145 rte_stats->imissed = stats->mpc;
1146 rte_stats->ierrors = rte_stats->ibadcrc +
1147 rte_stats->ibadlen +
1148 rte_stats->imissed +
1149 stats->rxerrc + stats->algnerrc + stats->cexterr;
1152 rte_stats->oerrors = stats->ecol + stats->latecol;
1154 /* XON/XOFF pause frames */
1155 rte_stats->tx_pause_xon = stats->xontxc;
1156 rte_stats->rx_pause_xon = stats->xonrxc;
1157 rte_stats->tx_pause_xoff = stats->xofftxc;
1158 rte_stats->rx_pause_xoff = stats->xoffrxc;
1160 rte_stats->ipackets = stats->gprc;
1161 rte_stats->opackets = stats->gptc;
1162 rte_stats->ibytes = stats->gorc;
1163 rte_stats->obytes = stats->gotc;
1167 eth_igb_stats_reset(struct rte_eth_dev *dev)
1169 struct e1000_hw_stats *hw_stats =
1170 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1172 /* HW registers are cleared on read */
1173 eth_igb_stats_get(dev, NULL);
1175 /* Reset software totals */
1176 memset(hw_stats, 0, sizeof(*hw_stats));
1180 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1182 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1183 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1184 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1186 /* Good Rx packets, include VF loopback */
1187 UPDATE_VF_STAT(E1000_VFGPRC,
1188 hw_stats->last_gprc, hw_stats->gprc);
1190 /* Good Rx octets, include VF loopback */
1191 UPDATE_VF_STAT(E1000_VFGORC,
1192 hw_stats->last_gorc, hw_stats->gorc);
1194 /* Good Tx packets, include VF loopback */
1195 UPDATE_VF_STAT(E1000_VFGPTC,
1196 hw_stats->last_gptc, hw_stats->gptc);
1198 /* Good Tx octets, include VF loopback */
1199 UPDATE_VF_STAT(E1000_VFGOTC,
1200 hw_stats->last_gotc, hw_stats->gotc);
1202 /* Rx Multicst packets */
1203 UPDATE_VF_STAT(E1000_VFMPRC,
1204 hw_stats->last_mprc, hw_stats->mprc);
1206 /* Good Rx loopback packets */
1207 UPDATE_VF_STAT(E1000_VFGPRLBC,
1208 hw_stats->last_gprlbc, hw_stats->gprlbc);
1210 /* Good Rx loopback octets */
1211 UPDATE_VF_STAT(E1000_VFGORLBC,
1212 hw_stats->last_gorlbc, hw_stats->gorlbc);
1214 /* Good Tx loopback packets */
1215 UPDATE_VF_STAT(E1000_VFGPTLBC,
1216 hw_stats->last_gptlbc, hw_stats->gptlbc);
1218 /* Good Tx loopback octets */
1219 UPDATE_VF_STAT(E1000_VFGOTLBC,
1220 hw_stats->last_gotlbc, hw_stats->gotlbc);
1222 if (rte_stats == NULL)
1225 memset(rte_stats, 0, sizeof(*rte_stats));
1226 rte_stats->ipackets = hw_stats->gprc;
1227 rte_stats->ibytes = hw_stats->gorc;
1228 rte_stats->opackets = hw_stats->gptc;
1229 rte_stats->obytes = hw_stats->gotc;
1230 rte_stats->imcasts = hw_stats->mprc;
1231 rte_stats->ilbpackets = hw_stats->gprlbc;
1232 rte_stats->ilbbytes = hw_stats->gorlbc;
1233 rte_stats->olbpackets = hw_stats->gptlbc;
1234 rte_stats->olbbytes = hw_stats->gotlbc;
1239 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1241 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1242 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1244 /* Sync HW register to the last stats */
1245 eth_igbvf_stats_get(dev, NULL);
1247 /* reset HW current stats*/
1248 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1249 offsetof(struct e1000_vf_stats, gprc));
1254 eth_igb_infos_get(struct rte_eth_dev *dev,
1255 struct rte_eth_dev_info *dev_info)
1257 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1259 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1260 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1261 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1262 dev_info->rx_offload_capa =
1263 DEV_RX_OFFLOAD_VLAN_STRIP |
1264 DEV_RX_OFFLOAD_IPV4_CKSUM |
1265 DEV_RX_OFFLOAD_UDP_CKSUM |
1266 DEV_RX_OFFLOAD_TCP_CKSUM;
1267 dev_info->tx_offload_capa =
1268 DEV_TX_OFFLOAD_VLAN_INSERT |
1269 DEV_TX_OFFLOAD_IPV4_CKSUM |
1270 DEV_TX_OFFLOAD_UDP_CKSUM |
1271 DEV_TX_OFFLOAD_TCP_CKSUM |
1272 DEV_TX_OFFLOAD_SCTP_CKSUM;
1274 switch (hw->mac.type) {
1276 dev_info->max_rx_queues = 4;
1277 dev_info->max_tx_queues = 4;
1278 dev_info->max_vmdq_pools = 0;
1282 dev_info->max_rx_queues = 16;
1283 dev_info->max_tx_queues = 16;
1284 dev_info->max_vmdq_pools = ETH_8_POOLS;
1288 dev_info->max_rx_queues = 8;
1289 dev_info->max_tx_queues = 8;
1290 dev_info->max_vmdq_pools = ETH_8_POOLS;
1294 dev_info->max_rx_queues = 8;
1295 dev_info->max_tx_queues = 8;
1296 dev_info->max_vmdq_pools = ETH_8_POOLS;
1300 dev_info->max_rx_queues = 8;
1301 dev_info->max_tx_queues = 8;
1305 dev_info->max_rx_queues = 4;
1306 dev_info->max_tx_queues = 4;
1307 dev_info->max_vmdq_pools = 0;
1311 dev_info->max_rx_queues = 2;
1312 dev_info->max_tx_queues = 2;
1313 dev_info->max_vmdq_pools = 0;
1316 case e1000_vfadapt_i350:
1317 dev_info->max_rx_queues = 1;
1318 dev_info->max_tx_queues = 1;
1319 dev_info->max_vmdq_pools = 0;
1323 /* Should not happen */
1324 dev_info->max_rx_queues = 0;
1325 dev_info->max_tx_queues = 0;
1326 dev_info->max_vmdq_pools = 0;
1330 /* return 0 means link status changed, -1 means not changed */
1332 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1334 struct e1000_hw *hw =
1335 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1336 struct rte_eth_link link, old;
1337 int link_check, count;
1340 hw->mac.get_link_status = 1;
1342 /* possible wait-to-complete in up to 9 seconds */
1343 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1344 /* Read the real link status */
1345 switch (hw->phy.media_type) {
1346 case e1000_media_type_copper:
1347 /* Do the work to read phy */
1348 e1000_check_for_link(hw);
1349 link_check = !hw->mac.get_link_status;
1352 case e1000_media_type_fiber:
1353 e1000_check_for_link(hw);
1354 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1358 case e1000_media_type_internal_serdes:
1359 e1000_check_for_link(hw);
1360 link_check = hw->mac.serdes_has_link;
1363 /* VF device is type_unknown */
1364 case e1000_media_type_unknown:
1365 eth_igbvf_link_update(hw);
1366 link_check = !hw->mac.get_link_status;
1372 if (link_check || wait_to_complete == 0)
1374 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1376 memset(&link, 0, sizeof(link));
1377 rte_igb_dev_atomic_read_link_status(dev, &link);
1380 /* Now we check if a transition has happened */
1382 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1384 link.link_status = 1;
1385 } else if (!link_check) {
1386 link.link_speed = 0;
1387 link.link_duplex = 0;
1388 link.link_status = 0;
1390 rte_igb_dev_atomic_write_link_status(dev, &link);
1393 if (old.link_status == link.link_status)
1401 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1402 * For ASF and Pass Through versions of f/w this means
1403 * that the driver is loaded.
1406 igb_hw_control_acquire(struct e1000_hw *hw)
1410 /* Let firmware know the driver has taken over */
1411 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1412 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1416 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1417 * For ASF and Pass Through versions of f/w this means that the
1418 * driver is no longer loaded.
1421 igb_hw_control_release(struct e1000_hw *hw)
1425 /* Let firmware taken over control of h/w */
1426 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1427 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1428 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1432 * Bit of a misnomer, what this really means is
1433 * to enable OS management of the system... aka
1434 * to disable special hardware management features.
1437 igb_init_manageability(struct e1000_hw *hw)
1439 if (e1000_enable_mng_pass_thru(hw)) {
1440 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1441 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1443 /* disable hardware interception of ARP */
1444 manc &= ~(E1000_MANC_ARP_EN);
1446 /* enable receiving management packets to the host */
1447 manc |= E1000_MANC_EN_MNG2HOST;
1448 manc2h |= 1 << 5; /* Mng Port 623 */
1449 manc2h |= 1 << 6; /* Mng Port 664 */
1450 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1451 E1000_WRITE_REG(hw, E1000_MANC, manc);
1456 igb_release_manageability(struct e1000_hw *hw)
1458 if (e1000_enable_mng_pass_thru(hw)) {
1459 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1461 manc |= E1000_MANC_ARP_EN;
1462 manc &= ~E1000_MANC_EN_MNG2HOST;
1464 E1000_WRITE_REG(hw, E1000_MANC, manc);
1469 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1471 struct e1000_hw *hw =
1472 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1475 rctl = E1000_READ_REG(hw, E1000_RCTL);
1476 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1477 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1481 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1483 struct e1000_hw *hw =
1484 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1487 rctl = E1000_READ_REG(hw, E1000_RCTL);
1488 rctl &= (~E1000_RCTL_UPE);
1489 if (dev->data->all_multicast == 1)
1490 rctl |= E1000_RCTL_MPE;
1492 rctl &= (~E1000_RCTL_MPE);
1493 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1497 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1499 struct e1000_hw *hw =
1500 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1503 rctl = E1000_READ_REG(hw, E1000_RCTL);
1504 rctl |= E1000_RCTL_MPE;
1505 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1509 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1511 struct e1000_hw *hw =
1512 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1515 if (dev->data->promiscuous == 1)
1516 return; /* must remain in all_multicast mode */
1517 rctl = E1000_READ_REG(hw, E1000_RCTL);
1518 rctl &= (~E1000_RCTL_MPE);
1519 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1523 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1525 struct e1000_hw *hw =
1526 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1527 struct e1000_vfta * shadow_vfta =
1528 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1533 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1534 E1000_VFTA_ENTRY_MASK);
1535 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1536 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1541 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1543 /* update local VFTA copy */
1544 shadow_vfta->vfta[vid_idx] = vfta;
1550 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1552 struct e1000_hw *hw =
1553 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1554 uint32_t reg = ETHER_TYPE_VLAN ;
1556 reg |= (tpid << 16);
1557 E1000_WRITE_REG(hw, E1000_VET, reg);
1561 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1563 struct e1000_hw *hw =
1564 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1567 /* Filter Table Disable */
1568 reg = E1000_READ_REG(hw, E1000_RCTL);
1569 reg &= ~E1000_RCTL_CFIEN;
1570 reg &= ~E1000_RCTL_VFE;
1571 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1575 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1577 struct e1000_hw *hw =
1578 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1579 struct e1000_vfta * shadow_vfta =
1580 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1584 /* Filter Table Enable, CFI not used for packet acceptance */
1585 reg = E1000_READ_REG(hw, E1000_RCTL);
1586 reg &= ~E1000_RCTL_CFIEN;
1587 reg |= E1000_RCTL_VFE;
1588 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1590 /* restore VFTA table */
1591 for (i = 0; i < IGB_VFTA_SIZE; i++)
1592 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1596 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1598 struct e1000_hw *hw =
1599 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1602 /* VLAN Mode Disable */
1603 reg = E1000_READ_REG(hw, E1000_CTRL);
1604 reg &= ~E1000_CTRL_VME;
1605 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1609 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1611 struct e1000_hw *hw =
1612 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1615 /* VLAN Mode Enable */
1616 reg = E1000_READ_REG(hw, E1000_CTRL);
1617 reg |= E1000_CTRL_VME;
1618 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1622 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1624 struct e1000_hw *hw =
1625 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1628 /* CTRL_EXT: Extended VLAN */
1629 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1630 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1631 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1633 /* Update maximum packet length */
1634 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1635 E1000_WRITE_REG(hw, E1000_RLPML,
1636 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1641 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1643 struct e1000_hw *hw =
1644 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1647 /* CTRL_EXT: Extended VLAN */
1648 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1649 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1650 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1652 /* Update maximum packet length */
1653 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1654 E1000_WRITE_REG(hw, E1000_RLPML,
1655 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1660 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1662 if(mask & ETH_VLAN_STRIP_MASK){
1663 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1664 igb_vlan_hw_strip_enable(dev);
1666 igb_vlan_hw_strip_disable(dev);
1669 if(mask & ETH_VLAN_FILTER_MASK){
1670 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1671 igb_vlan_hw_filter_enable(dev);
1673 igb_vlan_hw_filter_disable(dev);
1676 if(mask & ETH_VLAN_EXTEND_MASK){
1677 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1678 igb_vlan_hw_extend_enable(dev);
1680 igb_vlan_hw_extend_disable(dev);
1686 * It enables the interrupt mask and then enable the interrupt.
1689 * Pointer to struct rte_eth_dev.
1692 * - On success, zero.
1693 * - On failure, a negative value.
1696 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1698 struct e1000_interrupt *intr =
1699 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1701 intr->mask |= E1000_ICR_LSC;
1707 * It reads ICR and gets interrupt causes, check it and set a bit flag
1708 * to update link status.
1711 * Pointer to struct rte_eth_dev.
1714 * - On success, zero.
1715 * - On failure, a negative value.
1718 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1721 struct e1000_hw *hw =
1722 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1723 struct e1000_interrupt *intr =
1724 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1726 igb_intr_disable(hw);
1728 /* read-on-clear nic registers here */
1729 icr = E1000_READ_REG(hw, E1000_ICR);
1732 if (icr & E1000_ICR_LSC) {
1733 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1736 if (icr & E1000_ICR_VMMB)
1737 intr->flags |= E1000_FLAG_MAILBOX;
1743 * It executes link_update after knowing an interrupt is prsent.
1746 * Pointer to struct rte_eth_dev.
1749 * - On success, zero.
1750 * - On failure, a negative value.
1753 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1755 struct e1000_hw *hw =
1756 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757 struct e1000_interrupt *intr =
1758 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1759 uint32_t tctl, rctl;
1760 struct rte_eth_link link;
1763 if (intr->flags & E1000_FLAG_MAILBOX) {
1764 igb_pf_mbx_process(dev);
1765 intr->flags &= ~E1000_FLAG_MAILBOX;
1768 igb_intr_enable(dev);
1769 rte_intr_enable(&(dev->pci_dev->intr_handle));
1771 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1772 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1774 /* set get_link_status to check register later */
1775 hw->mac.get_link_status = 1;
1776 ret = eth_igb_link_update(dev, 0);
1778 /* check if link has changed */
1782 memset(&link, 0, sizeof(link));
1783 rte_igb_dev_atomic_read_link_status(dev, &link);
1784 if (link.link_status) {
1786 " Port %d: Link Up - speed %u Mbps - %s\n",
1787 dev->data->port_id, (unsigned)link.link_speed,
1788 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1789 "full-duplex" : "half-duplex");
1791 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1792 dev->data->port_id);
1794 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1795 dev->pci_dev->addr.domain,
1796 dev->pci_dev->addr.bus,
1797 dev->pci_dev->addr.devid,
1798 dev->pci_dev->addr.function);
1799 tctl = E1000_READ_REG(hw, E1000_TCTL);
1800 rctl = E1000_READ_REG(hw, E1000_RCTL);
1801 if (link.link_status) {
1803 tctl |= E1000_TCTL_EN;
1804 rctl |= E1000_RCTL_EN;
1807 tctl &= ~E1000_TCTL_EN;
1808 rctl &= ~E1000_RCTL_EN;
1810 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1811 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1812 E1000_WRITE_FLUSH(hw);
1813 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1820 * Interrupt handler which shall be registered at first.
1823 * Pointer to interrupt handle.
1825 * The address of parameter (struct rte_eth_dev *) regsitered before.
1831 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1834 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1836 eth_igb_interrupt_get_status(dev);
1837 eth_igb_interrupt_action(dev);
1841 eth_igb_led_on(struct rte_eth_dev *dev)
1843 struct e1000_hw *hw;
1845 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1846 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1850 eth_igb_led_off(struct rte_eth_dev *dev)
1852 struct e1000_hw *hw;
1854 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1855 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1859 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1861 struct e1000_hw *hw;
1863 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1869 uint32_t rx_buf_size;
1870 uint32_t max_high_water;
1873 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1874 rx_buf_size = igb_get_rx_buffer_size(hw);
1875 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1877 /* At least reserve one Ethernet frame for watermark */
1878 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1879 if ((fc_conf->high_water > max_high_water) ||
1880 (fc_conf->high_water < fc_conf->low_water)) {
1881 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1882 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1886 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1887 hw->fc.pause_time = fc_conf->pause_time;
1888 hw->fc.high_water = fc_conf->high_water;
1889 hw->fc.low_water = fc_conf->low_water;
1890 hw->fc.send_xon = fc_conf->send_xon;
1892 err = e1000_setup_link_generic(hw);
1893 if (err == E1000_SUCCESS) {
1895 /* check if we want to forward MAC frames - driver doesn't have native
1896 * capability to do that, so we'll write the registers ourselves */
1898 rctl = E1000_READ_REG(hw, E1000_RCTL);
1900 /* set or clear MFLCN.PMCF bit depending on configuration */
1901 if (fc_conf->mac_ctrl_frame_fwd != 0)
1902 rctl |= E1000_RCTL_PMCF;
1904 rctl &= ~E1000_RCTL_PMCF;
1906 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1907 E1000_WRITE_FLUSH(hw);
1912 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1916 #define E1000_RAH_POOLSEL_SHIFT (18)
1918 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1919 uint32_t index, __rte_unused uint32_t pool)
1921 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1925 rah = E1000_READ_REG(hw, E1000_RAH(index));
1926 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
1927 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
1931 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1933 uint8_t addr[ETHER_ADDR_LEN];
1934 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1936 memset(addr, 0, sizeof(addr));
1938 e1000_rar_set(hw, addr, index);
1942 * Virtual Function operations
1945 igbvf_intr_disable(struct e1000_hw *hw)
1947 PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1949 /* Clear interrupt mask to stop from interrupts being generated */
1950 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
1952 E1000_WRITE_FLUSH(hw);
1956 igbvf_stop_adapter(struct rte_eth_dev *dev)
1960 struct rte_eth_dev_info dev_info;
1961 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1963 memset(&dev_info, 0, sizeof(dev_info));
1964 eth_igb_infos_get(dev, &dev_info);
1966 /* Clear interrupt mask to stop from interrupts being generated */
1967 igbvf_intr_disable(hw);
1969 /* Clear any pending interrupts, flush previous writes */
1970 E1000_READ_REG(hw, E1000_EICR);
1972 /* Disable the transmit unit. Each queue must be disabled. */
1973 for (i = 0; i < dev_info.max_tx_queues; i++)
1974 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1976 /* Disable the receive unit by stopping each queue */
1977 for (i = 0; i < dev_info.max_rx_queues; i++) {
1978 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1979 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1980 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1981 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1985 /* flush all queues disables */
1986 E1000_WRITE_FLUSH(hw);
1990 static int eth_igbvf_link_update(struct e1000_hw *hw)
1992 struct e1000_mbx_info *mbx = &hw->mbx;
1993 struct e1000_mac_info *mac = &hw->mac;
1994 int ret_val = E1000_SUCCESS;
1996 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1999 * We only want to run this if there has been a rst asserted.
2000 * in this case that could mean a link change, device reset,
2001 * or a virtual function reset
2004 /* If we were hit with a reset or timeout drop the link */
2005 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2006 mac->get_link_status = TRUE;
2008 if (!mac->get_link_status)
2011 /* if link status is down no point in checking to see if pf is up */
2012 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2015 /* if we passed all the tests above then the link is up and we no
2016 * longer need to check for link */
2017 mac->get_link_status = FALSE;
2025 igbvf_dev_configure(struct rte_eth_dev *dev)
2027 struct rte_eth_conf* conf = &dev->data->dev_conf;
2029 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2030 dev->data->port_id);
2033 * VF has no ability to enable/disable HW CRC
2034 * Keep the persistent behavior the same as Host PF
2036 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2037 if (!conf->rxmode.hw_strip_crc) {
2038 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2039 conf->rxmode.hw_strip_crc = 1;
2042 if (conf->rxmode.hw_strip_crc) {
2043 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2044 conf->rxmode.hw_strip_crc = 0;
2052 igbvf_dev_start(struct rte_eth_dev *dev)
2054 struct e1000_hw *hw =
2055 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2058 PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
2060 hw->mac.ops.reset_hw(hw);
2063 igbvf_set_vfta_all(dev,1);
2065 eth_igbvf_tx_init(dev);
2067 /* This can fail when allocating mbufs for descriptor rings */
2068 ret = eth_igbvf_rx_init(dev);
2070 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2071 igb_dev_clear_queues(dev);
2079 igbvf_dev_stop(struct rte_eth_dev *dev)
2081 PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
2083 igbvf_stop_adapter(dev);
2086 * Clear what we set, but we still keep shadow_vfta to
2087 * restore after device starts
2089 igbvf_set_vfta_all(dev,0);
2091 igb_dev_clear_queues(dev);
2095 igbvf_dev_close(struct rte_eth_dev *dev)
2097 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099 PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
2103 igbvf_dev_stop(dev);
2106 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2108 struct e1000_mbx_info *mbx = &hw->mbx;
2111 /* After set vlan, vlan strip will also be enabled in igb driver*/
2112 msgbuf[0] = E1000_VF_SET_VLAN;
2114 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2116 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2118 return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2121 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2123 struct e1000_hw *hw =
2124 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125 struct e1000_vfta * shadow_vfta =
2126 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2127 int i = 0, j = 0, vfta = 0, mask = 1;
2129 for (i = 0; i < IGB_VFTA_SIZE; i++){
2130 vfta = shadow_vfta->vfta[i];
2133 for (j = 0; j < 32; j++){
2136 (uint16_t)((i<<5)+j), on);
2145 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2147 struct e1000_hw *hw =
2148 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149 struct e1000_vfta * shadow_vfta =
2150 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2151 uint32_t vid_idx = 0;
2152 uint32_t vid_bit = 0;
2155 PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
2157 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2158 ret = igbvf_set_vfta(hw, vlan_id, !!on);
2160 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2163 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2164 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2166 /*Save what we set and retore it after device reset*/
2168 shadow_vfta->vfta[vid_idx] |= vid_bit;
2170 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2176 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2177 struct rte_eth_rss_reta *reta_conf)
2181 struct e1000_hw *hw =
2182 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2186 * 128-entries in 32 registers
2188 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2189 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2190 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2192 mask = (uint8_t)((reta_conf->mask_hi >>
2193 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2196 /* If all 4 entries were set,don't need read RETA register */
2198 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2200 for (j = 0; j < 4; j++) {
2201 if (mask & (0x1 << j)) {
2203 reta &= ~(0xFF << 8 * j);
2204 reta |= reta_conf->reta[i + j] << 8 * j;
2207 E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2215 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2216 struct rte_eth_rss_reta *reta_conf)
2220 struct e1000_hw *hw =
2221 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2224 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2225 * 128-entries in 32 registers
2227 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2228 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2229 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2231 mask = (uint8_t)((reta_conf->mask_hi >>
2232 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2235 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2236 for (j = 0; j < 4; j++) {
2237 if (mask & (0x1 << j))
2238 reta_conf->reta[i + j] =
2239 (uint8_t)((reta >> 8 * j) & 0xFF);
2247 #define MAC_TYPE_FILTER_SUP(type) do {\
2248 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2249 (type) != e1000_82576)\
2254 * add the syn filter
2257 * dev: Pointer to struct rte_eth_dev.
2258 * filter: ponter to the filter that will be added.
2259 * rx_queue: the queue id the filter assigned to.
2262 * - On success, zero.
2263 * - On failure, a negative value.
2266 eth_igb_add_syn_filter(struct rte_eth_dev *dev,
2267 struct rte_syn_filter *filter, uint16_t rx_queue)
2269 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2270 uint32_t synqf, rfctl;
2272 MAC_TYPE_FILTER_SUP(hw->mac.type);
2274 if (rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2277 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2278 if (synqf & E1000_SYN_FILTER_ENABLE)
2281 synqf = (uint32_t)(((rx_queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2282 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2284 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2285 if (filter->hig_pri)
2286 rfctl |= E1000_RFCTL_SYNQFP;
2288 rfctl &= ~E1000_RFCTL_SYNQFP;
2290 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2291 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2296 * remove the syn filter
2299 * dev: Pointer to struct rte_eth_dev.
2302 * - On success, zero.
2303 * - On failure, a negative value.
2306 eth_igb_remove_syn_filter(struct rte_eth_dev *dev)
2308 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2310 MAC_TYPE_FILTER_SUP(hw->mac.type);
2312 E1000_WRITE_REG(hw, E1000_SYNQF(0), 0);
2317 * get the syn filter's info
2320 * dev: Pointer to struct rte_eth_dev.
2321 * filter: ponter to the filter that returns.
2322 * *rx_queue: pointer to the queue id the filter assigned to.
2325 * - On success, zero.
2326 * - On failure, a negative value.
2329 eth_igb_get_syn_filter(struct rte_eth_dev *dev,
2330 struct rte_syn_filter *filter, uint16_t *rx_queue)
2332 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2333 uint32_t synqf, rfctl;
2335 MAC_TYPE_FILTER_SUP(hw->mac.type);
2336 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2337 if (synqf & E1000_SYN_FILTER_ENABLE) {
2338 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2339 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2340 *rx_queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2341 E1000_SYN_FILTER_QUEUE_SHIFT);
2348 * add an ethertype filter
2351 * dev: Pointer to struct rte_eth_dev.
2352 * index: the index the filter allocates.
2353 * filter: ponter to the filter that will be added.
2354 * rx_queue: the queue id the filter assigned to.
2357 * - On success, zero.
2358 * - On failure, a negative value.
2361 eth_igb_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2362 struct rte_ethertype_filter *filter, uint16_t rx_queue)
2364 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2367 MAC_TYPE_FILTER_SUP(hw->mac.type);
2369 if (index >= E1000_MAX_ETQF_FILTERS || rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2372 etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2373 if (etqf & E1000_ETQF_FILTER_ENABLE)
2374 return -EINVAL; /* filter index is in use. */
2378 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
2379 etqf |= (uint32_t)(filter->ethertype & E1000_ETQF_ETHERTYPE);
2380 etqf |= rx_queue << E1000_ETQF_QUEUE_SHIFT;
2382 if (filter->priority_en) {
2383 PMD_INIT_LOG(ERR, "vlan and priority (%d) is not supported"
2384 " in E1000.", filter->priority);
2388 E1000_WRITE_REG(hw, E1000_ETQF(index), etqf);
2393 * remove an ethertype filter
2396 * dev: Pointer to struct rte_eth_dev.
2397 * index: the index the filter allocates.
2400 * - On success, zero.
2401 * - On failure, a negative value.
2404 eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev, uint16_t index)
2406 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2408 MAC_TYPE_FILTER_SUP(hw->mac.type);
2410 if (index >= E1000_MAX_ETQF_FILTERS)
2413 E1000_WRITE_REG(hw, E1000_ETQF(index), 0);
2418 * get an ethertype filter
2421 * dev: Pointer to struct rte_eth_dev.
2422 * index: the index the filter allocates.
2423 * filter: ponter to the filter that will be gotten.
2424 * *rx_queue: the ponited of the queue id the filter assigned to.
2427 * - On success, zero.
2428 * - On failure, a negative value.
2431 eth_igb_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2432 struct rte_ethertype_filter *filter, uint16_t *rx_queue)
2434 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2437 MAC_TYPE_FILTER_SUP(hw->mac.type);
2439 if (index >= E1000_MAX_ETQF_FILTERS)
2442 etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2443 if (etqf & E1000_ETQF_FILTER_ENABLE) {
2444 filter->ethertype = etqf & E1000_ETQF_ETHERTYPE;
2445 filter->priority_en = 0;
2446 *rx_queue = (etqf & E1000_ETQF_QUEUE) >> E1000_ETQF_QUEUE_SHIFT;
2452 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
2453 if ((type) != e1000_82580 && (type) != e1000_i350)\
2458 * add a 2tuple filter
2461 * dev: Pointer to struct rte_eth_dev.
2462 * index: the index the filter allocates.
2463 * filter: ponter to the filter that will be added.
2464 * rx_queue: the queue id the filter assigned to.
2467 * - On success, zero.
2468 * - On failure, a negative value.
2471 eth_igb_add_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2472 struct rte_2tuple_filter *filter, uint16_t rx_queue)
2474 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475 uint32_t ttqf, imir = 0;
2476 uint32_t imir_ext = 0;
2478 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2480 if (index >= E1000_MAX_TTQF_FILTERS ||
2481 rx_queue >= IGB_MAX_RX_QUEUE_NUM ||
2482 filter->priority > E1000_2TUPLE_MAX_PRI)
2483 return -EINVAL; /* filter index is out of range. */
2484 if (filter->tcp_flags > TCP_FLAG_ALL)
2485 return -EINVAL; /* flags is invalid. */
2487 ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2488 if (ttqf & E1000_TTQF_QUEUE_ENABLE)
2489 return -EINVAL; /* filter index is in use. */
2491 imir = (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2492 if (filter->dst_port_mask == 1) /* 1b means not compare. */
2493 imir |= E1000_IMIR_PORT_BP;
2495 imir &= ~E1000_IMIR_PORT_BP;
2497 imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2500 ttqf |= E1000_TTQF_QUEUE_ENABLE;
2501 ttqf |= (uint32_t)(rx_queue << E1000_TTQF_QUEUE_SHIFT);
2502 ttqf |= (uint32_t)(filter->protocol & E1000_TTQF_PROTOCOL_MASK);
2503 if (filter->protocol_mask == 1)
2504 ttqf |= E1000_TTQF_MASK_ENABLE;
2506 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2508 imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2509 /* tcp flags bits setting. */
2510 if (filter->tcp_flags & TCP_FLAG_ALL) {
2511 if (filter->tcp_flags & TCP_UGR_FLAG)
2512 imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2513 if (filter->tcp_flags & TCP_ACK_FLAG)
2514 imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2515 if (filter->tcp_flags & TCP_PSH_FLAG)
2516 imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2517 if (filter->tcp_flags & TCP_RST_FLAG)
2518 imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2519 if (filter->tcp_flags & TCP_SYN_FLAG)
2520 imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2521 if (filter->tcp_flags & TCP_FIN_FLAG)
2522 imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2523 imir_ext &= ~E1000_IMIR_EXT_CTRL_BP;
2525 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2526 E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2527 E1000_WRITE_REG(hw, E1000_TTQF(index), ttqf);
2528 E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2533 * remove a 2tuple filter
2536 * dev: Pointer to struct rte_eth_dev.
2537 * index: the index the filter allocates.
2540 * - On success, zero.
2541 * - On failure, a negative value.
2544 eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2547 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2551 if (index >= E1000_MAX_TTQF_FILTERS)
2552 return -EINVAL; /* filter index is out of range */
2554 E1000_WRITE_REG(hw, E1000_TTQF(index), 0);
2555 E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2556 E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2561 * get a 2tuple filter
2564 * dev: Pointer to struct rte_eth_dev.
2565 * index: the index the filter allocates.
2566 * filter: ponter to the filter that returns.
2567 * *rx_queue: pointer of the queue id the filter assigned to.
2570 * - On success, zero.
2571 * - On failure, a negative value.
2574 eth_igb_get_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2575 struct rte_2tuple_filter *filter, uint16_t *rx_queue)
2577 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578 uint32_t imir, ttqf, imir_ext;
2580 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2582 if (index >= E1000_MAX_TTQF_FILTERS)
2583 return -EINVAL; /* filter index is out of range. */
2585 ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2586 if (ttqf & E1000_TTQF_QUEUE_ENABLE) {
2587 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2588 filter->protocol = ttqf & E1000_TTQF_PROTOCOL_MASK;
2589 filter->protocol_mask = (ttqf & E1000_TTQF_MASK_ENABLE) ? 1 : 0;
2590 *rx_queue = (ttqf & E1000_TTQF_RX_QUEUE_MASK) >>
2591 E1000_TTQF_QUEUE_SHIFT;
2592 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2593 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2594 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2595 E1000_IMIR_PRIORITY_SHIFT;
2597 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2598 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2599 if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2600 filter->tcp_flags |= TCP_UGR_FLAG;
2601 if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2602 filter->tcp_flags |= TCP_ACK_FLAG;
2603 if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2604 filter->tcp_flags |= TCP_PSH_FLAG;
2605 if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2606 filter->tcp_flags |= TCP_RST_FLAG;
2607 if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2608 filter->tcp_flags |= TCP_SYN_FLAG;
2609 if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2610 filter->tcp_flags |= TCP_FIN_FLAG;
2612 filter->tcp_flags = 0;
2622 * dev: Pointer to struct rte_eth_dev.
2623 * index: the index the filter allocates.
2624 * filter: ponter to the filter that will be added.
2625 * rx_queue: the queue id the filter assigned to.
2628 * - On success, zero.
2629 * - On failure, a negative value.
2632 eth_igb_add_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2633 struct rte_flex_filter *filter, uint16_t rx_queue)
2635 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636 uint32_t wufc, en_bits = 0;
2637 uint32_t queueing = 0;
2638 uint32_t reg_off = 0;
2641 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2643 if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2644 return -EINVAL; /* filter index is out of range. */
2646 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN ||
2647 filter->len % 8 != 0 ||
2648 filter->priority > E1000_MAX_FLEX_FILTER_PRI)
2651 wufc = E1000_READ_REG(hw, E1000_WUFC);
2652 en_bits = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2653 if ((wufc & en_bits) == en_bits)
2654 return -EINVAL; /* the filter is in use. */
2656 E1000_WRITE_REG(hw, E1000_WUFC,
2657 wufc | E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index));
2660 if (index < E1000_MAX_FHFT)
2661 reg_off = E1000_FHFT(index);
2663 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2665 for (i = 0; i < 16; i++) {
2666 E1000_WRITE_REG(hw, reg_off + i*4*4, filter->dwords[j]);
2667 E1000_WRITE_REG(hw, reg_off + (i*4+1)*4, filter->dwords[++j]);
2668 E1000_WRITE_REG(hw, reg_off + (i*4+2)*4,
2669 (uint32_t)filter->mask[i]);
2672 queueing |= filter->len |
2673 (rx_queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2674 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2675 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET, queueing);
2680 * remove a flex filter
2683 * dev: Pointer to struct rte_eth_dev.
2684 * index: the index the filter allocates.
2687 * - On success, zero.
2688 * - On failure, a negative value.
2691 eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
2694 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2695 uint32_t wufc, reg_off = 0;
2698 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2700 if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2701 return -EINVAL; /* filter index is out of range. */
2703 wufc = E1000_READ_REG(hw, E1000_WUFC);
2704 E1000_WRITE_REG(hw, E1000_WUFC, wufc & (~(E1000_WUFC_FLX0 << index)));
2706 if (index < E1000_MAX_FHFT)
2707 reg_off = E1000_FHFT(index);
2709 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2711 for (i = 0; i < 64; i++)
2712 E1000_WRITE_REG(hw, reg_off + i*4, 0);
2720 * dev: Pointer to struct rte_eth_dev.
2721 * index: the index the filter allocates.
2722 * filter: ponter to the filter that returns.
2723 * *rx_queue: the pointer of the queue id the filter assigned to.
2726 * - On success, zero.
2727 * - On failure, a negative value.
2730 eth_igb_get_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2731 struct rte_flex_filter *filter, uint16_t *rx_queue)
2733 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2734 uint32_t wufc, queueing, wufc_en = 0;
2737 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2739 if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2740 return -EINVAL; /* filter index is out of range. */
2742 wufc = E1000_READ_REG(hw, E1000_WUFC);
2743 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2745 if ((wufc & wufc_en) == wufc_en) {
2746 uint32_t reg_off = 0;
2748 if (index < E1000_MAX_FHFT)
2749 reg_off = E1000_FHFT(index);
2751 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2753 for (i = 0; i < 16; i++, j = i * 2) {
2755 E1000_READ_REG(hw, reg_off + i*4*4);
2756 filter->dwords[j+1] =
2757 E1000_READ_REG(hw, reg_off + (i*4+1)*4);
2759 E1000_READ_REG(hw, reg_off + (i*4+2)*4);
2761 queueing = E1000_READ_REG(hw,
2762 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2763 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2764 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2765 E1000_FHFT_QUEUEING_PRIO_SHIFT;
2766 *rx_queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2767 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2774 * add a 5tuple filter
2777 * dev: Pointer to struct rte_eth_dev.
2778 * index: the index the filter allocates.
2779 * filter: ponter to the filter that will be added.
2780 * rx_queue: the queue id the filter assigned to.
2783 * - On success, zero.
2784 * - On failure, a negative value.
2787 eth_igb_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2788 struct rte_5tuple_filter *filter, uint16_t rx_queue)
2790 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2791 uint32_t ftqf, spqf = 0;
2793 uint32_t imir_ext = 0;
2795 if (hw->mac.type != e1000_82576)
2798 if (index >= E1000_MAX_FTQF_FILTERS ||
2799 rx_queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2800 return -EINVAL; /* filter index is out of range. */
2802 ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2803 if (ftqf & E1000_FTQF_QUEUE_ENABLE)
2804 return -EINVAL; /* filter index is in use. */
2807 ftqf |= filter->protocol & E1000_FTQF_PROTOCOL_MASK;
2808 if (filter->src_ip_mask == 1) /* 1b means not compare. */
2809 ftqf |= E1000_FTQF_SOURCE_ADDR_MASK;
2810 if (filter->dst_ip_mask == 1)
2811 ftqf |= E1000_FTQF_DEST_ADDR_MASK;
2812 if (filter->src_port_mask == 1)
2813 ftqf |= E1000_FTQF_SOURCE_PORT_MASK;
2814 if (filter->protocol_mask == 1)
2815 ftqf |= E1000_FTQF_PROTOCOL_COMP_MASK;
2816 ftqf |= (rx_queue << E1000_FTQF_QUEUE_SHIFT) & E1000_FTQF_QUEUE_MASK;
2817 ftqf |= E1000_FTQF_VF_MASK_EN;
2818 ftqf |= E1000_FTQF_QUEUE_ENABLE;
2819 E1000_WRITE_REG(hw, E1000_FTQF(index), ftqf);
2820 E1000_WRITE_REG(hw, E1000_DAQF(index), filter->dst_ip);
2821 E1000_WRITE_REG(hw, E1000_SAQF(index), filter->src_ip);
2823 spqf |= filter->src_port & E1000_SPQF_SRCPORT;
2824 E1000_WRITE_REG(hw, E1000_SPQF(index), spqf);
2826 imir |= (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2827 if (filter->dst_port_mask == 1) /* 1b means not compare. */
2828 imir |= E1000_IMIR_PORT_BP;
2830 imir &= ~E1000_IMIR_PORT_BP;
2831 imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2833 imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2834 /* tcp flags bits setting. */
2835 if (filter->tcp_flags & TCP_FLAG_ALL) {
2836 if (filter->tcp_flags & TCP_UGR_FLAG)
2837 imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2838 if (filter->tcp_flags & TCP_ACK_FLAG)
2839 imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2840 if (filter->tcp_flags & TCP_PSH_FLAG)
2841 imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2842 if (filter->tcp_flags & TCP_RST_FLAG)
2843 imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2844 if (filter->tcp_flags & TCP_SYN_FLAG)
2845 imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2846 if (filter->tcp_flags & TCP_FIN_FLAG)
2847 imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2849 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2850 E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2851 E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2856 * remove a 5tuple filter
2859 * dev: Pointer to struct rte_eth_dev.
2860 * index: the index the filter allocates
2863 * - On success, zero.
2864 * - On failure, a negative value.
2867 eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
2870 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2872 if (hw->mac.type != e1000_82576)
2875 if (index >= E1000_MAX_FTQF_FILTERS)
2876 return -EINVAL; /* filter index is out of range. */
2878 E1000_WRITE_REG(hw, E1000_FTQF(index), 0);
2879 E1000_WRITE_REG(hw, E1000_DAQF(index), 0);
2880 E1000_WRITE_REG(hw, E1000_SAQF(index), 0);
2881 E1000_WRITE_REG(hw, E1000_SPQF(index), 0);
2882 E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2883 E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2888 * get a 5tuple filter
2891 * dev: Pointer to struct rte_eth_dev.
2892 * index: the index the filter allocates
2893 * filter: ponter to the filter that returns
2894 * *rx_queue: pointer of the queue id the filter assigned to
2897 * - On success, zero.
2898 * - On failure, a negative value.
2901 eth_igb_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2902 struct rte_5tuple_filter *filter, uint16_t *rx_queue)
2904 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2905 uint32_t spqf, ftqf, imir, imir_ext;
2907 if (hw->mac.type != e1000_82576)
2910 if (index >= E1000_MAX_FTQF_FILTERS)
2911 return -EINVAL; /* filter index is out of range. */
2913 ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2914 if (ftqf & E1000_FTQF_QUEUE_ENABLE) {
2915 filter->src_ip_mask =
2916 (ftqf & E1000_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
2917 filter->dst_ip_mask =
2918 (ftqf & E1000_FTQF_DEST_ADDR_MASK) ? 1 : 0;
2919 filter->src_port_mask =
2920 (ftqf & E1000_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
2921 filter->protocol_mask =
2922 (ftqf & E1000_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
2924 (uint8_t)ftqf & E1000_FTQF_PROTOCOL_MASK;
2925 *rx_queue = (uint16_t)((ftqf & E1000_FTQF_QUEUE_MASK) >>
2926 E1000_FTQF_QUEUE_SHIFT);
2928 spqf = E1000_READ_REG(hw, E1000_SPQF(index));
2929 filter->src_port = spqf & E1000_SPQF_SRCPORT;
2931 filter->dst_ip = E1000_READ_REG(hw, E1000_DAQF(index));
2932 filter->src_ip = E1000_READ_REG(hw, E1000_SAQF(index));
2934 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2935 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2936 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2937 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2938 E1000_IMIR_PRIORITY_SHIFT;
2940 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2941 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2942 if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2943 filter->tcp_flags |= TCP_UGR_FLAG;
2944 if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2945 filter->tcp_flags |= TCP_ACK_FLAG;
2946 if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2947 filter->tcp_flags |= TCP_PSH_FLAG;
2948 if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2949 filter->tcp_flags |= TCP_RST_FLAG;
2950 if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2951 filter->tcp_flags |= TCP_SYN_FLAG;
2952 if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2953 filter->tcp_flags |= TCP_FIN_FLAG;
2955 filter->tcp_flags = 0;
2961 static struct rte_driver pmd_igb_drv = {
2963 .init = rte_igb_pmd_init,
2966 static struct rte_driver pmd_igbvf_drv = {
2968 .init = rte_igbvf_pmd_init,
2971 PMD_REGISTER_DRIVER(pmd_igb_drv);
2972 PMD_REGISTER_DRIVER(pmd_igbvf_drv);