lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 static int  eth_igb_configure(struct rte_eth_dev *dev);
  61 static int  eth_igb_start(struct rte_eth_dev *dev);
  62 static void eth_igb_stop(struct rte_eth_dev *dev);
  63 static void eth_igb_close(struct rte_eth_dev *dev);
  64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  68 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  69                                 int wait_to_complete);
  70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  71                                 struct rte_eth_stats *rte_stats);
  72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  74                                 struct rte_eth_dev_info *dev_info);
  75 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  76                                 struct rte_eth_fc_conf *fc_conf);
  77 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  78 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  79 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  80 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  81                                                         void *param);
  82 static int  igb_hardware_init(struct e1000_hw *hw);
  83 static void igb_hw_control_acquire(struct e1000_hw *hw);
  84 static void igb_hw_control_release(struct e1000_hw *hw);
  85 static void igb_init_manageability(struct e1000_hw *hw);
  86 static void igb_release_manageability(struct e1000_hw *hw);
  87
  88 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  89                 uint16_t vlan_id, int on);
  90 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
  91 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  92
  93 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  94 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  95 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  96 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  97 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
  98 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
  99
 100 static int eth_igb_led_on(struct rte_eth_dev *dev);
 101 static int eth_igb_led_off(struct rte_eth_dev *dev);
 102
 103 static void igb_intr_disable(struct e1000_hw *hw);
 104 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 105 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 106                 struct ether_addr *mac_addr,
 107                 uint32_t index, uint32_t pool);
 108 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 109
 110 static void igbvf_intr_disable(struct e1000_hw *hw);
 111 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 112 static int igbvf_dev_start(struct rte_eth_dev *dev);
 113 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 114 static void igbvf_dev_close(struct rte_eth_dev *dev);
 115 static int eth_igbvf_link_update(struct e1000_hw *hw);
 116 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 117 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 118 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 119                 uint16_t vlan_id, int on);
 120 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 121 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 122 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 123                  struct rte_eth_rss_reta *reta_conf);
 124 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 125                 struct rte_eth_rss_reta *reta_conf);
 126
 127 static int eth_igb_add_syn_filter(struct rte_eth_dev *dev,
 128                         struct rte_syn_filter *filter, uint16_t rx_queue);
 129 static int eth_igb_remove_syn_filter(struct rte_eth_dev *dev);
 130 static int eth_igb_get_syn_filter(struct rte_eth_dev *dev,
 131                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 132 static int eth_igb_add_ethertype_filter(struct rte_eth_dev *dev,
 133                         uint16_t index,
 134                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 135 static int eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev,
 136                         uint16_t index);
 137 static int eth_igb_get_ethertype_filter(struct rte_eth_dev *dev,
 138                         uint16_t index,
 139                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 140 static int eth_igb_add_2tuple_filter(struct rte_eth_dev *dev,
 141                         uint16_t index,
 142                         struct rte_2tuple_filter *filter, uint16_t rx_queue);
 143 static int eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 144                         uint16_t index);
 145 static int eth_igb_get_2tuple_filter(struct rte_eth_dev *dev,
 146                         uint16_t index,
 147                         struct rte_2tuple_filter *filter, uint16_t *rx_queue);
 148 static int eth_igb_add_flex_filter(struct rte_eth_dev *dev,
 149                         uint16_t index,
 150                         struct rte_flex_filter *filter, uint16_t rx_queue);
 151 static int eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
 152                         uint16_t index);
 153 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 154                         uint16_t index,
 155                         struct rte_flex_filter *filter, uint16_t *rx_queue);
 156 static int eth_igb_add_5tuple_filter(struct rte_eth_dev *dev,
 157                         uint16_t index,
 158                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 159 static int eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
 160                         uint16_t index);
 161 static int eth_igb_get_5tuple_filter(struct rte_eth_dev *dev,
 162                         uint16_t index,
 163                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 164
 165 /*
 166  * Define VF Stats MACRO for Non "cleared on read" register
 167  */
 168 #define UPDATE_VF_STAT(reg, last, cur)            \
 169 {                                                 \
 170         u32 latest = E1000_READ_REG(hw, reg);     \
 171         cur += latest - last;                     \
 172         last = latest;                            \
 173 }
 174
 175
 176 #define IGB_FC_PAUSE_TIME 0x0680
 177 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 178 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 179
 180 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 181
 182 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 183
 184 /*
 185  * The set of PCI devices this driver supports
 186  */
 187 static struct rte_pci_id pci_id_igb_map[] = {
 188
 189 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 190 #include "rte_pci_dev_ids.h"
 191
 192 {.device_id = 0},
 193 };
 194
 195 /*
 196  * The set of PCI devices this driver supports (for 82576&I350 VF)
 197  */
 198 static struct rte_pci_id pci_id_igbvf_map[] = {
 199
 200 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 201 #include "rte_pci_dev_ids.h"
 202
 203 {.device_id = 0},
 204 };
 205
 206 static struct eth_dev_ops eth_igb_ops = {
 207         .dev_configure        = eth_igb_configure,
 208         .dev_start            = eth_igb_start,
 209         .dev_stop             = eth_igb_stop,
 210         .dev_close            = eth_igb_close,
 211         .promiscuous_enable   = eth_igb_promiscuous_enable,
 212         .promiscuous_disable  = eth_igb_promiscuous_disable,
 213         .allmulticast_enable  = eth_igb_allmulticast_enable,
 214         .allmulticast_disable = eth_igb_allmulticast_disable,
 215         .link_update          = eth_igb_link_update,
 216         .stats_get            = eth_igb_stats_get,
 217         .stats_reset          = eth_igb_stats_reset,
 218         .dev_infos_get        = eth_igb_infos_get,
 219         .vlan_filter_set      = eth_igb_vlan_filter_set,
 220         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 221         .vlan_offload_set     = eth_igb_vlan_offload_set,
 222         .rx_queue_setup       = eth_igb_rx_queue_setup,
 223         .rx_queue_release     = eth_igb_rx_queue_release,
 224         .rx_queue_count       = eth_igb_rx_queue_count,
 225         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 226         .tx_queue_setup       = eth_igb_tx_queue_setup,
 227         .tx_queue_release     = eth_igb_tx_queue_release,
 228         .dev_led_on           = eth_igb_led_on,
 229         .dev_led_off          = eth_igb_led_off,
 230         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 231         .mac_addr_add         = eth_igb_rar_set,
 232         .mac_addr_remove      = eth_igb_rar_clear,
 233         .reta_update          = eth_igb_rss_reta_update,
 234         .reta_query           = eth_igb_rss_reta_query,
 235         .rss_hash_update      = eth_igb_rss_hash_update,
 236         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 237         .add_syn_filter          = eth_igb_add_syn_filter,
 238         .remove_syn_filter       = eth_igb_remove_syn_filter,
 239         .get_syn_filter          = eth_igb_get_syn_filter,
 240         .add_ethertype_filter    = eth_igb_add_ethertype_filter,
 241         .remove_ethertype_filter = eth_igb_remove_ethertype_filter,
 242         .get_ethertype_filter    = eth_igb_get_ethertype_filter,
 243         .add_2tuple_filter       = eth_igb_add_2tuple_filter,
 244         .remove_2tuple_filter    = eth_igb_remove_2tuple_filter,
 245         .get_2tuple_filter       = eth_igb_get_2tuple_filter,
 246         .add_flex_filter         = eth_igb_add_flex_filter,
 247         .remove_flex_filter      = eth_igb_remove_flex_filter,
 248         .get_flex_filter         = eth_igb_get_flex_filter,
 249         .add_5tuple_filter       = eth_igb_add_5tuple_filter,
 250         .remove_5tuple_filter    = eth_igb_remove_5tuple_filter,
 251         .get_5tuple_filter       = eth_igb_get_5tuple_filter,
 252 };
 253
 254 /*
 255  * dev_ops for virtual function, bare necessities for basic vf
 256  * operation have been implemented
 257  */
 258 static struct eth_dev_ops igbvf_eth_dev_ops = {
 259         .dev_configure        = igbvf_dev_configure,
 260         .dev_start            = igbvf_dev_start,
 261         .dev_stop             = igbvf_dev_stop,
 262         .dev_close            = igbvf_dev_close,
 263         .link_update          = eth_igb_link_update,
 264         .stats_get            = eth_igbvf_stats_get,
 265         .stats_reset          = eth_igbvf_stats_reset,
 266         .vlan_filter_set      = igbvf_vlan_filter_set,
 267         .dev_infos_get        = eth_igb_infos_get,
 268         .rx_queue_setup       = eth_igb_rx_queue_setup,
 269         .rx_queue_release     = eth_igb_rx_queue_release,
 270         .tx_queue_setup       = eth_igb_tx_queue_setup,
 271         .tx_queue_release     = eth_igb_tx_queue_release,
 272 };
 273
 274 /**
 275  * Atomically reads the link status information from global
 276  * structure rte_eth_dev.
 277  *
 278  * @param dev
 279  *   - Pointer to the structure rte_eth_dev to read from.
 280  *   - Pointer to the buffer to be saved with the link status.
 281  *
 282  * @return
 283  *   - On success, zero.
 284  *   - On failure, negative value.
 285  */
 286 static inline int
 287 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 288                                 struct rte_eth_link *link)
 289 {
 290         struct rte_eth_link *dst = link;
 291         struct rte_eth_link *src = &(dev->data->dev_link);
 292
 293         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 294                                         *(uint64_t *)src) == 0)
 295                 return -1;
 296
 297         return 0;
 298 }
 299
 300 /**
 301  * Atomically writes the link status information into global
 302  * structure rte_eth_dev.
 303  *
 304  * @param dev
 305  *   - Pointer to the structure rte_eth_dev to read from.
 306  *   - Pointer to the buffer to be saved with the link status.
 307  *
 308  * @return
 309  *   - On success, zero.
 310  *   - On failure, negative value.
 311  */
 312 static inline int
 313 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 314                                 struct rte_eth_link *link)
 315 {
 316         struct rte_eth_link *dst = &(dev->data->dev_link);
 317         struct rte_eth_link *src = link;
 318
 319         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 320                                         *(uint64_t *)src) == 0)
 321                 return -1;
 322
 323         return 0;
 324 }
 325
 326 static inline void
 327 igb_intr_enable(struct rte_eth_dev *dev)
 328 {
 329         struct e1000_interrupt *intr =
 330                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 331         struct e1000_hw *hw =
 332                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 333
 334         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 335         E1000_WRITE_FLUSH(hw);
 336 }
 337
 338 static void
 339 igb_intr_disable(struct e1000_hw *hw)
 340 {
 341         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 342         E1000_WRITE_FLUSH(hw);
 343 }
 344
 345 static inline int32_t
 346 igb_pf_reset_hw(struct e1000_hw *hw)
 347 {
 348         uint32_t ctrl_ext;
 349         int32_t status;
 350
 351         status = e1000_reset_hw(hw);
 352
 353         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 354         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 355         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 356         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 357         E1000_WRITE_FLUSH(hw);
 358
 359         return status;
 360 }
 361
 362 static void
 363 igb_identify_hardware(struct rte_eth_dev *dev)
 364 {
 365         struct e1000_hw *hw =
 366                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 367
 368         hw->vendor_id = dev->pci_dev->id.vendor_id;
 369         hw->device_id = dev->pci_dev->id.device_id;
 370         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 371         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 372
 373         e1000_set_mac_type(hw);
 374
 375         /* need to check if it is a vf device below */
 376 }
 377
 378 static int
 379 igb_reset_swfw_lock(struct e1000_hw *hw)
 380 {
 381         int ret_val;
 382
 383         /*
 384          * Do mac ops initialization manually here, since we will need
 385          * some function pointers set by this call.
 386          */
 387         ret_val = e1000_init_mac_params(hw);
 388         if (ret_val)
 389                 return ret_val;
 390
 391         /*
 392          * SMBI lock should not fail in this early stage. If this is the case,
 393          * it is due to an improper exit of the application.
 394          * So force the release of the faulty lock.
 395          */
 396         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 397                 DEBUGOUT("SMBI lock released");
 398         }
 399         e1000_put_hw_semaphore_generic(hw);
 400
 401         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 402                 uint16_t mask;
 403
 404                 /*
 405                  * Phy lock should not fail in this early stage. If this is the case,
 406                  * it is due to an improper exit of the application.
 407                  * So force the release of the faulty lock.
 408                  */
 409                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 410                 if (hw->bus.func > E1000_FUNC_1)
 411                         mask <<= 2;
 412                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 413                         DEBUGOUT1("SWFW phy%d lock released", hw->bus.func);
 414                 }
 415                 hw->mac.ops.release_swfw_sync(hw, mask);
 416
 417                 /*
 418                  * This one is more tricky since it is common to all ports; but
 419                  * swfw_sync retries last long enough (1s) to be almost sure that if
 420                  * lock can not be taken it is due to an improper lock of the
 421                  * semaphore.
 422                  */
 423                 mask = E1000_SWFW_EEP_SM;
 424                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 425                         DEBUGOUT("SWFW common locks released");
 426                 }
 427                 hw->mac.ops.release_swfw_sync(hw, mask);
 428         }
 429
 430         return E1000_SUCCESS;
 431 }
 432
 433 static int
 434 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 435                    struct rte_eth_dev *eth_dev)
 436 {
 437         int error = 0;
 438         struct rte_pci_device *pci_dev;
 439         struct e1000_hw *hw =
 440                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 441         struct e1000_vfta * shadow_vfta =
 442                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 443         uint32_t ctrl_ext;
 444
 445         pci_dev = eth_dev->pci_dev;
 446         eth_dev->dev_ops = &eth_igb_ops;
 447         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 448         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 449
 450         /* for secondary processes, we don't initialise any further as primary
 451          * has already done this work. Only check we don't need a different
 452          * RX function */
 453         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 454                 if (eth_dev->data->scattered_rx)
 455                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 456                 return 0;
 457         }
 458
 459         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 460
 461         igb_identify_hardware(eth_dev);
 462         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 463                 error = -EIO;
 464                 goto err_late;
 465         }
 466
 467         e1000_get_bus_info(hw);
 468
 469         /* Reset any pending lock */
 470         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 471                 error = -EIO;
 472                 goto err_late;
 473         }
 474
 475         /* Finish initialization */
 476         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 477                 error = -EIO;
 478                 goto err_late;
 479         }
 480
 481         hw->mac.autoneg = 1;
 482         hw->phy.autoneg_wait_to_complete = 0;
 483         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 484
 485         /* Copper options */
 486         if (hw->phy.media_type == e1000_media_type_copper) {
 487                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 488                 hw->phy.disable_polarity_correction = 0;
 489                 hw->phy.ms_type = e1000_ms_hw_default;
 490         }
 491
 492         /*
 493          * Start from a known state, this is important in reading the nvm
 494          * and mac from that.
 495          */
 496         igb_pf_reset_hw(hw);
 497
 498         /* Make sure we have a good EEPROM before we read from it */
 499         if (e1000_validate_nvm_checksum(hw) < 0) {
 500                 /*
 501                  * Some PCI-E parts fail the first check due to
 502                  * the link being in sleep state, call it again,
 503                  * if it fails a second time its a real issue.
 504                  */
 505                 if (e1000_validate_nvm_checksum(hw) < 0) {
 506                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 507                         error = -EIO;
 508                         goto err_late;
 509                 }
 510         }
 511
 512         /* Read the permanent MAC address out of the EEPROM */
 513         if (e1000_read_mac_addr(hw) != 0) {
 514                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 515                 error = -EIO;
 516                 goto err_late;
 517         }
 518
 519         /* Allocate memory for storing MAC addresses */
 520         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 521                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 522         if (eth_dev->data->mac_addrs == NULL) {
 523                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 524                                                 "store MAC addresses",
 525                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 526                 error = -ENOMEM;
 527                 goto err_late;
 528         }
 529
 530         /* Copy the permanent MAC address */
 531         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 532
 533         /* initialize the vfta */
 534         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 535
 536         /* Now initialize the hardware */
 537         if (igb_hardware_init(hw) != 0) {
 538                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 539                 rte_free(eth_dev->data->mac_addrs);
 540                 eth_dev->data->mac_addrs = NULL;
 541                 error = -ENODEV;
 542                 goto err_late;
 543         }
 544         hw->mac.get_link_status = 1;
 545
 546         /* Indicate SOL/IDER usage */
 547         if (e1000_check_reset_block(hw) < 0) {
 548                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 549                                         "SOL/IDER session");
 550         }
 551
 552         /* initialize PF if max_vfs not zero */
 553         igb_pf_host_init(eth_dev);
 554
 555         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 556         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 557         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 558         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 559         E1000_WRITE_FLUSH(hw);
 560
 561         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 562                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 563                      pci_dev->id.device_id);
 564
 565         rte_intr_callback_register(&(pci_dev->intr_handle),
 566                 eth_igb_interrupt_handler, (void *)eth_dev);
 567
 568         /* enable uio intr after callback register */
 569         rte_intr_enable(&(pci_dev->intr_handle));
 570
 571         /* enable support intr */
 572         igb_intr_enable(eth_dev);
 573
 574         return 0;
 575
 576 err_late:
 577         igb_hw_control_release(hw);
 578
 579         return (error);
 580 }
 581
 582 /*
 583  * Virtual Function device init
 584  */
 585 static int
 586 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 587                 struct rte_eth_dev *eth_dev)
 588 {
 589         struct rte_pci_device *pci_dev;
 590         struct e1000_hw *hw =
 591                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 592         int diag;
 593
 594         PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 595
 596         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 597         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 598         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 599
 600         /* for secondary processes, we don't initialise any further as primary
 601          * has already done this work. Only check we don't need a different
 602          * RX function */
 603         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 604                 if (eth_dev->data->scattered_rx)
 605                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 606                 return 0;
 607         }
 608
 609         pci_dev = eth_dev->pci_dev;
 610
 611         hw->device_id = pci_dev->id.device_id;
 612         hw->vendor_id = pci_dev->id.vendor_id;
 613         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 614
 615         /* Initialize the shared code */
 616         diag = e1000_setup_init_funcs(hw, TRUE);
 617         if (diag != 0) {
 618                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 619                         diag);
 620                 return -EIO;
 621         }
 622
 623         /* init_mailbox_params */
 624         hw->mbx.ops.init_params(hw);
 625
 626         /* Disable the interrupts for VF */
 627         igbvf_intr_disable(hw);
 628
 629         diag = hw->mac.ops.reset_hw(hw);
 630
 631         /* Allocate memory for storing MAC addresses */
 632         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 633                 hw->mac.rar_entry_count, 0);
 634         if (eth_dev->data->mac_addrs == NULL) {
 635                 PMD_INIT_LOG(ERR,
 636                         "Failed to allocate %d bytes needed to store MAC "
 637                         "addresses",
 638                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 639                 return -ENOMEM;
 640         }
 641
 642         /* Copy the permanent MAC address */
 643         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 644                         &eth_dev->data->mac_addrs[0]);
 645
 646         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
 647                         "mac.type=%s\n",
 648                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 649                         pci_dev->id.device_id,
 650                         "igb_mac_82576_vf");
 651
 652         return 0;
 653 }
 654
 655 static struct eth_driver rte_igb_pmd = {
 656         {
 657                 .name = "rte_igb_pmd",
 658                 .id_table = pci_id_igb_map,
 659                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 660         },
 661         .eth_dev_init = eth_igb_dev_init,
 662         .dev_private_size = sizeof(struct e1000_adapter),
 663 };
 664
 665 /*
 666  * virtual function driver struct
 667  */
 668 static struct eth_driver rte_igbvf_pmd = {
 669         {
 670                 .name = "rte_igbvf_pmd",
 671                 .id_table = pci_id_igbvf_map,
 672                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 673         },
 674         .eth_dev_init = eth_igbvf_dev_init,
 675         .dev_private_size = sizeof(struct e1000_adapter),
 676 };
 677
 678 static int
 679 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 680 {
 681         rte_eth_driver_register(&rte_igb_pmd);
 682         return 0;
 683 }
 684
 685 static void
 686 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 687 {
 688         struct e1000_hw *hw =
 689                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 690         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 691         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 692         rctl |= E1000_RCTL_VFE;
 693         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 694 }
 695
 696 /*
 697  * VF Driver initialization routine.
 698  * Invoked one at EAL init time.
 699  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 700  */
 701 static int
 702 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 703 {
 704         DEBUGFUNC("rte_igbvf_pmd_init");
 705
 706         rte_eth_driver_register(&rte_igbvf_pmd);
 707         return (0);
 708 }
 709
 710 static int
 711 eth_igb_configure(struct rte_eth_dev *dev)
 712 {
 713         struct e1000_interrupt *intr =
 714                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 715
 716         PMD_INIT_LOG(DEBUG, ">>");
 717
 718         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 719
 720         PMD_INIT_LOG(DEBUG, "<<");
 721
 722         return (0);
 723 }
 724
 725 static int
 726 eth_igb_start(struct rte_eth_dev *dev)
 727 {
 728         struct e1000_hw *hw =
 729                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 730         int ret, i, mask;
 731         uint32_t ctrl_ext;
 732
 733         PMD_INIT_LOG(DEBUG, ">>");
 734
 735         /* Power up the phy. Needed to make the link go Up */
 736         e1000_power_up_phy(hw);
 737
 738         /*
 739          * Packet Buffer Allocation (PBA)
 740          * Writing PBA sets the receive portion of the buffer
 741          * the remainder is used for the transmit buffer.
 742          */
 743         if (hw->mac.type == e1000_82575) {
 744                 uint32_t pba;
 745
 746                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 747                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 748         }
 749
 750         /* Put the address into the Receive Address Array */
 751         e1000_rar_set(hw, hw->mac.addr, 0);
 752
 753         /* Initialize the hardware */
 754         if (igb_hardware_init(hw)) {
 755                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 756                 return (-EIO);
 757         }
 758
 759         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 760
 761         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 762         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 763         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 764         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 765         E1000_WRITE_FLUSH(hw);
 766
 767         /* configure PF module if SRIOV enabled */
 768         igb_pf_host_configure(dev);
 769
 770         /* Configure for OS presence */
 771         igb_init_manageability(hw);
 772
 773         eth_igb_tx_init(dev);
 774
 775         /* This can fail when allocating mbufs for descriptor rings */
 776         ret = eth_igb_rx_init(dev);
 777         if (ret) {
 778                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 779                 igb_dev_clear_queues(dev);
 780                 return ret;
 781         }
 782
 783         e1000_clear_hw_cntrs_base_generic(hw);
 784
 785         /*
 786          * VLAN Offload Settings
 787          */
 788         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 789                         ETH_VLAN_EXTEND_MASK;
 790         eth_igb_vlan_offload_set(dev, mask);
 791
 792         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 793                 /* Enable VLAN filter since VMDq always use VLAN filter */
 794                 igb_vmdq_vlan_hw_filter_enable(dev);
 795         }
 796
 797         /*
 798          * Configure the Interrupt Moderation register (EITR) with the maximum
 799          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 800          * spurious [DMA] memory updates of RX and TX ring descriptors.
 801          *
 802          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 803          * spurious memory updates per second should be expected.
 804          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 805          *
 806          * Because interrupts are not used at all, the MSI-X is not activated
 807          * and interrupt moderation is controlled by EITR[0].
 808          *
 809          * Note that having [almost] disabled memory updates of RX and TX ring
 810          * descriptors through the Interrupt Moderation mechanism, memory
 811          * updates of ring descriptors are now moderated by the configurable
 812          * value of Write-Back Threshold registers.
 813          */
 814         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 815                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 816                 uint32_t ivar;
 817
 818                 /* Enable all RX & TX queues in the IVAR registers */
 819                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 820                 for (i = 0; i < 8; i++)
 821                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 822
 823                 /* Configure EITR with the maximum possible value (0xFFFF) */
 824                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 825         }
 826
 827         /* Setup link speed and duplex */
 828         switch (dev->data->dev_conf.link_speed) {
 829         case ETH_LINK_SPEED_AUTONEG:
 830                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 831                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 832                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 833                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 834                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 835                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 836                 else
 837                         goto error_invalid_config;
 838                 break;
 839         case ETH_LINK_SPEED_10:
 840                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 841                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 842                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 843                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 844                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 845                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 846                 else
 847                         goto error_invalid_config;
 848                 break;
 849         case ETH_LINK_SPEED_100:
 850                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 851                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 852                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 853                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 854                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 855                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 856                 else
 857                         goto error_invalid_config;
 858                 break;
 859         case ETH_LINK_SPEED_1000:
 860                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 861                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 862                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 863                 else
 864                         goto error_invalid_config;
 865                 break;
 866         case ETH_LINK_SPEED_10000:
 867         default:
 868                 goto error_invalid_config;
 869         }
 870         e1000_setup_link(hw);
 871
 872         /* check if lsc interrupt feature is enabled */
 873         if (dev->data->dev_conf.intr_conf.lsc != 0)
 874                 ret = eth_igb_lsc_interrupt_setup(dev);
 875
 876         /* resume enabled intr since hw reset */
 877         igb_intr_enable(dev);
 878
 879         PMD_INIT_LOG(DEBUG, "<<");
 880
 881         return (0);
 882
 883 error_invalid_config:
 884         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 885                         dev->data->dev_conf.link_speed,
 886                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 887         igb_dev_clear_queues(dev);
 888         return (-EINVAL);
 889 }
 890
 891 /*********************************************************************
 892  *
 893  *  This routine disables all traffic on the adapter by issuing a
 894  *  global reset on the MAC.
 895  *
 896  **********************************************************************/
 897 static void
 898 eth_igb_stop(struct rte_eth_dev *dev)
 899 {
 900         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 901         struct rte_eth_link link;
 902
 903         igb_intr_disable(hw);
 904         igb_pf_reset_hw(hw);
 905         E1000_WRITE_REG(hw, E1000_WUC, 0);
 906
 907         /* Set bit for Go Link disconnect */
 908         if (hw->mac.type >= e1000_82580) {
 909                 uint32_t phpm_reg;
 910
 911                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 912                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 913                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 914         }
 915
 916         /* Power down the phy. Needed to make the link go Down */
 917         e1000_power_down_phy(hw);
 918
 919         igb_dev_clear_queues(dev);
 920
 921         /* clear the recorded link status */
 922         memset(&link, 0, sizeof(link));
 923         rte_igb_dev_atomic_write_link_status(dev, &link);
 924 }
 925
 926 static void
 927 eth_igb_close(struct rte_eth_dev *dev)
 928 {
 929         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 930         struct rte_eth_link link;
 931
 932         eth_igb_stop(dev);
 933         e1000_phy_hw_reset(hw);
 934         igb_release_manageability(hw);
 935         igb_hw_control_release(hw);
 936
 937         /* Clear bit for Go Link disconnect */
 938         if (hw->mac.type >= e1000_82580) {
 939                 uint32_t phpm_reg;
 940
 941                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 942                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
 943                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 944         }
 945
 946         igb_dev_clear_queues(dev);
 947
 948         memset(&link, 0, sizeof(link));
 949         rte_igb_dev_atomic_write_link_status(dev, &link);
 950 }
 951
 952 static int
 953 igb_get_rx_buffer_size(struct e1000_hw *hw)
 954 {
 955         uint32_t rx_buf_size;
 956         if (hw->mac.type == e1000_82576) {
 957                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 958         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 959                 /* PBS needs to be translated according to a lookup table */
 960                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 961                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 962                 rx_buf_size = (rx_buf_size << 10);
 963         } else if (hw->mac.type == e1000_i210) {
 964                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 965         } else {
 966                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 967         }
 968
 969         return rx_buf_size;
 970 }
 971
 972 /*********************************************************************
 973  *
 974  *  Initialize the hardware
 975  *
 976  **********************************************************************/
 977 static int
 978 igb_hardware_init(struct e1000_hw *hw)
 979 {
 980         uint32_t rx_buf_size;
 981         int diag;
 982
 983         /* Let the firmware know the OS is in control */
 984         igb_hw_control_acquire(hw);
 985
 986         /*
 987          * These parameters control the automatic generation (Tx) and
 988          * response (Rx) to Ethernet PAUSE frames.
 989          * - High water mark should allow for at least two standard size (1518)
 990          *   frames to be received after sending an XOFF.
 991          * - Low water mark works best when it is very near the high water mark.
 992          *   This allows the receiver to restart by sending XON when it has
 993          *   drained a bit. Here we use an arbitrary value of 1500 which will
 994          *   restart after one full frame is pulled from the buffer. There
 995          *   could be several smaller frames in the buffer and if so they will
 996          *   not trigger the XON until their total number reduces the buffer
 997          *   by 1500.
 998          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 999          */
1000         rx_buf_size = igb_get_rx_buffer_size(hw);
1001
1002         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1003         hw->fc.low_water = hw->fc.high_water - 1500;
1004         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1005         hw->fc.send_xon = 1;
1006
1007         /* Set Flow control, use the tunable location if sane */
1008         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1009                 hw->fc.requested_mode = igb_fc_setting;
1010         else
1011                 hw->fc.requested_mode = e1000_fc_none;
1012
1013         /* Issue a global reset */
1014         igb_pf_reset_hw(hw);
1015         E1000_WRITE_REG(hw, E1000_WUC, 0);
1016
1017         diag = e1000_init_hw(hw);
1018         if (diag < 0)
1019                 return (diag);
1020
1021         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1022         e1000_get_phy_info(hw);
1023         e1000_check_for_link(hw);
1024
1025         return (0);
1026 }
1027
1028 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1029 static void
1030 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1031 {
1032         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1033         struct e1000_hw_stats *stats =
1034                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1035         int pause_frames;
1036
1037         if(hw->phy.media_type == e1000_media_type_copper ||
1038             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1039                 stats->symerrs +=
1040                     E1000_READ_REG(hw,E1000_SYMERRS);
1041                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1042         }
1043
1044         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1045         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1046         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1047         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1048
1049         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1050         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1051         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1052         stats->dc += E1000_READ_REG(hw, E1000_DC);
1053         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1054         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1055         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1056         /*
1057         ** For watchdog management we need to know if we have been
1058         ** paused during the last interval, so capture that here.
1059         */
1060         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1061         stats->xoffrxc += pause_frames;
1062         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1063         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1064         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1065         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1066         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1067         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1068         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1069         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1070         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1071         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1072         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1073         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1074
1075         /* For the 64-bit byte counters the low dword must be read first. */
1076         /* Both registers clear on the read of the high dword */
1077
1078         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1079         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1080         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1081         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1082
1083         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1084         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1085         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1086         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1087         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1088
1089         stats->tor += E1000_READ_REG(hw, E1000_TORH);
1090         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1091
1092         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1093         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1094         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1095         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1096         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1097         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1098         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1099         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1100         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1101         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1102
1103         /* Interrupt Counts */
1104
1105         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1106         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1107         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1108         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1109         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1110         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1111         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1112         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1113         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1114
1115         /* Host to Card Statistics */
1116
1117         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1118         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1119         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1120         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1121         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1122         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1123         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1124         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1125         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1126         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1127         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1128         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1129         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1130         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1131
1132         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1133         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1134         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1135         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1136         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1137         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1138
1139         if (rte_stats == NULL)
1140                 return;
1141
1142         /* Rx Errors */
1143         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
1144             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
1145
1146         /* Tx Errors */
1147         rte_stats->oerrors = stats->ecol + stats->latecol;
1148
1149         /* XON/XOFF pause frames */
1150         rte_stats->tx_pause_xon  = stats->xontxc;
1151         rte_stats->rx_pause_xon  = stats->xonrxc;
1152         rte_stats->tx_pause_xoff = stats->xofftxc;
1153         rte_stats->rx_pause_xoff = stats->xoffrxc;
1154
1155         rte_stats->ipackets = stats->gprc;
1156         rte_stats->opackets = stats->gptc;
1157         rte_stats->ibytes   = stats->gorc;
1158         rte_stats->obytes   = stats->gotc;
1159 }
1160
1161 static void
1162 eth_igb_stats_reset(struct rte_eth_dev *dev)
1163 {
1164         struct e1000_hw_stats *hw_stats =
1165                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1166
1167         /* HW registers are cleared on read */
1168         eth_igb_stats_get(dev, NULL);
1169
1170         /* Reset software totals */
1171         memset(hw_stats, 0, sizeof(*hw_stats));
1172 }
1173
1174 static void
1175 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1176 {
1177         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1178         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1179                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1180
1181         /* Good Rx packets, include VF loopback */
1182         UPDATE_VF_STAT(E1000_VFGPRC,
1183             hw_stats->last_gprc, hw_stats->gprc);
1184
1185         /* Good Rx octets, include VF loopback */
1186         UPDATE_VF_STAT(E1000_VFGORC,
1187             hw_stats->last_gorc, hw_stats->gorc);
1188
1189         /* Good Tx packets, include VF loopback */
1190         UPDATE_VF_STAT(E1000_VFGPTC,
1191             hw_stats->last_gptc, hw_stats->gptc);
1192
1193         /* Good Tx octets, include VF loopback */
1194         UPDATE_VF_STAT(E1000_VFGOTC,
1195             hw_stats->last_gotc, hw_stats->gotc);
1196
1197         /* Rx Multicst packets */
1198         UPDATE_VF_STAT(E1000_VFMPRC,
1199             hw_stats->last_mprc, hw_stats->mprc);
1200
1201         /* Good Rx loopback packets */
1202         UPDATE_VF_STAT(E1000_VFGPRLBC,
1203             hw_stats->last_gprlbc, hw_stats->gprlbc);
1204
1205         /* Good Rx loopback octets */
1206         UPDATE_VF_STAT(E1000_VFGORLBC,
1207             hw_stats->last_gorlbc, hw_stats->gorlbc);
1208
1209         /* Good Tx loopback packets */
1210         UPDATE_VF_STAT(E1000_VFGPTLBC,
1211             hw_stats->last_gptlbc, hw_stats->gptlbc);
1212
1213         /* Good Tx loopback octets */
1214         UPDATE_VF_STAT(E1000_VFGOTLBC,
1215             hw_stats->last_gotlbc, hw_stats->gotlbc);
1216
1217         if (rte_stats == NULL)
1218                 return;
1219
1220         memset(rte_stats, 0, sizeof(*rte_stats));
1221         rte_stats->ipackets = hw_stats->gprc;
1222         rte_stats->ibytes = hw_stats->gorc;
1223         rte_stats->opackets = hw_stats->gptc;
1224         rte_stats->obytes = hw_stats->gotc;
1225         rte_stats->imcasts = hw_stats->mprc;
1226         rte_stats->ilbpackets = hw_stats->gprlbc;
1227         rte_stats->ilbbytes = hw_stats->gorlbc;
1228         rte_stats->olbpackets = hw_stats->gptlbc;
1229         rte_stats->olbbytes = hw_stats->gotlbc;
1230
1231 }
1232
1233 static void
1234 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1235 {
1236         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1237                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1238
1239         /* Sync HW register to the last stats */
1240         eth_igbvf_stats_get(dev, NULL);
1241
1242         /* reset HW current stats*/
1243         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1244                offsetof(struct e1000_vf_stats, gprc));
1245
1246 }
1247
1248 static void
1249 eth_igb_infos_get(struct rte_eth_dev *dev,
1250                     struct rte_eth_dev_info *dev_info)
1251 {
1252         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1253
1254         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1255         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1256         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1257         dev_info->rx_offload_capa =
1258                 DEV_RX_OFFLOAD_VLAN_STRIP |
1259                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1260                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1261                 DEV_RX_OFFLOAD_TCP_CKSUM;
1262         dev_info->tx_offload_capa =
1263                 DEV_TX_OFFLOAD_VLAN_INSERT |
1264                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1265                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1266                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1267                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1268
1269         switch (hw->mac.type) {
1270         case e1000_82575:
1271                 dev_info->max_rx_queues = 4;
1272                 dev_info->max_tx_queues = 4;
1273                 dev_info->max_vmdq_pools = 0;
1274                 break;
1275
1276         case e1000_82576:
1277                 dev_info->max_rx_queues = 16;
1278                 dev_info->max_tx_queues = 16;
1279                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1280                 break;
1281
1282         case e1000_82580:
1283                 dev_info->max_rx_queues = 8;
1284                 dev_info->max_tx_queues = 8;
1285                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1286                 break;
1287
1288         case e1000_i350:
1289                 dev_info->max_rx_queues = 8;
1290                 dev_info->max_tx_queues = 8;
1291                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1292                 break;
1293
1294         case e1000_i354:
1295                 dev_info->max_rx_queues = 8;
1296                 dev_info->max_tx_queues = 8;
1297                 break;
1298
1299         case e1000_i210:
1300                 dev_info->max_rx_queues = 4;
1301                 dev_info->max_tx_queues = 4;
1302                 dev_info->max_vmdq_pools = 0;
1303                 break;
1304
1305         case e1000_vfadapt:
1306                 dev_info->max_rx_queues = 2;
1307                 dev_info->max_tx_queues = 2;
1308                 dev_info->max_vmdq_pools = 0;
1309                 break;
1310
1311         case e1000_vfadapt_i350:
1312                 dev_info->max_rx_queues = 1;
1313                 dev_info->max_tx_queues = 1;
1314                 dev_info->max_vmdq_pools = 0;
1315                 break;
1316
1317         default:
1318                 /* Should not happen */
1319                 dev_info->max_rx_queues = 0;
1320                 dev_info->max_tx_queues = 0;
1321                 dev_info->max_vmdq_pools = 0;
1322         }
1323 }
1324
1325 /* return 0 means link status changed, -1 means not changed */
1326 static int
1327 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1328 {
1329         struct e1000_hw *hw =
1330                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1331         struct rte_eth_link link, old;
1332         int link_check, count;
1333
1334         link_check = 0;
1335         hw->mac.get_link_status = 1;
1336
1337         /* possible wait-to-complete in up to 9 seconds */
1338         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1339                 /* Read the real link status */
1340                 switch (hw->phy.media_type) {
1341                 case e1000_media_type_copper:
1342                         /* Do the work to read phy */
1343                         e1000_check_for_link(hw);
1344                         link_check = !hw->mac.get_link_status;
1345                         break;
1346
1347                 case e1000_media_type_fiber:
1348                         e1000_check_for_link(hw);
1349                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1350                                       E1000_STATUS_LU);
1351                         break;
1352
1353                 case e1000_media_type_internal_serdes:
1354                         e1000_check_for_link(hw);
1355                         link_check = hw->mac.serdes_has_link;
1356                         break;
1357
1358                 /* VF device is type_unknown */
1359                 case e1000_media_type_unknown:
1360                         eth_igbvf_link_update(hw);
1361                         link_check = !hw->mac.get_link_status;
1362                         break;
1363
1364                 default:
1365                         break;
1366                 }
1367                 if (link_check || wait_to_complete == 0)
1368                         break;
1369                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1370         }
1371         memset(&link, 0, sizeof(link));
1372         rte_igb_dev_atomic_read_link_status(dev, &link);
1373         old = link;
1374
1375         /* Now we check if a transition has happened */
1376         if (link_check) {
1377                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1378                                           &link.link_duplex);
1379                 link.link_status = 1;
1380         } else if (!link_check) {
1381                 link.link_speed = 0;
1382                 link.link_duplex = 0;
1383                 link.link_status = 0;
1384         }
1385         rte_igb_dev_atomic_write_link_status(dev, &link);
1386
1387         /* not changed */
1388         if (old.link_status == link.link_status)
1389                 return -1;
1390
1391         /* changed */
1392         return 0;
1393 }
1394
1395 /*
1396  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1397  * For ASF and Pass Through versions of f/w this means
1398  * that the driver is loaded.
1399  */
1400 static void
1401 igb_hw_control_acquire(struct e1000_hw *hw)
1402 {
1403         uint32_t ctrl_ext;
1404
1405         /* Let firmware know the driver has taken over */
1406         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1407         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1408 }
1409
1410 /*
1411  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1412  * For ASF and Pass Through versions of f/w this means that the
1413  * driver is no longer loaded.
1414  */
1415 static void
1416 igb_hw_control_release(struct e1000_hw *hw)
1417 {
1418         uint32_t ctrl_ext;
1419
1420         /* Let firmware taken over control of h/w */
1421         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1422         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1423                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1424 }
1425
1426 /*
1427  * Bit of a misnomer, what this really means is
1428  * to enable OS management of the system... aka
1429  * to disable special hardware management features.
1430  */
1431 static void
1432 igb_init_manageability(struct e1000_hw *hw)
1433 {
1434         if (e1000_enable_mng_pass_thru(hw)) {
1435                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1436                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1437
1438                 /* disable hardware interception of ARP */
1439                 manc &= ~(E1000_MANC_ARP_EN);
1440
1441                 /* enable receiving management packets to the host */
1442                 manc |= E1000_MANC_EN_MNG2HOST;
1443                 manc2h |= 1 << 5;  /* Mng Port 623 */
1444                 manc2h |= 1 << 6;  /* Mng Port 664 */
1445                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1446                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1447         }
1448 }
1449
1450 static void
1451 igb_release_manageability(struct e1000_hw *hw)
1452 {
1453         if (e1000_enable_mng_pass_thru(hw)) {
1454                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1455
1456                 manc |= E1000_MANC_ARP_EN;
1457                 manc &= ~E1000_MANC_EN_MNG2HOST;
1458
1459                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1460         }
1461 }
1462
1463 static void
1464 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1465 {
1466         struct e1000_hw *hw =
1467                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1468         uint32_t rctl;
1469
1470         rctl = E1000_READ_REG(hw, E1000_RCTL);
1471         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1472         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1473 }
1474
1475 static void
1476 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1477 {
1478         struct e1000_hw *hw =
1479                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1480         uint32_t rctl;
1481
1482         rctl = E1000_READ_REG(hw, E1000_RCTL);
1483         rctl &= (~E1000_RCTL_UPE);
1484         if (dev->data->all_multicast == 1)
1485                 rctl |= E1000_RCTL_MPE;
1486         else
1487                 rctl &= (~E1000_RCTL_MPE);
1488         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1489 }
1490
1491 static void
1492 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1493 {
1494         struct e1000_hw *hw =
1495                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1496         uint32_t rctl;
1497
1498         rctl = E1000_READ_REG(hw, E1000_RCTL);
1499         rctl |= E1000_RCTL_MPE;
1500         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1501 }
1502
1503 static void
1504 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1505 {
1506         struct e1000_hw *hw =
1507                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1508         uint32_t rctl;
1509
1510         if (dev->data->promiscuous == 1)
1511                 return; /* must remain in all_multicast mode */
1512         rctl = E1000_READ_REG(hw, E1000_RCTL);
1513         rctl &= (~E1000_RCTL_MPE);
1514         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1515 }
1516
1517 static int
1518 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1519 {
1520         struct e1000_hw *hw =
1521                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1522         struct e1000_vfta * shadow_vfta =
1523                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1524         uint32_t vfta;
1525         uint32_t vid_idx;
1526         uint32_t vid_bit;
1527
1528         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1529                               E1000_VFTA_ENTRY_MASK);
1530         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1531         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1532         if (on)
1533                 vfta |= vid_bit;
1534         else
1535                 vfta &= ~vid_bit;
1536         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1537
1538         /* update local VFTA copy */
1539         shadow_vfta->vfta[vid_idx] = vfta;
1540
1541         return 0;
1542 }
1543
1544 static void
1545 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1546 {
1547         struct e1000_hw *hw =
1548                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1549         uint32_t reg = ETHER_TYPE_VLAN ;
1550
1551         reg |= (tpid << 16);
1552         E1000_WRITE_REG(hw, E1000_VET, reg);
1553 }
1554
1555 static void
1556 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1557 {
1558         struct e1000_hw *hw =
1559                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1560         uint32_t reg;
1561
1562         /* Filter Table Disable */
1563         reg = E1000_READ_REG(hw, E1000_RCTL);
1564         reg &= ~E1000_RCTL_CFIEN;
1565         reg &= ~E1000_RCTL_VFE;
1566         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1567 }
1568
1569 static void
1570 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1571 {
1572         struct e1000_hw *hw =
1573                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1574         struct e1000_vfta * shadow_vfta =
1575                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1576         uint32_t reg;
1577         int i;
1578
1579         /* Filter Table Enable, CFI not used for packet acceptance */
1580         reg = E1000_READ_REG(hw, E1000_RCTL);
1581         reg &= ~E1000_RCTL_CFIEN;
1582         reg |= E1000_RCTL_VFE;
1583         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1584
1585         /* restore VFTA table */
1586         for (i = 0; i < IGB_VFTA_SIZE; i++)
1587                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1588 }
1589
1590 static void
1591 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1592 {
1593         struct e1000_hw *hw =
1594                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595         uint32_t reg;
1596
1597         /* VLAN Mode Disable */
1598         reg = E1000_READ_REG(hw, E1000_CTRL);
1599         reg &= ~E1000_CTRL_VME;
1600         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1601 }
1602
1603 static void
1604 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1605 {
1606         struct e1000_hw *hw =
1607                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1608         uint32_t reg;
1609
1610         /* VLAN Mode Enable */
1611         reg = E1000_READ_REG(hw, E1000_CTRL);
1612         reg |= E1000_CTRL_VME;
1613         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1614 }
1615
1616 static void
1617 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1618 {
1619         struct e1000_hw *hw =
1620                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1621         uint32_t reg;
1622
1623         /* CTRL_EXT: Extended VLAN */
1624         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1625         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1626         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1627
1628         /* Update maximum packet length */
1629         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1630                 E1000_WRITE_REG(hw, E1000_RLPML,
1631                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1632                                                 VLAN_TAG_SIZE);
1633 }
1634
1635 static void
1636 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1637 {
1638         struct e1000_hw *hw =
1639                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640         uint32_t reg;
1641
1642         /* CTRL_EXT: Extended VLAN */
1643         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1644         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1645         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1646
1647         /* Update maximum packet length */
1648         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1649                 E1000_WRITE_REG(hw, E1000_RLPML,
1650                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1651                                                 2 * VLAN_TAG_SIZE);
1652 }
1653
1654 static void
1655 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1656 {
1657         if(mask & ETH_VLAN_STRIP_MASK){
1658                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1659                         igb_vlan_hw_strip_enable(dev);
1660                 else
1661                         igb_vlan_hw_strip_disable(dev);
1662         }
1663
1664         if(mask & ETH_VLAN_FILTER_MASK){
1665                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1666                         igb_vlan_hw_filter_enable(dev);
1667                 else
1668                         igb_vlan_hw_filter_disable(dev);
1669         }
1670
1671         if(mask & ETH_VLAN_EXTEND_MASK){
1672                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1673                         igb_vlan_hw_extend_enable(dev);
1674                 else
1675                         igb_vlan_hw_extend_disable(dev);
1676         }
1677 }
1678
1679
1680 /**
1681  * It enables the interrupt mask and then enable the interrupt.
1682  *
1683  * @param dev
1684  *  Pointer to struct rte_eth_dev.
1685  *
1686  * @return
1687  *  - On success, zero.
1688  *  - On failure, a negative value.
1689  */
1690 static int
1691 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1692 {
1693         struct e1000_interrupt *intr =
1694                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1695
1696         intr->mask |= E1000_ICR_LSC;
1697
1698         return 0;
1699 }
1700
1701 /*
1702  * It reads ICR and gets interrupt causes, check it and set a bit flag
1703  * to update link status.
1704  *
1705  * @param dev
1706  *  Pointer to struct rte_eth_dev.
1707  *
1708  * @return
1709  *  - On success, zero.
1710  *  - On failure, a negative value.
1711  */
1712 static int
1713 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1714 {
1715         uint32_t icr;
1716         struct e1000_hw *hw =
1717                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1718         struct e1000_interrupt *intr =
1719                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1720
1721         igb_intr_disable(hw);
1722
1723         /* read-on-clear nic registers here */
1724         icr = E1000_READ_REG(hw, E1000_ICR);
1725
1726         intr->flags = 0;
1727         if (icr & E1000_ICR_LSC) {
1728                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1729         }
1730
1731         if (icr & E1000_ICR_VMMB)
1732                 intr->flags |= E1000_FLAG_MAILBOX;
1733
1734         return 0;
1735 }
1736
1737 /*
1738  * It executes link_update after knowing an interrupt is prsent.
1739  *
1740  * @param dev
1741  *  Pointer to struct rte_eth_dev.
1742  *
1743  * @return
1744  *  - On success, zero.
1745  *  - On failure, a negative value.
1746  */
1747 static int
1748 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1749 {
1750         struct e1000_hw *hw =
1751                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752         struct e1000_interrupt *intr =
1753                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1754         uint32_t tctl, rctl;
1755         struct rte_eth_link link;
1756         int ret;
1757
1758         if (intr->flags & E1000_FLAG_MAILBOX) {
1759                 igb_pf_mbx_process(dev);
1760                 intr->flags &= ~E1000_FLAG_MAILBOX;
1761         }
1762
1763         igb_intr_enable(dev);
1764         rte_intr_enable(&(dev->pci_dev->intr_handle));
1765
1766         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1767                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1768
1769                 /* set get_link_status to check register later */
1770                 hw->mac.get_link_status = 1;
1771                 ret = eth_igb_link_update(dev, 0);
1772
1773                 /* check if link has changed */
1774                 if (ret < 0)
1775                         return 0;
1776
1777                 memset(&link, 0, sizeof(link));
1778                 rte_igb_dev_atomic_read_link_status(dev, &link);
1779                 if (link.link_status) {
1780                         PMD_INIT_LOG(INFO,
1781                                 " Port %d: Link Up - speed %u Mbps - %s\n",
1782                                 dev->data->port_id, (unsigned)link.link_speed,
1783                                 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1784                                         "full-duplex" : "half-duplex");
1785                 } else {
1786                         PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1787                                                 dev->data->port_id);
1788                 }
1789                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1790                                         dev->pci_dev->addr.domain,
1791                                         dev->pci_dev->addr.bus,
1792                                         dev->pci_dev->addr.devid,
1793                                         dev->pci_dev->addr.function);
1794                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1795                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1796                 if (link.link_status) {
1797                         /* enable Tx/Rx */
1798                         tctl |= E1000_TCTL_EN;
1799                         rctl |= E1000_RCTL_EN;
1800                 } else {
1801                         /* disable Tx/Rx */
1802                         tctl &= ~E1000_TCTL_EN;
1803                         rctl &= ~E1000_RCTL_EN;
1804                 }
1805                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1806                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1807                 E1000_WRITE_FLUSH(hw);
1808                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1809         }
1810
1811         return 0;
1812 }
1813
1814 /**
1815  * Interrupt handler which shall be registered at first.
1816  *
1817  * @param handle
1818  *  Pointer to interrupt handle.
1819  * @param param
1820  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1821  *
1822  * @return
1823  *  void
1824  */
1825 static void
1826 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1827                                                         void *param)
1828 {
1829         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1830
1831         eth_igb_interrupt_get_status(dev);
1832         eth_igb_interrupt_action(dev);
1833 }
1834
1835 static int
1836 eth_igb_led_on(struct rte_eth_dev *dev)
1837 {
1838         struct e1000_hw *hw;
1839
1840         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1841         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1842 }
1843
1844 static int
1845 eth_igb_led_off(struct rte_eth_dev *dev)
1846 {
1847         struct e1000_hw *hw;
1848
1849         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1850         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1851 }
1852
1853 static int
1854 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1855 {
1856         struct e1000_hw *hw;
1857         int err;
1858         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1859                 e1000_fc_none,
1860                 e1000_fc_rx_pause,
1861                 e1000_fc_tx_pause,
1862                 e1000_fc_full
1863         };
1864         uint32_t rx_buf_size;
1865         uint32_t max_high_water;
1866         uint32_t rctl;
1867
1868         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869         rx_buf_size = igb_get_rx_buffer_size(hw);
1870         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1871
1872         /* At least reserve one Ethernet frame for watermark */
1873         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1874         if ((fc_conf->high_water > max_high_water) ||
1875                 (fc_conf->high_water < fc_conf->low_water)) {
1876                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1877                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1878                 return (-EINVAL);
1879         }
1880
1881         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1882         hw->fc.pause_time     = fc_conf->pause_time;
1883         hw->fc.high_water     = fc_conf->high_water;
1884         hw->fc.low_water      = fc_conf->low_water;
1885         hw->fc.send_xon       = fc_conf->send_xon;
1886
1887         err = e1000_setup_link_generic(hw);
1888         if (err == E1000_SUCCESS) {
1889
1890                 /* check if we want to forward MAC frames - driver doesn't have native
1891                  * capability to do that, so we'll write the registers ourselves */
1892
1893                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1894
1895                 /* set or clear MFLCN.PMCF bit depending on configuration */
1896                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1897                         rctl |= E1000_RCTL_PMCF;
1898                 else
1899                         rctl &= ~E1000_RCTL_PMCF;
1900
1901                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1902                 E1000_WRITE_FLUSH(hw);
1903
1904                 return 0;
1905         }
1906
1907         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1908         return (-EIO);
1909 }
1910
1911 #define E1000_RAH_POOLSEL_SHIFT      (18)
1912 static void
1913 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1914                 uint32_t index, __rte_unused uint32_t pool)
1915 {
1916         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917         uint32_t rah;
1918
1919         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1920         rah = E1000_READ_REG(hw, E1000_RAH(index));
1921         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
1922         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
1923 }
1924
1925 static void
1926 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1927 {
1928         uint8_t addr[ETHER_ADDR_LEN];
1929         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930
1931         memset(addr, 0, sizeof(addr));
1932
1933         e1000_rar_set(hw, addr, index);
1934 }
1935
1936 /*
1937  * Virtual Function operations
1938  */
1939 static void
1940 igbvf_intr_disable(struct e1000_hw *hw)
1941 {
1942         PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1943
1944         /* Clear interrupt mask to stop from interrupts being generated */
1945         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
1946
1947         E1000_WRITE_FLUSH(hw);
1948 }
1949
1950 static void
1951 igbvf_stop_adapter(struct rte_eth_dev *dev)
1952 {
1953         u32 reg_val;
1954         u16 i;
1955         struct rte_eth_dev_info dev_info;
1956         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1957
1958         memset(&dev_info, 0, sizeof(dev_info));
1959         eth_igb_infos_get(dev, &dev_info);
1960
1961         /* Clear interrupt mask to stop from interrupts being generated */
1962         igbvf_intr_disable(hw);
1963
1964         /* Clear any pending interrupts, flush previous writes */
1965         E1000_READ_REG(hw, E1000_EICR);
1966
1967         /* Disable the transmit unit.  Each queue must be disabled. */
1968         for (i = 0; i < dev_info.max_tx_queues; i++)
1969                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1970
1971         /* Disable the receive unit by stopping each queue */
1972         for (i = 0; i < dev_info.max_rx_queues; i++) {
1973                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1974                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1975                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1976                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1977                         ;
1978         }
1979
1980         /* flush all queues disables */
1981         E1000_WRITE_FLUSH(hw);
1982         msec_delay(2);
1983 }
1984
1985 static int eth_igbvf_link_update(struct e1000_hw *hw)
1986 {
1987         struct e1000_mbx_info *mbx = &hw->mbx;
1988         struct e1000_mac_info *mac = &hw->mac;
1989         int ret_val = E1000_SUCCESS;
1990
1991         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1992
1993         /*
1994          * We only want to run this if there has been a rst asserted.
1995          * in this case that could mean a link change, device reset,
1996          * or a virtual function reset
1997          */
1998
1999         /* If we were hit with a reset or timeout drop the link */
2000         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2001                 mac->get_link_status = TRUE;
2002
2003         if (!mac->get_link_status)
2004                 goto out;
2005
2006         /* if link status is down no point in checking to see if pf is up */
2007         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2008                 goto out;
2009
2010         /* if we passed all the tests above then the link is up and we no
2011          * longer need to check for link */
2012         mac->get_link_status = FALSE;
2013
2014 out:
2015         return ret_val;
2016 }
2017
2018
2019 static int
2020 igbvf_dev_configure(struct rte_eth_dev *dev)
2021 {
2022         struct rte_eth_conf* conf = &dev->data->dev_conf;
2023
2024         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2025                 dev->data->port_id);
2026
2027         /*
2028          * VF has no ability to enable/disable HW CRC
2029          * Keep the persistent behavior the same as Host PF
2030          */
2031 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2032         if (!conf->rxmode.hw_strip_crc) {
2033                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2034                 conf->rxmode.hw_strip_crc = 1;
2035         }
2036 #else
2037         if (conf->rxmode.hw_strip_crc) {
2038                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2039                 conf->rxmode.hw_strip_crc = 0;
2040         }
2041 #endif
2042
2043         return 0;
2044 }
2045
2046 static int
2047 igbvf_dev_start(struct rte_eth_dev *dev)
2048 {
2049         struct e1000_hw *hw =
2050                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051         int ret;
2052
2053         PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
2054
2055         hw->mac.ops.reset_hw(hw);
2056
2057         /* Set all vfta */
2058         igbvf_set_vfta_all(dev,1);
2059
2060         eth_igbvf_tx_init(dev);
2061
2062         /* This can fail when allocating mbufs for descriptor rings */
2063         ret = eth_igbvf_rx_init(dev);
2064         if (ret) {
2065                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2066                 igb_dev_clear_queues(dev);
2067                 return ret;
2068         }
2069
2070         return 0;
2071 }
2072
2073 static void
2074 igbvf_dev_stop(struct rte_eth_dev *dev)
2075 {
2076         PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
2077
2078         igbvf_stop_adapter(dev);
2079
2080         /*
2081           * Clear what we set, but we still keep shadow_vfta to
2082           * restore after device starts
2083           */
2084         igbvf_set_vfta_all(dev,0);
2085
2086         igb_dev_clear_queues(dev);
2087 }
2088
2089 static void
2090 igbvf_dev_close(struct rte_eth_dev *dev)
2091 {
2092         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2093
2094         PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
2095
2096         e1000_reset_hw(hw);
2097
2098         igbvf_dev_stop(dev);
2099 }
2100
2101 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2102 {
2103         struct e1000_mbx_info *mbx = &hw->mbx;
2104         uint32_t msgbuf[2];
2105
2106         /* After set vlan, vlan strip will also be enabled in igb driver*/
2107         msgbuf[0] = E1000_VF_SET_VLAN;
2108         msgbuf[1] = vid;
2109         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2110         if (on)
2111                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2112
2113         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2114 }
2115
2116 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2117 {
2118         struct e1000_hw *hw =
2119                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120         struct e1000_vfta * shadow_vfta =
2121                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2122         int i = 0, j = 0, vfta = 0, mask = 1;
2123
2124         for (i = 0; i < IGB_VFTA_SIZE; i++){
2125                 vfta = shadow_vfta->vfta[i];
2126                 if(vfta){
2127                         mask = 1;
2128                         for (j = 0; j < 32; j++){
2129                                 if(vfta & mask)
2130                                         igbvf_set_vfta(hw,
2131                                                 (uint16_t)((i<<5)+j), on);
2132                                 mask<<=1;
2133                         }
2134                 }
2135         }
2136
2137 }
2138
2139 static int
2140 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2141 {
2142         struct e1000_hw *hw =
2143                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144         struct e1000_vfta * shadow_vfta =
2145                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2146         uint32_t vid_idx = 0;
2147         uint32_t vid_bit = 0;
2148         int ret = 0;
2149
2150         PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
2151
2152         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2153         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2154         if(ret){
2155                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2156                 return ret;
2157         }
2158         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2159         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2160
2161         /*Save what we set and retore it after device reset*/
2162         if (on)
2163                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2164         else
2165                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2166
2167         return 0;
2168 }
2169
2170 static int
2171 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2172                                 struct rte_eth_rss_reta *reta_conf)
2173 {
2174         uint8_t i,j,mask;
2175         uint32_t reta;
2176         struct e1000_hw *hw =
2177                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2178
2179         /*
2180          * Update Redirection Table RETA[n],n=0...31,The redirection table has
2181          * 128-entries in 32 registers
2182          */
2183         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2184                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2185                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2186                 else
2187                         mask = (uint8_t)((reta_conf->mask_hi >>
2188                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2189                 if (mask != 0) {
2190                         reta = 0;
2191                         /* If all 4 entries were set,don't need read RETA register */
2192                         if (mask != 0xF)
2193                                 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2194
2195                         for (j = 0; j < 4; j++) {
2196                                 if (mask & (0x1 << j)) {
2197                                         if (mask != 0xF)
2198                                                 reta &= ~(0xFF << 8 * j);
2199                                         reta |= reta_conf->reta[i + j] << 8 * j;
2200                                 }
2201                         }
2202                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2203                 }
2204         }
2205
2206         return 0;
2207 }
2208
2209 static int
2210 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2211                                 struct rte_eth_rss_reta *reta_conf)
2212 {
2213         uint8_t i,j,mask;
2214         uint32_t reta;
2215         struct e1000_hw *hw =
2216                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2217
2218         /*
2219          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2220          * 128-entries in 32 registers
2221          */
2222         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2223                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2224                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2225                 else
2226                         mask = (uint8_t)((reta_conf->mask_hi >>
2227                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2228
2229                 if (mask != 0) {
2230                         reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2231                         for (j = 0; j < 4; j++) {
2232                                 if (mask & (0x1 << j))
2233                                         reta_conf->reta[i + j] =
2234                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2235                         }
2236                 }
2237         }
2238
2239         return 0;
2240 }
2241
2242 #define MAC_TYPE_FILTER_SUP(type)    do {\
2243         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2244                 (type) != e1000_82576)\
2245                 return -ENOSYS;\
2246 } while (0)
2247
2248 /*
2249  * add the syn filter
2250  *
2251  * @param
2252  * dev: Pointer to struct rte_eth_dev.
2253  * filter: ponter to the filter that will be added.
2254  * rx_queue: the queue id the filter assigned to.
2255  *
2256  * @return
2257  *    - On success, zero.
2258  *    - On failure, a negative value.
2259  */
2260 static int
2261 eth_igb_add_syn_filter(struct rte_eth_dev *dev,
2262                         struct rte_syn_filter *filter, uint16_t rx_queue)
2263 {
2264         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2265         uint32_t synqf, rfctl;
2266
2267         MAC_TYPE_FILTER_SUP(hw->mac.type);
2268
2269         if (rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2270                 return -EINVAL;
2271
2272         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2273         if (synqf & E1000_SYN_FILTER_ENABLE)
2274                 return -EINVAL;
2275
2276         synqf = (uint32_t)(((rx_queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2277                 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2278
2279         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2280         if (filter->hig_pri)
2281                 rfctl |= E1000_RFCTL_SYNQFP;
2282         else
2283                 rfctl &= ~E1000_RFCTL_SYNQFP;
2284
2285         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2286         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2287         return 0;
2288 }
2289
2290 /*
2291  * remove the syn filter
2292  *
2293  * @param
2294  * dev: Pointer to struct rte_eth_dev.
2295  *
2296  * @return
2297  *    - On success, zero.
2298  *    - On failure, a negative value.
2299  */
2300 static int
2301 eth_igb_remove_syn_filter(struct rte_eth_dev *dev)
2302 {
2303         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2304
2305         MAC_TYPE_FILTER_SUP(hw->mac.type);
2306
2307         E1000_WRITE_REG(hw, E1000_SYNQF(0), 0);
2308         return 0;
2309 }
2310
2311 /*
2312  * get the syn filter's info
2313  *
2314  * @param
2315  * dev: Pointer to struct rte_eth_dev.
2316  * filter: ponter to the filter that returns.
2317  * *rx_queue: pointer to the queue id the filter assigned to.
2318  *
2319  * @return
2320  *    - On success, zero.
2321  *    - On failure, a negative value.
2322  */
2323 static int
2324 eth_igb_get_syn_filter(struct rte_eth_dev *dev,
2325                         struct rte_syn_filter *filter, uint16_t *rx_queue)
2326 {
2327         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2328         uint32_t synqf, rfctl;
2329
2330         MAC_TYPE_FILTER_SUP(hw->mac.type);
2331         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2332         if (synqf & E1000_SYN_FILTER_ENABLE) {
2333                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2334                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2335                 *rx_queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2336                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2337                 return 0;
2338         }
2339         return -ENOENT;
2340 }
2341
2342 /*
2343  * add an ethertype filter
2344  *
2345  * @param
2346  * dev: Pointer to struct rte_eth_dev.
2347  * index: the index the filter allocates.
2348  * filter: ponter to the filter that will be added.
2349  * rx_queue: the queue id the filter assigned to.
2350  *
2351  * @return
2352  *    - On success, zero.
2353  *    - On failure, a negative value.
2354  */
2355 static int
2356 eth_igb_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2357                         struct rte_ethertype_filter *filter, uint16_t rx_queue)
2358 {
2359         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2360         uint32_t etqf;
2361
2362         MAC_TYPE_FILTER_SUP(hw->mac.type);
2363
2364         if (index >= E1000_MAX_ETQF_FILTERS || rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2365                 return -EINVAL;
2366
2367         etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2368         if (etqf & E1000_ETQF_FILTER_ENABLE)
2369                 return -EINVAL;  /* filter index is in use. */
2370         else
2371                 etqf = 0;
2372
2373         etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
2374         etqf |= (uint32_t)(filter->ethertype & E1000_ETQF_ETHERTYPE);
2375         etqf |= rx_queue << E1000_ETQF_QUEUE_SHIFT;
2376
2377         if (filter->priority_en) {
2378                 PMD_INIT_LOG(ERR, "vlan and priority (%d) is not supported"
2379                         " in E1000.", filter->priority);
2380                 return -EINVAL;
2381         }
2382
2383         E1000_WRITE_REG(hw, E1000_ETQF(index), etqf);
2384         return 0;
2385 }
2386
2387 /*
2388  * remove an ethertype filter
2389  *
2390  * @param
2391  * dev: Pointer to struct rte_eth_dev.
2392  * index: the index the filter allocates.
2393  *
2394  * @return
2395  *    - On success, zero.
2396  *    - On failure, a negative value.
2397  */
2398 static int
2399 eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev, uint16_t index)
2400 {
2401         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2402
2403         MAC_TYPE_FILTER_SUP(hw->mac.type);
2404
2405         if (index >= E1000_MAX_ETQF_FILTERS)
2406                 return -EINVAL;
2407
2408         E1000_WRITE_REG(hw, E1000_ETQF(index), 0);
2409         return 0;
2410 }
2411
2412 /*
2413  * get an ethertype filter
2414  *
2415  * @param
2416  * dev: Pointer to struct rte_eth_dev.
2417  * index: the index the filter allocates.
2418  * filter: ponter to the filter that will be gotten.
2419  * *rx_queue: the ponited of the queue id the filter assigned to.
2420  *
2421  * @return
2422  *    - On success, zero.
2423  *    - On failure, a negative value.
2424  */
2425 static int
2426 eth_igb_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2427                         struct rte_ethertype_filter *filter, uint16_t *rx_queue)
2428 {
2429         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430         uint32_t etqf;
2431
2432         MAC_TYPE_FILTER_SUP(hw->mac.type);
2433
2434         if (index >= E1000_MAX_ETQF_FILTERS)
2435                 return -EINVAL;
2436
2437         etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2438         if (etqf & E1000_ETQF_FILTER_ENABLE) {
2439                 filter->ethertype = etqf & E1000_ETQF_ETHERTYPE;
2440                 filter->priority_en = 0;
2441                 *rx_queue = (etqf & E1000_ETQF_QUEUE) >> E1000_ETQF_QUEUE_SHIFT;
2442                 return 0;
2443         }
2444         return -ENOENT;
2445 }
2446
2447 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2448         if ((type) != e1000_82580 && (type) != e1000_i350)\
2449                 return -ENOSYS; \
2450 } while (0)
2451
2452 /*
2453  * add a 2tuple filter
2454  *
2455  * @param
2456  * dev: Pointer to struct rte_eth_dev.
2457  * index: the index the filter allocates.
2458  * filter: ponter to the filter that will be added.
2459  * rx_queue: the queue id the filter assigned to.
2460  *
2461  * @return
2462  *    - On success, zero.
2463  *    - On failure, a negative value.
2464  */
2465 static int
2466 eth_igb_add_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2467                         struct rte_2tuple_filter *filter, uint16_t rx_queue)
2468 {
2469         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2470         uint32_t ttqf, imir = 0;
2471         uint32_t imir_ext = 0;
2472
2473         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2474
2475         if (index >= E1000_MAX_TTQF_FILTERS ||
2476                 rx_queue >= IGB_MAX_RX_QUEUE_NUM ||
2477                 filter->priority > E1000_2TUPLE_MAX_PRI)
2478                 return -EINVAL;  /* filter index is out of range. */
2479         if  (filter->tcp_flags > TCP_FLAG_ALL)
2480                 return -EINVAL;  /* flags is invalid. */
2481
2482         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2483         if (ttqf & E1000_TTQF_QUEUE_ENABLE)
2484                 return -EINVAL;  /* filter index is in use. */
2485
2486         imir = (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2487         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2488                 imir |= E1000_IMIR_PORT_BP;
2489         else
2490                 imir &= ~E1000_IMIR_PORT_BP;
2491
2492         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2493
2494         ttqf = 0;
2495         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2496         ttqf |= (uint32_t)(rx_queue << E1000_TTQF_QUEUE_SHIFT);
2497         ttqf |= (uint32_t)(filter->protocol & E1000_TTQF_PROTOCOL_MASK);
2498         if (filter->protocol_mask == 1)
2499                 ttqf |= E1000_TTQF_MASK_ENABLE;
2500         else
2501                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2502
2503         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2504         /* tcp flags bits setting. */
2505         if (filter->tcp_flags & TCP_FLAG_ALL) {
2506                 if (filter->tcp_flags & TCP_UGR_FLAG)
2507                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2508                 if (filter->tcp_flags & TCP_ACK_FLAG)
2509                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2510                 if (filter->tcp_flags & TCP_PSH_FLAG)
2511                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2512                 if (filter->tcp_flags & TCP_RST_FLAG)
2513                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2514                 if (filter->tcp_flags & TCP_SYN_FLAG)
2515                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2516                 if (filter->tcp_flags & TCP_FIN_FLAG)
2517                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2518                 imir_ext &= ~E1000_IMIR_EXT_CTRL_BP;
2519         } else
2520                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2521         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2522         E1000_WRITE_REG(hw, E1000_TTQF(index), ttqf);
2523         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2524         return 0;
2525 }
2526
2527 /*
2528  * remove a 2tuple filter
2529  *
2530  * @param
2531  * dev: Pointer to struct rte_eth_dev.
2532  * index: the index the filter allocates.
2533  *
2534  * @return
2535  *    - On success, zero.
2536  *    - On failure, a negative value.
2537  */
2538 static int
2539 eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2540                         uint16_t index)
2541 {
2542         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2543
2544         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2545
2546         if (index >= E1000_MAX_TTQF_FILTERS)
2547                 return -EINVAL;  /* filter index is out of range */
2548
2549         E1000_WRITE_REG(hw, E1000_TTQF(index), 0);
2550         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2551         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2552         return 0;
2553 }
2554
2555 /*
2556  * get a 2tuple filter
2557  *
2558  * @param
2559  * dev: Pointer to struct rte_eth_dev.
2560  * index: the index the filter allocates.
2561  * filter: ponter to the filter that returns.
2562  * *rx_queue: pointer of the queue id the filter assigned to.
2563  *
2564  * @return
2565  *    - On success, zero.
2566  *    - On failure, a negative value.
2567  */
2568 static int
2569 eth_igb_get_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2570                         struct rte_2tuple_filter *filter, uint16_t *rx_queue)
2571 {
2572         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2573         uint32_t imir, ttqf, imir_ext;
2574
2575         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2576
2577         if (index >= E1000_MAX_TTQF_FILTERS)
2578                 return -EINVAL;  /* filter index is out of range. */
2579
2580         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2581         if (ttqf & E1000_TTQF_QUEUE_ENABLE) {
2582                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2583                 filter->protocol = ttqf & E1000_TTQF_PROTOCOL_MASK;
2584                 filter->protocol_mask = (ttqf & E1000_TTQF_MASK_ENABLE) ? 1 : 0;
2585                 *rx_queue = (ttqf & E1000_TTQF_RX_QUEUE_MASK) >>
2586                                 E1000_TTQF_QUEUE_SHIFT;
2587                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2588                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2589                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2590                         E1000_IMIR_PRIORITY_SHIFT;
2591
2592                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2593                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2594                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2595                                 filter->tcp_flags |= TCP_UGR_FLAG;
2596                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2597                                 filter->tcp_flags |= TCP_ACK_FLAG;
2598                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2599                                 filter->tcp_flags |= TCP_PSH_FLAG;
2600                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2601                                 filter->tcp_flags |= TCP_RST_FLAG;
2602                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2603                                 filter->tcp_flags |= TCP_SYN_FLAG;
2604                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2605                                 filter->tcp_flags |= TCP_FIN_FLAG;
2606                 } else
2607                         filter->tcp_flags = 0;
2608                 return 0;
2609         }
2610         return -ENOENT;
2611 }
2612
2613 /*
2614  * add a flex filter
2615  *
2616  * @param
2617  * dev: Pointer to struct rte_eth_dev.
2618  * index: the index the filter allocates.
2619  * filter: ponter to the filter that will be added.
2620  * rx_queue: the queue id the filter assigned to.
2621  *
2622  * @return
2623  *    - On success, zero.
2624  *     - On failure, a negative value.
2625  */
2626 static int
2627 eth_igb_add_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2628                         struct rte_flex_filter *filter, uint16_t rx_queue)
2629 {
2630         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2631         uint32_t wufc, en_bits = 0;
2632         uint32_t queueing = 0;
2633         uint32_t reg_off = 0;
2634         uint8_t i, j = 0;
2635
2636         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2637
2638         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2639                 return -EINVAL;  /* filter index is out of range. */
2640
2641         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN ||
2642                 filter->len % 8 != 0 ||
2643                 filter->priority > E1000_MAX_FLEX_FILTER_PRI)
2644                 return -EINVAL;
2645
2646         wufc = E1000_READ_REG(hw, E1000_WUFC);
2647         en_bits = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2648         if ((wufc & en_bits) == en_bits)
2649                 return -EINVAL;  /* the filter is in use. */
2650
2651         E1000_WRITE_REG(hw, E1000_WUFC,
2652                 wufc | E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index));
2653
2654         j = 0;
2655         if (index < E1000_MAX_FHFT)
2656                 reg_off = E1000_FHFT(index);
2657         else
2658                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2659
2660         for (i = 0; i < 16; i++) {
2661                 E1000_WRITE_REG(hw, reg_off + i*4*4, filter->dwords[j]);
2662                 E1000_WRITE_REG(hw, reg_off + (i*4+1)*4, filter->dwords[++j]);
2663                 E1000_WRITE_REG(hw, reg_off + (i*4+2)*4,
2664                                 (uint32_t)filter->mask[i]);
2665                 ++j;
2666         }
2667         queueing |= filter->len |
2668                 (rx_queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2669                 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2670         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET, queueing);
2671         return 0;
2672 }
2673
2674 /*
2675  * remove a flex filter
2676  *
2677  * @param
2678  * dev: Pointer to struct rte_eth_dev.
2679  * index: the index the filter allocates.
2680  *
2681  * @return
2682  *    - On success, zero.
2683  *    - On failure, a negative value.
2684  */
2685 static int
2686 eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
2687                                 uint16_t index)
2688 {
2689         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2690         uint32_t wufc, reg_off = 0;
2691         uint8_t i;
2692
2693         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2694
2695         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2696                 return -EINVAL;  /* filter index is out of range. */
2697
2698         wufc = E1000_READ_REG(hw, E1000_WUFC);
2699         E1000_WRITE_REG(hw, E1000_WUFC, wufc & (~(E1000_WUFC_FLX0 << index)));
2700
2701         if (index < E1000_MAX_FHFT)
2702                 reg_off = E1000_FHFT(index);
2703         else
2704                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2705
2706         for (i = 0; i < 64; i++)
2707                 E1000_WRITE_REG(hw, reg_off + i*4, 0);
2708         return 0;
2709 }
2710
2711 /*
2712  * get a flex filter
2713  *
2714  * @param
2715  * dev: Pointer to struct rte_eth_dev.
2716  * index: the index the filter allocates.
2717  * filter: ponter to the filter that returns.
2718  * *rx_queue: the pointer of the queue id the filter assigned to.
2719  *
2720  * @return
2721  *    - On success, zero.
2722  *    - On failure, a negative value.
2723  */
2724 static int
2725 eth_igb_get_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2726                         struct rte_flex_filter *filter, uint16_t *rx_queue)
2727 {
2728         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2729         uint32_t wufc, queueing, wufc_en = 0;
2730         uint8_t i, j;
2731
2732         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2733
2734         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2735                 return -EINVAL;  /* filter index is out of range. */
2736
2737         wufc = E1000_READ_REG(hw, E1000_WUFC);
2738         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2739
2740         if ((wufc & wufc_en) == wufc_en) {
2741                 uint32_t reg_off = 0;
2742                 j = 0;
2743                 if (index < E1000_MAX_FHFT)
2744                         reg_off = E1000_FHFT(index);
2745                 else
2746                         reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2747
2748                 for (i = 0; i < 16; i++, j = i * 2) {
2749                         filter->dwords[j] =
2750                                 E1000_READ_REG(hw, reg_off + i*4*4);
2751                         filter->dwords[j+1] =
2752                                 E1000_READ_REG(hw, reg_off + (i*4+1)*4);
2753                         filter->mask[i] =
2754                                 E1000_READ_REG(hw, reg_off + (i*4+2)*4);
2755                 }
2756                 queueing = E1000_READ_REG(hw,
2757                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2758                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2759                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2760                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
2761                 *rx_queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2762                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2763                 return 0;
2764         }
2765         return -ENOENT;
2766 }
2767
2768 /*
2769  * add a 5tuple filter
2770  *
2771  * @param
2772  * dev: Pointer to struct rte_eth_dev.
2773  * index: the index the filter allocates.
2774  * filter: ponter to the filter that will be added.
2775  * rx_queue: the queue id the filter assigned to.
2776  *
2777  * @return
2778  *    - On success, zero.
2779  *    - On failure, a negative value.
2780  */
2781 static int
2782 eth_igb_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2783                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
2784 {
2785         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2786         uint32_t ftqf, spqf = 0;
2787         uint32_t imir = 0;
2788         uint32_t imir_ext = 0;
2789
2790         if (hw->mac.type != e1000_82576)
2791                 return -ENOSYS;
2792
2793         if (index >= E1000_MAX_FTQF_FILTERS ||
2794                 rx_queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2795                 return -EINVAL;  /* filter index is out of range. */
2796
2797         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2798         if (ftqf & E1000_FTQF_QUEUE_ENABLE)
2799                 return -EINVAL;  /* filter index is in use. */
2800
2801         ftqf = 0;
2802         ftqf |= filter->protocol & E1000_FTQF_PROTOCOL_MASK;
2803         if (filter->src_ip_mask == 1) /* 1b means not compare. */
2804                 ftqf |= E1000_FTQF_SOURCE_ADDR_MASK;
2805         if (filter->dst_ip_mask == 1)
2806                 ftqf |= E1000_FTQF_DEST_ADDR_MASK;
2807         if (filter->src_port_mask == 1)
2808                 ftqf |= E1000_FTQF_SOURCE_PORT_MASK;
2809         if (filter->protocol_mask == 1)
2810                 ftqf |= E1000_FTQF_PROTOCOL_COMP_MASK;
2811         ftqf |= (rx_queue << E1000_FTQF_QUEUE_SHIFT) & E1000_FTQF_QUEUE_MASK;
2812         ftqf |= E1000_FTQF_VF_MASK_EN;
2813         ftqf |= E1000_FTQF_QUEUE_ENABLE;
2814         E1000_WRITE_REG(hw, E1000_FTQF(index), ftqf);
2815         E1000_WRITE_REG(hw, E1000_DAQF(index), filter->dst_ip);
2816         E1000_WRITE_REG(hw, E1000_SAQF(index), filter->src_ip);
2817
2818         spqf |= filter->src_port & E1000_SPQF_SRCPORT;
2819         E1000_WRITE_REG(hw, E1000_SPQF(index), spqf);
2820
2821         imir |= (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2822         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2823                 imir |= E1000_IMIR_PORT_BP;
2824         else
2825                 imir &= ~E1000_IMIR_PORT_BP;
2826         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2827
2828         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2829         /* tcp flags bits setting. */
2830         if (filter->tcp_flags & TCP_FLAG_ALL) {
2831                 if (filter->tcp_flags & TCP_UGR_FLAG)
2832                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2833                 if (filter->tcp_flags & TCP_ACK_FLAG)
2834                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2835                 if (filter->tcp_flags & TCP_PSH_FLAG)
2836                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2837                 if (filter->tcp_flags & TCP_RST_FLAG)
2838                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2839                 if (filter->tcp_flags & TCP_SYN_FLAG)
2840                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2841                 if (filter->tcp_flags & TCP_FIN_FLAG)
2842                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2843         } else
2844                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2845         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2846         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2847         return 0;
2848 }
2849
2850 /*
2851  * remove a 5tuple filter
2852  *
2853  * @param
2854  * dev: Pointer to struct rte_eth_dev.
2855  * index: the index the filter allocates
2856  *
2857  * @return
2858  *    - On success, zero.
2859  *    - On failure, a negative value.
2860  */
2861 static int
2862 eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
2863                                 uint16_t index)
2864 {
2865         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2866
2867         if (hw->mac.type != e1000_82576)
2868                 return -ENOSYS;
2869
2870         if (index >= E1000_MAX_FTQF_FILTERS)
2871                 return -EINVAL;  /* filter index is out of range. */
2872
2873         E1000_WRITE_REG(hw, E1000_FTQF(index), 0);
2874         E1000_WRITE_REG(hw, E1000_DAQF(index), 0);
2875         E1000_WRITE_REG(hw, E1000_SAQF(index), 0);
2876         E1000_WRITE_REG(hw, E1000_SPQF(index), 0);
2877         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2878         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2879         return 0;
2880 }
2881
2882 /*
2883  * get a 5tuple filter
2884  *
2885  * @param
2886  * dev: Pointer to struct rte_eth_dev.
2887  * index: the index the filter allocates
2888  * filter: ponter to the filter that returns
2889  * *rx_queue: pointer of the queue id the filter assigned to
2890  *
2891  * @return
2892  *    - On success, zero.
2893  *    - On failure, a negative value.
2894  */
2895 static int
2896 eth_igb_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2897                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
2898 {
2899         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2900         uint32_t spqf, ftqf, imir, imir_ext;
2901
2902         if (hw->mac.type != e1000_82576)
2903                 return -ENOSYS;
2904
2905         if (index >= E1000_MAX_FTQF_FILTERS)
2906                 return -EINVAL;  /* filter index is out of range. */
2907
2908         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2909         if (ftqf & E1000_FTQF_QUEUE_ENABLE) {
2910                 filter->src_ip_mask =
2911                         (ftqf & E1000_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
2912                 filter->dst_ip_mask =
2913                         (ftqf & E1000_FTQF_DEST_ADDR_MASK) ? 1 : 0;
2914                 filter->src_port_mask =
2915                         (ftqf & E1000_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
2916                 filter->protocol_mask =
2917                         (ftqf & E1000_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
2918                 filter->protocol =
2919                         (uint8_t)ftqf & E1000_FTQF_PROTOCOL_MASK;
2920                 *rx_queue = (uint16_t)((ftqf & E1000_FTQF_QUEUE_MASK) >>
2921                                 E1000_FTQF_QUEUE_SHIFT);
2922
2923                 spqf = E1000_READ_REG(hw, E1000_SPQF(index));
2924                 filter->src_port = spqf & E1000_SPQF_SRCPORT;
2925
2926                 filter->dst_ip = E1000_READ_REG(hw, E1000_DAQF(index));
2927                 filter->src_ip = E1000_READ_REG(hw, E1000_SAQF(index));
2928
2929                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2930                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2931                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2932                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2933                         E1000_IMIR_PRIORITY_SHIFT;
2934
2935                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2936                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2937                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2938                                 filter->tcp_flags |= TCP_UGR_FLAG;
2939                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2940                                 filter->tcp_flags |= TCP_ACK_FLAG;
2941                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2942                                 filter->tcp_flags |= TCP_PSH_FLAG;
2943                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2944                                 filter->tcp_flags |= TCP_RST_FLAG;
2945                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2946                                 filter->tcp_flags |= TCP_SYN_FLAG;
2947                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2948                                 filter->tcp_flags |= TCP_FIN_FLAG;
2949                 } else
2950                         filter->tcp_flags = 0;
2951                 return 0;
2952         }
2953         return -ENOENT;
2954 }
2955
2956 static struct rte_driver pmd_igb_drv = {
2957         .type = PMD_PDEV,
2958         .init = rte_igb_pmd_init,
2959 };
2960
2961 static struct rte_driver pmd_igbvf_drv = {
2962         .type = PMD_PDEV,
2963         .init = rte_igbvf_pmd_init,
2964 };
2965
2966 PMD_REGISTER_DRIVER(pmd_igb_drv);
2967 PMD_REGISTER_DRIVER(pmd_igbvf_drv);