lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 static int  eth_igb_configure(struct rte_eth_dev *dev);
  73 static int  eth_igb_start(struct rte_eth_dev *dev);
  74 static void eth_igb_stop(struct rte_eth_dev *dev);
  75 static void eth_igb_close(struct rte_eth_dev *dev);
  76 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  77 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  78 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  79 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  80 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  81                                 int wait_to_complete);
  82 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  83                                 struct rte_eth_stats *rte_stats);
  84 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  85 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  86                               struct rte_eth_dev_info *dev_info);
  87 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
  88                                 struct rte_eth_dev_info *dev_info);
  89 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
  90                                 struct rte_eth_fc_conf *fc_conf);
  91 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  92                                 struct rte_eth_fc_conf *fc_conf);
  93 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  94 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  95 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  96 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  97                                                         void *param);
  98 static int  igb_hardware_init(struct e1000_hw *hw);
  99 static void igb_hw_control_acquire(struct e1000_hw *hw);
 100 static void igb_hw_control_release(struct e1000_hw *hw);
 101 static void igb_init_manageability(struct e1000_hw *hw);
 102 static void igb_release_manageability(struct e1000_hw *hw);
 103
 104 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 105
 106 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 107                 uint16_t vlan_id, int on);
 108 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 109 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 110
 111 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 112 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 113 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 114 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 115 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 116 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 117
 118 static int eth_igb_led_on(struct rte_eth_dev *dev);
 119 static int eth_igb_led_off(struct rte_eth_dev *dev);
 120
 121 static void igb_intr_disable(struct e1000_hw *hw);
 122 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 123 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 124                 struct ether_addr *mac_addr,
 125                 uint32_t index, uint32_t pool);
 126 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 127
 128 static void igbvf_intr_disable(struct e1000_hw *hw);
 129 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 130 static int igbvf_dev_start(struct rte_eth_dev *dev);
 131 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 132 static void igbvf_dev_close(struct rte_eth_dev *dev);
 133 static int eth_igbvf_link_update(struct e1000_hw *hw);
 134 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 135 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 136 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 137                 uint16_t vlan_id, int on);
 138 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 139 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 140 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 141                  struct rte_eth_rss_reta *reta_conf);
 142 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 143                 struct rte_eth_rss_reta *reta_conf);
 144
 145 static int eth_igb_add_syn_filter(struct rte_eth_dev *dev,
 146                         struct rte_syn_filter *filter, uint16_t rx_queue);
 147 static int eth_igb_remove_syn_filter(struct rte_eth_dev *dev);
 148 static int eth_igb_get_syn_filter(struct rte_eth_dev *dev,
 149                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 150 static int eth_igb_add_ethertype_filter(struct rte_eth_dev *dev,
 151                         uint16_t index,
 152                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 153 static int eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev,
 154                         uint16_t index);
 155 static int eth_igb_get_ethertype_filter(struct rte_eth_dev *dev,
 156                         uint16_t index,
 157                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 158 static int eth_igb_add_2tuple_filter(struct rte_eth_dev *dev,
 159                         uint16_t index,
 160                         struct rte_2tuple_filter *filter, uint16_t rx_queue);
 161 static int eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 162                         uint16_t index);
 163 static int eth_igb_get_2tuple_filter(struct rte_eth_dev *dev,
 164                         uint16_t index,
 165                         struct rte_2tuple_filter *filter, uint16_t *rx_queue);
 166 static int eth_igb_add_flex_filter(struct rte_eth_dev *dev,
 167                         uint16_t index,
 168                         struct rte_flex_filter *filter, uint16_t rx_queue);
 169 static int eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
 170                         uint16_t index);
 171 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 172                         uint16_t index,
 173                         struct rte_flex_filter *filter, uint16_t *rx_queue);
 174 static int eth_igb_add_5tuple_filter(struct rte_eth_dev *dev,
 175                         uint16_t index,
 176                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 177 static int eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
 178                         uint16_t index);
 179 static int eth_igb_get_5tuple_filter(struct rte_eth_dev *dev,
 180                         uint16_t index,
 181                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 182
 183 /*
 184  * Define VF Stats MACRO for Non "cleared on read" register
 185  */
 186 #define UPDATE_VF_STAT(reg, last, cur)            \
 187 {                                                 \
 188         u32 latest = E1000_READ_REG(hw, reg);     \
 189         cur += latest - last;                     \
 190         last = latest;                            \
 191 }
 192
 193
 194 #define IGB_FC_PAUSE_TIME 0x0680
 195 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 196 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 197
 198 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 199
 200 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 201
 202 /*
 203  * The set of PCI devices this driver supports
 204  */
 205 static struct rte_pci_id pci_id_igb_map[] = {
 206
 207 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 208 #include "rte_pci_dev_ids.h"
 209
 210 {.device_id = 0},
 211 };
 212
 213 /*
 214  * The set of PCI devices this driver supports (for 82576&I350 VF)
 215  */
 216 static struct rte_pci_id pci_id_igbvf_map[] = {
 217
 218 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 219 #include "rte_pci_dev_ids.h"
 220
 221 {.device_id = 0},
 222 };
 223
 224 static struct eth_dev_ops eth_igb_ops = {
 225         .dev_configure        = eth_igb_configure,
 226         .dev_start            = eth_igb_start,
 227         .dev_stop             = eth_igb_stop,
 228         .dev_close            = eth_igb_close,
 229         .promiscuous_enable   = eth_igb_promiscuous_enable,
 230         .promiscuous_disable  = eth_igb_promiscuous_disable,
 231         .allmulticast_enable  = eth_igb_allmulticast_enable,
 232         .allmulticast_disable = eth_igb_allmulticast_disable,
 233         .link_update          = eth_igb_link_update,
 234         .stats_get            = eth_igb_stats_get,
 235         .stats_reset          = eth_igb_stats_reset,
 236         .dev_infos_get        = eth_igb_infos_get,
 237         .mtu_set              = eth_igb_mtu_set,
 238         .vlan_filter_set      = eth_igb_vlan_filter_set,
 239         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 240         .vlan_offload_set     = eth_igb_vlan_offload_set,
 241         .rx_queue_setup       = eth_igb_rx_queue_setup,
 242         .rx_queue_release     = eth_igb_rx_queue_release,
 243         .rx_queue_count       = eth_igb_rx_queue_count,
 244         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 245         .tx_queue_setup       = eth_igb_tx_queue_setup,
 246         .tx_queue_release     = eth_igb_tx_queue_release,
 247         .dev_led_on           = eth_igb_led_on,
 248         .dev_led_off          = eth_igb_led_off,
 249         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 250         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 251         .mac_addr_add         = eth_igb_rar_set,
 252         .mac_addr_remove      = eth_igb_rar_clear,
 253         .reta_update          = eth_igb_rss_reta_update,
 254         .reta_query           = eth_igb_rss_reta_query,
 255         .rss_hash_update      = eth_igb_rss_hash_update,
 256         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 257         .add_syn_filter          = eth_igb_add_syn_filter,
 258         .remove_syn_filter       = eth_igb_remove_syn_filter,
 259         .get_syn_filter          = eth_igb_get_syn_filter,
 260         .add_ethertype_filter    = eth_igb_add_ethertype_filter,
 261         .remove_ethertype_filter = eth_igb_remove_ethertype_filter,
 262         .get_ethertype_filter    = eth_igb_get_ethertype_filter,
 263         .add_2tuple_filter       = eth_igb_add_2tuple_filter,
 264         .remove_2tuple_filter    = eth_igb_remove_2tuple_filter,
 265         .get_2tuple_filter       = eth_igb_get_2tuple_filter,
 266         .add_flex_filter         = eth_igb_add_flex_filter,
 267         .remove_flex_filter      = eth_igb_remove_flex_filter,
 268         .get_flex_filter         = eth_igb_get_flex_filter,
 269         .add_5tuple_filter       = eth_igb_add_5tuple_filter,
 270         .remove_5tuple_filter    = eth_igb_remove_5tuple_filter,
 271         .get_5tuple_filter       = eth_igb_get_5tuple_filter,
 272 };
 273
 274 /*
 275  * dev_ops for virtual function, bare necessities for basic vf
 276  * operation have been implemented
 277  */
 278 static struct eth_dev_ops igbvf_eth_dev_ops = {
 279         .dev_configure        = igbvf_dev_configure,
 280         .dev_start            = igbvf_dev_start,
 281         .dev_stop             = igbvf_dev_stop,
 282         .dev_close            = igbvf_dev_close,
 283         .link_update          = eth_igb_link_update,
 284         .stats_get            = eth_igbvf_stats_get,
 285         .stats_reset          = eth_igbvf_stats_reset,
 286         .vlan_filter_set      = igbvf_vlan_filter_set,
 287         .dev_infos_get        = eth_igbvf_infos_get,
 288         .rx_queue_setup       = eth_igb_rx_queue_setup,
 289         .rx_queue_release     = eth_igb_rx_queue_release,
 290         .tx_queue_setup       = eth_igb_tx_queue_setup,
 291         .tx_queue_release     = eth_igb_tx_queue_release,
 292 };
 293
 294 /**
 295  * Atomically reads the link status information from global
 296  * structure rte_eth_dev.
 297  *
 298  * @param dev
 299  *   - Pointer to the structure rte_eth_dev to read from.
 300  *   - Pointer to the buffer to be saved with the link status.
 301  *
 302  * @return
 303  *   - On success, zero.
 304  *   - On failure, negative value.
 305  */
 306 static inline int
 307 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 308                                 struct rte_eth_link *link)
 309 {
 310         struct rte_eth_link *dst = link;
 311         struct rte_eth_link *src = &(dev->data->dev_link);
 312
 313         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 314                                         *(uint64_t *)src) == 0)
 315                 return -1;
 316
 317         return 0;
 318 }
 319
 320 /**
 321  * Atomically writes the link status information into global
 322  * structure rte_eth_dev.
 323  *
 324  * @param dev
 325  *   - Pointer to the structure rte_eth_dev to read from.
 326  *   - Pointer to the buffer to be saved with the link status.
 327  *
 328  * @return
 329  *   - On success, zero.
 330  *   - On failure, negative value.
 331  */
 332 static inline int
 333 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 334                                 struct rte_eth_link *link)
 335 {
 336         struct rte_eth_link *dst = &(dev->data->dev_link);
 337         struct rte_eth_link *src = link;
 338
 339         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 340                                         *(uint64_t *)src) == 0)
 341                 return -1;
 342
 343         return 0;
 344 }
 345
 346 static inline void
 347 igb_intr_enable(struct rte_eth_dev *dev)
 348 {
 349         struct e1000_interrupt *intr =
 350                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 351         struct e1000_hw *hw =
 352                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 353
 354         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 355         E1000_WRITE_FLUSH(hw);
 356 }
 357
 358 static void
 359 igb_intr_disable(struct e1000_hw *hw)
 360 {
 361         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 362         E1000_WRITE_FLUSH(hw);
 363 }
 364
 365 static inline int32_t
 366 igb_pf_reset_hw(struct e1000_hw *hw)
 367 {
 368         uint32_t ctrl_ext;
 369         int32_t status;
 370
 371         status = e1000_reset_hw(hw);
 372
 373         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 374         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 375         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 376         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 377         E1000_WRITE_FLUSH(hw);
 378
 379         return status;
 380 }
 381
 382 static void
 383 igb_identify_hardware(struct rte_eth_dev *dev)
 384 {
 385         struct e1000_hw *hw =
 386                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 387
 388         hw->vendor_id = dev->pci_dev->id.vendor_id;
 389         hw->device_id = dev->pci_dev->id.device_id;
 390         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 391         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 392
 393         e1000_set_mac_type(hw);
 394
 395         /* need to check if it is a vf device below */
 396 }
 397
 398 static int
 399 igb_reset_swfw_lock(struct e1000_hw *hw)
 400 {
 401         int ret_val;
 402
 403         /*
 404          * Do mac ops initialization manually here, since we will need
 405          * some function pointers set by this call.
 406          */
 407         ret_val = e1000_init_mac_params(hw);
 408         if (ret_val)
 409                 return ret_val;
 410
 411         /*
 412          * SMBI lock should not fail in this early stage. If this is the case,
 413          * it is due to an improper exit of the application.
 414          * So force the release of the faulty lock.
 415          */
 416         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 417                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 418         }
 419         e1000_put_hw_semaphore_generic(hw);
 420
 421         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 422                 uint16_t mask;
 423
 424                 /*
 425                  * Phy lock should not fail in this early stage. If this is the case,
 426                  * it is due to an improper exit of the application.
 427                  * So force the release of the faulty lock.
 428                  */
 429                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 430                 if (hw->bus.func > E1000_FUNC_1)
 431                         mask <<= 2;
 432                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 433                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 434                                     hw->bus.func);
 435                 }
 436                 hw->mac.ops.release_swfw_sync(hw, mask);
 437
 438                 /*
 439                  * This one is more tricky since it is common to all ports; but
 440                  * swfw_sync retries last long enough (1s) to be almost sure that if
 441                  * lock can not be taken it is due to an improper lock of the
 442                  * semaphore.
 443                  */
 444                 mask = E1000_SWFW_EEP_SM;
 445                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 446                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 447                 }
 448                 hw->mac.ops.release_swfw_sync(hw, mask);
 449         }
 450
 451         return E1000_SUCCESS;
 452 }
 453
 454 static int
 455 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 456                    struct rte_eth_dev *eth_dev)
 457 {
 458         int error = 0;
 459         struct rte_pci_device *pci_dev;
 460         struct e1000_hw *hw =
 461                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 462         struct e1000_vfta * shadow_vfta =
 463                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 464         uint32_t ctrl_ext;
 465
 466         pci_dev = eth_dev->pci_dev;
 467         eth_dev->dev_ops = &eth_igb_ops;
 468         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 469         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 470
 471         /* for secondary processes, we don't initialise any further as primary
 472          * has already done this work. Only check we don't need a different
 473          * RX function */
 474         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 475                 if (eth_dev->data->scattered_rx)
 476                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 477                 return 0;
 478         }
 479
 480         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 481
 482         igb_identify_hardware(eth_dev);
 483         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 484                 error = -EIO;
 485                 goto err_late;
 486         }
 487
 488         e1000_get_bus_info(hw);
 489
 490         /* Reset any pending lock */
 491         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 492                 error = -EIO;
 493                 goto err_late;
 494         }
 495
 496         /* Finish initialization */
 497         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 498                 error = -EIO;
 499                 goto err_late;
 500         }
 501
 502         hw->mac.autoneg = 1;
 503         hw->phy.autoneg_wait_to_complete = 0;
 504         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 505
 506         /* Copper options */
 507         if (hw->phy.media_type == e1000_media_type_copper) {
 508                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 509                 hw->phy.disable_polarity_correction = 0;
 510                 hw->phy.ms_type = e1000_ms_hw_default;
 511         }
 512
 513         /*
 514          * Start from a known state, this is important in reading the nvm
 515          * and mac from that.
 516          */
 517         igb_pf_reset_hw(hw);
 518
 519         /* Make sure we have a good EEPROM before we read from it */
 520         if (e1000_validate_nvm_checksum(hw) < 0) {
 521                 /*
 522                  * Some PCI-E parts fail the first check due to
 523                  * the link being in sleep state, call it again,
 524                  * if it fails a second time its a real issue.
 525                  */
 526                 if (e1000_validate_nvm_checksum(hw) < 0) {
 527                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 528                         error = -EIO;
 529                         goto err_late;
 530                 }
 531         }
 532
 533         /* Read the permanent MAC address out of the EEPROM */
 534         if (e1000_read_mac_addr(hw) != 0) {
 535                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 536                 error = -EIO;
 537                 goto err_late;
 538         }
 539
 540         /* Allocate memory for storing MAC addresses */
 541         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 542                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 543         if (eth_dev->data->mac_addrs == NULL) {
 544                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 545                                                 "store MAC addresses",
 546                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 547                 error = -ENOMEM;
 548                 goto err_late;
 549         }
 550
 551         /* Copy the permanent MAC address */
 552         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 553
 554         /* initialize the vfta */
 555         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 556
 557         /* Now initialize the hardware */
 558         if (igb_hardware_init(hw) != 0) {
 559                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 560                 rte_free(eth_dev->data->mac_addrs);
 561                 eth_dev->data->mac_addrs = NULL;
 562                 error = -ENODEV;
 563                 goto err_late;
 564         }
 565         hw->mac.get_link_status = 1;
 566
 567         /* Indicate SOL/IDER usage */
 568         if (e1000_check_reset_block(hw) < 0) {
 569                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 570                                         "SOL/IDER session");
 571         }
 572
 573         /* initialize PF if max_vfs not zero */
 574         igb_pf_host_init(eth_dev);
 575
 576         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 577         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 578         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 579         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 580         E1000_WRITE_FLUSH(hw);
 581
 582         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
 583                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 584                      pci_dev->id.device_id);
 585
 586         rte_intr_callback_register(&(pci_dev->intr_handle),
 587                 eth_igb_interrupt_handler, (void *)eth_dev);
 588
 589         /* enable uio intr after callback register */
 590         rte_intr_enable(&(pci_dev->intr_handle));
 591
 592         /* enable support intr */
 593         igb_intr_enable(eth_dev);
 594
 595         return 0;
 596
 597 err_late:
 598         igb_hw_control_release(hw);
 599
 600         return (error);
 601 }
 602
 603 /*
 604  * Virtual Function device init
 605  */
 606 static int
 607 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 608                 struct rte_eth_dev *eth_dev)
 609 {
 610         struct rte_pci_device *pci_dev;
 611         struct e1000_hw *hw =
 612                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 613         int diag;
 614
 615         PMD_INIT_FUNC_TRACE();
 616
 617         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 618         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 619         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 620
 621         /* for secondary processes, we don't initialise any further as primary
 622          * has already done this work. Only check we don't need a different
 623          * RX function */
 624         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 625                 if (eth_dev->data->scattered_rx)
 626                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 627                 return 0;
 628         }
 629
 630         pci_dev = eth_dev->pci_dev;
 631
 632         hw->device_id = pci_dev->id.device_id;
 633         hw->vendor_id = pci_dev->id.vendor_id;
 634         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 635
 636         /* Initialize the shared code (base driver) */
 637         diag = e1000_setup_init_funcs(hw, TRUE);
 638         if (diag != 0) {
 639                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 640                         diag);
 641                 return -EIO;
 642         }
 643
 644         /* init_mailbox_params */
 645         hw->mbx.ops.init_params(hw);
 646
 647         /* Disable the interrupts for VF */
 648         igbvf_intr_disable(hw);
 649
 650         diag = hw->mac.ops.reset_hw(hw);
 651
 652         /* Allocate memory for storing MAC addresses */
 653         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 654                 hw->mac.rar_entry_count, 0);
 655         if (eth_dev->data->mac_addrs == NULL) {
 656                 PMD_INIT_LOG(ERR,
 657                         "Failed to allocate %d bytes needed to store MAC "
 658                         "addresses",
 659                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 660                 return -ENOMEM;
 661         }
 662
 663         /* Copy the permanent MAC address */
 664         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 665                         &eth_dev->data->mac_addrs[0]);
 666
 667         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 668                      "mac.type=%s",
 669                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 670                      pci_dev->id.device_id, "igb_mac_82576_vf");
 671
 672         return 0;
 673 }
 674
 675 static struct eth_driver rte_igb_pmd = {
 676         {
 677                 .name = "rte_igb_pmd",
 678                 .id_table = pci_id_igb_map,
 679                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 680         },
 681         .eth_dev_init = eth_igb_dev_init,
 682         .dev_private_size = sizeof(struct e1000_adapter),
 683 };
 684
 685 /*
 686  * virtual function driver struct
 687  */
 688 static struct eth_driver rte_igbvf_pmd = {
 689         {
 690                 .name = "rte_igbvf_pmd",
 691                 .id_table = pci_id_igbvf_map,
 692                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 693         },
 694         .eth_dev_init = eth_igbvf_dev_init,
 695         .dev_private_size = sizeof(struct e1000_adapter),
 696 };
 697
 698 static int
 699 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 700 {
 701         rte_eth_driver_register(&rte_igb_pmd);
 702         return 0;
 703 }
 704
 705 static void
 706 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 707 {
 708         struct e1000_hw *hw =
 709                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 710         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 711         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 712         rctl |= E1000_RCTL_VFE;
 713         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 714 }
 715
 716 /*
 717  * VF Driver initialization routine.
 718  * Invoked one at EAL init time.
 719  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 720  */
 721 static int
 722 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 723 {
 724         PMD_INIT_FUNC_TRACE();
 725
 726         rte_eth_driver_register(&rte_igbvf_pmd);
 727         return (0);
 728 }
 729
 730 static int
 731 eth_igb_configure(struct rte_eth_dev *dev)
 732 {
 733         struct e1000_interrupt *intr =
 734                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 735
 736         PMD_INIT_FUNC_TRACE();
 737         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 738         PMD_INIT_FUNC_TRACE();
 739
 740         return (0);
 741 }
 742
 743 static int
 744 eth_igb_start(struct rte_eth_dev *dev)
 745 {
 746         struct e1000_hw *hw =
 747                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 748         int ret, i, mask;
 749         uint32_t ctrl_ext;
 750
 751         PMD_INIT_FUNC_TRACE();
 752
 753         /* Power up the phy. Needed to make the link go Up */
 754         e1000_power_up_phy(hw);
 755
 756         /*
 757          * Packet Buffer Allocation (PBA)
 758          * Writing PBA sets the receive portion of the buffer
 759          * the remainder is used for the transmit buffer.
 760          */
 761         if (hw->mac.type == e1000_82575) {
 762                 uint32_t pba;
 763
 764                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 765                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 766         }
 767
 768         /* Put the address into the Receive Address Array */
 769         e1000_rar_set(hw, hw->mac.addr, 0);
 770
 771         /* Initialize the hardware */
 772         if (igb_hardware_init(hw)) {
 773                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 774                 return (-EIO);
 775         }
 776
 777         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 778
 779         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 780         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 781         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 782         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 783         E1000_WRITE_FLUSH(hw);
 784
 785         /* configure PF module if SRIOV enabled */
 786         igb_pf_host_configure(dev);
 787
 788         /* Configure for OS presence */
 789         igb_init_manageability(hw);
 790
 791         eth_igb_tx_init(dev);
 792
 793         /* This can fail when allocating mbufs for descriptor rings */
 794         ret = eth_igb_rx_init(dev);
 795         if (ret) {
 796                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 797                 igb_dev_clear_queues(dev);
 798                 return ret;
 799         }
 800
 801         e1000_clear_hw_cntrs_base_generic(hw);
 802
 803         /*
 804          * VLAN Offload Settings
 805          */
 806         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 807                         ETH_VLAN_EXTEND_MASK;
 808         eth_igb_vlan_offload_set(dev, mask);
 809
 810         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 811                 /* Enable VLAN filter since VMDq always use VLAN filter */
 812                 igb_vmdq_vlan_hw_filter_enable(dev);
 813         }
 814
 815         /*
 816          * Configure the Interrupt Moderation register (EITR) with the maximum
 817          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 818          * spurious [DMA] memory updates of RX and TX ring descriptors.
 819          *
 820          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 821          * spurious memory updates per second should be expected.
 822          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 823          *
 824          * Because interrupts are not used at all, the MSI-X is not activated
 825          * and interrupt moderation is controlled by EITR[0].
 826          *
 827          * Note that having [almost] disabled memory updates of RX and TX ring
 828          * descriptors through the Interrupt Moderation mechanism, memory
 829          * updates of ring descriptors are now moderated by the configurable
 830          * value of Write-Back Threshold registers.
 831          */
 832         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 833                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
 834                 (hw->mac.type == e1000_i211)) {
 835                 uint32_t ivar;
 836
 837                 /* Enable all RX & TX queues in the IVAR registers */
 838                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 839                 for (i = 0; i < 8; i++)
 840                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 841
 842                 /* Configure EITR with the maximum possible value (0xFFFF) */
 843                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 844         }
 845
 846         /* Setup link speed and duplex */
 847         switch (dev->data->dev_conf.link_speed) {
 848         case ETH_LINK_SPEED_AUTONEG:
 849                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 850                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 851                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 852                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 853                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 854                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 855                 else
 856                         goto error_invalid_config;
 857                 break;
 858         case ETH_LINK_SPEED_10:
 859                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 860                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 861                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 862                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 863                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 864                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 865                 else
 866                         goto error_invalid_config;
 867                 break;
 868         case ETH_LINK_SPEED_100:
 869                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 870                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 871                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 872                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 873                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 874                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 875                 else
 876                         goto error_invalid_config;
 877                 break;
 878         case ETH_LINK_SPEED_1000:
 879                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 880                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 881                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 882                 else
 883                         goto error_invalid_config;
 884                 break;
 885         case ETH_LINK_SPEED_10000:
 886         default:
 887                 goto error_invalid_config;
 888         }
 889         e1000_setup_link(hw);
 890
 891         /* check if lsc interrupt feature is enabled */
 892         if (dev->data->dev_conf.intr_conf.lsc != 0)
 893                 ret = eth_igb_lsc_interrupt_setup(dev);
 894
 895         /* resume enabled intr since hw reset */
 896         igb_intr_enable(dev);
 897
 898         PMD_INIT_LOG(DEBUG, "<<");
 899
 900         return (0);
 901
 902 error_invalid_config:
 903         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 904                      dev->data->dev_conf.link_speed,
 905                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 906         igb_dev_clear_queues(dev);
 907         return (-EINVAL);
 908 }
 909
 910 /*********************************************************************
 911  *
 912  *  This routine disables all traffic on the adapter by issuing a
 913  *  global reset on the MAC.
 914  *
 915  **********************************************************************/
 916 static void
 917 eth_igb_stop(struct rte_eth_dev *dev)
 918 {
 919         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 920         struct rte_eth_link link;
 921
 922         igb_intr_disable(hw);
 923         igb_pf_reset_hw(hw);
 924         E1000_WRITE_REG(hw, E1000_WUC, 0);
 925
 926         /* Set bit for Go Link disconnect */
 927         if (hw->mac.type >= e1000_82580) {
 928                 uint32_t phpm_reg;
 929
 930                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 931                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 932                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 933         }
 934
 935         /* Power down the phy. Needed to make the link go Down */
 936         e1000_power_down_phy(hw);
 937
 938         igb_dev_clear_queues(dev);
 939
 940         /* clear the recorded link status */
 941         memset(&link, 0, sizeof(link));
 942         rte_igb_dev_atomic_write_link_status(dev, &link);
 943 }
 944
 945 static void
 946 eth_igb_close(struct rte_eth_dev *dev)
 947 {
 948         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 949         struct rte_eth_link link;
 950
 951         eth_igb_stop(dev);
 952         e1000_phy_hw_reset(hw);
 953         igb_release_manageability(hw);
 954         igb_hw_control_release(hw);
 955
 956         /* Clear bit for Go Link disconnect */
 957         if (hw->mac.type >= e1000_82580) {
 958                 uint32_t phpm_reg;
 959
 960                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 961                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
 962                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 963         }
 964
 965         igb_dev_clear_queues(dev);
 966
 967         memset(&link, 0, sizeof(link));
 968         rte_igb_dev_atomic_write_link_status(dev, &link);
 969 }
 970
 971 static int
 972 igb_get_rx_buffer_size(struct e1000_hw *hw)
 973 {
 974         uint32_t rx_buf_size;
 975         if (hw->mac.type == e1000_82576) {
 976                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 977         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 978                 /* PBS needs to be translated according to a lookup table */
 979                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 980                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 981                 rx_buf_size = (rx_buf_size << 10);
 982         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
 983                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 984         } else {
 985                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 986         }
 987
 988         return rx_buf_size;
 989 }
 990
 991 /*********************************************************************
 992  *
 993  *  Initialize the hardware
 994  *
 995  **********************************************************************/
 996 static int
 997 igb_hardware_init(struct e1000_hw *hw)
 998 {
 999         uint32_t rx_buf_size;
1000         int diag;
1001
1002         /* Let the firmware know the OS is in control */
1003         igb_hw_control_acquire(hw);
1004
1005         /*
1006          * These parameters control the automatic generation (Tx) and
1007          * response (Rx) to Ethernet PAUSE frames.
1008          * - High water mark should allow for at least two standard size (1518)
1009          *   frames to be received after sending an XOFF.
1010          * - Low water mark works best when it is very near the high water mark.
1011          *   This allows the receiver to restart by sending XON when it has
1012          *   drained a bit. Here we use an arbitrary value of 1500 which will
1013          *   restart after one full frame is pulled from the buffer. There
1014          *   could be several smaller frames in the buffer and if so they will
1015          *   not trigger the XON until their total number reduces the buffer
1016          *   by 1500.
1017          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1018          */
1019         rx_buf_size = igb_get_rx_buffer_size(hw);
1020
1021         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1022         hw->fc.low_water = hw->fc.high_water - 1500;
1023         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1024         hw->fc.send_xon = 1;
1025
1026         /* Set Flow control, use the tunable location if sane */
1027         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1028                 hw->fc.requested_mode = igb_fc_setting;
1029         else
1030                 hw->fc.requested_mode = e1000_fc_none;
1031
1032         /* Issue a global reset */
1033         igb_pf_reset_hw(hw);
1034         E1000_WRITE_REG(hw, E1000_WUC, 0);
1035
1036         diag = e1000_init_hw(hw);
1037         if (diag < 0)
1038                 return (diag);
1039
1040         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1041         e1000_get_phy_info(hw);
1042         e1000_check_for_link(hw);
1043
1044         return (0);
1045 }
1046
1047 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1048 static void
1049 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1050 {
1051         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1052         struct e1000_hw_stats *stats =
1053                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1054         int pause_frames;
1055
1056         if(hw->phy.media_type == e1000_media_type_copper ||
1057             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1058                 stats->symerrs +=
1059                     E1000_READ_REG(hw,E1000_SYMERRS);
1060                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1061         }
1062
1063         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1064         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1065         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1066         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1067
1068         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1069         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1070         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1071         stats->dc += E1000_READ_REG(hw, E1000_DC);
1072         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1073         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1074         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1075         /*
1076         ** For watchdog management we need to know if we have been
1077         ** paused during the last interval, so capture that here.
1078         */
1079         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1080         stats->xoffrxc += pause_frames;
1081         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1082         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1083         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1084         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1085         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1086         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1087         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1088         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1089         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1090         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1091         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1092         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1093
1094         /* For the 64-bit byte counters the low dword must be read first. */
1095         /* Both registers clear on the read of the high dword */
1096
1097         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1098         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1099         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1100         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1101
1102         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1103         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1104         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1105         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1106         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1107
1108         stats->tor += E1000_READ_REG(hw, E1000_TORH);
1109         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1110
1111         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1112         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1113         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1114         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1115         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1116         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1117         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1118         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1119         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1120         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1121
1122         /* Interrupt Counts */
1123
1124         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1125         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1126         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1127         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1128         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1129         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1130         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1131         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1132         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1133
1134         /* Host to Card Statistics */
1135
1136         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1137         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1138         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1139         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1140         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1141         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1142         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1143         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1144         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1145         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1146         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1147         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1148         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1149         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1150
1151         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1152         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1153         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1154         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1155         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1156         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1157
1158         if (rte_stats == NULL)
1159                 return;
1160
1161         /* Rx Errors */
1162         rte_stats->ibadcrc = stats->crcerrs;
1163         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1164         rte_stats->imissed = stats->mpc;
1165         rte_stats->ierrors = rte_stats->ibadcrc +
1166                              rte_stats->ibadlen +
1167                              rte_stats->imissed +
1168                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1169
1170         /* Tx Errors */
1171         rte_stats->oerrors = stats->ecol + stats->latecol;
1172
1173         /* XON/XOFF pause frames */
1174         rte_stats->tx_pause_xon  = stats->xontxc;
1175         rte_stats->rx_pause_xon  = stats->xonrxc;
1176         rte_stats->tx_pause_xoff = stats->xofftxc;
1177         rte_stats->rx_pause_xoff = stats->xoffrxc;
1178
1179         rte_stats->ipackets = stats->gprc;
1180         rte_stats->opackets = stats->gptc;
1181         rte_stats->ibytes   = stats->gorc;
1182         rte_stats->obytes   = stats->gotc;
1183 }
1184
1185 static void
1186 eth_igb_stats_reset(struct rte_eth_dev *dev)
1187 {
1188         struct e1000_hw_stats *hw_stats =
1189                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1190
1191         /* HW registers are cleared on read */
1192         eth_igb_stats_get(dev, NULL);
1193
1194         /* Reset software totals */
1195         memset(hw_stats, 0, sizeof(*hw_stats));
1196 }
1197
1198 static void
1199 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1200 {
1201         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1202         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1203                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1204
1205         /* Good Rx packets, include VF loopback */
1206         UPDATE_VF_STAT(E1000_VFGPRC,
1207             hw_stats->last_gprc, hw_stats->gprc);
1208
1209         /* Good Rx octets, include VF loopback */
1210         UPDATE_VF_STAT(E1000_VFGORC,
1211             hw_stats->last_gorc, hw_stats->gorc);
1212
1213         /* Good Tx packets, include VF loopback */
1214         UPDATE_VF_STAT(E1000_VFGPTC,
1215             hw_stats->last_gptc, hw_stats->gptc);
1216
1217         /* Good Tx octets, include VF loopback */
1218         UPDATE_VF_STAT(E1000_VFGOTC,
1219             hw_stats->last_gotc, hw_stats->gotc);
1220
1221         /* Rx Multicst packets */
1222         UPDATE_VF_STAT(E1000_VFMPRC,
1223             hw_stats->last_mprc, hw_stats->mprc);
1224
1225         /* Good Rx loopback packets */
1226         UPDATE_VF_STAT(E1000_VFGPRLBC,
1227             hw_stats->last_gprlbc, hw_stats->gprlbc);
1228
1229         /* Good Rx loopback octets */
1230         UPDATE_VF_STAT(E1000_VFGORLBC,
1231             hw_stats->last_gorlbc, hw_stats->gorlbc);
1232
1233         /* Good Tx loopback packets */
1234         UPDATE_VF_STAT(E1000_VFGPTLBC,
1235             hw_stats->last_gptlbc, hw_stats->gptlbc);
1236
1237         /* Good Tx loopback octets */
1238         UPDATE_VF_STAT(E1000_VFGOTLBC,
1239             hw_stats->last_gotlbc, hw_stats->gotlbc);
1240
1241         if (rte_stats == NULL)
1242                 return;
1243
1244         memset(rte_stats, 0, sizeof(*rte_stats));
1245         rte_stats->ipackets = hw_stats->gprc;
1246         rte_stats->ibytes = hw_stats->gorc;
1247         rte_stats->opackets = hw_stats->gptc;
1248         rte_stats->obytes = hw_stats->gotc;
1249         rte_stats->imcasts = hw_stats->mprc;
1250         rte_stats->ilbpackets = hw_stats->gprlbc;
1251         rte_stats->ilbbytes = hw_stats->gorlbc;
1252         rte_stats->olbpackets = hw_stats->gptlbc;
1253         rte_stats->olbbytes = hw_stats->gotlbc;
1254
1255 }
1256
1257 static void
1258 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1259 {
1260         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1261                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1262
1263         /* Sync HW register to the last stats */
1264         eth_igbvf_stats_get(dev, NULL);
1265
1266         /* reset HW current stats*/
1267         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1268                offsetof(struct e1000_vf_stats, gprc));
1269
1270 }
1271
1272 static void
1273 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1274 {
1275         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1276
1277         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1278         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1279         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1280         dev_info->rx_offload_capa =
1281                 DEV_RX_OFFLOAD_VLAN_STRIP |
1282                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1283                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1284                 DEV_RX_OFFLOAD_TCP_CKSUM;
1285         dev_info->tx_offload_capa =
1286                 DEV_TX_OFFLOAD_VLAN_INSERT |
1287                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1288                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1289                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1290                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1291
1292         switch (hw->mac.type) {
1293         case e1000_82575:
1294                 dev_info->max_rx_queues = 4;
1295                 dev_info->max_tx_queues = 4;
1296                 dev_info->max_vmdq_pools = 0;
1297                 break;
1298
1299         case e1000_82576:
1300                 dev_info->max_rx_queues = 16;
1301                 dev_info->max_tx_queues = 16;
1302                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1303                 dev_info->vmdq_queue_num = 16;
1304                 break;
1305
1306         case e1000_82580:
1307                 dev_info->max_rx_queues = 8;
1308                 dev_info->max_tx_queues = 8;
1309                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1310                 dev_info->vmdq_queue_num = 8;
1311                 break;
1312
1313         case e1000_i350:
1314                 dev_info->max_rx_queues = 8;
1315                 dev_info->max_tx_queues = 8;
1316                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1317                 dev_info->vmdq_queue_num = 8;
1318                 break;
1319
1320         case e1000_i354:
1321                 dev_info->max_rx_queues = 8;
1322                 dev_info->max_tx_queues = 8;
1323                 break;
1324
1325         case e1000_i210:
1326                 dev_info->max_rx_queues = 4;
1327                 dev_info->max_tx_queues = 4;
1328                 dev_info->max_vmdq_pools = 0;
1329                 break;
1330
1331         case e1000_i211:
1332                 dev_info->max_rx_queues = 2;
1333                 dev_info->max_tx_queues = 2;
1334                 dev_info->max_vmdq_pools = 0;
1335                 break;
1336
1337         default:
1338                 /* Should not happen */
1339                 break;
1340         }
1341         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1342
1343         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1344                 .rx_thresh = {
1345                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1346                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1347                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1348                 },
1349                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1350                 .rx_drop_en = 0,
1351         };
1352
1353         dev_info->default_txconf = (struct rte_eth_txconf) {
1354                 .tx_thresh = {
1355                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1356                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1357                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1358                 },
1359                 .txq_flags = 0,
1360         };
1361 }
1362
1363 static void
1364 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1365 {
1366         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1367
1368         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1369         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1370         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1371         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1372                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1373                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1374                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1375         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1376                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1377                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1378                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1379                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1380         switch (hw->mac.type) {
1381         case e1000_vfadapt:
1382                 dev_info->max_rx_queues = 2;
1383                 dev_info->max_tx_queues = 2;
1384                 break;
1385         case e1000_vfadapt_i350:
1386                 dev_info->max_rx_queues = 1;
1387                 dev_info->max_tx_queues = 1;
1388                 break;
1389         default:
1390                 /* Should not happen */
1391                 break;
1392         }
1393
1394         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1395                 .rx_thresh = {
1396                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1397                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1398                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1399                 },
1400                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1401                 .rx_drop_en = 0,
1402         };
1403
1404         dev_info->default_txconf = (struct rte_eth_txconf) {
1405                 .tx_thresh = {
1406                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1407                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1408                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1409                 },
1410                 .txq_flags = 0,
1411         };
1412 }
1413
1414 /* return 0 means link status changed, -1 means not changed */
1415 static int
1416 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1417 {
1418         struct e1000_hw *hw =
1419                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1420         struct rte_eth_link link, old;
1421         int link_check, count;
1422
1423         link_check = 0;
1424         hw->mac.get_link_status = 1;
1425
1426         /* possible wait-to-complete in up to 9 seconds */
1427         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1428                 /* Read the real link status */
1429                 switch (hw->phy.media_type) {
1430                 case e1000_media_type_copper:
1431                         /* Do the work to read phy */
1432                         e1000_check_for_link(hw);
1433                         link_check = !hw->mac.get_link_status;
1434                         break;
1435
1436                 case e1000_media_type_fiber:
1437                         e1000_check_for_link(hw);
1438                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1439                                       E1000_STATUS_LU);
1440                         break;
1441
1442                 case e1000_media_type_internal_serdes:
1443                         e1000_check_for_link(hw);
1444                         link_check = hw->mac.serdes_has_link;
1445                         break;
1446
1447                 /* VF device is type_unknown */
1448                 case e1000_media_type_unknown:
1449                         eth_igbvf_link_update(hw);
1450                         link_check = !hw->mac.get_link_status;
1451                         break;
1452
1453                 default:
1454                         break;
1455                 }
1456                 if (link_check || wait_to_complete == 0)
1457                         break;
1458                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1459         }
1460         memset(&link, 0, sizeof(link));
1461         rte_igb_dev_atomic_read_link_status(dev, &link);
1462         old = link;
1463
1464         /* Now we check if a transition has happened */
1465         if (link_check) {
1466                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1467                                           &link.link_duplex);
1468                 link.link_status = 1;
1469         } else if (!link_check) {
1470                 link.link_speed = 0;
1471                 link.link_duplex = 0;
1472                 link.link_status = 0;
1473         }
1474         rte_igb_dev_atomic_write_link_status(dev, &link);
1475
1476         /* not changed */
1477         if (old.link_status == link.link_status)
1478                 return -1;
1479
1480         /* changed */
1481         return 0;
1482 }
1483
1484 /*
1485  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1486  * For ASF and Pass Through versions of f/w this means
1487  * that the driver is loaded.
1488  */
1489 static void
1490 igb_hw_control_acquire(struct e1000_hw *hw)
1491 {
1492         uint32_t ctrl_ext;
1493
1494         /* Let firmware know the driver has taken over */
1495         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1496         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1497 }
1498
1499 /*
1500  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1501  * For ASF and Pass Through versions of f/w this means that the
1502  * driver is no longer loaded.
1503  */
1504 static void
1505 igb_hw_control_release(struct e1000_hw *hw)
1506 {
1507         uint32_t ctrl_ext;
1508
1509         /* Let firmware taken over control of h/w */
1510         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1511         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1512                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1513 }
1514
1515 /*
1516  * Bit of a misnomer, what this really means is
1517  * to enable OS management of the system... aka
1518  * to disable special hardware management features.
1519  */
1520 static void
1521 igb_init_manageability(struct e1000_hw *hw)
1522 {
1523         if (e1000_enable_mng_pass_thru(hw)) {
1524                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1525                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1526
1527                 /* disable hardware interception of ARP */
1528                 manc &= ~(E1000_MANC_ARP_EN);
1529
1530                 /* enable receiving management packets to the host */
1531                 manc |= E1000_MANC_EN_MNG2HOST;
1532                 manc2h |= 1 << 5;  /* Mng Port 623 */
1533                 manc2h |= 1 << 6;  /* Mng Port 664 */
1534                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1535                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1536         }
1537 }
1538
1539 static void
1540 igb_release_manageability(struct e1000_hw *hw)
1541 {
1542         if (e1000_enable_mng_pass_thru(hw)) {
1543                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1544
1545                 manc |= E1000_MANC_ARP_EN;
1546                 manc &= ~E1000_MANC_EN_MNG2HOST;
1547
1548                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1549         }
1550 }
1551
1552 static void
1553 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1554 {
1555         struct e1000_hw *hw =
1556                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1557         uint32_t rctl;
1558
1559         rctl = E1000_READ_REG(hw, E1000_RCTL);
1560         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1561         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1562 }
1563
1564 static void
1565 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1566 {
1567         struct e1000_hw *hw =
1568                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1569         uint32_t rctl;
1570
1571         rctl = E1000_READ_REG(hw, E1000_RCTL);
1572         rctl &= (~E1000_RCTL_UPE);
1573         if (dev->data->all_multicast == 1)
1574                 rctl |= E1000_RCTL_MPE;
1575         else
1576                 rctl &= (~E1000_RCTL_MPE);
1577         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1578 }
1579
1580 static void
1581 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1582 {
1583         struct e1000_hw *hw =
1584                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585         uint32_t rctl;
1586
1587         rctl = E1000_READ_REG(hw, E1000_RCTL);
1588         rctl |= E1000_RCTL_MPE;
1589         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1590 }
1591
1592 static void
1593 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1594 {
1595         struct e1000_hw *hw =
1596                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1597         uint32_t rctl;
1598
1599         if (dev->data->promiscuous == 1)
1600                 return; /* must remain in all_multicast mode */
1601         rctl = E1000_READ_REG(hw, E1000_RCTL);
1602         rctl &= (~E1000_RCTL_MPE);
1603         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1604 }
1605
1606 static int
1607 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1608 {
1609         struct e1000_hw *hw =
1610                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1611         struct e1000_vfta * shadow_vfta =
1612                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1613         uint32_t vfta;
1614         uint32_t vid_idx;
1615         uint32_t vid_bit;
1616
1617         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1618                               E1000_VFTA_ENTRY_MASK);
1619         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1620         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1621         if (on)
1622                 vfta |= vid_bit;
1623         else
1624                 vfta &= ~vid_bit;
1625         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1626
1627         /* update local VFTA copy */
1628         shadow_vfta->vfta[vid_idx] = vfta;
1629
1630         return 0;
1631 }
1632
1633 static void
1634 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1635 {
1636         struct e1000_hw *hw =
1637                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1638         uint32_t reg = ETHER_TYPE_VLAN ;
1639
1640         reg |= (tpid << 16);
1641         E1000_WRITE_REG(hw, E1000_VET, reg);
1642 }
1643
1644 static void
1645 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1646 {
1647         struct e1000_hw *hw =
1648                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1649         uint32_t reg;
1650
1651         /* Filter Table Disable */
1652         reg = E1000_READ_REG(hw, E1000_RCTL);
1653         reg &= ~E1000_RCTL_CFIEN;
1654         reg &= ~E1000_RCTL_VFE;
1655         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1656 }
1657
1658 static void
1659 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1660 {
1661         struct e1000_hw *hw =
1662                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663         struct e1000_vfta * shadow_vfta =
1664                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1665         uint32_t reg;
1666         int i;
1667
1668         /* Filter Table Enable, CFI not used for packet acceptance */
1669         reg = E1000_READ_REG(hw, E1000_RCTL);
1670         reg &= ~E1000_RCTL_CFIEN;
1671         reg |= E1000_RCTL_VFE;
1672         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1673
1674         /* restore VFTA table */
1675         for (i = 0; i < IGB_VFTA_SIZE; i++)
1676                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1677 }
1678
1679 static void
1680 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1681 {
1682         struct e1000_hw *hw =
1683                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1684         uint32_t reg;
1685
1686         /* VLAN Mode Disable */
1687         reg = E1000_READ_REG(hw, E1000_CTRL);
1688         reg &= ~E1000_CTRL_VME;
1689         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1690 }
1691
1692 static void
1693 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1694 {
1695         struct e1000_hw *hw =
1696                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1697         uint32_t reg;
1698
1699         /* VLAN Mode Enable */
1700         reg = E1000_READ_REG(hw, E1000_CTRL);
1701         reg |= E1000_CTRL_VME;
1702         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1703 }
1704
1705 static void
1706 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1707 {
1708         struct e1000_hw *hw =
1709                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1710         uint32_t reg;
1711
1712         /* CTRL_EXT: Extended VLAN */
1713         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1714         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1715         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1716
1717         /* Update maximum packet length */
1718         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1719                 E1000_WRITE_REG(hw, E1000_RLPML,
1720                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1721                                                 VLAN_TAG_SIZE);
1722 }
1723
1724 static void
1725 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1726 {
1727         struct e1000_hw *hw =
1728                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729         uint32_t reg;
1730
1731         /* CTRL_EXT: Extended VLAN */
1732         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1733         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1734         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1735
1736         /* Update maximum packet length */
1737         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1738                 E1000_WRITE_REG(hw, E1000_RLPML,
1739                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1740                                                 2 * VLAN_TAG_SIZE);
1741 }
1742
1743 static void
1744 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1745 {
1746         if(mask & ETH_VLAN_STRIP_MASK){
1747                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1748                         igb_vlan_hw_strip_enable(dev);
1749                 else
1750                         igb_vlan_hw_strip_disable(dev);
1751         }
1752
1753         if(mask & ETH_VLAN_FILTER_MASK){
1754                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1755                         igb_vlan_hw_filter_enable(dev);
1756                 else
1757                         igb_vlan_hw_filter_disable(dev);
1758         }
1759
1760         if(mask & ETH_VLAN_EXTEND_MASK){
1761                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1762                         igb_vlan_hw_extend_enable(dev);
1763                 else
1764                         igb_vlan_hw_extend_disable(dev);
1765         }
1766 }
1767
1768
1769 /**
1770  * It enables the interrupt mask and then enable the interrupt.
1771  *
1772  * @param dev
1773  *  Pointer to struct rte_eth_dev.
1774  *
1775  * @return
1776  *  - On success, zero.
1777  *  - On failure, a negative value.
1778  */
1779 static int
1780 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1781 {
1782         struct e1000_interrupt *intr =
1783                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1784
1785         intr->mask |= E1000_ICR_LSC;
1786
1787         return 0;
1788 }
1789
1790 /*
1791  * It reads ICR and gets interrupt causes, check it and set a bit flag
1792  * to update link status.
1793  *
1794  * @param dev
1795  *  Pointer to struct rte_eth_dev.
1796  *
1797  * @return
1798  *  - On success, zero.
1799  *  - On failure, a negative value.
1800  */
1801 static int
1802 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1803 {
1804         uint32_t icr;
1805         struct e1000_hw *hw =
1806                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1807         struct e1000_interrupt *intr =
1808                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1809
1810         igb_intr_disable(hw);
1811
1812         /* read-on-clear nic registers here */
1813         icr = E1000_READ_REG(hw, E1000_ICR);
1814
1815         intr->flags = 0;
1816         if (icr & E1000_ICR_LSC) {
1817                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1818         }
1819
1820         if (icr & E1000_ICR_VMMB)
1821                 intr->flags |= E1000_FLAG_MAILBOX;
1822
1823         return 0;
1824 }
1825
1826 /*
1827  * It executes link_update after knowing an interrupt is prsent.
1828  *
1829  * @param dev
1830  *  Pointer to struct rte_eth_dev.
1831  *
1832  * @return
1833  *  - On success, zero.
1834  *  - On failure, a negative value.
1835  */
1836 static int
1837 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1838 {
1839         struct e1000_hw *hw =
1840                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1841         struct e1000_interrupt *intr =
1842                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1843         uint32_t tctl, rctl;
1844         struct rte_eth_link link;
1845         int ret;
1846
1847         if (intr->flags & E1000_FLAG_MAILBOX) {
1848                 igb_pf_mbx_process(dev);
1849                 intr->flags &= ~E1000_FLAG_MAILBOX;
1850         }
1851
1852         igb_intr_enable(dev);
1853         rte_intr_enable(&(dev->pci_dev->intr_handle));
1854
1855         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1856                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1857
1858                 /* set get_link_status to check register later */
1859                 hw->mac.get_link_status = 1;
1860                 ret = eth_igb_link_update(dev, 0);
1861
1862                 /* check if link has changed */
1863                 if (ret < 0)
1864                         return 0;
1865
1866                 memset(&link, 0, sizeof(link));
1867                 rte_igb_dev_atomic_read_link_status(dev, &link);
1868                 if (link.link_status) {
1869                         PMD_INIT_LOG(INFO,
1870                                      " Port %d: Link Up - speed %u Mbps - %s",
1871                                      dev->data->port_id,
1872                                      (unsigned)link.link_speed,
1873                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1874                                      "full-duplex" : "half-duplex");
1875                 } else {
1876                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
1877                                      dev->data->port_id);
1878                 }
1879                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1880                              dev->pci_dev->addr.domain,
1881                              dev->pci_dev->addr.bus,
1882                              dev->pci_dev->addr.devid,
1883                              dev->pci_dev->addr.function);
1884                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1885                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1886                 if (link.link_status) {
1887                         /* enable Tx/Rx */
1888                         tctl |= E1000_TCTL_EN;
1889                         rctl |= E1000_RCTL_EN;
1890                 } else {
1891                         /* disable Tx/Rx */
1892                         tctl &= ~E1000_TCTL_EN;
1893                         rctl &= ~E1000_RCTL_EN;
1894                 }
1895                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1896                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1897                 E1000_WRITE_FLUSH(hw);
1898                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1899         }
1900
1901         return 0;
1902 }
1903
1904 /**
1905  * Interrupt handler which shall be registered at first.
1906  *
1907  * @param handle
1908  *  Pointer to interrupt handle.
1909  * @param param
1910  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1911  *
1912  * @return
1913  *  void
1914  */
1915 static void
1916 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1917                                                         void *param)
1918 {
1919         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1920
1921         eth_igb_interrupt_get_status(dev);
1922         eth_igb_interrupt_action(dev);
1923 }
1924
1925 static int
1926 eth_igb_led_on(struct rte_eth_dev *dev)
1927 {
1928         struct e1000_hw *hw;
1929
1930         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1931         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1932 }
1933
1934 static int
1935 eth_igb_led_off(struct rte_eth_dev *dev)
1936 {
1937         struct e1000_hw *hw;
1938
1939         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1940         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1941 }
1942
1943 static int
1944 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1945 {
1946         struct e1000_hw *hw;
1947         uint32_t ctrl;
1948         int tx_pause;
1949         int rx_pause;
1950
1951         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1952         fc_conf->pause_time = hw->fc.pause_time;
1953         fc_conf->high_water = hw->fc.high_water;
1954         fc_conf->low_water = hw->fc.low_water;
1955         fc_conf->send_xon = hw->fc.send_xon;
1956         fc_conf->autoneg = hw->mac.autoneg;
1957
1958         /*
1959          * Return rx_pause and tx_pause status according to actual setting of
1960          * the TFCE and RFCE bits in the CTRL register.
1961          */
1962         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1963         if (ctrl & E1000_CTRL_TFCE)
1964                 tx_pause = 1;
1965         else
1966                 tx_pause = 0;
1967
1968         if (ctrl & E1000_CTRL_RFCE)
1969                 rx_pause = 1;
1970         else
1971                 rx_pause = 0;
1972
1973         if (rx_pause && tx_pause)
1974                 fc_conf->mode = RTE_FC_FULL;
1975         else if (rx_pause)
1976                 fc_conf->mode = RTE_FC_RX_PAUSE;
1977         else if (tx_pause)
1978                 fc_conf->mode = RTE_FC_TX_PAUSE;
1979         else
1980                 fc_conf->mode = RTE_FC_NONE;
1981
1982         return 0;
1983 }
1984
1985 static int
1986 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1987 {
1988         struct e1000_hw *hw;
1989         int err;
1990         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1991                 e1000_fc_none,
1992                 e1000_fc_rx_pause,
1993                 e1000_fc_tx_pause,
1994                 e1000_fc_full
1995         };
1996         uint32_t rx_buf_size;
1997         uint32_t max_high_water;
1998         uint32_t rctl;
1999
2000         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2001         if (fc_conf->autoneg != hw->mac.autoneg)
2002                 return -ENOTSUP;
2003         rx_buf_size = igb_get_rx_buffer_size(hw);
2004         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2005
2006         /* At least reserve one Ethernet frame for watermark */
2007         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2008         if ((fc_conf->high_water > max_high_water) ||
2009             (fc_conf->high_water < fc_conf->low_water)) {
2010                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2011                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2012                 return (-EINVAL);
2013         }
2014
2015         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2016         hw->fc.pause_time     = fc_conf->pause_time;
2017         hw->fc.high_water     = fc_conf->high_water;
2018         hw->fc.low_water      = fc_conf->low_water;
2019         hw->fc.send_xon       = fc_conf->send_xon;
2020
2021         err = e1000_setup_link_generic(hw);
2022         if (err == E1000_SUCCESS) {
2023
2024                 /* check if we want to forward MAC frames - driver doesn't have native
2025                  * capability to do that, so we'll write the registers ourselves */
2026
2027                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2028
2029                 /* set or clear MFLCN.PMCF bit depending on configuration */
2030                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2031                         rctl |= E1000_RCTL_PMCF;
2032                 else
2033                         rctl &= ~E1000_RCTL_PMCF;
2034
2035                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2036                 E1000_WRITE_FLUSH(hw);
2037
2038                 return 0;
2039         }
2040
2041         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2042         return (-EIO);
2043 }
2044
2045 #define E1000_RAH_POOLSEL_SHIFT      (18)
2046 static void
2047 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2048                 uint32_t index, __rte_unused uint32_t pool)
2049 {
2050         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051         uint32_t rah;
2052
2053         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2054         rah = E1000_READ_REG(hw, E1000_RAH(index));
2055         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2056         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2057 }
2058
2059 static void
2060 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2061 {
2062         uint8_t addr[ETHER_ADDR_LEN];
2063         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2064
2065         memset(addr, 0, sizeof(addr));
2066
2067         e1000_rar_set(hw, addr, index);
2068 }
2069
2070 /*
2071  * Virtual Function operations
2072  */
2073 static void
2074 igbvf_intr_disable(struct e1000_hw *hw)
2075 {
2076         PMD_INIT_FUNC_TRACE();
2077
2078         /* Clear interrupt mask to stop from interrupts being generated */
2079         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2080
2081         E1000_WRITE_FLUSH(hw);
2082 }
2083
2084 static void
2085 igbvf_stop_adapter(struct rte_eth_dev *dev)
2086 {
2087         u32 reg_val;
2088         u16 i;
2089         struct rte_eth_dev_info dev_info;
2090         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091
2092         memset(&dev_info, 0, sizeof(dev_info));
2093         eth_igbvf_infos_get(dev, &dev_info);
2094
2095         /* Clear interrupt mask to stop from interrupts being generated */
2096         igbvf_intr_disable(hw);
2097
2098         /* Clear any pending interrupts, flush previous writes */
2099         E1000_READ_REG(hw, E1000_EICR);
2100
2101         /* Disable the transmit unit.  Each queue must be disabled. */
2102         for (i = 0; i < dev_info.max_tx_queues; i++)
2103                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2104
2105         /* Disable the receive unit by stopping each queue */
2106         for (i = 0; i < dev_info.max_rx_queues; i++) {
2107                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2108                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2109                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2110                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2111                         ;
2112         }
2113
2114         /* flush all queues disables */
2115         E1000_WRITE_FLUSH(hw);
2116         msec_delay(2);
2117 }
2118
2119 static int eth_igbvf_link_update(struct e1000_hw *hw)
2120 {
2121         struct e1000_mbx_info *mbx = &hw->mbx;
2122         struct e1000_mac_info *mac = &hw->mac;
2123         int ret_val = E1000_SUCCESS;
2124
2125         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2126
2127         /*
2128          * We only want to run this if there has been a rst asserted.
2129          * in this case that could mean a link change, device reset,
2130          * or a virtual function reset
2131          */
2132
2133         /* If we were hit with a reset or timeout drop the link */
2134         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2135                 mac->get_link_status = TRUE;
2136
2137         if (!mac->get_link_status)
2138                 goto out;
2139
2140         /* if link status is down no point in checking to see if pf is up */
2141         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2142                 goto out;
2143
2144         /* if we passed all the tests above then the link is up and we no
2145          * longer need to check for link */
2146         mac->get_link_status = FALSE;
2147
2148 out:
2149         return ret_val;
2150 }
2151
2152
2153 static int
2154 igbvf_dev_configure(struct rte_eth_dev *dev)
2155 {
2156         struct rte_eth_conf* conf = &dev->data->dev_conf;
2157
2158         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2159                      dev->data->port_id);
2160
2161         /*
2162          * VF has no ability to enable/disable HW CRC
2163          * Keep the persistent behavior the same as Host PF
2164          */
2165 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2166         if (!conf->rxmode.hw_strip_crc) {
2167                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2168                 conf->rxmode.hw_strip_crc = 1;
2169         }
2170 #else
2171         if (conf->rxmode.hw_strip_crc) {
2172                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2173                 conf->rxmode.hw_strip_crc = 0;
2174         }
2175 #endif
2176
2177         return 0;
2178 }
2179
2180 static int
2181 igbvf_dev_start(struct rte_eth_dev *dev)
2182 {
2183         struct e1000_hw *hw =
2184                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185         int ret;
2186
2187         PMD_INIT_FUNC_TRACE();
2188
2189         hw->mac.ops.reset_hw(hw);
2190
2191         /* Set all vfta */
2192         igbvf_set_vfta_all(dev,1);
2193
2194         eth_igbvf_tx_init(dev);
2195
2196         /* This can fail when allocating mbufs for descriptor rings */
2197         ret = eth_igbvf_rx_init(dev);
2198         if (ret) {
2199                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2200                 igb_dev_clear_queues(dev);
2201                 return ret;
2202         }
2203
2204         return 0;
2205 }
2206
2207 static void
2208 igbvf_dev_stop(struct rte_eth_dev *dev)
2209 {
2210         PMD_INIT_FUNC_TRACE();
2211
2212         igbvf_stop_adapter(dev);
2213
2214         /*
2215           * Clear what we set, but we still keep shadow_vfta to
2216           * restore after device starts
2217           */
2218         igbvf_set_vfta_all(dev,0);
2219
2220         igb_dev_clear_queues(dev);
2221 }
2222
2223 static void
2224 igbvf_dev_close(struct rte_eth_dev *dev)
2225 {
2226         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227
2228         PMD_INIT_FUNC_TRACE();
2229
2230         e1000_reset_hw(hw);
2231
2232         igbvf_dev_stop(dev);
2233 }
2234
2235 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2236 {
2237         struct e1000_mbx_info *mbx = &hw->mbx;
2238         uint32_t msgbuf[2];
2239
2240         /* After set vlan, vlan strip will also be enabled in igb driver*/
2241         msgbuf[0] = E1000_VF_SET_VLAN;
2242         msgbuf[1] = vid;
2243         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2244         if (on)
2245                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2246
2247         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2248 }
2249
2250 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2251 {
2252         struct e1000_hw *hw =
2253                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2254         struct e1000_vfta * shadow_vfta =
2255                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2256         int i = 0, j = 0, vfta = 0, mask = 1;
2257
2258         for (i = 0; i < IGB_VFTA_SIZE; i++){
2259                 vfta = shadow_vfta->vfta[i];
2260                 if(vfta){
2261                         mask = 1;
2262                         for (j = 0; j < 32; j++){
2263                                 if(vfta & mask)
2264                                         igbvf_set_vfta(hw,
2265                                                 (uint16_t)((i<<5)+j), on);
2266                                 mask<<=1;
2267                         }
2268                 }
2269         }
2270
2271 }
2272
2273 static int
2274 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2275 {
2276         struct e1000_hw *hw =
2277                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2278         struct e1000_vfta * shadow_vfta =
2279                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2280         uint32_t vid_idx = 0;
2281         uint32_t vid_bit = 0;
2282         int ret = 0;
2283
2284         PMD_INIT_FUNC_TRACE();
2285
2286         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2287         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2288         if(ret){
2289                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2290                 return ret;
2291         }
2292         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2293         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2294
2295         /*Save what we set and retore it after device reset*/
2296         if (on)
2297                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2298         else
2299                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2300
2301         return 0;
2302 }
2303
2304 static int
2305 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2306                                 struct rte_eth_rss_reta *reta_conf)
2307 {
2308         uint8_t i,j,mask;
2309         uint32_t reta;
2310         struct e1000_hw *hw =
2311                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2312
2313         /*
2314          * Update Redirection Table RETA[n],n=0...31,The redirection table has
2315          * 128-entries in 32 registers
2316          */
2317         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2318                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2319                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2320                 else
2321                         mask = (uint8_t)((reta_conf->mask_hi >>
2322                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2323                 if (mask != 0) {
2324                         reta = 0;
2325                         /* If all 4 entries were set,don't need read RETA register */
2326                         if (mask != 0xF)
2327                                 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2328
2329                         for (j = 0; j < 4; j++) {
2330                                 if (mask & (0x1 << j)) {
2331                                         if (mask != 0xF)
2332                                                 reta &= ~(0xFF << 8 * j);
2333                                         reta |= reta_conf->reta[i + j] << 8 * j;
2334                                 }
2335                         }
2336                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2337                 }
2338         }
2339
2340         return 0;
2341 }
2342
2343 static int
2344 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2345                                 struct rte_eth_rss_reta *reta_conf)
2346 {
2347         uint8_t i,j,mask;
2348         uint32_t reta;
2349         struct e1000_hw *hw =
2350                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2351
2352         /*
2353          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2354          * 128-entries in 32 registers
2355          */
2356         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2357                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2358                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2359                 else
2360                         mask = (uint8_t)((reta_conf->mask_hi >>
2361                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2362
2363                 if (mask != 0) {
2364                         reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2365                         for (j = 0; j < 4; j++) {
2366                                 if (mask & (0x1 << j))
2367                                         reta_conf->reta[i + j] =
2368                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2369                         }
2370                 }
2371         }
2372
2373         return 0;
2374 }
2375
2376 #define MAC_TYPE_FILTER_SUP(type)    do {\
2377         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2378                 (type) != e1000_82576)\
2379                 return -ENOSYS;\
2380 } while (0)
2381
2382 /*
2383  * add the syn filter
2384  *
2385  * @param
2386  * dev: Pointer to struct rte_eth_dev.
2387  * filter: ponter to the filter that will be added.
2388  * rx_queue: the queue id the filter assigned to.
2389  *
2390  * @return
2391  *    - On success, zero.
2392  *    - On failure, a negative value.
2393  */
2394 static int
2395 eth_igb_add_syn_filter(struct rte_eth_dev *dev,
2396                         struct rte_syn_filter *filter, uint16_t rx_queue)
2397 {
2398         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399         uint32_t synqf, rfctl;
2400
2401         MAC_TYPE_FILTER_SUP(hw->mac.type);
2402
2403         if (rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2404                 return -EINVAL;
2405
2406         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2407         if (synqf & E1000_SYN_FILTER_ENABLE)
2408                 return -EINVAL;
2409
2410         synqf = (uint32_t)(((rx_queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2411                 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2412
2413         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2414         if (filter->hig_pri)
2415                 rfctl |= E1000_RFCTL_SYNQFP;
2416         else
2417                 rfctl &= ~E1000_RFCTL_SYNQFP;
2418
2419         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2420         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2421         return 0;
2422 }
2423
2424 /*
2425  * remove the syn filter
2426  *
2427  * @param
2428  * dev: Pointer to struct rte_eth_dev.
2429  *
2430  * @return
2431  *    - On success, zero.
2432  *    - On failure, a negative value.
2433  */
2434 static int
2435 eth_igb_remove_syn_filter(struct rte_eth_dev *dev)
2436 {
2437         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2438
2439         MAC_TYPE_FILTER_SUP(hw->mac.type);
2440
2441         E1000_WRITE_REG(hw, E1000_SYNQF(0), 0);
2442         return 0;
2443 }
2444
2445 /*
2446  * get the syn filter's info
2447  *
2448  * @param
2449  * dev: Pointer to struct rte_eth_dev.
2450  * filter: ponter to the filter that returns.
2451  * *rx_queue: pointer to the queue id the filter assigned to.
2452  *
2453  * @return
2454  *    - On success, zero.
2455  *    - On failure, a negative value.
2456  */
2457 static int
2458 eth_igb_get_syn_filter(struct rte_eth_dev *dev,
2459                         struct rte_syn_filter *filter, uint16_t *rx_queue)
2460 {
2461         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2462         uint32_t synqf, rfctl;
2463
2464         MAC_TYPE_FILTER_SUP(hw->mac.type);
2465         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2466         if (synqf & E1000_SYN_FILTER_ENABLE) {
2467                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2468                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2469                 *rx_queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2470                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2471                 return 0;
2472         }
2473         return -ENOENT;
2474 }
2475
2476 /*
2477  * add an ethertype filter
2478  *
2479  * @param
2480  * dev: Pointer to struct rte_eth_dev.
2481  * index: the index the filter allocates.
2482  * filter: ponter to the filter that will be added.
2483  * rx_queue: the queue id the filter assigned to.
2484  *
2485  * @return
2486  *    - On success, zero.
2487  *    - On failure, a negative value.
2488  */
2489 static int
2490 eth_igb_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2491                         struct rte_ethertype_filter *filter, uint16_t rx_queue)
2492 {
2493         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2494         uint32_t etqf;
2495
2496         MAC_TYPE_FILTER_SUP(hw->mac.type);
2497
2498         if (index >= E1000_MAX_ETQF_FILTERS || rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2499                 return -EINVAL;
2500
2501         etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2502         if (etqf & E1000_ETQF_FILTER_ENABLE)
2503                 return -EINVAL;  /* filter index is in use. */
2504         else
2505                 etqf = 0;
2506
2507         etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
2508         etqf |= (uint32_t)(filter->ethertype & E1000_ETQF_ETHERTYPE);
2509         etqf |= rx_queue << E1000_ETQF_QUEUE_SHIFT;
2510
2511         if (filter->priority_en) {
2512                 PMD_INIT_LOG(ERR, "vlan and priority (%d) is not supported"
2513                         " in E1000.", filter->priority);
2514                 return -EINVAL;
2515         }
2516
2517         E1000_WRITE_REG(hw, E1000_ETQF(index), etqf);
2518         return 0;
2519 }
2520
2521 /*
2522  * remove an ethertype filter
2523  *
2524  * @param
2525  * dev: Pointer to struct rte_eth_dev.
2526  * index: the index the filter allocates.
2527  *
2528  * @return
2529  *    - On success, zero.
2530  *    - On failure, a negative value.
2531  */
2532 static int
2533 eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev, uint16_t index)
2534 {
2535         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536
2537         MAC_TYPE_FILTER_SUP(hw->mac.type);
2538
2539         if (index >= E1000_MAX_ETQF_FILTERS)
2540                 return -EINVAL;
2541
2542         E1000_WRITE_REG(hw, E1000_ETQF(index), 0);
2543         return 0;
2544 }
2545
2546 /*
2547  * get an ethertype filter
2548  *
2549  * @param
2550  * dev: Pointer to struct rte_eth_dev.
2551  * index: the index the filter allocates.
2552  * filter: ponter to the filter that will be gotten.
2553  * *rx_queue: the ponited of the queue id the filter assigned to.
2554  *
2555  * @return
2556  *    - On success, zero.
2557  *    - On failure, a negative value.
2558  */
2559 static int
2560 eth_igb_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2561                         struct rte_ethertype_filter *filter, uint16_t *rx_queue)
2562 {
2563         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2564         uint32_t etqf;
2565
2566         MAC_TYPE_FILTER_SUP(hw->mac.type);
2567
2568         if (index >= E1000_MAX_ETQF_FILTERS)
2569                 return -EINVAL;
2570
2571         etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2572         if (etqf & E1000_ETQF_FILTER_ENABLE) {
2573                 filter->ethertype = etqf & E1000_ETQF_ETHERTYPE;
2574                 filter->priority_en = 0;
2575                 *rx_queue = (etqf & E1000_ETQF_QUEUE) >> E1000_ETQF_QUEUE_SHIFT;
2576                 return 0;
2577         }
2578         return -ENOENT;
2579 }
2580
2581 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2582         if ((type) != e1000_82580 && (type) != e1000_i350)\
2583                 return -ENOSYS; \
2584 } while (0)
2585
2586 /*
2587  * add a 2tuple filter
2588  *
2589  * @param
2590  * dev: Pointer to struct rte_eth_dev.
2591  * index: the index the filter allocates.
2592  * filter: ponter to the filter that will be added.
2593  * rx_queue: the queue id the filter assigned to.
2594  *
2595  * @return
2596  *    - On success, zero.
2597  *    - On failure, a negative value.
2598  */
2599 static int
2600 eth_igb_add_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2601                         struct rte_2tuple_filter *filter, uint16_t rx_queue)
2602 {
2603         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2604         uint32_t ttqf, imir = 0;
2605         uint32_t imir_ext = 0;
2606
2607         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2608
2609         if (index >= E1000_MAX_TTQF_FILTERS ||
2610                 rx_queue >= IGB_MAX_RX_QUEUE_NUM ||
2611                 filter->priority > E1000_2TUPLE_MAX_PRI)
2612                 return -EINVAL;  /* filter index is out of range. */
2613         if  (filter->tcp_flags > TCP_FLAG_ALL)
2614                 return -EINVAL;  /* flags is invalid. */
2615
2616         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2617         if (ttqf & E1000_TTQF_QUEUE_ENABLE)
2618                 return -EINVAL;  /* filter index is in use. */
2619
2620         imir = (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2621         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2622                 imir |= E1000_IMIR_PORT_BP;
2623         else
2624                 imir &= ~E1000_IMIR_PORT_BP;
2625
2626         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2627
2628         ttqf = 0;
2629         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2630         ttqf |= (uint32_t)(rx_queue << E1000_TTQF_QUEUE_SHIFT);
2631         ttqf |= (uint32_t)(filter->protocol & E1000_TTQF_PROTOCOL_MASK);
2632         if (filter->protocol_mask == 1)
2633                 ttqf |= E1000_TTQF_MASK_ENABLE;
2634         else
2635                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2636
2637         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2638         /* tcp flags bits setting. */
2639         if (filter->tcp_flags & TCP_FLAG_ALL) {
2640                 if (filter->tcp_flags & TCP_UGR_FLAG)
2641                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2642                 if (filter->tcp_flags & TCP_ACK_FLAG)
2643                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2644                 if (filter->tcp_flags & TCP_PSH_FLAG)
2645                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2646                 if (filter->tcp_flags & TCP_RST_FLAG)
2647                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2648                 if (filter->tcp_flags & TCP_SYN_FLAG)
2649                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2650                 if (filter->tcp_flags & TCP_FIN_FLAG)
2651                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2652                 imir_ext &= ~E1000_IMIR_EXT_CTRL_BP;
2653         } else
2654                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2655         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2656         E1000_WRITE_REG(hw, E1000_TTQF(index), ttqf);
2657         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2658         return 0;
2659 }
2660
2661 /*
2662  * remove a 2tuple filter
2663  *
2664  * @param
2665  * dev: Pointer to struct rte_eth_dev.
2666  * index: the index the filter allocates.
2667  *
2668  * @return
2669  *    - On success, zero.
2670  *    - On failure, a negative value.
2671  */
2672 static int
2673 eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2674                         uint16_t index)
2675 {
2676         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2677
2678         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2679
2680         if (index >= E1000_MAX_TTQF_FILTERS)
2681                 return -EINVAL;  /* filter index is out of range */
2682
2683         E1000_WRITE_REG(hw, E1000_TTQF(index), 0);
2684         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2685         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2686         return 0;
2687 }
2688
2689 /*
2690  * get a 2tuple filter
2691  *
2692  * @param
2693  * dev: Pointer to struct rte_eth_dev.
2694  * index: the index the filter allocates.
2695  * filter: ponter to the filter that returns.
2696  * *rx_queue: pointer of the queue id the filter assigned to.
2697  *
2698  * @return
2699  *    - On success, zero.
2700  *    - On failure, a negative value.
2701  */
2702 static int
2703 eth_igb_get_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2704                         struct rte_2tuple_filter *filter, uint16_t *rx_queue)
2705 {
2706         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2707         uint32_t imir, ttqf, imir_ext;
2708
2709         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2710
2711         if (index >= E1000_MAX_TTQF_FILTERS)
2712                 return -EINVAL;  /* filter index is out of range. */
2713
2714         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2715         if (ttqf & E1000_TTQF_QUEUE_ENABLE) {
2716                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2717                 filter->protocol = ttqf & E1000_TTQF_PROTOCOL_MASK;
2718                 filter->protocol_mask = (ttqf & E1000_TTQF_MASK_ENABLE) ? 1 : 0;
2719                 *rx_queue = (ttqf & E1000_TTQF_RX_QUEUE_MASK) >>
2720                                 E1000_TTQF_QUEUE_SHIFT;
2721                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2722                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2723                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2724                         E1000_IMIR_PRIORITY_SHIFT;
2725
2726                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2727                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2728                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2729                                 filter->tcp_flags |= TCP_UGR_FLAG;
2730                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2731                                 filter->tcp_flags |= TCP_ACK_FLAG;
2732                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2733                                 filter->tcp_flags |= TCP_PSH_FLAG;
2734                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2735                                 filter->tcp_flags |= TCP_RST_FLAG;
2736                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2737                                 filter->tcp_flags |= TCP_SYN_FLAG;
2738                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2739                                 filter->tcp_flags |= TCP_FIN_FLAG;
2740                 } else
2741                         filter->tcp_flags = 0;
2742                 return 0;
2743         }
2744         return -ENOENT;
2745 }
2746
2747 /*
2748  * add a flex filter
2749  *
2750  * @param
2751  * dev: Pointer to struct rte_eth_dev.
2752  * index: the index the filter allocates.
2753  * filter: ponter to the filter that will be added.
2754  * rx_queue: the queue id the filter assigned to.
2755  *
2756  * @return
2757  *    - On success, zero.
2758  *     - On failure, a negative value.
2759  */
2760 static int
2761 eth_igb_add_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2762                         struct rte_flex_filter *filter, uint16_t rx_queue)
2763 {
2764         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2765         uint32_t wufc, en_bits = 0;
2766         uint32_t queueing = 0;
2767         uint32_t reg_off = 0;
2768         uint8_t i, j = 0;
2769
2770         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2771
2772         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2773                 return -EINVAL;  /* filter index is out of range. */
2774
2775         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN ||
2776                 filter->len % 8 != 0 ||
2777                 filter->priority > E1000_MAX_FLEX_FILTER_PRI)
2778                 return -EINVAL;
2779
2780         wufc = E1000_READ_REG(hw, E1000_WUFC);
2781         en_bits = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2782         if ((wufc & en_bits) == en_bits)
2783                 return -EINVAL;  /* the filter is in use. */
2784
2785         E1000_WRITE_REG(hw, E1000_WUFC,
2786                 wufc | E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index));
2787
2788         j = 0;
2789         if (index < E1000_MAX_FHFT)
2790                 reg_off = E1000_FHFT(index);
2791         else
2792                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2793
2794         for (i = 0; i < 16; i++) {
2795                 E1000_WRITE_REG(hw, reg_off + i*4*4, filter->dwords[j]);
2796                 E1000_WRITE_REG(hw, reg_off + (i*4+1)*4, filter->dwords[++j]);
2797                 E1000_WRITE_REG(hw, reg_off + (i*4+2)*4,
2798                                 (uint32_t)filter->mask[i]);
2799                 ++j;
2800         }
2801         queueing |= filter->len |
2802                 (rx_queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2803                 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2804         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET, queueing);
2805         return 0;
2806 }
2807
2808 /*
2809  * remove a flex filter
2810  *
2811  * @param
2812  * dev: Pointer to struct rte_eth_dev.
2813  * index: the index the filter allocates.
2814  *
2815  * @return
2816  *    - On success, zero.
2817  *    - On failure, a negative value.
2818  */
2819 static int
2820 eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
2821                                 uint16_t index)
2822 {
2823         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2824         uint32_t wufc, reg_off = 0;
2825         uint8_t i;
2826
2827         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2828
2829         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2830                 return -EINVAL;  /* filter index is out of range. */
2831
2832         wufc = E1000_READ_REG(hw, E1000_WUFC);
2833         E1000_WRITE_REG(hw, E1000_WUFC, wufc & (~(E1000_WUFC_FLX0 << index)));
2834
2835         if (index < E1000_MAX_FHFT)
2836                 reg_off = E1000_FHFT(index);
2837         else
2838                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2839
2840         for (i = 0; i < 64; i++)
2841                 E1000_WRITE_REG(hw, reg_off + i*4, 0);
2842         return 0;
2843 }
2844
2845 /*
2846  * get a flex filter
2847  *
2848  * @param
2849  * dev: Pointer to struct rte_eth_dev.
2850  * index: the index the filter allocates.
2851  * filter: ponter to the filter that returns.
2852  * *rx_queue: the pointer of the queue id the filter assigned to.
2853  *
2854  * @return
2855  *    - On success, zero.
2856  *    - On failure, a negative value.
2857  */
2858 static int
2859 eth_igb_get_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2860                         struct rte_flex_filter *filter, uint16_t *rx_queue)
2861 {
2862         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2863         uint32_t wufc, queueing, wufc_en = 0;
2864         uint8_t i, j;
2865
2866         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2867
2868         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2869                 return -EINVAL;  /* filter index is out of range. */
2870
2871         wufc = E1000_READ_REG(hw, E1000_WUFC);
2872         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2873
2874         if ((wufc & wufc_en) == wufc_en) {
2875                 uint32_t reg_off = 0;
2876                 j = 0;
2877                 if (index < E1000_MAX_FHFT)
2878                         reg_off = E1000_FHFT(index);
2879                 else
2880                         reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2881
2882                 for (i = 0; i < 16; i++, j = i * 2) {
2883                         filter->dwords[j] =
2884                                 E1000_READ_REG(hw, reg_off + i*4*4);
2885                         filter->dwords[j+1] =
2886                                 E1000_READ_REG(hw, reg_off + (i*4+1)*4);
2887                         filter->mask[i] =
2888                                 E1000_READ_REG(hw, reg_off + (i*4+2)*4);
2889                 }
2890                 queueing = E1000_READ_REG(hw,
2891                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2892                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2893                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2894                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
2895                 *rx_queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2896                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2897                 return 0;
2898         }
2899         return -ENOENT;
2900 }
2901
2902 /*
2903  * add a 5tuple filter
2904  *
2905  * @param
2906  * dev: Pointer to struct rte_eth_dev.
2907  * index: the index the filter allocates.
2908  * filter: ponter to the filter that will be added.
2909  * rx_queue: the queue id the filter assigned to.
2910  *
2911  * @return
2912  *    - On success, zero.
2913  *    - On failure, a negative value.
2914  */
2915 static int
2916 eth_igb_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2917                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
2918 {
2919         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2920         uint32_t ftqf, spqf = 0;
2921         uint32_t imir = 0;
2922         uint32_t imir_ext = 0;
2923
2924         if (hw->mac.type != e1000_82576)
2925                 return -ENOSYS;
2926
2927         if (index >= E1000_MAX_FTQF_FILTERS ||
2928                 rx_queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2929                 return -EINVAL;  /* filter index is out of range. */
2930
2931         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2932         if (ftqf & E1000_FTQF_QUEUE_ENABLE)
2933                 return -EINVAL;  /* filter index is in use. */
2934
2935         ftqf = 0;
2936         ftqf |= filter->protocol & E1000_FTQF_PROTOCOL_MASK;
2937         if (filter->src_ip_mask == 1) /* 1b means not compare. */
2938                 ftqf |= E1000_FTQF_SOURCE_ADDR_MASK;
2939         if (filter->dst_ip_mask == 1)
2940                 ftqf |= E1000_FTQF_DEST_ADDR_MASK;
2941         if (filter->src_port_mask == 1)
2942                 ftqf |= E1000_FTQF_SOURCE_PORT_MASK;
2943         if (filter->protocol_mask == 1)
2944                 ftqf |= E1000_FTQF_PROTOCOL_COMP_MASK;
2945         ftqf |= (rx_queue << E1000_FTQF_QUEUE_SHIFT) & E1000_FTQF_QUEUE_MASK;
2946         ftqf |= E1000_FTQF_VF_MASK_EN;
2947         ftqf |= E1000_FTQF_QUEUE_ENABLE;
2948         E1000_WRITE_REG(hw, E1000_FTQF(index), ftqf);
2949         E1000_WRITE_REG(hw, E1000_DAQF(index), filter->dst_ip);
2950         E1000_WRITE_REG(hw, E1000_SAQF(index), filter->src_ip);
2951
2952         spqf |= filter->src_port & E1000_SPQF_SRCPORT;
2953         E1000_WRITE_REG(hw, E1000_SPQF(index), spqf);
2954
2955         imir |= (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2956         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2957                 imir |= E1000_IMIR_PORT_BP;
2958         else
2959                 imir &= ~E1000_IMIR_PORT_BP;
2960         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2961
2962         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2963         /* tcp flags bits setting. */
2964         if (filter->tcp_flags & TCP_FLAG_ALL) {
2965                 if (filter->tcp_flags & TCP_UGR_FLAG)
2966                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2967                 if (filter->tcp_flags & TCP_ACK_FLAG)
2968                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2969                 if (filter->tcp_flags & TCP_PSH_FLAG)
2970                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2971                 if (filter->tcp_flags & TCP_RST_FLAG)
2972                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2973                 if (filter->tcp_flags & TCP_SYN_FLAG)
2974                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2975                 if (filter->tcp_flags & TCP_FIN_FLAG)
2976                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2977         } else
2978                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2979         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2980         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2981         return 0;
2982 }
2983
2984 /*
2985  * remove a 5tuple filter
2986  *
2987  * @param
2988  * dev: Pointer to struct rte_eth_dev.
2989  * index: the index the filter allocates
2990  *
2991  * @return
2992  *    - On success, zero.
2993  *    - On failure, a negative value.
2994  */
2995 static int
2996 eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
2997                                 uint16_t index)
2998 {
2999         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3000
3001         if (hw->mac.type != e1000_82576)
3002                 return -ENOSYS;
3003
3004         if (index >= E1000_MAX_FTQF_FILTERS)
3005                 return -EINVAL;  /* filter index is out of range. */
3006
3007         E1000_WRITE_REG(hw, E1000_FTQF(index), 0);
3008         E1000_WRITE_REG(hw, E1000_DAQF(index), 0);
3009         E1000_WRITE_REG(hw, E1000_SAQF(index), 0);
3010         E1000_WRITE_REG(hw, E1000_SPQF(index), 0);
3011         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
3012         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
3013         return 0;
3014 }
3015
3016 /*
3017  * get a 5tuple filter
3018  *
3019  * @param
3020  * dev: Pointer to struct rte_eth_dev.
3021  * index: the index the filter allocates
3022  * filter: ponter to the filter that returns
3023  * *rx_queue: pointer of the queue id the filter assigned to
3024  *
3025  * @return
3026  *    - On success, zero.
3027  *    - On failure, a negative value.
3028  */
3029 static int
3030 eth_igb_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3031                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3032 {
3033         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3034         uint32_t spqf, ftqf, imir, imir_ext;
3035
3036         if (hw->mac.type != e1000_82576)
3037                 return -ENOSYS;
3038
3039         if (index >= E1000_MAX_FTQF_FILTERS)
3040                 return -EINVAL;  /* filter index is out of range. */
3041
3042         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
3043         if (ftqf & E1000_FTQF_QUEUE_ENABLE) {
3044                 filter->src_ip_mask =
3045                         (ftqf & E1000_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3046                 filter->dst_ip_mask =
3047                         (ftqf & E1000_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3048                 filter->src_port_mask =
3049                         (ftqf & E1000_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3050                 filter->protocol_mask =
3051                         (ftqf & E1000_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3052                 filter->protocol =
3053                         (uint8_t)ftqf & E1000_FTQF_PROTOCOL_MASK;
3054                 *rx_queue = (uint16_t)((ftqf & E1000_FTQF_QUEUE_MASK) >>
3055                                 E1000_FTQF_QUEUE_SHIFT);
3056
3057                 spqf = E1000_READ_REG(hw, E1000_SPQF(index));
3058                 filter->src_port = spqf & E1000_SPQF_SRCPORT;
3059
3060                 filter->dst_ip = E1000_READ_REG(hw, E1000_DAQF(index));
3061                 filter->src_ip = E1000_READ_REG(hw, E1000_SAQF(index));
3062
3063                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
3064                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
3065                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
3066                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
3067                         E1000_IMIR_PRIORITY_SHIFT;
3068
3069                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
3070                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
3071                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
3072                                 filter->tcp_flags |= TCP_UGR_FLAG;
3073                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
3074                                 filter->tcp_flags |= TCP_ACK_FLAG;
3075                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
3076                                 filter->tcp_flags |= TCP_PSH_FLAG;
3077                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
3078                                 filter->tcp_flags |= TCP_RST_FLAG;
3079                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
3080                                 filter->tcp_flags |= TCP_SYN_FLAG;
3081                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
3082                                 filter->tcp_flags |= TCP_FIN_FLAG;
3083                 } else
3084                         filter->tcp_flags = 0;
3085                 return 0;
3086         }
3087         return -ENOENT;
3088 }
3089
3090 static int
3091 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3092 {
3093         uint32_t rctl;
3094         struct e1000_hw *hw;
3095         struct rte_eth_dev_info dev_info;
3096         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3097                                      VLAN_TAG_SIZE);
3098
3099         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3100
3101 #ifdef RTE_LIBRTE_82571_SUPPORT
3102         /* XXX: not bigger than max_rx_pktlen */
3103         if (hw->mac.type == e1000_82571)
3104                 return -ENOTSUP;
3105 #endif
3106         eth_igb_infos_get(dev, &dev_info);
3107
3108         /* check that mtu is within the allowed range */
3109         if ((mtu < ETHER_MIN_MTU) ||
3110             (frame_size > dev_info.max_rx_pktlen))
3111                 return -EINVAL;
3112
3113         /* refuse mtu that requires the support of scattered packets when this
3114          * feature has not been enabled before. */
3115         if (!dev->data->scattered_rx &&
3116             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3117                 return -EINVAL;
3118
3119         rctl = E1000_READ_REG(hw, E1000_RCTL);
3120
3121         /* switch to jumbo mode if needed */
3122         if (frame_size > ETHER_MAX_LEN) {
3123                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3124                 rctl |= E1000_RCTL_LPE;
3125         } else {
3126                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3127                 rctl &= ~E1000_RCTL_LPE;
3128         }
3129         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3130
3131         /* update max frame size */
3132         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3133
3134         E1000_WRITE_REG(hw, E1000_RLPML,
3135                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3136
3137         return 0;
3138 }
3139
3140 static struct rte_driver pmd_igb_drv = {
3141         .type = PMD_PDEV,
3142         .init = rte_igb_pmd_init,
3143 };
3144
3145 static struct rte_driver pmd_igbvf_drv = {
3146         .type = PMD_PDEV,
3147         .init = rte_igbvf_pmd_init,
3148 };
3149
3150 PMD_REGISTER_DRIVER(pmd_igb_drv);
3151 PMD_REGISTER_DRIVER(pmd_igbvf_drv);