lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54
  55 #include "e1000_logs.h"
  56 #include "e1000/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 static int  eth_igb_configure(struct rte_eth_dev *dev);
  60 static int  eth_igb_start(struct rte_eth_dev *dev);
  61 static void eth_igb_stop(struct rte_eth_dev *dev);
  62 static void eth_igb_close(struct rte_eth_dev *dev);
  63 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  64 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  65 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  66 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  67 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  68                                 int wait_to_complete);
  69 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  70                                 struct rte_eth_stats *rte_stats);
  71 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  72 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  73                                 struct rte_eth_dev_info *dev_info);
  74 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  75                                 struct rte_eth_fc_conf *fc_conf);
  76 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  77 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  78 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  79 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  80                                                         void *param);
  81 static int  igb_hardware_init(struct e1000_hw *hw);
  82 static void igb_hw_control_acquire(struct e1000_hw *hw);
  83 static void igb_hw_control_release(struct e1000_hw *hw);
  84 static void igb_init_manageability(struct e1000_hw *hw);
  85 static void igb_release_manageability(struct e1000_hw *hw);
  86
  87 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  88                 uint16_t vlan_id, int on);
  89 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
  90 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  91
  92 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  93 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  94 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  95 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  96 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
  97 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
  98
  99 static int eth_igb_led_on(struct rte_eth_dev *dev);
 100 static int eth_igb_led_off(struct rte_eth_dev *dev);
 101
 102 static void igb_intr_disable(struct e1000_hw *hw);
 103 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 104 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 105                 struct ether_addr *mac_addr,
 106                 uint32_t index, uint32_t pool);
 107 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 108
 109 static void igbvf_intr_disable(struct e1000_hw *hw);
 110 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 111 static int igbvf_dev_start(struct rte_eth_dev *dev);
 112 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 113 static void igbvf_dev_close(struct rte_eth_dev *dev);
 114 static int eth_igbvf_link_update(struct e1000_hw *hw);
 115 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 116 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 117 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 118                 uint16_t vlan_id, int on);
 119 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 120 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 121 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 122                  struct rte_eth_rss_reta *reta_conf);
 123 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 124                 struct rte_eth_rss_reta *reta_conf);
 125
 126 /*
 127  * Define VF Stats MACRO for Non "cleared on read" register
 128  */
 129 #define UPDATE_VF_STAT(reg, last, cur)            \
 130 {                                                 \
 131         u32 latest = E1000_READ_REG(hw, reg);     \
 132         cur += latest - last;                     \
 133         last = latest;                            \
 134 }
 135
 136
 137 #define IGB_FC_PAUSE_TIME 0x0680
 138 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 139 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 140
 141 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 142
 143 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 144
 145 /*
 146  * The set of PCI devices this driver supports
 147  */
 148 static struct rte_pci_id pci_id_igb_map[] = {
 149
 150 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 151 #include "rte_pci_dev_ids.h"
 152
 153 {.device_id = 0},
 154 };
 155
 156 /*
 157  * The set of PCI devices this driver supports (for 82576&I350 VF)
 158  */
 159 static struct rte_pci_id pci_id_igbvf_map[] = {
 160
 161 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 162 #include "rte_pci_dev_ids.h"
 163
 164 {.device_id = 0},
 165 };
 166
 167 static struct eth_dev_ops eth_igb_ops = {
 168         .dev_configure        = eth_igb_configure,
 169         .dev_start            = eth_igb_start,
 170         .dev_stop             = eth_igb_stop,
 171         .dev_close            = eth_igb_close,
 172         .promiscuous_enable   = eth_igb_promiscuous_enable,
 173         .promiscuous_disable  = eth_igb_promiscuous_disable,
 174         .allmulticast_enable  = eth_igb_allmulticast_enable,
 175         .allmulticast_disable = eth_igb_allmulticast_disable,
 176         .link_update          = eth_igb_link_update,
 177         .stats_get            = eth_igb_stats_get,
 178         .stats_reset          = eth_igb_stats_reset,
 179         .dev_infos_get        = eth_igb_infos_get,
 180         .vlan_filter_set      = eth_igb_vlan_filter_set,
 181         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 182         .vlan_offload_set     = eth_igb_vlan_offload_set,
 183         .rx_queue_setup       = eth_igb_rx_queue_setup,
 184         .rx_queue_release     = eth_igb_rx_queue_release,
 185         .rx_queue_count       = eth_igb_rx_queue_count,
 186         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 187         .tx_queue_setup       = eth_igb_tx_queue_setup,
 188         .tx_queue_release     = eth_igb_tx_queue_release,
 189         .dev_led_on           = eth_igb_led_on,
 190         .dev_led_off          = eth_igb_led_off,
 191         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 192         .mac_addr_add         = eth_igb_rar_set,
 193         .mac_addr_remove      = eth_igb_rar_clear,
 194         .reta_update          = eth_igb_rss_reta_update,
 195         .reta_query           = eth_igb_rss_reta_query,
 196 };
 197
 198 /*
 199  * dev_ops for virtual function, bare necessities for basic vf
 200  * operation have been implemented
 201  */
 202 static struct eth_dev_ops igbvf_eth_dev_ops = {
 203         .dev_configure        = igbvf_dev_configure,
 204         .dev_start            = igbvf_dev_start,
 205         .dev_stop             = igbvf_dev_stop,
 206         .dev_close            = igbvf_dev_close,
 207         .link_update          = eth_igb_link_update,
 208         .stats_get            = eth_igbvf_stats_get,
 209         .stats_reset          = eth_igbvf_stats_reset,
 210         .vlan_filter_set      = igbvf_vlan_filter_set,
 211         .dev_infos_get        = eth_igb_infos_get,
 212         .rx_queue_setup       = eth_igb_rx_queue_setup,
 213         .rx_queue_release     = eth_igb_rx_queue_release,
 214         .tx_queue_setup       = eth_igb_tx_queue_setup,
 215         .tx_queue_release     = eth_igb_tx_queue_release,
 216 };
 217
 218 /**
 219  * Atomically reads the link status information from global
 220  * structure rte_eth_dev.
 221  *
 222  * @param dev
 223  *   - Pointer to the structure rte_eth_dev to read from.
 224  *   - Pointer to the buffer to be saved with the link status.
 225  *
 226  * @return
 227  *   - On success, zero.
 228  *   - On failure, negative value.
 229  */
 230 static inline int
 231 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 232                                 struct rte_eth_link *link)
 233 {
 234         struct rte_eth_link *dst = link;
 235         struct rte_eth_link *src = &(dev->data->dev_link);
 236
 237         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 238                                         *(uint64_t *)src) == 0)
 239                 return -1;
 240
 241         return 0;
 242 }
 243
 244 /**
 245  * Atomically writes the link status information into global
 246  * structure rte_eth_dev.
 247  *
 248  * @param dev
 249  *   - Pointer to the structure rte_eth_dev to read from.
 250  *   - Pointer to the buffer to be saved with the link status.
 251  *
 252  * @return
 253  *   - On success, zero.
 254  *   - On failure, negative value.
 255  */
 256 static inline int
 257 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 258                                 struct rte_eth_link *link)
 259 {
 260         struct rte_eth_link *dst = &(dev->data->dev_link);
 261         struct rte_eth_link *src = link;
 262
 263         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 264                                         *(uint64_t *)src) == 0)
 265                 return -1;
 266
 267         return 0;
 268 }
 269
 270 static inline void
 271 igb_intr_enable(struct rte_eth_dev *dev)
 272 {
 273         struct e1000_interrupt *intr =
 274                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 275         struct e1000_hw *hw =
 276                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 277
 278         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 279         E1000_WRITE_FLUSH(hw);
 280 }
 281
 282 static void
 283 igb_intr_disable(struct e1000_hw *hw)
 284 {
 285         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 286         E1000_WRITE_FLUSH(hw);
 287 }
 288
 289 static inline int32_t
 290 igb_pf_reset_hw(struct e1000_hw *hw)
 291 {
 292         uint32_t ctrl_ext;
 293         int32_t status;
 294
 295         status = e1000_reset_hw(hw);
 296
 297         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 298         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 299         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 300         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 301         E1000_WRITE_FLUSH(hw);
 302
 303         return status;
 304 }
 305
 306 static void
 307 igb_identify_hardware(struct rte_eth_dev *dev)
 308 {
 309         struct e1000_hw *hw =
 310                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 311
 312         hw->vendor_id = dev->pci_dev->id.vendor_id;
 313         hw->device_id = dev->pci_dev->id.device_id;
 314         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 315         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 316
 317         e1000_set_mac_type(hw);
 318
 319         /* need to check if it is a vf device below */
 320 }
 321
 322 static int
 323 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 324                    struct rte_eth_dev *eth_dev)
 325 {
 326         int error = 0;
 327         struct rte_pci_device *pci_dev;
 328         struct e1000_hw *hw =
 329                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 330         struct e1000_vfta * shadow_vfta =
 331                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 332         uint32_t ctrl_ext;
 333
 334         pci_dev = eth_dev->pci_dev;
 335         eth_dev->dev_ops = &eth_igb_ops;
 336         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 337         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 338
 339         /* for secondary processes, we don't initialise any further as primary
 340          * has already done this work. Only check we don't need a different
 341          * RX function */
 342         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 343                 if (eth_dev->data->scattered_rx)
 344                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 345                 return 0;
 346         }
 347
 348         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 349
 350         igb_identify_hardware(eth_dev);
 351         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 352                 error = -EIO;
 353                 goto err_late;
 354         }
 355
 356         e1000_get_bus_info(hw);
 357
 358         hw->mac.autoneg = 1;
 359         hw->phy.autoneg_wait_to_complete = 0;
 360         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 361
 362         /* Copper options */
 363         if (hw->phy.media_type == e1000_media_type_copper) {
 364                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 365                 hw->phy.disable_polarity_correction = 0;
 366                 hw->phy.ms_type = e1000_ms_hw_default;
 367         }
 368
 369         /*
 370          * Start from a known state, this is important in reading the nvm
 371          * and mac from that.
 372          */
 373         igb_pf_reset_hw(hw);
 374
 375         /* Make sure we have a good EEPROM before we read from it */
 376         if (e1000_validate_nvm_checksum(hw) < 0) {
 377                 /*
 378                  * Some PCI-E parts fail the first check due to
 379                  * the link being in sleep state, call it again,
 380                  * if it fails a second time its a real issue.
 381                  */
 382                 if (e1000_validate_nvm_checksum(hw) < 0) {
 383                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 384                         error = -EIO;
 385                         goto err_late;
 386                 }
 387         }
 388
 389         /* Read the permanent MAC address out of the EEPROM */
 390         if (e1000_read_mac_addr(hw) != 0) {
 391                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 392                 error = -EIO;
 393                 goto err_late;
 394         }
 395
 396         /* Allocate memory for storing MAC addresses */
 397         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 398                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 399         if (eth_dev->data->mac_addrs == NULL) {
 400                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 401                                                 "store MAC addresses",
 402                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 403                 error = -ENOMEM;
 404                 goto err_late;
 405         }
 406
 407         /* Copy the permanent MAC address */
 408         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 409
 410         /* initialize the vfta */
 411         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 412
 413         /* Now initialize the hardware */
 414         if (igb_hardware_init(hw) != 0) {
 415                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 416                 rte_free(eth_dev->data->mac_addrs);
 417                 eth_dev->data->mac_addrs = NULL;
 418                 error = -ENODEV;
 419                 goto err_late;
 420         }
 421         hw->mac.get_link_status = 1;
 422
 423         /* Indicate SOL/IDER usage */
 424         if (e1000_check_reset_block(hw) < 0) {
 425                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 426                                         "SOL/IDER session");
 427         }
 428
 429         /* initialize PF if max_vfs not zero */
 430         igb_pf_host_init(eth_dev);
 431
 432         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 433         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 434         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 435         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 436         E1000_WRITE_FLUSH(hw);
 437
 438         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 439                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 440                      pci_dev->id.device_id);
 441
 442         rte_intr_callback_register(&(pci_dev->intr_handle),
 443                 eth_igb_interrupt_handler, (void *)eth_dev);
 444
 445         /* enable uio intr after callback register */
 446         rte_intr_enable(&(pci_dev->intr_handle));
 447
 448         /* enable support intr */
 449         igb_intr_enable(eth_dev);
 450
 451         return 0;
 452
 453 err_late:
 454         igb_hw_control_release(hw);
 455
 456         return (error);
 457 }
 458
 459 /*
 460  * Virtual Function device init
 461  */
 462 static int
 463 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 464                 struct rte_eth_dev *eth_dev)
 465 {
 466         struct rte_pci_device *pci_dev;
 467         struct e1000_hw *hw =
 468                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 469         int diag;
 470
 471         PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 472
 473         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 474         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 475         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 476
 477         /* for secondary processes, we don't initialise any further as primary
 478          * has already done this work. Only check we don't need a different
 479          * RX function */
 480         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 481                 if (eth_dev->data->scattered_rx)
 482                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 483                 return 0;
 484         }
 485
 486         pci_dev = eth_dev->pci_dev;
 487
 488         hw->device_id = pci_dev->id.device_id;
 489         hw->vendor_id = pci_dev->id.vendor_id;
 490         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 491
 492         /* Initialize the shared code */
 493         diag = e1000_setup_init_funcs(hw, TRUE);
 494         if (diag != 0) {
 495                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 496                         diag);
 497                 return -EIO;
 498         }
 499
 500         /* init_mailbox_params */
 501         hw->mbx.ops.init_params(hw);
 502
 503         /* Disable the interrupts for VF */
 504         igbvf_intr_disable(hw);
 505
 506         diag = hw->mac.ops.reset_hw(hw);
 507
 508         /* Allocate memory for storing MAC addresses */
 509         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 510                 hw->mac.rar_entry_count, 0);
 511         if (eth_dev->data->mac_addrs == NULL) {
 512                 PMD_INIT_LOG(ERR,
 513                         "Failed to allocate %d bytes needed to store MAC "
 514                         "addresses",
 515                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 516                 return -ENOMEM;
 517         }
 518
 519         /* Copy the permanent MAC address */
 520         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 521                         &eth_dev->data->mac_addrs[0]);
 522
 523         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
 524                         "mac.type=%s\n",
 525                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 526                         pci_dev->id.device_id,
 527                         "igb_mac_82576_vf");
 528
 529         return 0;
 530 }
 531
 532 static struct eth_driver rte_igb_pmd = {
 533         {
 534                 .name = "rte_igb_pmd",
 535                 .id_table = pci_id_igb_map,
 536 #ifdef RTE_EAL_UNBIND_PORTS
 537                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 538 #endif
 539         },
 540         .eth_dev_init = eth_igb_dev_init,
 541         .dev_private_size = sizeof(struct e1000_adapter),
 542 };
 543
 544 /*
 545  * virtual function driver struct
 546  */
 547 static struct eth_driver rte_igbvf_pmd = {
 548         {
 549                 .name = "rte_igbvf_pmd",
 550                 .id_table = pci_id_igbvf_map,
 551 #ifdef RTE_EAL_UNBIND_PORTS
 552                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 553 #endif
 554         },
 555         .eth_dev_init = eth_igbvf_dev_init,
 556         .dev_private_size = sizeof(struct e1000_adapter),
 557 };
 558
 559 int
 560 rte_igb_pmd_init(void)
 561 {
 562         rte_eth_driver_register(&rte_igb_pmd);
 563         return 0;
 564 }
 565
 566 /*
 567  * VF Driver initialization routine.
 568  * Invoked one at EAL init time.
 569  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 570  */
 571 int
 572 rte_igbvf_pmd_init(void)
 573 {
 574         DEBUGFUNC("rte_igbvf_pmd_init");
 575
 576         rte_eth_driver_register(&rte_igbvf_pmd);
 577         return (0);
 578 }
 579
 580 static int
 581 eth_igb_configure(struct rte_eth_dev *dev)
 582 {
 583         struct e1000_interrupt *intr =
 584                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 585
 586         PMD_INIT_LOG(DEBUG, ">>");
 587
 588         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 589
 590         PMD_INIT_LOG(DEBUG, "<<");
 591
 592         return (0);
 593 }
 594
 595 static int
 596 eth_igb_start(struct rte_eth_dev *dev)
 597 {
 598         struct e1000_hw *hw =
 599                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 600         int ret, i, mask;
 601         uint32_t ctrl_ext;
 602
 603         PMD_INIT_LOG(DEBUG, ">>");
 604
 605         /* Power up the phy. Needed to make the link go Up */
 606         e1000_power_up_phy(hw);
 607
 608         /*
 609          * Packet Buffer Allocation (PBA)
 610          * Writing PBA sets the receive portion of the buffer
 611          * the remainder is used for the transmit buffer.
 612          */
 613         if (hw->mac.type == e1000_82575) {
 614                 uint32_t pba;
 615
 616                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 617                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 618         }
 619
 620         /* Put the address into the Receive Address Array */
 621         e1000_rar_set(hw, hw->mac.addr, 0);
 622
 623         /* Initialize the hardware */
 624         if (igb_hardware_init(hw)) {
 625                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 626                 return (-EIO);
 627         }
 628
 629         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 630
 631         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 632         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 633         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 634         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 635         E1000_WRITE_FLUSH(hw);
 636
 637         /* configure PF module if SRIOV enabled */
 638         igb_pf_host_configure(dev);
 639
 640         /* Configure for OS presence */
 641         igb_init_manageability(hw);
 642
 643         eth_igb_tx_init(dev);
 644
 645         /* This can fail when allocating mbufs for descriptor rings */
 646         ret = eth_igb_rx_init(dev);
 647         if (ret) {
 648                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 649                 igb_dev_clear_queues(dev);
 650                 return ret;
 651         }
 652
 653         e1000_clear_hw_cntrs_base_generic(hw);
 654
 655         /*
 656          * VLAN Offload Settings
 657          */
 658         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 659                         ETH_VLAN_EXTEND_MASK;
 660         eth_igb_vlan_offload_set(dev, mask);
 661
 662         /*
 663          * Configure the Interrupt Moderation register (EITR) with the maximum
 664          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 665          * spurious [DMA] memory updates of RX and TX ring descriptors.
 666          *
 667          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 668          * spurious memory updates per second should be expected.
 669          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 670          *
 671          * Because interrupts are not used at all, the MSI-X is not activated
 672          * and interrupt moderation is controlled by EITR[0].
 673          *
 674          * Note that having [almost] disabled memory updates of RX and TX ring
 675          * descriptors through the Interrupt Moderation mechanism, memory
 676          * updates of ring descriptors are now moderated by the configurable
 677          * value of Write-Back Threshold registers.
 678          */
 679         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 680                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 681                 uint32_t ivar;
 682
 683                 /* Enable all RX & TX queues in the IVAR registers */
 684                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 685                 for (i = 0; i < 8; i++)
 686                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 687
 688                 /* Configure EITR with the maximum possible value (0xFFFF) */
 689                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 690         }
 691
 692         /* Setup link speed and duplex */
 693         switch (dev->data->dev_conf.link_speed) {
 694         case ETH_LINK_SPEED_AUTONEG:
 695                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 696                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 697                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 698                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 699                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 700                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 701                 else
 702                         goto error_invalid_config;
 703                 break;
 704         case ETH_LINK_SPEED_10:
 705                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 706                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 707                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 708                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 709                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 710                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 711                 else
 712                         goto error_invalid_config;
 713                 break;
 714         case ETH_LINK_SPEED_100:
 715                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 716                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 717                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 718                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 719                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 720                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 721                 else
 722                         goto error_invalid_config;
 723                 break;
 724         case ETH_LINK_SPEED_1000:
 725                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 726                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 727                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 728                 else
 729                         goto error_invalid_config;
 730                 break;
 731         case ETH_LINK_SPEED_10000:
 732         default:
 733                 goto error_invalid_config;
 734         }
 735         e1000_setup_link(hw);
 736
 737         /* check if lsc interrupt feature is enabled */
 738         if (dev->data->dev_conf.intr_conf.lsc != 0)
 739                 ret = eth_igb_lsc_interrupt_setup(dev);
 740
 741         /* resume enabled intr since hw reset */
 742         igb_intr_enable(dev);
 743
 744         PMD_INIT_LOG(DEBUG, "<<");
 745
 746         return (0);
 747
 748 error_invalid_config:
 749         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 750                         dev->data->dev_conf.link_speed,
 751                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 752         igb_dev_clear_queues(dev);
 753         return (-EINVAL);
 754 }
 755
 756 /*********************************************************************
 757  *
 758  *  This routine disables all traffic on the adapter by issuing a
 759  *  global reset on the MAC.
 760  *
 761  **********************************************************************/
 762 static void
 763 eth_igb_stop(struct rte_eth_dev *dev)
 764 {
 765         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 766         struct rte_eth_link link;
 767
 768         igb_intr_disable(hw);
 769         igb_pf_reset_hw(hw);
 770         E1000_WRITE_REG(hw, E1000_WUC, 0);
 771
 772         /* Set bit for Go Link disconnect */
 773         if (hw->mac.type >= e1000_82580) {
 774                 uint32_t phpm_reg;
 775
 776                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 777                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 778                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 779         }
 780
 781         /* Power down the phy. Needed to make the link go Down */
 782         e1000_power_down_phy(hw);
 783
 784         igb_dev_clear_queues(dev);
 785
 786         /* clear the recorded link status */
 787         memset(&link, 0, sizeof(link));
 788         rte_igb_dev_atomic_write_link_status(dev, &link);
 789 }
 790
 791 static void
 792 eth_igb_close(struct rte_eth_dev *dev)
 793 {
 794         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 795         struct rte_eth_link link;
 796
 797         eth_igb_stop(dev);
 798         e1000_phy_hw_reset(hw);
 799         igb_release_manageability(hw);
 800         igb_hw_control_release(hw);
 801
 802         /* Clear bit for Go Link disconnect */
 803         if (hw->mac.type >= e1000_82580) {
 804                 uint32_t phpm_reg;
 805
 806                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 807                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
 808                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 809         }
 810
 811         igb_dev_clear_queues(dev);
 812
 813         memset(&link, 0, sizeof(link));
 814         rte_igb_dev_atomic_write_link_status(dev, &link);
 815 }
 816
 817 static int
 818 igb_get_rx_buffer_size(struct e1000_hw *hw)
 819 {
 820         uint32_t rx_buf_size;
 821         if (hw->mac.type == e1000_82576) {
 822                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 823         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 824                 /* PBS needs to be translated according to a lookup table */
 825                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 826                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 827                 rx_buf_size = (rx_buf_size << 10);
 828         } else if (hw->mac.type == e1000_i210) {
 829                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 830         } else {
 831                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 832         }
 833
 834         return rx_buf_size;
 835 }
 836
 837 /*********************************************************************
 838  *
 839  *  Initialize the hardware
 840  *
 841  **********************************************************************/
 842 static int
 843 igb_hardware_init(struct e1000_hw *hw)
 844 {
 845         uint32_t rx_buf_size;
 846         int diag;
 847
 848         /* Let the firmware know the OS is in control */
 849         igb_hw_control_acquire(hw);
 850
 851         /*
 852          * These parameters control the automatic generation (Tx) and
 853          * response (Rx) to Ethernet PAUSE frames.
 854          * - High water mark should allow for at least two standard size (1518)
 855          *   frames to be received after sending an XOFF.
 856          * - Low water mark works best when it is very near the high water mark.
 857          *   This allows the receiver to restart by sending XON when it has
 858          *   drained a bit. Here we use an arbitary value of 1500 which will
 859          *   restart after one full frame is pulled from the buffer. There
 860          *   could be several smaller frames in the buffer and if so they will
 861          *   not trigger the XON until their total number reduces the buffer
 862          *   by 1500.
 863          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 864          */
 865         rx_buf_size = igb_get_rx_buffer_size(hw);
 866
 867         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
 868         hw->fc.low_water = hw->fc.high_water - 1500;
 869         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
 870         hw->fc.send_xon = 1;
 871
 872         /* Set Flow control, use the tunable location if sane */
 873         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
 874                 hw->fc.requested_mode = igb_fc_setting;
 875         else
 876                 hw->fc.requested_mode = e1000_fc_none;
 877
 878         /* Issue a global reset */
 879         igb_pf_reset_hw(hw);
 880         E1000_WRITE_REG(hw, E1000_WUC, 0);
 881
 882         diag = e1000_init_hw(hw);
 883         if (diag < 0)
 884                 return (diag);
 885
 886         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 887         e1000_get_phy_info(hw);
 888         e1000_check_for_link(hw);
 889
 890         return (0);
 891 }
 892
 893 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
 894 static void
 895 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 896 {
 897         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 898         struct e1000_hw_stats *stats =
 899                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 900         int pause_frames;
 901
 902         if(hw->phy.media_type == e1000_media_type_copper ||
 903             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 904                 stats->symerrs +=
 905                     E1000_READ_REG(hw,E1000_SYMERRS);
 906                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 907         }
 908
 909         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 910         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 911         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 912         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 913
 914         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 915         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 916         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 917         stats->dc += E1000_READ_REG(hw, E1000_DC);
 918         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 919         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 920         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 921         /*
 922         ** For watchdog management we need to know if we have been
 923         ** paused during the last interval, so capture that here.
 924         */
 925         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 926         stats->xoffrxc += pause_frames;
 927         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 928         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 929         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 930         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 931         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 932         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 933         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 934         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 935         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 936         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 937         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 938         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 939
 940         /* For the 64-bit byte counters the low dword must be read first. */
 941         /* Both registers clear on the read of the high dword */
 942
 943         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 944         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 945         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 946         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 947
 948         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 949         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 950         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 951         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 952         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 953
 954         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 955         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 956
 957         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 958         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 959         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 960         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 961         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 962         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 963         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 964         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 965         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 966         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 967
 968         /* Interrupt Counts */
 969
 970         stats->iac += E1000_READ_REG(hw, E1000_IAC);
 971         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 972         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 973         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 974         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 975         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 976         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 977         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 978         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 979
 980         /* Host to Card Statistics */
 981
 982         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
 983         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
 984         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
 985         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
 986         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
 987         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
 988         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
 989         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
 990         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
 991         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
 992         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
 993         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
 994         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
 995         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
 996
 997         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 998         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 999         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1000         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1001         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1002         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1003
1004         if (rte_stats == NULL)
1005                 return;
1006
1007         /* Rx Errors */
1008         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
1009             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
1010
1011         /* Tx Errors */
1012         rte_stats->oerrors = stats->ecol + stats->latecol;
1013
1014         rte_stats->ipackets = stats->gprc;
1015         rte_stats->opackets = stats->gptc;
1016         rte_stats->ibytes   = stats->gorc;
1017         rte_stats->obytes   = stats->gotc;
1018 }
1019
1020 static void
1021 eth_igb_stats_reset(struct rte_eth_dev *dev)
1022 {
1023         struct e1000_hw_stats *hw_stats =
1024                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1025
1026         /* HW registers are cleared on read */
1027         eth_igb_stats_get(dev, NULL);
1028
1029         /* Reset software totals */
1030         memset(hw_stats, 0, sizeof(*hw_stats));
1031 }
1032
1033 static void
1034 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1035 {
1036         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1038                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1039
1040         /* Good Rx packets, include VF loopback */
1041         UPDATE_VF_STAT(E1000_VFGPRC,
1042             hw_stats->last_gprc, hw_stats->gprc);
1043
1044         /* Good Rx octets, include VF loopback */
1045         UPDATE_VF_STAT(E1000_VFGORC,
1046             hw_stats->last_gorc, hw_stats->gorc);
1047
1048         /* Good Tx packets, include VF loopback */
1049         UPDATE_VF_STAT(E1000_VFGPTC,
1050             hw_stats->last_gptc, hw_stats->gptc);
1051
1052         /* Good Tx octets, include VF loopback */
1053         UPDATE_VF_STAT(E1000_VFGOTC,
1054             hw_stats->last_gotc, hw_stats->gotc);
1055
1056         /* Rx Multicst packets */
1057         UPDATE_VF_STAT(E1000_VFMPRC,
1058             hw_stats->last_mprc, hw_stats->mprc);
1059
1060         /* Good Rx loopback packets */
1061         UPDATE_VF_STAT(E1000_VFGPRLBC,
1062             hw_stats->last_gprlbc, hw_stats->gprlbc);
1063
1064         /* Good Rx loopback octets */
1065         UPDATE_VF_STAT(E1000_VFGORLBC,
1066             hw_stats->last_gorlbc, hw_stats->gorlbc);
1067
1068         /* Good Tx loopback packets */
1069         UPDATE_VF_STAT(E1000_VFGPTLBC,
1070             hw_stats->last_gptlbc, hw_stats->gptlbc);
1071
1072         /* Good Tx loopback octets */
1073         UPDATE_VF_STAT(E1000_VFGOTLBC,
1074             hw_stats->last_gotlbc, hw_stats->gotlbc);
1075
1076         if (rte_stats == NULL)
1077                 return;
1078
1079         memset(rte_stats, 0, sizeof(*rte_stats));
1080         rte_stats->ipackets = hw_stats->gprc;
1081         rte_stats->ibytes = hw_stats->gorc;
1082         rte_stats->opackets = hw_stats->gptc;
1083         rte_stats->obytes = hw_stats->gotc;
1084         rte_stats->imcasts = hw_stats->mprc;
1085         rte_stats->ilbpackets = hw_stats->gprlbc;
1086         rte_stats->ilbbytes = hw_stats->gorlbc;
1087         rte_stats->olbpackets = hw_stats->gptlbc;
1088         rte_stats->olbbytes = hw_stats->gotlbc;
1089
1090 }
1091
1092 static void
1093 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1094 {
1095         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1096                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1097
1098         /* Sync HW register to the last stats */
1099         eth_igbvf_stats_get(dev, NULL);
1100
1101         /* reset HW current stats*/
1102         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1103                offsetof(struct e1000_vf_stats, gprc));
1104
1105 }
1106
1107 static void
1108 eth_igb_infos_get(struct rte_eth_dev *dev,
1109                     struct rte_eth_dev_info *dev_info)
1110 {
1111         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1112
1113         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1114         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1115         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1116
1117         switch (hw->mac.type) {
1118         case e1000_82575:
1119                 dev_info->max_rx_queues = 4;
1120                 dev_info->max_tx_queues = 4;
1121                 break;
1122
1123         case e1000_82576:
1124                 dev_info->max_rx_queues = 16;
1125                 dev_info->max_tx_queues = 16;
1126                 break;
1127
1128         case e1000_82580:
1129                 dev_info->max_rx_queues = 8;
1130                 dev_info->max_tx_queues = 8;
1131                 break;
1132
1133         case e1000_i350:
1134                 dev_info->max_rx_queues = 8;
1135                 dev_info->max_tx_queues = 8;
1136                 break;
1137
1138         case e1000_i210:
1139                 dev_info->max_rx_queues = 4;
1140                 dev_info->max_tx_queues = 4;
1141                 break;
1142
1143         case e1000_vfadapt:
1144                 dev_info->max_rx_queues = 2;
1145                 dev_info->max_tx_queues = 2;
1146                 break;
1147
1148         case e1000_vfadapt_i350:
1149                 dev_info->max_rx_queues = 1;
1150                 dev_info->max_tx_queues = 1;
1151                 break;
1152
1153         default:
1154                 /* Should not happen */
1155                 dev_info->max_rx_queues = 0;
1156                 dev_info->max_tx_queues = 0;
1157         }
1158 }
1159
1160 /* return 0 means link status changed, -1 means not changed */
1161 static int
1162 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1163 {
1164         struct e1000_hw *hw =
1165                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1166         struct rte_eth_link link, old;
1167         int link_check, count;
1168
1169         link_check = 0;
1170         hw->mac.get_link_status = 1;
1171
1172         /* possible wait-to-complete in up to 9 seconds */
1173         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1174                 /* Read the real link status */
1175                 switch (hw->phy.media_type) {
1176                 case e1000_media_type_copper:
1177                         /* Do the work to read phy */
1178                         e1000_check_for_link(hw);
1179                         link_check = !hw->mac.get_link_status;
1180                         break;
1181
1182                 case e1000_media_type_fiber:
1183                         e1000_check_for_link(hw);
1184                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1185                                       E1000_STATUS_LU);
1186                         break;
1187
1188                 case e1000_media_type_internal_serdes:
1189                         e1000_check_for_link(hw);
1190                         link_check = hw->mac.serdes_has_link;
1191                         break;
1192
1193                 /* VF device is type_unknown */
1194                 case e1000_media_type_unknown:
1195                         eth_igbvf_link_update(hw);
1196                         link_check = !hw->mac.get_link_status;
1197                         break;
1198
1199                 default:
1200                         break;
1201                 }
1202                 if (link_check || wait_to_complete == 0)
1203                         break;
1204                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1205         }
1206         memset(&link, 0, sizeof(link));
1207         rte_igb_dev_atomic_read_link_status(dev, &link);
1208         old = link;
1209
1210         /* Now we check if a transition has happened */
1211         if (link_check) {
1212                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1213                                           &link.link_duplex);
1214                 link.link_status = 1;
1215         } else if (!link_check) {
1216                 link.link_speed = 0;
1217                 link.link_duplex = 0;
1218                 link.link_status = 0;
1219         }
1220         rte_igb_dev_atomic_write_link_status(dev, &link);
1221
1222         /* not changed */
1223         if (old.link_status == link.link_status)
1224                 return -1;
1225
1226         /* changed */
1227         return 0;
1228 }
1229
1230 /*
1231  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1232  * For ASF and Pass Through versions of f/w this means
1233  * that the driver is loaded.
1234  */
1235 static void
1236 igb_hw_control_acquire(struct e1000_hw *hw)
1237 {
1238         uint32_t ctrl_ext;
1239
1240         /* Let firmware know the driver has taken over */
1241         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1242         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1243 }
1244
1245 /*
1246  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1247  * For ASF and Pass Through versions of f/w this means that the
1248  * driver is no longer loaded.
1249  */
1250 static void
1251 igb_hw_control_release(struct e1000_hw *hw)
1252 {
1253         uint32_t ctrl_ext;
1254
1255         /* Let firmware taken over control of h/w */
1256         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1257         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1258                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1259 }
1260
1261 /*
1262  * Bit of a misnomer, what this really means is
1263  * to enable OS management of the system... aka
1264  * to disable special hardware management features.
1265  */
1266 static void
1267 igb_init_manageability(struct e1000_hw *hw)
1268 {
1269         if (e1000_enable_mng_pass_thru(hw)) {
1270                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1271                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1272
1273                 /* disable hardware interception of ARP */
1274                 manc &= ~(E1000_MANC_ARP_EN);
1275
1276                 /* enable receiving management packets to the host */
1277                 manc |= E1000_MANC_EN_MNG2HOST;
1278                 manc2h |= 1 << 5;  /* Mng Port 623 */
1279                 manc2h |= 1 << 6;  /* Mng Port 664 */
1280                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1281                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1282         }
1283 }
1284
1285 static void
1286 igb_release_manageability(struct e1000_hw *hw)
1287 {
1288         if (e1000_enable_mng_pass_thru(hw)) {
1289                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1290
1291                 manc |= E1000_MANC_ARP_EN;
1292                 manc &= ~E1000_MANC_EN_MNG2HOST;
1293
1294                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1295         }
1296 }
1297
1298 static void
1299 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1300 {
1301         struct e1000_hw *hw =
1302                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1303         uint32_t rctl;
1304
1305         rctl = E1000_READ_REG(hw, E1000_RCTL);
1306         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1307         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1308 }
1309
1310 static void
1311 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1312 {
1313         struct e1000_hw *hw =
1314                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1315         uint32_t rctl;
1316
1317         rctl = E1000_READ_REG(hw, E1000_RCTL);
1318         rctl &= (~E1000_RCTL_UPE);
1319         if (dev->data->all_multicast == 1)
1320                 rctl |= E1000_RCTL_MPE;
1321         else
1322                 rctl &= (~E1000_RCTL_MPE);
1323         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1324 }
1325
1326 static void
1327 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1328 {
1329         struct e1000_hw *hw =
1330                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1331         uint32_t rctl;
1332
1333         rctl = E1000_READ_REG(hw, E1000_RCTL);
1334         rctl |= E1000_RCTL_MPE;
1335         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1336 }
1337
1338 static void
1339 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1340 {
1341         struct e1000_hw *hw =
1342                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1343         uint32_t rctl;
1344
1345         if (dev->data->promiscuous == 1)
1346                 return; /* must remain in all_multicast mode */
1347         rctl = E1000_READ_REG(hw, E1000_RCTL);
1348         rctl &= (~E1000_RCTL_MPE);
1349         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1350 }
1351
1352 static int
1353 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1354 {
1355         struct e1000_hw *hw =
1356                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1357         struct e1000_vfta * shadow_vfta =
1358                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1359         uint32_t vfta;
1360         uint32_t vid_idx;
1361         uint32_t vid_bit;
1362
1363         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1364                               E1000_VFTA_ENTRY_MASK);
1365         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1366         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1367         if (on)
1368                 vfta |= vid_bit;
1369         else
1370                 vfta &= ~vid_bit;
1371         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1372
1373         /* update local VFTA copy */
1374         shadow_vfta->vfta[vid_idx] = vfta;
1375
1376         return 0;
1377 }
1378
1379 static void
1380 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1381 {
1382         struct e1000_hw *hw =
1383                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1384         uint32_t reg = ETHER_TYPE_VLAN ;
1385
1386         reg |= (tpid << 16);
1387         E1000_WRITE_REG(hw, E1000_VET, reg);
1388 }
1389
1390 static void
1391 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1392 {
1393         struct e1000_hw *hw =
1394                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1395         uint32_t reg;
1396
1397         /* Filter Table Disable */
1398         reg = E1000_READ_REG(hw, E1000_RCTL);
1399         reg &= ~E1000_RCTL_CFIEN;
1400         reg &= ~E1000_RCTL_VFE;
1401         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1402 }
1403
1404 static void
1405 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1406 {
1407         struct e1000_hw *hw =
1408                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1409         struct e1000_vfta * shadow_vfta =
1410                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1411         uint32_t reg;
1412         int i;
1413
1414         /* Filter Table Enable, CFI not used for packet acceptance */
1415         reg = E1000_READ_REG(hw, E1000_RCTL);
1416         reg &= ~E1000_RCTL_CFIEN;
1417         reg |= E1000_RCTL_VFE;
1418         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1419
1420         /* restore VFTA table */
1421         for (i = 0; i < IGB_VFTA_SIZE; i++)
1422                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1423 }
1424
1425 static void
1426 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1427 {
1428         struct e1000_hw *hw =
1429                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1430         uint32_t reg;
1431
1432         /* VLAN Mode Disable */
1433         reg = E1000_READ_REG(hw, E1000_CTRL);
1434         reg &= ~E1000_CTRL_VME;
1435         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1436 }
1437
1438 static void
1439 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1440 {
1441         struct e1000_hw *hw =
1442                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1443         uint32_t reg;
1444
1445         /* VLAN Mode Enable */
1446         reg = E1000_READ_REG(hw, E1000_CTRL);
1447         reg |= E1000_CTRL_VME;
1448         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1449 }
1450
1451 static void
1452 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1453 {
1454         struct e1000_hw *hw =
1455                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1456         uint32_t reg;
1457
1458         /* CTRL_EXT: Extended VLAN */
1459         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1460         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1461         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1462
1463         /* Update maximum packet length */
1464         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1465                 E1000_WRITE_REG(hw, E1000_RLPML,
1466                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1467                                                 VLAN_TAG_SIZE);
1468 }
1469
1470 static void
1471 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1472 {
1473         struct e1000_hw *hw =
1474                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1475         uint32_t reg;
1476
1477         /* CTRL_EXT: Extended VLAN */
1478         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1479         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1480         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1481
1482         /* Update maximum packet length */
1483         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1484                 E1000_WRITE_REG(hw, E1000_RLPML,
1485                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1486                                                 2 * VLAN_TAG_SIZE);
1487 }
1488
1489 static void
1490 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1491 {
1492         if(mask & ETH_VLAN_STRIP_MASK){
1493                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1494                         igb_vlan_hw_strip_enable(dev);
1495                 else
1496                         igb_vlan_hw_strip_disable(dev);
1497         }
1498
1499         if(mask & ETH_VLAN_FILTER_MASK){
1500                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1501                         igb_vlan_hw_filter_enable(dev);
1502                 else
1503                         igb_vlan_hw_filter_disable(dev);
1504         }
1505
1506         if(mask & ETH_VLAN_EXTEND_MASK){
1507                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1508                         igb_vlan_hw_extend_enable(dev);
1509                 else
1510                         igb_vlan_hw_extend_disable(dev);
1511         }
1512 }
1513
1514
1515 /**
1516  * It enables the interrupt mask and then enable the interrupt.
1517  *
1518  * @param dev
1519  *  Pointer to struct rte_eth_dev.
1520  *
1521  * @return
1522  *  - On success, zero.
1523  *  - On failure, a negative value.
1524  */
1525 static int
1526 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1527 {
1528         struct e1000_interrupt *intr =
1529                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1530
1531         intr->mask |= E1000_ICR_LSC;
1532
1533         return 0;
1534 }
1535
1536 /*
1537  * It reads ICR and gets interrupt causes, check it and set a bit flag
1538  * to update link status.
1539  *
1540  * @param dev
1541  *  Pointer to struct rte_eth_dev.
1542  *
1543  * @return
1544  *  - On success, zero.
1545  *  - On failure, a negative value.
1546  */
1547 static int
1548 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1549 {
1550         uint32_t icr;
1551         struct e1000_hw *hw =
1552                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1553         struct e1000_interrupt *intr =
1554                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1555
1556         igb_intr_disable(hw);
1557
1558         /* read-on-clear nic registers here */
1559         icr = E1000_READ_REG(hw, E1000_ICR);
1560
1561         intr->flags = 0;
1562         if (icr & E1000_ICR_LSC) {
1563                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1564         }
1565
1566         if (icr & E1000_ICR_VMMB)
1567                 intr->flags |= E1000_FLAG_MAILBOX;
1568
1569         return 0;
1570 }
1571
1572 /*
1573  * It executes link_update after knowing an interrupt is prsent.
1574  *
1575  * @param dev
1576  *  Pointer to struct rte_eth_dev.
1577  *
1578  * @return
1579  *  - On success, zero.
1580  *  - On failure, a negative value.
1581  */
1582 static int
1583 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1584 {
1585         struct e1000_hw *hw =
1586                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1587         struct e1000_interrupt *intr =
1588                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1589         uint32_t tctl, rctl;
1590         struct rte_eth_link link;
1591         int ret;
1592
1593         if (intr->flags & E1000_FLAG_MAILBOX) {
1594                 igb_pf_mbx_process(dev);
1595                 intr->flags &= ~E1000_FLAG_MAILBOX;
1596         }
1597
1598         igb_intr_enable(dev);
1599         rte_intr_enable(&(dev->pci_dev->intr_handle));
1600
1601         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1602                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1603
1604                 /* set get_link_status to check register later */
1605                 hw->mac.get_link_status = 1;
1606                 ret = eth_igb_link_update(dev, 0);
1607
1608                 /* check if link has changed */
1609                 if (ret < 0)
1610                         return 0;
1611
1612                 memset(&link, 0, sizeof(link));
1613                 rte_igb_dev_atomic_read_link_status(dev, &link);
1614                 if (link.link_status) {
1615                         PMD_INIT_LOG(INFO,
1616                                 " Port %d: Link Up - speed %u Mbps - %s\n",
1617                                 dev->data->port_id, (unsigned)link.link_speed,
1618                                 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1619                                         "full-duplex" : "half-duplex");
1620                 } else {
1621                         PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1622                                                 dev->data->port_id);
1623                 }
1624                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1625                                         dev->pci_dev->addr.domain,
1626                                         dev->pci_dev->addr.bus,
1627                                         dev->pci_dev->addr.devid,
1628                                         dev->pci_dev->addr.function);
1629                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1630                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1631                 if (link.link_status) {
1632                         /* enable Tx/Rx */
1633                         tctl |= E1000_TCTL_EN;
1634                         rctl |= E1000_RCTL_EN;
1635                 } else {
1636                         /* disable Tx/Rx */
1637                         tctl &= ~E1000_TCTL_EN;
1638                         rctl &= ~E1000_RCTL_EN;
1639                 }
1640                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1641                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1642                 E1000_WRITE_FLUSH(hw);
1643                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1644         }
1645
1646         return 0;
1647 }
1648
1649 /**
1650  * Interrupt handler which shall be registered at first.
1651  *
1652  * @param handle
1653  *  Pointer to interrupt handle.
1654  * @param param
1655  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1656  *
1657  * @return
1658  *  void
1659  */
1660 static void
1661 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1662                                                         void *param)
1663 {
1664         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1665
1666         eth_igb_interrupt_get_status(dev);
1667         eth_igb_interrupt_action(dev);
1668 }
1669
1670 static int
1671 eth_igb_led_on(struct rte_eth_dev *dev)
1672 {
1673         struct e1000_hw *hw;
1674
1675         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1676         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1677 }
1678
1679 static int
1680 eth_igb_led_off(struct rte_eth_dev *dev)
1681 {
1682         struct e1000_hw *hw;
1683
1684         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1686 }
1687
1688 static int
1689 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1690 {
1691         struct e1000_hw *hw;
1692         int err;
1693         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1694                 e1000_fc_none,
1695                 e1000_fc_rx_pause,
1696                 e1000_fc_tx_pause,
1697                 e1000_fc_full
1698         };
1699         uint32_t rx_buf_size;
1700         uint32_t max_high_water;
1701
1702         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1703         rx_buf_size = igb_get_rx_buffer_size(hw);
1704         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1705
1706         /* At least reserve one Ethernet frame for watermark */
1707         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1708         if ((fc_conf->high_water > max_high_water) ||
1709                 (fc_conf->high_water < fc_conf->low_water)) {
1710                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1711                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1712                 return (-EINVAL);
1713         }
1714
1715         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1716         hw->fc.pause_time     = fc_conf->pause_time;
1717         hw->fc.high_water     = fc_conf->high_water;
1718         hw->fc.low_water      = fc_conf->low_water;
1719         hw->fc.send_xon       = fc_conf->send_xon;
1720
1721         err = e1000_setup_link_generic(hw);
1722         if (err == E1000_SUCCESS) {
1723                 return 0;
1724         }
1725
1726         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1727         return (-EIO);
1728 }
1729
1730 #define E1000_RAH_POOLSEL_SHIFT      (18)
1731 static void
1732 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1733                 uint32_t index, __rte_unused uint32_t pool)
1734 {
1735         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1736         uint32_t rah;
1737
1738         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1739         rah = E1000_READ_REG(hw, E1000_RAH(index));
1740         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
1741         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
1742 }
1743
1744 static void
1745 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1746 {
1747         uint8_t addr[ETHER_ADDR_LEN];
1748         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1749
1750         memset(addr, 0, sizeof(addr));
1751
1752         e1000_rar_set(hw, addr, index);
1753 }
1754
1755 /*
1756  * Virtual Function operations
1757  */
1758 static void
1759 igbvf_intr_disable(struct e1000_hw *hw)
1760 {
1761         PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1762
1763         /* Clear interrupt mask to stop from interrupts being generated */
1764         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
1765
1766         E1000_WRITE_FLUSH(hw);
1767 }
1768
1769 static void
1770 igbvf_stop_adapter(struct rte_eth_dev *dev)
1771 {
1772         u32 reg_val;
1773         u16 i;
1774         struct rte_eth_dev_info dev_info;
1775         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1776
1777         memset(&dev_info, 0, sizeof(dev_info));
1778         eth_igb_infos_get(dev, &dev_info);
1779
1780         /* Clear interrupt mask to stop from interrupts being generated */
1781         igbvf_intr_disable(hw);
1782
1783         /* Clear any pending interrupts, flush previous writes */
1784         E1000_READ_REG(hw, E1000_EICR);
1785
1786         /* Disable the transmit unit.  Each queue must be disabled. */
1787         for (i = 0; i < dev_info.max_tx_queues; i++)
1788                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1789
1790         /* Disable the receive unit by stopping each queue */
1791         for (i = 0; i < dev_info.max_rx_queues; i++) {
1792                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1793                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1794                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1795                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1796                         ;
1797         }
1798
1799         /* flush all queues disables */
1800         E1000_WRITE_FLUSH(hw);
1801         msec_delay(2);
1802 }
1803
1804 static int eth_igbvf_link_update(struct e1000_hw *hw)
1805 {
1806         struct e1000_mbx_info *mbx = &hw->mbx;
1807         struct e1000_mac_info *mac = &hw->mac;
1808         int ret_val = E1000_SUCCESS;
1809
1810         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1811
1812         /*
1813          * We only want to run this if there has been a rst asserted.
1814          * in this case that could mean a link change, device reset,
1815          * or a virtual function reset
1816          */
1817
1818         /* If we were hit with a reset or timeout drop the link */
1819         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1820                 mac->get_link_status = TRUE;
1821
1822         if (!mac->get_link_status)
1823                 goto out;
1824
1825         /* if link status is down no point in checking to see if pf is up */
1826         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1827                 goto out;
1828
1829         /* if we passed all the tests above then the link is up and we no
1830          * longer need to check for link */
1831         mac->get_link_status = FALSE;
1832
1833 out:
1834         return ret_val;
1835 }
1836
1837
1838 static int
1839 igbvf_dev_configure(struct rte_eth_dev *dev)
1840 {
1841         struct rte_eth_conf* conf = &dev->data->dev_conf;
1842
1843         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1844                 dev->data->port_id);
1845
1846         /*
1847          * VF has no ability to enable/disable HW CRC
1848          * Keep the persistent behavior the same as Host PF
1849          */
1850 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1851         if (!conf->rxmode.hw_strip_crc) {
1852                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1853                 conf->rxmode.hw_strip_crc = 1;
1854         }
1855 #else
1856         if (conf->rxmode.hw_strip_crc) {
1857                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1858                 conf->rxmode.hw_strip_crc = 0;
1859         }
1860 #endif
1861
1862         return 0;
1863 }
1864
1865 static int
1866 igbvf_dev_start(struct rte_eth_dev *dev)
1867 {
1868         struct e1000_hw *hw =
1869                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870         int ret;
1871
1872         PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1873
1874         hw->mac.ops.reset_hw(hw);
1875
1876         /* Set all vfta */
1877         igbvf_set_vfta_all(dev,1);
1878
1879         eth_igbvf_tx_init(dev);
1880
1881         /* This can fail when allocating mbufs for descriptor rings */
1882         ret = eth_igbvf_rx_init(dev);
1883         if (ret) {
1884                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1885                 igb_dev_clear_queues(dev);
1886                 return ret;
1887         }
1888
1889         return 0;
1890 }
1891
1892 static void
1893 igbvf_dev_stop(struct rte_eth_dev *dev)
1894 {
1895         PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1896
1897         igbvf_stop_adapter(dev);
1898
1899         /*
1900           * Clear what we set, but we still keep shadow_vfta to
1901           * restore after device starts
1902           */
1903         igbvf_set_vfta_all(dev,0);
1904
1905         igb_dev_clear_queues(dev);
1906 }
1907
1908 static void
1909 igbvf_dev_close(struct rte_eth_dev *dev)
1910 {
1911         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1912
1913         PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1914
1915         e1000_reset_hw(hw);
1916
1917         igbvf_dev_stop(dev);
1918 }
1919
1920 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1921 {
1922         struct e1000_mbx_info *mbx = &hw->mbx;
1923         uint32_t msgbuf[2];
1924
1925         /* After set vlan, vlan strip will also be enabled in igb driver*/
1926         msgbuf[0] = E1000_VF_SET_VLAN;
1927         msgbuf[1] = vid;
1928         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1929         if (on)
1930                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1931
1932         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1933 }
1934
1935 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1936 {
1937         struct e1000_hw *hw =
1938                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939         struct e1000_vfta * shadow_vfta =
1940                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1941         int i = 0, j = 0, vfta = 0, mask = 1;
1942
1943         for (i = 0; i < IGB_VFTA_SIZE; i++){
1944                 vfta = shadow_vfta->vfta[i];
1945                 if(vfta){
1946                         mask = 1;
1947                         for (j = 0; j < 32; j++){
1948                                 if(vfta & mask)
1949                                         igbvf_set_vfta(hw,
1950                                                 (uint16_t)((i<<5)+j), on);
1951                                 mask<<=1;
1952                         }
1953                 }
1954         }
1955
1956 }
1957
1958 static int
1959 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1960 {
1961         struct e1000_hw *hw =
1962                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1963         struct e1000_vfta * shadow_vfta =
1964                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1965         uint32_t vid_idx = 0;
1966         uint32_t vid_bit = 0;
1967         int ret = 0;
1968
1969         PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
1970
1971         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
1972         ret = igbvf_set_vfta(hw, vlan_id, !!on);
1973         if(ret){
1974                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
1975                 return ret;
1976         }
1977         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1978         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1979
1980         /*Save what we set and retore it after device reset*/
1981         if (on)
1982                 shadow_vfta->vfta[vid_idx] |= vid_bit;
1983         else
1984                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
1985
1986         return 0;
1987 }
1988
1989 static int
1990 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
1991                                 struct rte_eth_rss_reta *reta_conf)
1992 {
1993         uint8_t i,j,mask;
1994         uint32_t reta;
1995         struct e1000_hw *hw =
1996                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1997
1998         /*
1999          * Update Redirection Table RETA[n],n=0...31,The redirection table has
2000          * 128-entries in 32 registers
2001          */
2002         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2003                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2004                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2005                 else
2006                         mask = (uint8_t)((reta_conf->mask_hi >>
2007                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2008                 if (mask != 0) {
2009                         reta = 0;
2010                         /* If all 4 entries were set,don't need read RETA register */
2011                         if (mask != 0xF)
2012                                 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2013
2014                         for (j = 0; j < 4; j++) {
2015                                 if (mask & (0x1 << j)) {
2016                                         if (mask != 0xF)
2017                                                 reta &= ~(0xFF << 8 * j);
2018                                         reta |= reta_conf->reta[i + j] << 8 * j;
2019                                 }
2020                         }
2021                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2022                 }
2023         }
2024
2025         return 0;
2026 }
2027
2028 static int
2029 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2030                                 struct rte_eth_rss_reta *reta_conf)
2031 {
2032         uint8_t i,j,mask;
2033         uint32_t reta;
2034         struct e1000_hw *hw =
2035                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2036
2037         /*
2038          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2039          * 128-entries in 32 registers
2040          */
2041         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2042                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2043                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2044                 else
2045                         mask = (uint8_t)((reta_conf->mask_hi >>
2046                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2047
2048                 if (mask != 0) {
2049                         reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2050                         for (j = 0; j < 4; j++) {
2051                                 if (mask & (0x1 << j))
2052                                         reta_conf->reta[i + j] =
2053                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2054                         }
2055                 }
2056         }
2057
2058         return 0;
2059 }