lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 static int  eth_igb_configure(struct rte_eth_dev *dev);
  61 static int  eth_igb_start(struct rte_eth_dev *dev);
  62 static void eth_igb_stop(struct rte_eth_dev *dev);
  63 static void eth_igb_close(struct rte_eth_dev *dev);
  64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  68 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  69                                 int wait_to_complete);
  70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  71                                 struct rte_eth_stats *rte_stats);
  72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  74                                 struct rte_eth_dev_info *dev_info);
  75 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
  76                                 struct rte_eth_fc_conf *fc_conf);
  77 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  78                                 struct rte_eth_fc_conf *fc_conf);
  79 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  80 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  81 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  82 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  83                                                         void *param);
  84 static int  igb_hardware_init(struct e1000_hw *hw);
  85 static void igb_hw_control_acquire(struct e1000_hw *hw);
  86 static void igb_hw_control_release(struct e1000_hw *hw);
  87 static void igb_init_manageability(struct e1000_hw *hw);
  88 static void igb_release_manageability(struct e1000_hw *hw);
  89
  90 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  91
  92 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  93                 uint16_t vlan_id, int on);
  94 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
  95 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  96
  97 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  98 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  99 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 100 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 101 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 102 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 103
 104 static int eth_igb_led_on(struct rte_eth_dev *dev);
 105 static int eth_igb_led_off(struct rte_eth_dev *dev);
 106
 107 static void igb_intr_disable(struct e1000_hw *hw);
 108 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 109 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 110                 struct ether_addr *mac_addr,
 111                 uint32_t index, uint32_t pool);
 112 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 113
 114 static void igbvf_intr_disable(struct e1000_hw *hw);
 115 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 116 static int igbvf_dev_start(struct rte_eth_dev *dev);
 117 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 118 static void igbvf_dev_close(struct rte_eth_dev *dev);
 119 static int eth_igbvf_link_update(struct e1000_hw *hw);
 120 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 121 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 122 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 123                 uint16_t vlan_id, int on);
 124 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 125 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 126 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 127                  struct rte_eth_rss_reta *reta_conf);
 128 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 129                 struct rte_eth_rss_reta *reta_conf);
 130
 131 static int eth_igb_add_syn_filter(struct rte_eth_dev *dev,
 132                         struct rte_syn_filter *filter, uint16_t rx_queue);
 133 static int eth_igb_remove_syn_filter(struct rte_eth_dev *dev);
 134 static int eth_igb_get_syn_filter(struct rte_eth_dev *dev,
 135                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 136 static int eth_igb_add_ethertype_filter(struct rte_eth_dev *dev,
 137                         uint16_t index,
 138                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 139 static int eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev,
 140                         uint16_t index);
 141 static int eth_igb_get_ethertype_filter(struct rte_eth_dev *dev,
 142                         uint16_t index,
 143                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 144 static int eth_igb_add_2tuple_filter(struct rte_eth_dev *dev,
 145                         uint16_t index,
 146                         struct rte_2tuple_filter *filter, uint16_t rx_queue);
 147 static int eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 148                         uint16_t index);
 149 static int eth_igb_get_2tuple_filter(struct rte_eth_dev *dev,
 150                         uint16_t index,
 151                         struct rte_2tuple_filter *filter, uint16_t *rx_queue);
 152 static int eth_igb_add_flex_filter(struct rte_eth_dev *dev,
 153                         uint16_t index,
 154                         struct rte_flex_filter *filter, uint16_t rx_queue);
 155 static int eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
 156                         uint16_t index);
 157 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 158                         uint16_t index,
 159                         struct rte_flex_filter *filter, uint16_t *rx_queue);
 160 static int eth_igb_add_5tuple_filter(struct rte_eth_dev *dev,
 161                         uint16_t index,
 162                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 163 static int eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
 164                         uint16_t index);
 165 static int eth_igb_get_5tuple_filter(struct rte_eth_dev *dev,
 166                         uint16_t index,
 167                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 168
 169 /*
 170  * Define VF Stats MACRO for Non "cleared on read" register
 171  */
 172 #define UPDATE_VF_STAT(reg, last, cur)            \
 173 {                                                 \
 174         u32 latest = E1000_READ_REG(hw, reg);     \
 175         cur += latest - last;                     \
 176         last = latest;                            \
 177 }
 178
 179
 180 #define IGB_FC_PAUSE_TIME 0x0680
 181 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 182 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 183
 184 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 185
 186 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 187
 188 /*
 189  * The set of PCI devices this driver supports
 190  */
 191 static struct rte_pci_id pci_id_igb_map[] = {
 192
 193 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 194 #include "rte_pci_dev_ids.h"
 195
 196 {.device_id = 0},
 197 };
 198
 199 /*
 200  * The set of PCI devices this driver supports (for 82576&I350 VF)
 201  */
 202 static struct rte_pci_id pci_id_igbvf_map[] = {
 203
 204 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 205 #include "rte_pci_dev_ids.h"
 206
 207 {.device_id = 0},
 208 };
 209
 210 static struct eth_dev_ops eth_igb_ops = {
 211         .dev_configure        = eth_igb_configure,
 212         .dev_start            = eth_igb_start,
 213         .dev_stop             = eth_igb_stop,
 214         .dev_close            = eth_igb_close,
 215         .promiscuous_enable   = eth_igb_promiscuous_enable,
 216         .promiscuous_disable  = eth_igb_promiscuous_disable,
 217         .allmulticast_enable  = eth_igb_allmulticast_enable,
 218         .allmulticast_disable = eth_igb_allmulticast_disable,
 219         .link_update          = eth_igb_link_update,
 220         .stats_get            = eth_igb_stats_get,
 221         .stats_reset          = eth_igb_stats_reset,
 222         .dev_infos_get        = eth_igb_infos_get,
 223         .mtu_set              = eth_igb_mtu_set,
 224         .vlan_filter_set      = eth_igb_vlan_filter_set,
 225         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 226         .vlan_offload_set     = eth_igb_vlan_offload_set,
 227         .rx_queue_setup       = eth_igb_rx_queue_setup,
 228         .rx_queue_release     = eth_igb_rx_queue_release,
 229         .rx_queue_count       = eth_igb_rx_queue_count,
 230         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 231         .tx_queue_setup       = eth_igb_tx_queue_setup,
 232         .tx_queue_release     = eth_igb_tx_queue_release,
 233         .dev_led_on           = eth_igb_led_on,
 234         .dev_led_off          = eth_igb_led_off,
 235         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 236         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 237         .mac_addr_add         = eth_igb_rar_set,
 238         .mac_addr_remove      = eth_igb_rar_clear,
 239         .reta_update          = eth_igb_rss_reta_update,
 240         .reta_query           = eth_igb_rss_reta_query,
 241         .rss_hash_update      = eth_igb_rss_hash_update,
 242         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 243         .add_syn_filter          = eth_igb_add_syn_filter,
 244         .remove_syn_filter       = eth_igb_remove_syn_filter,
 245         .get_syn_filter          = eth_igb_get_syn_filter,
 246         .add_ethertype_filter    = eth_igb_add_ethertype_filter,
 247         .remove_ethertype_filter = eth_igb_remove_ethertype_filter,
 248         .get_ethertype_filter    = eth_igb_get_ethertype_filter,
 249         .add_2tuple_filter       = eth_igb_add_2tuple_filter,
 250         .remove_2tuple_filter    = eth_igb_remove_2tuple_filter,
 251         .get_2tuple_filter       = eth_igb_get_2tuple_filter,
 252         .add_flex_filter         = eth_igb_add_flex_filter,
 253         .remove_flex_filter      = eth_igb_remove_flex_filter,
 254         .get_flex_filter         = eth_igb_get_flex_filter,
 255         .add_5tuple_filter       = eth_igb_add_5tuple_filter,
 256         .remove_5tuple_filter    = eth_igb_remove_5tuple_filter,
 257         .get_5tuple_filter       = eth_igb_get_5tuple_filter,
 258 };
 259
 260 /*
 261  * dev_ops for virtual function, bare necessities for basic vf
 262  * operation have been implemented
 263  */
 264 static struct eth_dev_ops igbvf_eth_dev_ops = {
 265         .dev_configure        = igbvf_dev_configure,
 266         .dev_start            = igbvf_dev_start,
 267         .dev_stop             = igbvf_dev_stop,
 268         .dev_close            = igbvf_dev_close,
 269         .link_update          = eth_igb_link_update,
 270         .stats_get            = eth_igbvf_stats_get,
 271         .stats_reset          = eth_igbvf_stats_reset,
 272         .vlan_filter_set      = igbvf_vlan_filter_set,
 273         .dev_infos_get        = eth_igb_infos_get,
 274         .rx_queue_setup       = eth_igb_rx_queue_setup,
 275         .rx_queue_release     = eth_igb_rx_queue_release,
 276         .tx_queue_setup       = eth_igb_tx_queue_setup,
 277         .tx_queue_release     = eth_igb_tx_queue_release,
 278 };
 279
 280 /**
 281  * Atomically reads the link status information from global
 282  * structure rte_eth_dev.
 283  *
 284  * @param dev
 285  *   - Pointer to the structure rte_eth_dev to read from.
 286  *   - Pointer to the buffer to be saved with the link status.
 287  *
 288  * @return
 289  *   - On success, zero.
 290  *   - On failure, negative value.
 291  */
 292 static inline int
 293 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 294                                 struct rte_eth_link *link)
 295 {
 296         struct rte_eth_link *dst = link;
 297         struct rte_eth_link *src = &(dev->data->dev_link);
 298
 299         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 300                                         *(uint64_t *)src) == 0)
 301                 return -1;
 302
 303         return 0;
 304 }
 305
 306 /**
 307  * Atomically writes the link status information into global
 308  * structure rte_eth_dev.
 309  *
 310  * @param dev
 311  *   - Pointer to the structure rte_eth_dev to read from.
 312  *   - Pointer to the buffer to be saved with the link status.
 313  *
 314  * @return
 315  *   - On success, zero.
 316  *   - On failure, negative value.
 317  */
 318 static inline int
 319 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 320                                 struct rte_eth_link *link)
 321 {
 322         struct rte_eth_link *dst = &(dev->data->dev_link);
 323         struct rte_eth_link *src = link;
 324
 325         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 326                                         *(uint64_t *)src) == 0)
 327                 return -1;
 328
 329         return 0;
 330 }
 331
 332 static inline void
 333 igb_intr_enable(struct rte_eth_dev *dev)
 334 {
 335         struct e1000_interrupt *intr =
 336                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 337         struct e1000_hw *hw =
 338                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 339
 340         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 341         E1000_WRITE_FLUSH(hw);
 342 }
 343
 344 static void
 345 igb_intr_disable(struct e1000_hw *hw)
 346 {
 347         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 348         E1000_WRITE_FLUSH(hw);
 349 }
 350
 351 static inline int32_t
 352 igb_pf_reset_hw(struct e1000_hw *hw)
 353 {
 354         uint32_t ctrl_ext;
 355         int32_t status;
 356
 357         status = e1000_reset_hw(hw);
 358
 359         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 360         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 361         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 362         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 363         E1000_WRITE_FLUSH(hw);
 364
 365         return status;
 366 }
 367
 368 static void
 369 igb_identify_hardware(struct rte_eth_dev *dev)
 370 {
 371         struct e1000_hw *hw =
 372                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 373
 374         hw->vendor_id = dev->pci_dev->id.vendor_id;
 375         hw->device_id = dev->pci_dev->id.device_id;
 376         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 377         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 378
 379         e1000_set_mac_type(hw);
 380
 381         /* need to check if it is a vf device below */
 382 }
 383
 384 static int
 385 igb_reset_swfw_lock(struct e1000_hw *hw)
 386 {
 387         int ret_val;
 388
 389         /*
 390          * Do mac ops initialization manually here, since we will need
 391          * some function pointers set by this call.
 392          */
 393         ret_val = e1000_init_mac_params(hw);
 394         if (ret_val)
 395                 return ret_val;
 396
 397         /*
 398          * SMBI lock should not fail in this early stage. If this is the case,
 399          * it is due to an improper exit of the application.
 400          * So force the release of the faulty lock.
 401          */
 402         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 403                 DEBUGOUT("SMBI lock released");
 404         }
 405         e1000_put_hw_semaphore_generic(hw);
 406
 407         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 408                 uint16_t mask;
 409
 410                 /*
 411                  * Phy lock should not fail in this early stage. If this is the case,
 412                  * it is due to an improper exit of the application.
 413                  * So force the release of the faulty lock.
 414                  */
 415                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 416                 if (hw->bus.func > E1000_FUNC_1)
 417                         mask <<= 2;
 418                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 419                         DEBUGOUT1("SWFW phy%d lock released", hw->bus.func);
 420                 }
 421                 hw->mac.ops.release_swfw_sync(hw, mask);
 422
 423                 /*
 424                  * This one is more tricky since it is common to all ports; but
 425                  * swfw_sync retries last long enough (1s) to be almost sure that if
 426                  * lock can not be taken it is due to an improper lock of the
 427                  * semaphore.
 428                  */
 429                 mask = E1000_SWFW_EEP_SM;
 430                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 431                         DEBUGOUT("SWFW common locks released");
 432                 }
 433                 hw->mac.ops.release_swfw_sync(hw, mask);
 434         }
 435
 436         return E1000_SUCCESS;
 437 }
 438
 439 static int
 440 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 441                    struct rte_eth_dev *eth_dev)
 442 {
 443         int error = 0;
 444         struct rte_pci_device *pci_dev;
 445         struct e1000_hw *hw =
 446                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 447         struct e1000_vfta * shadow_vfta =
 448                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 449         uint32_t ctrl_ext;
 450
 451         pci_dev = eth_dev->pci_dev;
 452         eth_dev->dev_ops = &eth_igb_ops;
 453         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 454         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 455
 456         /* for secondary processes, we don't initialise any further as primary
 457          * has already done this work. Only check we don't need a different
 458          * RX function */
 459         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 460                 if (eth_dev->data->scattered_rx)
 461                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 462                 return 0;
 463         }
 464
 465         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 466
 467         igb_identify_hardware(eth_dev);
 468         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 469                 error = -EIO;
 470                 goto err_late;
 471         }
 472
 473         e1000_get_bus_info(hw);
 474
 475         /* Reset any pending lock */
 476         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 477                 error = -EIO;
 478                 goto err_late;
 479         }
 480
 481         /* Finish initialization */
 482         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 483                 error = -EIO;
 484                 goto err_late;
 485         }
 486
 487         hw->mac.autoneg = 1;
 488         hw->phy.autoneg_wait_to_complete = 0;
 489         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 490
 491         /* Copper options */
 492         if (hw->phy.media_type == e1000_media_type_copper) {
 493                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 494                 hw->phy.disable_polarity_correction = 0;
 495                 hw->phy.ms_type = e1000_ms_hw_default;
 496         }
 497
 498         /*
 499          * Start from a known state, this is important in reading the nvm
 500          * and mac from that.
 501          */
 502         igb_pf_reset_hw(hw);
 503
 504         /* Make sure we have a good EEPROM before we read from it */
 505         if (e1000_validate_nvm_checksum(hw) < 0) {
 506                 /*
 507                  * Some PCI-E parts fail the first check due to
 508                  * the link being in sleep state, call it again,
 509                  * if it fails a second time its a real issue.
 510                  */
 511                 if (e1000_validate_nvm_checksum(hw) < 0) {
 512                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 513                         error = -EIO;
 514                         goto err_late;
 515                 }
 516         }
 517
 518         /* Read the permanent MAC address out of the EEPROM */
 519         if (e1000_read_mac_addr(hw) != 0) {
 520                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 521                 error = -EIO;
 522                 goto err_late;
 523         }
 524
 525         /* Allocate memory for storing MAC addresses */
 526         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 527                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 528         if (eth_dev->data->mac_addrs == NULL) {
 529                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 530                                                 "store MAC addresses",
 531                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 532                 error = -ENOMEM;
 533                 goto err_late;
 534         }
 535
 536         /* Copy the permanent MAC address */
 537         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 538
 539         /* initialize the vfta */
 540         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 541
 542         /* Now initialize the hardware */
 543         if (igb_hardware_init(hw) != 0) {
 544                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 545                 rte_free(eth_dev->data->mac_addrs);
 546                 eth_dev->data->mac_addrs = NULL;
 547                 error = -ENODEV;
 548                 goto err_late;
 549         }
 550         hw->mac.get_link_status = 1;
 551
 552         /* Indicate SOL/IDER usage */
 553         if (e1000_check_reset_block(hw) < 0) {
 554                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 555                                         "SOL/IDER session");
 556         }
 557
 558         /* initialize PF if max_vfs not zero */
 559         igb_pf_host_init(eth_dev);
 560
 561         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 562         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 563         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 564         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 565         E1000_WRITE_FLUSH(hw);
 566
 567         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 568                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 569                      pci_dev->id.device_id);
 570
 571         rte_intr_callback_register(&(pci_dev->intr_handle),
 572                 eth_igb_interrupt_handler, (void *)eth_dev);
 573
 574         /* enable uio intr after callback register */
 575         rte_intr_enable(&(pci_dev->intr_handle));
 576
 577         /* enable support intr */
 578         igb_intr_enable(eth_dev);
 579
 580         return 0;
 581
 582 err_late:
 583         igb_hw_control_release(hw);
 584
 585         return (error);
 586 }
 587
 588 /*
 589  * Virtual Function device init
 590  */
 591 static int
 592 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 593                 struct rte_eth_dev *eth_dev)
 594 {
 595         struct rte_pci_device *pci_dev;
 596         struct e1000_hw *hw =
 597                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 598         int diag;
 599
 600         PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 601
 602         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 603         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 604         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 605
 606         /* for secondary processes, we don't initialise any further as primary
 607          * has already done this work. Only check we don't need a different
 608          * RX function */
 609         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 610                 if (eth_dev->data->scattered_rx)
 611                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 612                 return 0;
 613         }
 614
 615         pci_dev = eth_dev->pci_dev;
 616
 617         hw->device_id = pci_dev->id.device_id;
 618         hw->vendor_id = pci_dev->id.vendor_id;
 619         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 620
 621         /* Initialize the shared code (base driver) */
 622         diag = e1000_setup_init_funcs(hw, TRUE);
 623         if (diag != 0) {
 624                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 625                         diag);
 626                 return -EIO;
 627         }
 628
 629         /* init_mailbox_params */
 630         hw->mbx.ops.init_params(hw);
 631
 632         /* Disable the interrupts for VF */
 633         igbvf_intr_disable(hw);
 634
 635         diag = hw->mac.ops.reset_hw(hw);
 636
 637         /* Allocate memory for storing MAC addresses */
 638         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 639                 hw->mac.rar_entry_count, 0);
 640         if (eth_dev->data->mac_addrs == NULL) {
 641                 PMD_INIT_LOG(ERR,
 642                         "Failed to allocate %d bytes needed to store MAC "
 643                         "addresses",
 644                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 645                 return -ENOMEM;
 646         }
 647
 648         /* Copy the permanent MAC address */
 649         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 650                         &eth_dev->data->mac_addrs[0]);
 651
 652         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
 653                         "mac.type=%s\n",
 654                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 655                         pci_dev->id.device_id,
 656                         "igb_mac_82576_vf");
 657
 658         return 0;
 659 }
 660
 661 static struct eth_driver rte_igb_pmd = {
 662         {
 663                 .name = "rte_igb_pmd",
 664                 .id_table = pci_id_igb_map,
 665                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 666         },
 667         .eth_dev_init = eth_igb_dev_init,
 668         .dev_private_size = sizeof(struct e1000_adapter),
 669 };
 670
 671 /*
 672  * virtual function driver struct
 673  */
 674 static struct eth_driver rte_igbvf_pmd = {
 675         {
 676                 .name = "rte_igbvf_pmd",
 677                 .id_table = pci_id_igbvf_map,
 678                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 679         },
 680         .eth_dev_init = eth_igbvf_dev_init,
 681         .dev_private_size = sizeof(struct e1000_adapter),
 682 };
 683
 684 static int
 685 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 686 {
 687         rte_eth_driver_register(&rte_igb_pmd);
 688         return 0;
 689 }
 690
 691 static void
 692 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 693 {
 694         struct e1000_hw *hw =
 695                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 696         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 697         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 698         rctl |= E1000_RCTL_VFE;
 699         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 700 }
 701
 702 /*
 703  * VF Driver initialization routine.
 704  * Invoked one at EAL init time.
 705  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 706  */
 707 static int
 708 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 709 {
 710         DEBUGFUNC("rte_igbvf_pmd_init");
 711
 712         rte_eth_driver_register(&rte_igbvf_pmd);
 713         return (0);
 714 }
 715
 716 static int
 717 eth_igb_configure(struct rte_eth_dev *dev)
 718 {
 719         struct e1000_interrupt *intr =
 720                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 721
 722         PMD_INIT_LOG(DEBUG, ">>");
 723
 724         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 725
 726         PMD_INIT_LOG(DEBUG, "<<");
 727
 728         return (0);
 729 }
 730
 731 static int
 732 eth_igb_start(struct rte_eth_dev *dev)
 733 {
 734         struct e1000_hw *hw =
 735                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 736         int ret, i, mask;
 737         uint32_t ctrl_ext;
 738
 739         PMD_INIT_LOG(DEBUG, ">>");
 740
 741         /* Power up the phy. Needed to make the link go Up */
 742         e1000_power_up_phy(hw);
 743
 744         /*
 745          * Packet Buffer Allocation (PBA)
 746          * Writing PBA sets the receive portion of the buffer
 747          * the remainder is used for the transmit buffer.
 748          */
 749         if (hw->mac.type == e1000_82575) {
 750                 uint32_t pba;
 751
 752                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 753                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 754         }
 755
 756         /* Put the address into the Receive Address Array */
 757         e1000_rar_set(hw, hw->mac.addr, 0);
 758
 759         /* Initialize the hardware */
 760         if (igb_hardware_init(hw)) {
 761                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 762                 return (-EIO);
 763         }
 764
 765         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 766
 767         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 768         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 769         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 770         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 771         E1000_WRITE_FLUSH(hw);
 772
 773         /* configure PF module if SRIOV enabled */
 774         igb_pf_host_configure(dev);
 775
 776         /* Configure for OS presence */
 777         igb_init_manageability(hw);
 778
 779         eth_igb_tx_init(dev);
 780
 781         /* This can fail when allocating mbufs for descriptor rings */
 782         ret = eth_igb_rx_init(dev);
 783         if (ret) {
 784                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 785                 igb_dev_clear_queues(dev);
 786                 return ret;
 787         }
 788
 789         e1000_clear_hw_cntrs_base_generic(hw);
 790
 791         /*
 792          * VLAN Offload Settings
 793          */
 794         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 795                         ETH_VLAN_EXTEND_MASK;
 796         eth_igb_vlan_offload_set(dev, mask);
 797
 798         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 799                 /* Enable VLAN filter since VMDq always use VLAN filter */
 800                 igb_vmdq_vlan_hw_filter_enable(dev);
 801         }
 802
 803         /*
 804          * Configure the Interrupt Moderation register (EITR) with the maximum
 805          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 806          * spurious [DMA] memory updates of RX and TX ring descriptors.
 807          *
 808          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 809          * spurious memory updates per second should be expected.
 810          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 811          *
 812          * Because interrupts are not used at all, the MSI-X is not activated
 813          * and interrupt moderation is controlled by EITR[0].
 814          *
 815          * Note that having [almost] disabled memory updates of RX and TX ring
 816          * descriptors through the Interrupt Moderation mechanism, memory
 817          * updates of ring descriptors are now moderated by the configurable
 818          * value of Write-Back Threshold registers.
 819          */
 820         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 821                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 822                 uint32_t ivar;
 823
 824                 /* Enable all RX & TX queues in the IVAR registers */
 825                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 826                 for (i = 0; i < 8; i++)
 827                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 828
 829                 /* Configure EITR with the maximum possible value (0xFFFF) */
 830                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 831         }
 832
 833         /* Setup link speed and duplex */
 834         switch (dev->data->dev_conf.link_speed) {
 835         case ETH_LINK_SPEED_AUTONEG:
 836                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 837                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 838                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 839                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 840                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 841                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 842                 else
 843                         goto error_invalid_config;
 844                 break;
 845         case ETH_LINK_SPEED_10:
 846                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 847                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 848                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 849                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 850                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 851                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 852                 else
 853                         goto error_invalid_config;
 854                 break;
 855         case ETH_LINK_SPEED_100:
 856                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 857                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 858                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 859                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 860                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 861                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 862                 else
 863                         goto error_invalid_config;
 864                 break;
 865         case ETH_LINK_SPEED_1000:
 866                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 867                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 868                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 869                 else
 870                         goto error_invalid_config;
 871                 break;
 872         case ETH_LINK_SPEED_10000:
 873         default:
 874                 goto error_invalid_config;
 875         }
 876         e1000_setup_link(hw);
 877
 878         /* check if lsc interrupt feature is enabled */
 879         if (dev->data->dev_conf.intr_conf.lsc != 0)
 880                 ret = eth_igb_lsc_interrupt_setup(dev);
 881
 882         /* resume enabled intr since hw reset */
 883         igb_intr_enable(dev);
 884
 885         PMD_INIT_LOG(DEBUG, "<<");
 886
 887         return (0);
 888
 889 error_invalid_config:
 890         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 891                         dev->data->dev_conf.link_speed,
 892                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 893         igb_dev_clear_queues(dev);
 894         return (-EINVAL);
 895 }
 896
 897 /*********************************************************************
 898  *
 899  *  This routine disables all traffic on the adapter by issuing a
 900  *  global reset on the MAC.
 901  *
 902  **********************************************************************/
 903 static void
 904 eth_igb_stop(struct rte_eth_dev *dev)
 905 {
 906         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 907         struct rte_eth_link link;
 908
 909         igb_intr_disable(hw);
 910         igb_pf_reset_hw(hw);
 911         E1000_WRITE_REG(hw, E1000_WUC, 0);
 912
 913         /* Set bit for Go Link disconnect */
 914         if (hw->mac.type >= e1000_82580) {
 915                 uint32_t phpm_reg;
 916
 917                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 918                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 919                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 920         }
 921
 922         /* Power down the phy. Needed to make the link go Down */
 923         e1000_power_down_phy(hw);
 924
 925         igb_dev_clear_queues(dev);
 926
 927         /* clear the recorded link status */
 928         memset(&link, 0, sizeof(link));
 929         rte_igb_dev_atomic_write_link_status(dev, &link);
 930 }
 931
 932 static void
 933 eth_igb_close(struct rte_eth_dev *dev)
 934 {
 935         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 936         struct rte_eth_link link;
 937
 938         eth_igb_stop(dev);
 939         e1000_phy_hw_reset(hw);
 940         igb_release_manageability(hw);
 941         igb_hw_control_release(hw);
 942
 943         /* Clear bit for Go Link disconnect */
 944         if (hw->mac.type >= e1000_82580) {
 945                 uint32_t phpm_reg;
 946
 947                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 948                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
 949                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 950         }
 951
 952         igb_dev_clear_queues(dev);
 953
 954         memset(&link, 0, sizeof(link));
 955         rte_igb_dev_atomic_write_link_status(dev, &link);
 956 }
 957
 958 static int
 959 igb_get_rx_buffer_size(struct e1000_hw *hw)
 960 {
 961         uint32_t rx_buf_size;
 962         if (hw->mac.type == e1000_82576) {
 963                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 964         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 965                 /* PBS needs to be translated according to a lookup table */
 966                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 967                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 968                 rx_buf_size = (rx_buf_size << 10);
 969         } else if (hw->mac.type == e1000_i210) {
 970                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 971         } else {
 972                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 973         }
 974
 975         return rx_buf_size;
 976 }
 977
 978 /*********************************************************************
 979  *
 980  *  Initialize the hardware
 981  *
 982  **********************************************************************/
 983 static int
 984 igb_hardware_init(struct e1000_hw *hw)
 985 {
 986         uint32_t rx_buf_size;
 987         int diag;
 988
 989         /* Let the firmware know the OS is in control */
 990         igb_hw_control_acquire(hw);
 991
 992         /*
 993          * These parameters control the automatic generation (Tx) and
 994          * response (Rx) to Ethernet PAUSE frames.
 995          * - High water mark should allow for at least two standard size (1518)
 996          *   frames to be received after sending an XOFF.
 997          * - Low water mark works best when it is very near the high water mark.
 998          *   This allows the receiver to restart by sending XON when it has
 999          *   drained a bit. Here we use an arbitrary value of 1500 which will
1000          *   restart after one full frame is pulled from the buffer. There
1001          *   could be several smaller frames in the buffer and if so they will
1002          *   not trigger the XON until their total number reduces the buffer
1003          *   by 1500.
1004          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1005          */
1006         rx_buf_size = igb_get_rx_buffer_size(hw);
1007
1008         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1009         hw->fc.low_water = hw->fc.high_water - 1500;
1010         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1011         hw->fc.send_xon = 1;
1012
1013         /* Set Flow control, use the tunable location if sane */
1014         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1015                 hw->fc.requested_mode = igb_fc_setting;
1016         else
1017                 hw->fc.requested_mode = e1000_fc_none;
1018
1019         /* Issue a global reset */
1020         igb_pf_reset_hw(hw);
1021         E1000_WRITE_REG(hw, E1000_WUC, 0);
1022
1023         diag = e1000_init_hw(hw);
1024         if (diag < 0)
1025                 return (diag);
1026
1027         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1028         e1000_get_phy_info(hw);
1029         e1000_check_for_link(hw);
1030
1031         return (0);
1032 }
1033
1034 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1035 static void
1036 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1037 {
1038         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1039         struct e1000_hw_stats *stats =
1040                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1041         int pause_frames;
1042
1043         if(hw->phy.media_type == e1000_media_type_copper ||
1044             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1045                 stats->symerrs +=
1046                     E1000_READ_REG(hw,E1000_SYMERRS);
1047                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1048         }
1049
1050         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1051         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1052         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1053         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1054
1055         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1056         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1057         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1058         stats->dc += E1000_READ_REG(hw, E1000_DC);
1059         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1060         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1061         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1062         /*
1063         ** For watchdog management we need to know if we have been
1064         ** paused during the last interval, so capture that here.
1065         */
1066         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1067         stats->xoffrxc += pause_frames;
1068         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1069         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1070         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1071         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1072         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1073         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1074         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1075         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1076         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1077         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1078         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1079         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1080
1081         /* For the 64-bit byte counters the low dword must be read first. */
1082         /* Both registers clear on the read of the high dword */
1083
1084         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1085         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1086         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1087         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1088
1089         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1090         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1091         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1092         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1093         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1094
1095         stats->tor += E1000_READ_REG(hw, E1000_TORH);
1096         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1097
1098         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1099         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1100         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1101         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1102         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1103         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1104         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1105         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1106         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1107         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1108
1109         /* Interrupt Counts */
1110
1111         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1112         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1113         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1114         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1115         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1116         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1117         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1118         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1119         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1120
1121         /* Host to Card Statistics */
1122
1123         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1124         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1125         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1126         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1127         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1128         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1129         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1130         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1131         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1132         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1133         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1134         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1135         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1136         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1137
1138         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1139         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1140         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1141         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1142         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1143         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1144
1145         if (rte_stats == NULL)
1146                 return;
1147
1148         /* Rx Errors */
1149         rte_stats->ibadcrc = stats->crcerrs;
1150         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1151         rte_stats->imissed = stats->mpc;
1152         rte_stats->ierrors = rte_stats->ibadcrc +
1153                              rte_stats->ibadlen +
1154                              rte_stats->imissed +
1155                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1156
1157         /* Tx Errors */
1158         rte_stats->oerrors = stats->ecol + stats->latecol;
1159
1160         /* XON/XOFF pause frames */
1161         rte_stats->tx_pause_xon  = stats->xontxc;
1162         rte_stats->rx_pause_xon  = stats->xonrxc;
1163         rte_stats->tx_pause_xoff = stats->xofftxc;
1164         rte_stats->rx_pause_xoff = stats->xoffrxc;
1165
1166         rte_stats->ipackets = stats->gprc;
1167         rte_stats->opackets = stats->gptc;
1168         rte_stats->ibytes   = stats->gorc;
1169         rte_stats->obytes   = stats->gotc;
1170 }
1171
1172 static void
1173 eth_igb_stats_reset(struct rte_eth_dev *dev)
1174 {
1175         struct e1000_hw_stats *hw_stats =
1176                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1177
1178         /* HW registers are cleared on read */
1179         eth_igb_stats_get(dev, NULL);
1180
1181         /* Reset software totals */
1182         memset(hw_stats, 0, sizeof(*hw_stats));
1183 }
1184
1185 static void
1186 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1187 {
1188         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1189         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1190                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1191
1192         /* Good Rx packets, include VF loopback */
1193         UPDATE_VF_STAT(E1000_VFGPRC,
1194             hw_stats->last_gprc, hw_stats->gprc);
1195
1196         /* Good Rx octets, include VF loopback */
1197         UPDATE_VF_STAT(E1000_VFGORC,
1198             hw_stats->last_gorc, hw_stats->gorc);
1199
1200         /* Good Tx packets, include VF loopback */
1201         UPDATE_VF_STAT(E1000_VFGPTC,
1202             hw_stats->last_gptc, hw_stats->gptc);
1203
1204         /* Good Tx octets, include VF loopback */
1205         UPDATE_VF_STAT(E1000_VFGOTC,
1206             hw_stats->last_gotc, hw_stats->gotc);
1207
1208         /* Rx Multicst packets */
1209         UPDATE_VF_STAT(E1000_VFMPRC,
1210             hw_stats->last_mprc, hw_stats->mprc);
1211
1212         /* Good Rx loopback packets */
1213         UPDATE_VF_STAT(E1000_VFGPRLBC,
1214             hw_stats->last_gprlbc, hw_stats->gprlbc);
1215
1216         /* Good Rx loopback octets */
1217         UPDATE_VF_STAT(E1000_VFGORLBC,
1218             hw_stats->last_gorlbc, hw_stats->gorlbc);
1219
1220         /* Good Tx loopback packets */
1221         UPDATE_VF_STAT(E1000_VFGPTLBC,
1222             hw_stats->last_gptlbc, hw_stats->gptlbc);
1223
1224         /* Good Tx loopback octets */
1225         UPDATE_VF_STAT(E1000_VFGOTLBC,
1226             hw_stats->last_gotlbc, hw_stats->gotlbc);
1227
1228         if (rte_stats == NULL)
1229                 return;
1230
1231         memset(rte_stats, 0, sizeof(*rte_stats));
1232         rte_stats->ipackets = hw_stats->gprc;
1233         rte_stats->ibytes = hw_stats->gorc;
1234         rte_stats->opackets = hw_stats->gptc;
1235         rte_stats->obytes = hw_stats->gotc;
1236         rte_stats->imcasts = hw_stats->mprc;
1237         rte_stats->ilbpackets = hw_stats->gprlbc;
1238         rte_stats->ilbbytes = hw_stats->gorlbc;
1239         rte_stats->olbpackets = hw_stats->gptlbc;
1240         rte_stats->olbbytes = hw_stats->gotlbc;
1241
1242 }
1243
1244 static void
1245 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1246 {
1247         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1248                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1249
1250         /* Sync HW register to the last stats */
1251         eth_igbvf_stats_get(dev, NULL);
1252
1253         /* reset HW current stats*/
1254         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1255                offsetof(struct e1000_vf_stats, gprc));
1256
1257 }
1258
1259 static void
1260 eth_igb_infos_get(struct rte_eth_dev *dev,
1261                     struct rte_eth_dev_info *dev_info)
1262 {
1263         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1264
1265         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1266         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1267         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1268         dev_info->rx_offload_capa =
1269                 DEV_RX_OFFLOAD_VLAN_STRIP |
1270                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1271                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1272                 DEV_RX_OFFLOAD_TCP_CKSUM;
1273         dev_info->tx_offload_capa =
1274                 DEV_TX_OFFLOAD_VLAN_INSERT |
1275                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1276                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1277                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1278                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1279
1280         switch (hw->mac.type) {
1281         case e1000_82575:
1282                 dev_info->max_rx_queues = 4;
1283                 dev_info->max_tx_queues = 4;
1284                 dev_info->max_vmdq_pools = 0;
1285                 break;
1286
1287         case e1000_82576:
1288                 dev_info->max_rx_queues = 16;
1289                 dev_info->max_tx_queues = 16;
1290                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1291                 break;
1292
1293         case e1000_82580:
1294                 dev_info->max_rx_queues = 8;
1295                 dev_info->max_tx_queues = 8;
1296                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1297                 break;
1298
1299         case e1000_i350:
1300                 dev_info->max_rx_queues = 8;
1301                 dev_info->max_tx_queues = 8;
1302                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1303                 break;
1304
1305         case e1000_i354:
1306                 dev_info->max_rx_queues = 8;
1307                 dev_info->max_tx_queues = 8;
1308                 break;
1309
1310         case e1000_i210:
1311                 dev_info->max_rx_queues = 4;
1312                 dev_info->max_tx_queues = 4;
1313                 dev_info->max_vmdq_pools = 0;
1314                 break;
1315
1316         case e1000_vfadapt:
1317                 dev_info->max_rx_queues = 2;
1318                 dev_info->max_tx_queues = 2;
1319                 dev_info->max_vmdq_pools = 0;
1320                 break;
1321
1322         case e1000_vfadapt_i350:
1323                 dev_info->max_rx_queues = 1;
1324                 dev_info->max_tx_queues = 1;
1325                 dev_info->max_vmdq_pools = 0;
1326                 break;
1327
1328         default:
1329                 /* Should not happen */
1330                 dev_info->max_rx_queues = 0;
1331                 dev_info->max_tx_queues = 0;
1332                 dev_info->max_vmdq_pools = 0;
1333         }
1334 }
1335
1336 /* return 0 means link status changed, -1 means not changed */
1337 static int
1338 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1339 {
1340         struct e1000_hw *hw =
1341                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1342         struct rte_eth_link link, old;
1343         int link_check, count;
1344
1345         link_check = 0;
1346         hw->mac.get_link_status = 1;
1347
1348         /* possible wait-to-complete in up to 9 seconds */
1349         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1350                 /* Read the real link status */
1351                 switch (hw->phy.media_type) {
1352                 case e1000_media_type_copper:
1353                         /* Do the work to read phy */
1354                         e1000_check_for_link(hw);
1355                         link_check = !hw->mac.get_link_status;
1356                         break;
1357
1358                 case e1000_media_type_fiber:
1359                         e1000_check_for_link(hw);
1360                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1361                                       E1000_STATUS_LU);
1362                         break;
1363
1364                 case e1000_media_type_internal_serdes:
1365                         e1000_check_for_link(hw);
1366                         link_check = hw->mac.serdes_has_link;
1367                         break;
1368
1369                 /* VF device is type_unknown */
1370                 case e1000_media_type_unknown:
1371                         eth_igbvf_link_update(hw);
1372                         link_check = !hw->mac.get_link_status;
1373                         break;
1374
1375                 default:
1376                         break;
1377                 }
1378                 if (link_check || wait_to_complete == 0)
1379                         break;
1380                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1381         }
1382         memset(&link, 0, sizeof(link));
1383         rte_igb_dev_atomic_read_link_status(dev, &link);
1384         old = link;
1385
1386         /* Now we check if a transition has happened */
1387         if (link_check) {
1388                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1389                                           &link.link_duplex);
1390                 link.link_status = 1;
1391         } else if (!link_check) {
1392                 link.link_speed = 0;
1393                 link.link_duplex = 0;
1394                 link.link_status = 0;
1395         }
1396         rte_igb_dev_atomic_write_link_status(dev, &link);
1397
1398         /* not changed */
1399         if (old.link_status == link.link_status)
1400                 return -1;
1401
1402         /* changed */
1403         return 0;
1404 }
1405
1406 /*
1407  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1408  * For ASF and Pass Through versions of f/w this means
1409  * that the driver is loaded.
1410  */
1411 static void
1412 igb_hw_control_acquire(struct e1000_hw *hw)
1413 {
1414         uint32_t ctrl_ext;
1415
1416         /* Let firmware know the driver has taken over */
1417         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1418         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1419 }
1420
1421 /*
1422  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1423  * For ASF and Pass Through versions of f/w this means that the
1424  * driver is no longer loaded.
1425  */
1426 static void
1427 igb_hw_control_release(struct e1000_hw *hw)
1428 {
1429         uint32_t ctrl_ext;
1430
1431         /* Let firmware taken over control of h/w */
1432         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1433         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1434                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1435 }
1436
1437 /*
1438  * Bit of a misnomer, what this really means is
1439  * to enable OS management of the system... aka
1440  * to disable special hardware management features.
1441  */
1442 static void
1443 igb_init_manageability(struct e1000_hw *hw)
1444 {
1445         if (e1000_enable_mng_pass_thru(hw)) {
1446                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1447                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1448
1449                 /* disable hardware interception of ARP */
1450                 manc &= ~(E1000_MANC_ARP_EN);
1451
1452                 /* enable receiving management packets to the host */
1453                 manc |= E1000_MANC_EN_MNG2HOST;
1454                 manc2h |= 1 << 5;  /* Mng Port 623 */
1455                 manc2h |= 1 << 6;  /* Mng Port 664 */
1456                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1457                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1458         }
1459 }
1460
1461 static void
1462 igb_release_manageability(struct e1000_hw *hw)
1463 {
1464         if (e1000_enable_mng_pass_thru(hw)) {
1465                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1466
1467                 manc |= E1000_MANC_ARP_EN;
1468                 manc &= ~E1000_MANC_EN_MNG2HOST;
1469
1470                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1471         }
1472 }
1473
1474 static void
1475 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1476 {
1477         struct e1000_hw *hw =
1478                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1479         uint32_t rctl;
1480
1481         rctl = E1000_READ_REG(hw, E1000_RCTL);
1482         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1483         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1484 }
1485
1486 static void
1487 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1488 {
1489         struct e1000_hw *hw =
1490                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1491         uint32_t rctl;
1492
1493         rctl = E1000_READ_REG(hw, E1000_RCTL);
1494         rctl &= (~E1000_RCTL_UPE);
1495         if (dev->data->all_multicast == 1)
1496                 rctl |= E1000_RCTL_MPE;
1497         else
1498                 rctl &= (~E1000_RCTL_MPE);
1499         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1500 }
1501
1502 static void
1503 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1504 {
1505         struct e1000_hw *hw =
1506                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1507         uint32_t rctl;
1508
1509         rctl = E1000_READ_REG(hw, E1000_RCTL);
1510         rctl |= E1000_RCTL_MPE;
1511         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1512 }
1513
1514 static void
1515 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1516 {
1517         struct e1000_hw *hw =
1518                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1519         uint32_t rctl;
1520
1521         if (dev->data->promiscuous == 1)
1522                 return; /* must remain in all_multicast mode */
1523         rctl = E1000_READ_REG(hw, E1000_RCTL);
1524         rctl &= (~E1000_RCTL_MPE);
1525         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1526 }
1527
1528 static int
1529 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1530 {
1531         struct e1000_hw *hw =
1532                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1533         struct e1000_vfta * shadow_vfta =
1534                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1535         uint32_t vfta;
1536         uint32_t vid_idx;
1537         uint32_t vid_bit;
1538
1539         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1540                               E1000_VFTA_ENTRY_MASK);
1541         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1542         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1543         if (on)
1544                 vfta |= vid_bit;
1545         else
1546                 vfta &= ~vid_bit;
1547         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1548
1549         /* update local VFTA copy */
1550         shadow_vfta->vfta[vid_idx] = vfta;
1551
1552         return 0;
1553 }
1554
1555 static void
1556 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1557 {
1558         struct e1000_hw *hw =
1559                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1560         uint32_t reg = ETHER_TYPE_VLAN ;
1561
1562         reg |= (tpid << 16);
1563         E1000_WRITE_REG(hw, E1000_VET, reg);
1564 }
1565
1566 static void
1567 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1568 {
1569         struct e1000_hw *hw =
1570                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1571         uint32_t reg;
1572
1573         /* Filter Table Disable */
1574         reg = E1000_READ_REG(hw, E1000_RCTL);
1575         reg &= ~E1000_RCTL_CFIEN;
1576         reg &= ~E1000_RCTL_VFE;
1577         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1578 }
1579
1580 static void
1581 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1582 {
1583         struct e1000_hw *hw =
1584                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585         struct e1000_vfta * shadow_vfta =
1586                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1587         uint32_t reg;
1588         int i;
1589
1590         /* Filter Table Enable, CFI not used for packet acceptance */
1591         reg = E1000_READ_REG(hw, E1000_RCTL);
1592         reg &= ~E1000_RCTL_CFIEN;
1593         reg |= E1000_RCTL_VFE;
1594         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1595
1596         /* restore VFTA table */
1597         for (i = 0; i < IGB_VFTA_SIZE; i++)
1598                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1599 }
1600
1601 static void
1602 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1603 {
1604         struct e1000_hw *hw =
1605                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606         uint32_t reg;
1607
1608         /* VLAN Mode Disable */
1609         reg = E1000_READ_REG(hw, E1000_CTRL);
1610         reg &= ~E1000_CTRL_VME;
1611         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1612 }
1613
1614 static void
1615 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1616 {
1617         struct e1000_hw *hw =
1618                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1619         uint32_t reg;
1620
1621         /* VLAN Mode Enable */
1622         reg = E1000_READ_REG(hw, E1000_CTRL);
1623         reg |= E1000_CTRL_VME;
1624         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1625 }
1626
1627 static void
1628 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1629 {
1630         struct e1000_hw *hw =
1631                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1632         uint32_t reg;
1633
1634         /* CTRL_EXT: Extended VLAN */
1635         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1636         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1637         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1638
1639         /* Update maximum packet length */
1640         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1641                 E1000_WRITE_REG(hw, E1000_RLPML,
1642                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1643                                                 VLAN_TAG_SIZE);
1644 }
1645
1646 static void
1647 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1648 {
1649         struct e1000_hw *hw =
1650                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1651         uint32_t reg;
1652
1653         /* CTRL_EXT: Extended VLAN */
1654         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1655         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1656         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1657
1658         /* Update maximum packet length */
1659         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1660                 E1000_WRITE_REG(hw, E1000_RLPML,
1661                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1662                                                 2 * VLAN_TAG_SIZE);
1663 }
1664
1665 static void
1666 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1667 {
1668         if(mask & ETH_VLAN_STRIP_MASK){
1669                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1670                         igb_vlan_hw_strip_enable(dev);
1671                 else
1672                         igb_vlan_hw_strip_disable(dev);
1673         }
1674
1675         if(mask & ETH_VLAN_FILTER_MASK){
1676                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1677                         igb_vlan_hw_filter_enable(dev);
1678                 else
1679                         igb_vlan_hw_filter_disable(dev);
1680         }
1681
1682         if(mask & ETH_VLAN_EXTEND_MASK){
1683                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1684                         igb_vlan_hw_extend_enable(dev);
1685                 else
1686                         igb_vlan_hw_extend_disable(dev);
1687         }
1688 }
1689
1690
1691 /**
1692  * It enables the interrupt mask and then enable the interrupt.
1693  *
1694  * @param dev
1695  *  Pointer to struct rte_eth_dev.
1696  *
1697  * @return
1698  *  - On success, zero.
1699  *  - On failure, a negative value.
1700  */
1701 static int
1702 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1703 {
1704         struct e1000_interrupt *intr =
1705                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1706
1707         intr->mask |= E1000_ICR_LSC;
1708
1709         return 0;
1710 }
1711
1712 /*
1713  * It reads ICR and gets interrupt causes, check it and set a bit flag
1714  * to update link status.
1715  *
1716  * @param dev
1717  *  Pointer to struct rte_eth_dev.
1718  *
1719  * @return
1720  *  - On success, zero.
1721  *  - On failure, a negative value.
1722  */
1723 static int
1724 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1725 {
1726         uint32_t icr;
1727         struct e1000_hw *hw =
1728                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729         struct e1000_interrupt *intr =
1730                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1731
1732         igb_intr_disable(hw);
1733
1734         /* read-on-clear nic registers here */
1735         icr = E1000_READ_REG(hw, E1000_ICR);
1736
1737         intr->flags = 0;
1738         if (icr & E1000_ICR_LSC) {
1739                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1740         }
1741
1742         if (icr & E1000_ICR_VMMB)
1743                 intr->flags |= E1000_FLAG_MAILBOX;
1744
1745         return 0;
1746 }
1747
1748 /*
1749  * It executes link_update after knowing an interrupt is prsent.
1750  *
1751  * @param dev
1752  *  Pointer to struct rte_eth_dev.
1753  *
1754  * @return
1755  *  - On success, zero.
1756  *  - On failure, a negative value.
1757  */
1758 static int
1759 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1760 {
1761         struct e1000_hw *hw =
1762                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1763         struct e1000_interrupt *intr =
1764                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1765         uint32_t tctl, rctl;
1766         struct rte_eth_link link;
1767         int ret;
1768
1769         if (intr->flags & E1000_FLAG_MAILBOX) {
1770                 igb_pf_mbx_process(dev);
1771                 intr->flags &= ~E1000_FLAG_MAILBOX;
1772         }
1773
1774         igb_intr_enable(dev);
1775         rte_intr_enable(&(dev->pci_dev->intr_handle));
1776
1777         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1778                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1779
1780                 /* set get_link_status to check register later */
1781                 hw->mac.get_link_status = 1;
1782                 ret = eth_igb_link_update(dev, 0);
1783
1784                 /* check if link has changed */
1785                 if (ret < 0)
1786                         return 0;
1787
1788                 memset(&link, 0, sizeof(link));
1789                 rte_igb_dev_atomic_read_link_status(dev, &link);
1790                 if (link.link_status) {
1791                         PMD_INIT_LOG(INFO,
1792                                 " Port %d: Link Up - speed %u Mbps - %s\n",
1793                                 dev->data->port_id, (unsigned)link.link_speed,
1794                                 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1795                                         "full-duplex" : "half-duplex");
1796                 } else {
1797                         PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1798                                                 dev->data->port_id);
1799                 }
1800                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1801                                         dev->pci_dev->addr.domain,
1802                                         dev->pci_dev->addr.bus,
1803                                         dev->pci_dev->addr.devid,
1804                                         dev->pci_dev->addr.function);
1805                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1806                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1807                 if (link.link_status) {
1808                         /* enable Tx/Rx */
1809                         tctl |= E1000_TCTL_EN;
1810                         rctl |= E1000_RCTL_EN;
1811                 } else {
1812                         /* disable Tx/Rx */
1813                         tctl &= ~E1000_TCTL_EN;
1814                         rctl &= ~E1000_RCTL_EN;
1815                 }
1816                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1817                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1818                 E1000_WRITE_FLUSH(hw);
1819                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1820         }
1821
1822         return 0;
1823 }
1824
1825 /**
1826  * Interrupt handler which shall be registered at first.
1827  *
1828  * @param handle
1829  *  Pointer to interrupt handle.
1830  * @param param
1831  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1832  *
1833  * @return
1834  *  void
1835  */
1836 static void
1837 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1838                                                         void *param)
1839 {
1840         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1841
1842         eth_igb_interrupt_get_status(dev);
1843         eth_igb_interrupt_action(dev);
1844 }
1845
1846 static int
1847 eth_igb_led_on(struct rte_eth_dev *dev)
1848 {
1849         struct e1000_hw *hw;
1850
1851         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1852         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1853 }
1854
1855 static int
1856 eth_igb_led_off(struct rte_eth_dev *dev)
1857 {
1858         struct e1000_hw *hw;
1859
1860         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1861         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1862 }
1863
1864 static int
1865 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1866 {
1867         struct e1000_hw *hw;
1868         uint32_t ctrl;
1869         int tx_pause;
1870         int rx_pause;
1871
1872         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873         fc_conf->pause_time = hw->fc.pause_time;
1874         fc_conf->high_water = hw->fc.high_water;
1875         fc_conf->low_water = hw->fc.low_water;
1876         fc_conf->send_xon = hw->fc.send_xon;
1877         fc_conf->autoneg = hw->mac.autoneg;
1878
1879         /*
1880          * Return rx_pause and tx_pause status according to actual setting of
1881          * the TFCE and RFCE bits in the CTRL register.
1882          */
1883         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1884         if (ctrl & E1000_CTRL_TFCE)
1885                 tx_pause = 1;
1886         else
1887                 tx_pause = 0;
1888
1889         if (ctrl & E1000_CTRL_RFCE)
1890                 rx_pause = 1;
1891         else
1892                 rx_pause = 0;
1893
1894         if (rx_pause && tx_pause)
1895                 fc_conf->mode = RTE_FC_FULL;
1896         else if (rx_pause)
1897                 fc_conf->mode = RTE_FC_RX_PAUSE;
1898         else if (tx_pause)
1899                 fc_conf->mode = RTE_FC_TX_PAUSE;
1900         else
1901                 fc_conf->mode = RTE_FC_NONE;
1902
1903         return 0;
1904 }
1905
1906 static int
1907 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1908 {
1909         struct e1000_hw *hw;
1910         int err;
1911         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1912                 e1000_fc_none,
1913                 e1000_fc_rx_pause,
1914                 e1000_fc_tx_pause,
1915                 e1000_fc_full
1916         };
1917         uint32_t rx_buf_size;
1918         uint32_t max_high_water;
1919         uint32_t rctl;
1920
1921         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         if (fc_conf->autoneg != hw->mac.autoneg)
1923                 return -ENOTSUP;
1924         rx_buf_size = igb_get_rx_buffer_size(hw);
1925         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1926
1927         /* At least reserve one Ethernet frame for watermark */
1928         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1929         if ((fc_conf->high_water > max_high_water) ||
1930                 (fc_conf->high_water < fc_conf->low_water)) {
1931                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1932                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1933                 return (-EINVAL);
1934         }
1935
1936         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1937         hw->fc.pause_time     = fc_conf->pause_time;
1938         hw->fc.high_water     = fc_conf->high_water;
1939         hw->fc.low_water      = fc_conf->low_water;
1940         hw->fc.send_xon       = fc_conf->send_xon;
1941
1942         err = e1000_setup_link_generic(hw);
1943         if (err == E1000_SUCCESS) {
1944
1945                 /* check if we want to forward MAC frames - driver doesn't have native
1946                  * capability to do that, so we'll write the registers ourselves */
1947
1948                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1949
1950                 /* set or clear MFLCN.PMCF bit depending on configuration */
1951                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1952                         rctl |= E1000_RCTL_PMCF;
1953                 else
1954                         rctl &= ~E1000_RCTL_PMCF;
1955
1956                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1957                 E1000_WRITE_FLUSH(hw);
1958
1959                 return 0;
1960         }
1961
1962         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1963         return (-EIO);
1964 }
1965
1966 #define E1000_RAH_POOLSEL_SHIFT      (18)
1967 static void
1968 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1969                 uint32_t index, __rte_unused uint32_t pool)
1970 {
1971         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972         uint32_t rah;
1973
1974         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1975         rah = E1000_READ_REG(hw, E1000_RAH(index));
1976         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
1977         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
1978 }
1979
1980 static void
1981 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1982 {
1983         uint8_t addr[ETHER_ADDR_LEN];
1984         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985
1986         memset(addr, 0, sizeof(addr));
1987
1988         e1000_rar_set(hw, addr, index);
1989 }
1990
1991 /*
1992  * Virtual Function operations
1993  */
1994 static void
1995 igbvf_intr_disable(struct e1000_hw *hw)
1996 {
1997         PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1998
1999         /* Clear interrupt mask to stop from interrupts being generated */
2000         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2001
2002         E1000_WRITE_FLUSH(hw);
2003 }
2004
2005 static void
2006 igbvf_stop_adapter(struct rte_eth_dev *dev)
2007 {
2008         u32 reg_val;
2009         u16 i;
2010         struct rte_eth_dev_info dev_info;
2011         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2012
2013         memset(&dev_info, 0, sizeof(dev_info));
2014         eth_igb_infos_get(dev, &dev_info);
2015
2016         /* Clear interrupt mask to stop from interrupts being generated */
2017         igbvf_intr_disable(hw);
2018
2019         /* Clear any pending interrupts, flush previous writes */
2020         E1000_READ_REG(hw, E1000_EICR);
2021
2022         /* Disable the transmit unit.  Each queue must be disabled. */
2023         for (i = 0; i < dev_info.max_tx_queues; i++)
2024                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2025
2026         /* Disable the receive unit by stopping each queue */
2027         for (i = 0; i < dev_info.max_rx_queues; i++) {
2028                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2029                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2030                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2031                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2032                         ;
2033         }
2034
2035         /* flush all queues disables */
2036         E1000_WRITE_FLUSH(hw);
2037         msec_delay(2);
2038 }
2039
2040 static int eth_igbvf_link_update(struct e1000_hw *hw)
2041 {
2042         struct e1000_mbx_info *mbx = &hw->mbx;
2043         struct e1000_mac_info *mac = &hw->mac;
2044         int ret_val = E1000_SUCCESS;
2045
2046         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2047
2048         /*
2049          * We only want to run this if there has been a rst asserted.
2050          * in this case that could mean a link change, device reset,
2051          * or a virtual function reset
2052          */
2053
2054         /* If we were hit with a reset or timeout drop the link */
2055         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2056                 mac->get_link_status = TRUE;
2057
2058         if (!mac->get_link_status)
2059                 goto out;
2060
2061         /* if link status is down no point in checking to see if pf is up */
2062         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2063                 goto out;
2064
2065         /* if we passed all the tests above then the link is up and we no
2066          * longer need to check for link */
2067         mac->get_link_status = FALSE;
2068
2069 out:
2070         return ret_val;
2071 }
2072
2073
2074 static int
2075 igbvf_dev_configure(struct rte_eth_dev *dev)
2076 {
2077         struct rte_eth_conf* conf = &dev->data->dev_conf;
2078
2079         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2080                 dev->data->port_id);
2081
2082         /*
2083          * VF has no ability to enable/disable HW CRC
2084          * Keep the persistent behavior the same as Host PF
2085          */
2086 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2087         if (!conf->rxmode.hw_strip_crc) {
2088                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2089                 conf->rxmode.hw_strip_crc = 1;
2090         }
2091 #else
2092         if (conf->rxmode.hw_strip_crc) {
2093                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2094                 conf->rxmode.hw_strip_crc = 0;
2095         }
2096 #endif
2097
2098         return 0;
2099 }
2100
2101 static int
2102 igbvf_dev_start(struct rte_eth_dev *dev)
2103 {
2104         struct e1000_hw *hw =
2105                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106         int ret;
2107
2108         PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
2109
2110         hw->mac.ops.reset_hw(hw);
2111
2112         /* Set all vfta */
2113         igbvf_set_vfta_all(dev,1);
2114
2115         eth_igbvf_tx_init(dev);
2116
2117         /* This can fail when allocating mbufs for descriptor rings */
2118         ret = eth_igbvf_rx_init(dev);
2119         if (ret) {
2120                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2121                 igb_dev_clear_queues(dev);
2122                 return ret;
2123         }
2124
2125         return 0;
2126 }
2127
2128 static void
2129 igbvf_dev_stop(struct rte_eth_dev *dev)
2130 {
2131         PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
2132
2133         igbvf_stop_adapter(dev);
2134
2135         /*
2136           * Clear what we set, but we still keep shadow_vfta to
2137           * restore after device starts
2138           */
2139         igbvf_set_vfta_all(dev,0);
2140
2141         igb_dev_clear_queues(dev);
2142 }
2143
2144 static void
2145 igbvf_dev_close(struct rte_eth_dev *dev)
2146 {
2147         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148
2149         PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
2150
2151         e1000_reset_hw(hw);
2152
2153         igbvf_dev_stop(dev);
2154 }
2155
2156 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2157 {
2158         struct e1000_mbx_info *mbx = &hw->mbx;
2159         uint32_t msgbuf[2];
2160
2161         /* After set vlan, vlan strip will also be enabled in igb driver*/
2162         msgbuf[0] = E1000_VF_SET_VLAN;
2163         msgbuf[1] = vid;
2164         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2165         if (on)
2166                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2167
2168         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2169 }
2170
2171 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2172 {
2173         struct e1000_hw *hw =
2174                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2175         struct e1000_vfta * shadow_vfta =
2176                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2177         int i = 0, j = 0, vfta = 0, mask = 1;
2178
2179         for (i = 0; i < IGB_VFTA_SIZE; i++){
2180                 vfta = shadow_vfta->vfta[i];
2181                 if(vfta){
2182                         mask = 1;
2183                         for (j = 0; j < 32; j++){
2184                                 if(vfta & mask)
2185                                         igbvf_set_vfta(hw,
2186                                                 (uint16_t)((i<<5)+j), on);
2187                                 mask<<=1;
2188                         }
2189                 }
2190         }
2191
2192 }
2193
2194 static int
2195 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2196 {
2197         struct e1000_hw *hw =
2198                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2199         struct e1000_vfta * shadow_vfta =
2200                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2201         uint32_t vid_idx = 0;
2202         uint32_t vid_bit = 0;
2203         int ret = 0;
2204
2205         PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
2206
2207         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2208         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2209         if(ret){
2210                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2211                 return ret;
2212         }
2213         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2214         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2215
2216         /*Save what we set and retore it after device reset*/
2217         if (on)
2218                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2219         else
2220                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2221
2222         return 0;
2223 }
2224
2225 static int
2226 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2227                                 struct rte_eth_rss_reta *reta_conf)
2228 {
2229         uint8_t i,j,mask;
2230         uint32_t reta;
2231         struct e1000_hw *hw =
2232                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2233
2234         /*
2235          * Update Redirection Table RETA[n],n=0...31,The redirection table has
2236          * 128-entries in 32 registers
2237          */
2238         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2239                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2240                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2241                 else
2242                         mask = (uint8_t)((reta_conf->mask_hi >>
2243                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2244                 if (mask != 0) {
2245                         reta = 0;
2246                         /* If all 4 entries were set,don't need read RETA register */
2247                         if (mask != 0xF)
2248                                 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2249
2250                         for (j = 0; j < 4; j++) {
2251                                 if (mask & (0x1 << j)) {
2252                                         if (mask != 0xF)
2253                                                 reta &= ~(0xFF << 8 * j);
2254                                         reta |= reta_conf->reta[i + j] << 8 * j;
2255                                 }
2256                         }
2257                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2258                 }
2259         }
2260
2261         return 0;
2262 }
2263
2264 static int
2265 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2266                                 struct rte_eth_rss_reta *reta_conf)
2267 {
2268         uint8_t i,j,mask;
2269         uint32_t reta;
2270         struct e1000_hw *hw =
2271                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2272
2273         /*
2274          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2275          * 128-entries in 32 registers
2276          */
2277         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2278                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2279                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2280                 else
2281                         mask = (uint8_t)((reta_conf->mask_hi >>
2282                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2283
2284                 if (mask != 0) {
2285                         reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2286                         for (j = 0; j < 4; j++) {
2287                                 if (mask & (0x1 << j))
2288                                         reta_conf->reta[i + j] =
2289                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2290                         }
2291                 }
2292         }
2293
2294         return 0;
2295 }
2296
2297 #define MAC_TYPE_FILTER_SUP(type)    do {\
2298         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2299                 (type) != e1000_82576)\
2300                 return -ENOSYS;\
2301 } while (0)
2302
2303 /*
2304  * add the syn filter
2305  *
2306  * @param
2307  * dev: Pointer to struct rte_eth_dev.
2308  * filter: ponter to the filter that will be added.
2309  * rx_queue: the queue id the filter assigned to.
2310  *
2311  * @return
2312  *    - On success, zero.
2313  *    - On failure, a negative value.
2314  */
2315 static int
2316 eth_igb_add_syn_filter(struct rte_eth_dev *dev,
2317                         struct rte_syn_filter *filter, uint16_t rx_queue)
2318 {
2319         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2320         uint32_t synqf, rfctl;
2321
2322         MAC_TYPE_FILTER_SUP(hw->mac.type);
2323
2324         if (rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2325                 return -EINVAL;
2326
2327         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2328         if (synqf & E1000_SYN_FILTER_ENABLE)
2329                 return -EINVAL;
2330
2331         synqf = (uint32_t)(((rx_queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2332                 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2333
2334         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2335         if (filter->hig_pri)
2336                 rfctl |= E1000_RFCTL_SYNQFP;
2337         else
2338                 rfctl &= ~E1000_RFCTL_SYNQFP;
2339
2340         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2341         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2342         return 0;
2343 }
2344
2345 /*
2346  * remove the syn filter
2347  *
2348  * @param
2349  * dev: Pointer to struct rte_eth_dev.
2350  *
2351  * @return
2352  *    - On success, zero.
2353  *    - On failure, a negative value.
2354  */
2355 static int
2356 eth_igb_remove_syn_filter(struct rte_eth_dev *dev)
2357 {
2358         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2359
2360         MAC_TYPE_FILTER_SUP(hw->mac.type);
2361
2362         E1000_WRITE_REG(hw, E1000_SYNQF(0), 0);
2363         return 0;
2364 }
2365
2366 /*
2367  * get the syn filter's info
2368  *
2369  * @param
2370  * dev: Pointer to struct rte_eth_dev.
2371  * filter: ponter to the filter that returns.
2372  * *rx_queue: pointer to the queue id the filter assigned to.
2373  *
2374  * @return
2375  *    - On success, zero.
2376  *    - On failure, a negative value.
2377  */
2378 static int
2379 eth_igb_get_syn_filter(struct rte_eth_dev *dev,
2380                         struct rte_syn_filter *filter, uint16_t *rx_queue)
2381 {
2382         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2383         uint32_t synqf, rfctl;
2384
2385         MAC_TYPE_FILTER_SUP(hw->mac.type);
2386         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2387         if (synqf & E1000_SYN_FILTER_ENABLE) {
2388                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2389                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2390                 *rx_queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2391                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2392                 return 0;
2393         }
2394         return -ENOENT;
2395 }
2396
2397 /*
2398  * add an ethertype filter
2399  *
2400  * @param
2401  * dev: Pointer to struct rte_eth_dev.
2402  * index: the index the filter allocates.
2403  * filter: ponter to the filter that will be added.
2404  * rx_queue: the queue id the filter assigned to.
2405  *
2406  * @return
2407  *    - On success, zero.
2408  *    - On failure, a negative value.
2409  */
2410 static int
2411 eth_igb_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2412                         struct rte_ethertype_filter *filter, uint16_t rx_queue)
2413 {
2414         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2415         uint32_t etqf;
2416
2417         MAC_TYPE_FILTER_SUP(hw->mac.type);
2418
2419         if (index >= E1000_MAX_ETQF_FILTERS || rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2420                 return -EINVAL;
2421
2422         etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2423         if (etqf & E1000_ETQF_FILTER_ENABLE)
2424                 return -EINVAL;  /* filter index is in use. */
2425         else
2426                 etqf = 0;
2427
2428         etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
2429         etqf |= (uint32_t)(filter->ethertype & E1000_ETQF_ETHERTYPE);
2430         etqf |= rx_queue << E1000_ETQF_QUEUE_SHIFT;
2431
2432         if (filter->priority_en) {
2433                 PMD_INIT_LOG(ERR, "vlan and priority (%d) is not supported"
2434                         " in E1000.", filter->priority);
2435                 return -EINVAL;
2436         }
2437
2438         E1000_WRITE_REG(hw, E1000_ETQF(index), etqf);
2439         return 0;
2440 }
2441
2442 /*
2443  * remove an ethertype filter
2444  *
2445  * @param
2446  * dev: Pointer to struct rte_eth_dev.
2447  * index: the index the filter allocates.
2448  *
2449  * @return
2450  *    - On success, zero.
2451  *    - On failure, a negative value.
2452  */
2453 static int
2454 eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev, uint16_t index)
2455 {
2456         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457
2458         MAC_TYPE_FILTER_SUP(hw->mac.type);
2459
2460         if (index >= E1000_MAX_ETQF_FILTERS)
2461                 return -EINVAL;
2462
2463         E1000_WRITE_REG(hw, E1000_ETQF(index), 0);
2464         return 0;
2465 }
2466
2467 /*
2468  * get an ethertype filter
2469  *
2470  * @param
2471  * dev: Pointer to struct rte_eth_dev.
2472  * index: the index the filter allocates.
2473  * filter: ponter to the filter that will be gotten.
2474  * *rx_queue: the ponited of the queue id the filter assigned to.
2475  *
2476  * @return
2477  *    - On success, zero.
2478  *    - On failure, a negative value.
2479  */
2480 static int
2481 eth_igb_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2482                         struct rte_ethertype_filter *filter, uint16_t *rx_queue)
2483 {
2484         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2485         uint32_t etqf;
2486
2487         MAC_TYPE_FILTER_SUP(hw->mac.type);
2488
2489         if (index >= E1000_MAX_ETQF_FILTERS)
2490                 return -EINVAL;
2491
2492         etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2493         if (etqf & E1000_ETQF_FILTER_ENABLE) {
2494                 filter->ethertype = etqf & E1000_ETQF_ETHERTYPE;
2495                 filter->priority_en = 0;
2496                 *rx_queue = (etqf & E1000_ETQF_QUEUE) >> E1000_ETQF_QUEUE_SHIFT;
2497                 return 0;
2498         }
2499         return -ENOENT;
2500 }
2501
2502 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2503         if ((type) != e1000_82580 && (type) != e1000_i350)\
2504                 return -ENOSYS; \
2505 } while (0)
2506
2507 /*
2508  * add a 2tuple filter
2509  *
2510  * @param
2511  * dev: Pointer to struct rte_eth_dev.
2512  * index: the index the filter allocates.
2513  * filter: ponter to the filter that will be added.
2514  * rx_queue: the queue id the filter assigned to.
2515  *
2516  * @return
2517  *    - On success, zero.
2518  *    - On failure, a negative value.
2519  */
2520 static int
2521 eth_igb_add_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2522                         struct rte_2tuple_filter *filter, uint16_t rx_queue)
2523 {
2524         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2525         uint32_t ttqf, imir = 0;
2526         uint32_t imir_ext = 0;
2527
2528         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2529
2530         if (index >= E1000_MAX_TTQF_FILTERS ||
2531                 rx_queue >= IGB_MAX_RX_QUEUE_NUM ||
2532                 filter->priority > E1000_2TUPLE_MAX_PRI)
2533                 return -EINVAL;  /* filter index is out of range. */
2534         if  (filter->tcp_flags > TCP_FLAG_ALL)
2535                 return -EINVAL;  /* flags is invalid. */
2536
2537         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2538         if (ttqf & E1000_TTQF_QUEUE_ENABLE)
2539                 return -EINVAL;  /* filter index is in use. */
2540
2541         imir = (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2542         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2543                 imir |= E1000_IMIR_PORT_BP;
2544         else
2545                 imir &= ~E1000_IMIR_PORT_BP;
2546
2547         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2548
2549         ttqf = 0;
2550         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2551         ttqf |= (uint32_t)(rx_queue << E1000_TTQF_QUEUE_SHIFT);
2552         ttqf |= (uint32_t)(filter->protocol & E1000_TTQF_PROTOCOL_MASK);
2553         if (filter->protocol_mask == 1)
2554                 ttqf |= E1000_TTQF_MASK_ENABLE;
2555         else
2556                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2557
2558         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2559         /* tcp flags bits setting. */
2560         if (filter->tcp_flags & TCP_FLAG_ALL) {
2561                 if (filter->tcp_flags & TCP_UGR_FLAG)
2562                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2563                 if (filter->tcp_flags & TCP_ACK_FLAG)
2564                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2565                 if (filter->tcp_flags & TCP_PSH_FLAG)
2566                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2567                 if (filter->tcp_flags & TCP_RST_FLAG)
2568                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2569                 if (filter->tcp_flags & TCP_SYN_FLAG)
2570                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2571                 if (filter->tcp_flags & TCP_FIN_FLAG)
2572                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2573                 imir_ext &= ~E1000_IMIR_EXT_CTRL_BP;
2574         } else
2575                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2576         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2577         E1000_WRITE_REG(hw, E1000_TTQF(index), ttqf);
2578         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2579         return 0;
2580 }
2581
2582 /*
2583  * remove a 2tuple filter
2584  *
2585  * @param
2586  * dev: Pointer to struct rte_eth_dev.
2587  * index: the index the filter allocates.
2588  *
2589  * @return
2590  *    - On success, zero.
2591  *    - On failure, a negative value.
2592  */
2593 static int
2594 eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2595                         uint16_t index)
2596 {
2597         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2598
2599         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2600
2601         if (index >= E1000_MAX_TTQF_FILTERS)
2602                 return -EINVAL;  /* filter index is out of range */
2603
2604         E1000_WRITE_REG(hw, E1000_TTQF(index), 0);
2605         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2606         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2607         return 0;
2608 }
2609
2610 /*
2611  * get a 2tuple filter
2612  *
2613  * @param
2614  * dev: Pointer to struct rte_eth_dev.
2615  * index: the index the filter allocates.
2616  * filter: ponter to the filter that returns.
2617  * *rx_queue: pointer of the queue id the filter assigned to.
2618  *
2619  * @return
2620  *    - On success, zero.
2621  *    - On failure, a negative value.
2622  */
2623 static int
2624 eth_igb_get_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2625                         struct rte_2tuple_filter *filter, uint16_t *rx_queue)
2626 {
2627         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2628         uint32_t imir, ttqf, imir_ext;
2629
2630         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2631
2632         if (index >= E1000_MAX_TTQF_FILTERS)
2633                 return -EINVAL;  /* filter index is out of range. */
2634
2635         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2636         if (ttqf & E1000_TTQF_QUEUE_ENABLE) {
2637                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2638                 filter->protocol = ttqf & E1000_TTQF_PROTOCOL_MASK;
2639                 filter->protocol_mask = (ttqf & E1000_TTQF_MASK_ENABLE) ? 1 : 0;
2640                 *rx_queue = (ttqf & E1000_TTQF_RX_QUEUE_MASK) >>
2641                                 E1000_TTQF_QUEUE_SHIFT;
2642                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2643                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2644                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2645                         E1000_IMIR_PRIORITY_SHIFT;
2646
2647                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2648                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2649                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2650                                 filter->tcp_flags |= TCP_UGR_FLAG;
2651                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2652                                 filter->tcp_flags |= TCP_ACK_FLAG;
2653                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2654                                 filter->tcp_flags |= TCP_PSH_FLAG;
2655                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2656                                 filter->tcp_flags |= TCP_RST_FLAG;
2657                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2658                                 filter->tcp_flags |= TCP_SYN_FLAG;
2659                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2660                                 filter->tcp_flags |= TCP_FIN_FLAG;
2661                 } else
2662                         filter->tcp_flags = 0;
2663                 return 0;
2664         }
2665         return -ENOENT;
2666 }
2667
2668 /*
2669  * add a flex filter
2670  *
2671  * @param
2672  * dev: Pointer to struct rte_eth_dev.
2673  * index: the index the filter allocates.
2674  * filter: ponter to the filter that will be added.
2675  * rx_queue: the queue id the filter assigned to.
2676  *
2677  * @return
2678  *    - On success, zero.
2679  *     - On failure, a negative value.
2680  */
2681 static int
2682 eth_igb_add_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2683                         struct rte_flex_filter *filter, uint16_t rx_queue)
2684 {
2685         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2686         uint32_t wufc, en_bits = 0;
2687         uint32_t queueing = 0;
2688         uint32_t reg_off = 0;
2689         uint8_t i, j = 0;
2690
2691         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2692
2693         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2694                 return -EINVAL;  /* filter index is out of range. */
2695
2696         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN ||
2697                 filter->len % 8 != 0 ||
2698                 filter->priority > E1000_MAX_FLEX_FILTER_PRI)
2699                 return -EINVAL;
2700
2701         wufc = E1000_READ_REG(hw, E1000_WUFC);
2702         en_bits = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2703         if ((wufc & en_bits) == en_bits)
2704                 return -EINVAL;  /* the filter is in use. */
2705
2706         E1000_WRITE_REG(hw, E1000_WUFC,
2707                 wufc | E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index));
2708
2709         j = 0;
2710         if (index < E1000_MAX_FHFT)
2711                 reg_off = E1000_FHFT(index);
2712         else
2713                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2714
2715         for (i = 0; i < 16; i++) {
2716                 E1000_WRITE_REG(hw, reg_off + i*4*4, filter->dwords[j]);
2717                 E1000_WRITE_REG(hw, reg_off + (i*4+1)*4, filter->dwords[++j]);
2718                 E1000_WRITE_REG(hw, reg_off + (i*4+2)*4,
2719                                 (uint32_t)filter->mask[i]);
2720                 ++j;
2721         }
2722         queueing |= filter->len |
2723                 (rx_queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2724                 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2725         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET, queueing);
2726         return 0;
2727 }
2728
2729 /*
2730  * remove a flex filter
2731  *
2732  * @param
2733  * dev: Pointer to struct rte_eth_dev.
2734  * index: the index the filter allocates.
2735  *
2736  * @return
2737  *    - On success, zero.
2738  *    - On failure, a negative value.
2739  */
2740 static int
2741 eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
2742                                 uint16_t index)
2743 {
2744         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2745         uint32_t wufc, reg_off = 0;
2746         uint8_t i;
2747
2748         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2749
2750         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2751                 return -EINVAL;  /* filter index is out of range. */
2752
2753         wufc = E1000_READ_REG(hw, E1000_WUFC);
2754         E1000_WRITE_REG(hw, E1000_WUFC, wufc & (~(E1000_WUFC_FLX0 << index)));
2755
2756         if (index < E1000_MAX_FHFT)
2757                 reg_off = E1000_FHFT(index);
2758         else
2759                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2760
2761         for (i = 0; i < 64; i++)
2762                 E1000_WRITE_REG(hw, reg_off + i*4, 0);
2763         return 0;
2764 }
2765
2766 /*
2767  * get a flex filter
2768  *
2769  * @param
2770  * dev: Pointer to struct rte_eth_dev.
2771  * index: the index the filter allocates.
2772  * filter: ponter to the filter that returns.
2773  * *rx_queue: the pointer of the queue id the filter assigned to.
2774  *
2775  * @return
2776  *    - On success, zero.
2777  *    - On failure, a negative value.
2778  */
2779 static int
2780 eth_igb_get_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2781                         struct rte_flex_filter *filter, uint16_t *rx_queue)
2782 {
2783         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784         uint32_t wufc, queueing, wufc_en = 0;
2785         uint8_t i, j;
2786
2787         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2788
2789         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2790                 return -EINVAL;  /* filter index is out of range. */
2791
2792         wufc = E1000_READ_REG(hw, E1000_WUFC);
2793         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2794
2795         if ((wufc & wufc_en) == wufc_en) {
2796                 uint32_t reg_off = 0;
2797                 j = 0;
2798                 if (index < E1000_MAX_FHFT)
2799                         reg_off = E1000_FHFT(index);
2800                 else
2801                         reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2802
2803                 for (i = 0; i < 16; i++, j = i * 2) {
2804                         filter->dwords[j] =
2805                                 E1000_READ_REG(hw, reg_off + i*4*4);
2806                         filter->dwords[j+1] =
2807                                 E1000_READ_REG(hw, reg_off + (i*4+1)*4);
2808                         filter->mask[i] =
2809                                 E1000_READ_REG(hw, reg_off + (i*4+2)*4);
2810                 }
2811                 queueing = E1000_READ_REG(hw,
2812                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2813                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2814                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2815                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
2816                 *rx_queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2817                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2818                 return 0;
2819         }
2820         return -ENOENT;
2821 }
2822
2823 /*
2824  * add a 5tuple filter
2825  *
2826  * @param
2827  * dev: Pointer to struct rte_eth_dev.
2828  * index: the index the filter allocates.
2829  * filter: ponter to the filter that will be added.
2830  * rx_queue: the queue id the filter assigned to.
2831  *
2832  * @return
2833  *    - On success, zero.
2834  *    - On failure, a negative value.
2835  */
2836 static int
2837 eth_igb_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2838                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
2839 {
2840         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841         uint32_t ftqf, spqf = 0;
2842         uint32_t imir = 0;
2843         uint32_t imir_ext = 0;
2844
2845         if (hw->mac.type != e1000_82576)
2846                 return -ENOSYS;
2847
2848         if (index >= E1000_MAX_FTQF_FILTERS ||
2849                 rx_queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2850                 return -EINVAL;  /* filter index is out of range. */
2851
2852         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2853         if (ftqf & E1000_FTQF_QUEUE_ENABLE)
2854                 return -EINVAL;  /* filter index is in use. */
2855
2856         ftqf = 0;
2857         ftqf |= filter->protocol & E1000_FTQF_PROTOCOL_MASK;
2858         if (filter->src_ip_mask == 1) /* 1b means not compare. */
2859                 ftqf |= E1000_FTQF_SOURCE_ADDR_MASK;
2860         if (filter->dst_ip_mask == 1)
2861                 ftqf |= E1000_FTQF_DEST_ADDR_MASK;
2862         if (filter->src_port_mask == 1)
2863                 ftqf |= E1000_FTQF_SOURCE_PORT_MASK;
2864         if (filter->protocol_mask == 1)
2865                 ftqf |= E1000_FTQF_PROTOCOL_COMP_MASK;
2866         ftqf |= (rx_queue << E1000_FTQF_QUEUE_SHIFT) & E1000_FTQF_QUEUE_MASK;
2867         ftqf |= E1000_FTQF_VF_MASK_EN;
2868         ftqf |= E1000_FTQF_QUEUE_ENABLE;
2869         E1000_WRITE_REG(hw, E1000_FTQF(index), ftqf);
2870         E1000_WRITE_REG(hw, E1000_DAQF(index), filter->dst_ip);
2871         E1000_WRITE_REG(hw, E1000_SAQF(index), filter->src_ip);
2872
2873         spqf |= filter->src_port & E1000_SPQF_SRCPORT;
2874         E1000_WRITE_REG(hw, E1000_SPQF(index), spqf);
2875
2876         imir |= (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2877         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2878                 imir |= E1000_IMIR_PORT_BP;
2879         else
2880                 imir &= ~E1000_IMIR_PORT_BP;
2881         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2882
2883         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2884         /* tcp flags bits setting. */
2885         if (filter->tcp_flags & TCP_FLAG_ALL) {
2886                 if (filter->tcp_flags & TCP_UGR_FLAG)
2887                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2888                 if (filter->tcp_flags & TCP_ACK_FLAG)
2889                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2890                 if (filter->tcp_flags & TCP_PSH_FLAG)
2891                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2892                 if (filter->tcp_flags & TCP_RST_FLAG)
2893                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2894                 if (filter->tcp_flags & TCP_SYN_FLAG)
2895                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2896                 if (filter->tcp_flags & TCP_FIN_FLAG)
2897                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2898         } else
2899                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2900         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2901         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2902         return 0;
2903 }
2904
2905 /*
2906  * remove a 5tuple filter
2907  *
2908  * @param
2909  * dev: Pointer to struct rte_eth_dev.
2910  * index: the index the filter allocates
2911  *
2912  * @return
2913  *    - On success, zero.
2914  *    - On failure, a negative value.
2915  */
2916 static int
2917 eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
2918                                 uint16_t index)
2919 {
2920         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2921
2922         if (hw->mac.type != e1000_82576)
2923                 return -ENOSYS;
2924
2925         if (index >= E1000_MAX_FTQF_FILTERS)
2926                 return -EINVAL;  /* filter index is out of range. */
2927
2928         E1000_WRITE_REG(hw, E1000_FTQF(index), 0);
2929         E1000_WRITE_REG(hw, E1000_DAQF(index), 0);
2930         E1000_WRITE_REG(hw, E1000_SAQF(index), 0);
2931         E1000_WRITE_REG(hw, E1000_SPQF(index), 0);
2932         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2933         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2934         return 0;
2935 }
2936
2937 /*
2938  * get a 5tuple filter
2939  *
2940  * @param
2941  * dev: Pointer to struct rte_eth_dev.
2942  * index: the index the filter allocates
2943  * filter: ponter to the filter that returns
2944  * *rx_queue: pointer of the queue id the filter assigned to
2945  *
2946  * @return
2947  *    - On success, zero.
2948  *    - On failure, a negative value.
2949  */
2950 static int
2951 eth_igb_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2952                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
2953 {
2954         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2955         uint32_t spqf, ftqf, imir, imir_ext;
2956
2957         if (hw->mac.type != e1000_82576)
2958                 return -ENOSYS;
2959
2960         if (index >= E1000_MAX_FTQF_FILTERS)
2961                 return -EINVAL;  /* filter index is out of range. */
2962
2963         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2964         if (ftqf & E1000_FTQF_QUEUE_ENABLE) {
2965                 filter->src_ip_mask =
2966                         (ftqf & E1000_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
2967                 filter->dst_ip_mask =
2968                         (ftqf & E1000_FTQF_DEST_ADDR_MASK) ? 1 : 0;
2969                 filter->src_port_mask =
2970                         (ftqf & E1000_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
2971                 filter->protocol_mask =
2972                         (ftqf & E1000_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
2973                 filter->protocol =
2974                         (uint8_t)ftqf & E1000_FTQF_PROTOCOL_MASK;
2975                 *rx_queue = (uint16_t)((ftqf & E1000_FTQF_QUEUE_MASK) >>
2976                                 E1000_FTQF_QUEUE_SHIFT);
2977
2978                 spqf = E1000_READ_REG(hw, E1000_SPQF(index));
2979                 filter->src_port = spqf & E1000_SPQF_SRCPORT;
2980
2981                 filter->dst_ip = E1000_READ_REG(hw, E1000_DAQF(index));
2982                 filter->src_ip = E1000_READ_REG(hw, E1000_SAQF(index));
2983
2984                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2985                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2986                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2987                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2988                         E1000_IMIR_PRIORITY_SHIFT;
2989
2990                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2991                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2992                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2993                                 filter->tcp_flags |= TCP_UGR_FLAG;
2994                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2995                                 filter->tcp_flags |= TCP_ACK_FLAG;
2996                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2997                                 filter->tcp_flags |= TCP_PSH_FLAG;
2998                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2999                                 filter->tcp_flags |= TCP_RST_FLAG;
3000                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
3001                                 filter->tcp_flags |= TCP_SYN_FLAG;
3002                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
3003                                 filter->tcp_flags |= TCP_FIN_FLAG;
3004                 } else
3005                         filter->tcp_flags = 0;
3006                 return 0;
3007         }
3008         return -ENOENT;
3009 }
3010
3011 static int
3012 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3013 {
3014         uint32_t rctl;
3015         struct e1000_hw *hw;
3016         struct rte_eth_dev_info dev_info;
3017         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3018                                      VLAN_TAG_SIZE);
3019
3020         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3021
3022 #ifdef RTE_LIBRTE_82571_SUPPORT
3023         /* XXX: not bigger than max_rx_pktlen */
3024         if (hw->mac.type == e1000_82571)
3025                 return -ENOTSUP;
3026 #endif
3027         eth_igb_infos_get(dev, &dev_info);
3028
3029         /* check that mtu is within the allowed range */
3030         if ((mtu < ETHER_MIN_MTU) ||
3031             (frame_size > dev_info.max_rx_pktlen))
3032                 return -EINVAL;
3033
3034         /* refuse mtu that requires the support of scattered packets when this
3035          * feature has not been enabled before. */
3036         if (!dev->data->scattered_rx &&
3037             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3038                 return -EINVAL;
3039
3040         rctl = E1000_READ_REG(hw, E1000_RCTL);
3041
3042         /* switch to jumbo mode if needed */
3043         if (frame_size > ETHER_MAX_LEN) {
3044                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3045                 rctl |= E1000_RCTL_LPE;
3046         } else {
3047                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3048                 rctl &= ~E1000_RCTL_LPE;
3049         }
3050         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3051
3052         /* update max frame size */
3053         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3054
3055         E1000_WRITE_REG(hw, E1000_RLPML,
3056                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3057
3058         return 0;
3059 }
3060
3061 static struct rte_driver pmd_igb_drv = {
3062         .type = PMD_PDEV,
3063         .init = rte_igb_pmd_init,
3064 };
3065
3066 static struct rte_driver pmd_igbvf_drv = {
3067         .type = PMD_PDEV,
3068         .init = rte_igbvf_pmd_init,
3069 };
3070
3071 PMD_REGISTER_DRIVER(pmd_igb_drv);
3072 PMD_REGISTER_DRIVER(pmd_igbvf_drv);