lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #include <sys/queue.h>
  36 #include <stdio.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40
  41 #include <rte_common.h>
  42 #include <rte_interrupts.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_tailq.h>
  52 #include <rte_eal.h>
  53 #include <rte_atomic.h>
  54 #include <rte_malloc.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 static int  eth_igb_configure(struct rte_eth_dev *dev);
  61 static int  eth_igb_start(struct rte_eth_dev *dev);
  62 static void eth_igb_stop(struct rte_eth_dev *dev);
  63 static void eth_igb_close(struct rte_eth_dev *dev);
  64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  68 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  69                                 int wait_to_complete);
  70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  71                                 struct rte_eth_stats *rte_stats);
  72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  74                                 struct rte_eth_dev_info *dev_info);
  75 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  76                                 struct rte_eth_fc_conf *fc_conf);
  77 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  78 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  79 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  80 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  81                                                         void *param);
  82 static int  igb_hardware_init(struct e1000_hw *hw);
  83 static void igb_hw_control_acquire(struct e1000_hw *hw);
  84 static void igb_hw_control_release(struct e1000_hw *hw);
  85 static void igb_init_manageability(struct e1000_hw *hw);
  86 static void igb_release_manageability(struct e1000_hw *hw);
  87
  88 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  89                 uint16_t vlan_id, int on);
  90 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
  91 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  92
  93 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  94 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  95 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  96 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  97 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
  98 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
  99
 100 static int eth_igb_led_on(struct rte_eth_dev *dev);
 101 static int eth_igb_led_off(struct rte_eth_dev *dev);
 102
 103 static void igb_intr_disable(struct e1000_hw *hw);
 104 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 105 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 106                 struct ether_addr *mac_addr,
 107                 uint32_t index, uint32_t pool);
 108 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 109
 110 static void igbvf_intr_disable(struct e1000_hw *hw);
 111 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 112 static int igbvf_dev_start(struct rte_eth_dev *dev);
 113 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 114 static void igbvf_dev_close(struct rte_eth_dev *dev);
 115 static int eth_igbvf_link_update(struct e1000_hw *hw);
 116 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 117 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 118 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 119                 uint16_t vlan_id, int on);
 120 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 121 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 122
 123 /*
 124  * Define VF Stats MACRO for Non "cleared on read" register
 125  */
 126 #define UPDATE_VF_STAT(reg, last, cur)            \
 127 {                                                 \
 128         u32 latest = E1000_READ_REG(hw, reg);     \
 129         cur += latest - last;                     \
 130         last = latest;                            \
 131 }
 132
 133
 134 #define IGB_FC_PAUSE_TIME 0x0680
 135 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 136 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 137
 138 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 139
 140 /*
 141  * The set of PCI devices this driver supports
 142  */
 143 static struct rte_pci_id pci_id_igb_map[] = {
 144
 145 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 146 #include "rte_pci_dev_ids.h"
 147
 148 {.device_id = 0},
 149 };
 150
 151 /*
 152  * The set of PCI devices this driver supports (for 82576&I350 VF)
 153  */
 154 static struct rte_pci_id pci_id_igbvf_map[] = {
 155
 156 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 157 #include "rte_pci_dev_ids.h"
 158
 159 {.device_id = 0},
 160 };
 161
 162 static struct eth_dev_ops eth_igb_ops = {
 163         .dev_configure        = eth_igb_configure,
 164         .dev_start            = eth_igb_start,
 165         .dev_stop             = eth_igb_stop,
 166         .dev_close            = eth_igb_close,
 167         .promiscuous_enable   = eth_igb_promiscuous_enable,
 168         .promiscuous_disable  = eth_igb_promiscuous_disable,
 169         .allmulticast_enable  = eth_igb_allmulticast_enable,
 170         .allmulticast_disable = eth_igb_allmulticast_disable,
 171         .link_update          = eth_igb_link_update,
 172         .stats_get            = eth_igb_stats_get,
 173         .stats_reset          = eth_igb_stats_reset,
 174         .dev_infos_get        = eth_igb_infos_get,
 175         .vlan_filter_set      = eth_igb_vlan_filter_set,
 176         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 177         .vlan_offload_set     = eth_igb_vlan_offload_set,
 178         .rx_queue_setup       = eth_igb_rx_queue_setup,
 179         .rx_queue_release     = eth_igb_rx_queue_release,
 180         .tx_queue_setup       = eth_igb_tx_queue_setup,
 181         .tx_queue_release     = eth_igb_tx_queue_release,
 182         .dev_led_on           = eth_igb_led_on,
 183         .dev_led_off          = eth_igb_led_off,
 184         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 185         .mac_addr_add         = eth_igb_rar_set,
 186         .mac_addr_remove      = eth_igb_rar_clear,
 187 };
 188
 189 /*
 190  * dev_ops for virtual function, bare necessities for basic vf
 191  * operation have been implemented
 192  */
 193 static struct eth_dev_ops igbvf_eth_dev_ops = {
 194         .dev_configure        = igbvf_dev_configure,
 195         .dev_start            = igbvf_dev_start,
 196         .dev_stop             = igbvf_dev_stop,
 197         .dev_close            = igbvf_dev_close,
 198         .link_update          = eth_igb_link_update,
 199         .stats_get            = eth_igbvf_stats_get,
 200         .stats_reset          = eth_igbvf_stats_reset,
 201         .vlan_filter_set      = igbvf_vlan_filter_set,
 202         .dev_infos_get        = eth_igb_infos_get,
 203         .rx_queue_setup       = eth_igb_rx_queue_setup,
 204         .rx_queue_release     = eth_igb_rx_queue_release,
 205         .tx_queue_setup       = eth_igb_tx_queue_setup,
 206         .tx_queue_release     = eth_igb_tx_queue_release,
 207 };
 208
 209 /**
 210  * Atomically reads the link status information from global
 211  * structure rte_eth_dev.
 212  *
 213  * @param dev
 214  *   - Pointer to the structure rte_eth_dev to read from.
 215  *   - Pointer to the buffer to be saved with the link status.
 216  *
 217  * @return
 218  *   - On success, zero.
 219  *   - On failure, negative value.
 220  */
 221 static inline int
 222 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 223                                 struct rte_eth_link *link)
 224 {
 225         struct rte_eth_link *dst = link;
 226         struct rte_eth_link *src = &(dev->data->dev_link);
 227
 228         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 229                                         *(uint64_t *)src) == 0)
 230                 return -1;
 231
 232         return 0;
 233 }
 234
 235 /**
 236  * Atomically writes the link status information into global
 237  * structure rte_eth_dev.
 238  *
 239  * @param dev
 240  *   - Pointer to the structure rte_eth_dev to read from.
 241  *   - Pointer to the buffer to be saved with the link status.
 242  *
 243  * @return
 244  *   - On success, zero.
 245  *   - On failure, negative value.
 246  */
 247 static inline int
 248 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 249                                 struct rte_eth_link *link)
 250 {
 251         struct rte_eth_link *dst = &(dev->data->dev_link);
 252         struct rte_eth_link *src = link;
 253
 254         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 255                                         *(uint64_t *)src) == 0)
 256                 return -1;
 257
 258         return 0;
 259 }
 260
 261 static inline void
 262 igb_intr_enable(struct rte_eth_dev *dev)
 263 {
 264         struct e1000_interrupt *intr =
 265                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 266         struct e1000_hw *hw =
 267                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 268
 269         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 270         E1000_WRITE_FLUSH(hw);
 271 }
 272
 273 static void
 274 igb_intr_disable(struct e1000_hw *hw)
 275 {
 276         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 277         E1000_WRITE_FLUSH(hw);
 278 }
 279
 280 static void
 281 igb_identify_hardware(struct rte_eth_dev *dev)
 282 {
 283         struct e1000_hw *hw =
 284                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 285
 286         hw->vendor_id = dev->pci_dev->id.vendor_id;
 287         hw->device_id = dev->pci_dev->id.device_id;
 288         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 289         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 290
 291         e1000_set_mac_type(hw);
 292
 293         /* need to check if it is a vf device below */
 294 }
 295
 296 static int
 297 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 298                    struct rte_eth_dev *eth_dev)
 299 {
 300         int error = 0;
 301         struct rte_pci_device *pci_dev;
 302         struct e1000_hw *hw =
 303                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 304         struct e1000_vfta * shadow_vfta =
 305                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 306
 307         pci_dev = eth_dev->pci_dev;
 308         eth_dev->dev_ops = &eth_igb_ops;
 309         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 310         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 311
 312         /* for secondary processes, we don't initialise any further as primary
 313          * has already done this work. Only check we don't need a different
 314          * RX function */
 315         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 316                 if (eth_dev->data->scattered_rx)
 317                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 318                 return 0;
 319         }
 320
 321         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 322
 323         igb_identify_hardware(eth_dev);
 324         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 325                 error = -EIO;
 326                 goto err_late;
 327         }
 328
 329         e1000_get_bus_info(hw);
 330
 331         hw->mac.autoneg = 1;
 332         hw->phy.autoneg_wait_to_complete = 0;
 333         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 334
 335         /* Copper options */
 336         if (hw->phy.media_type == e1000_media_type_copper) {
 337                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 338                 hw->phy.disable_polarity_correction = 0;
 339                 hw->phy.ms_type = e1000_ms_hw_default;
 340         }
 341
 342         /*
 343          * Start from a known state, this is important in reading the nvm
 344          * and mac from that.
 345          */
 346         e1000_reset_hw(hw);
 347
 348         /* Make sure we have a good EEPROM before we read from it */
 349         if (e1000_validate_nvm_checksum(hw) < 0) {
 350                 /*
 351                  * Some PCI-E parts fail the first check due to
 352                  * the link being in sleep state, call it again,
 353                  * if it fails a second time its a real issue.
 354                  */
 355                 if (e1000_validate_nvm_checksum(hw) < 0) {
 356                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 357                         error = -EIO;
 358                         goto err_late;
 359                 }
 360         }
 361
 362         /* Read the permanent MAC address out of the EEPROM */
 363         if (e1000_read_mac_addr(hw) != 0) {
 364                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 365                 error = -EIO;
 366                 goto err_late;
 367         }
 368
 369         /* Allocate memory for storing MAC addresses */
 370         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 371                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 372         if (eth_dev->data->mac_addrs == NULL) {
 373                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 374                                                 "store MAC addresses",
 375                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 376                 error = -ENOMEM;
 377                 goto err_late;
 378         }
 379
 380         /* Copy the permanent MAC address */
 381         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 382
 383         /* initialize the vfta */
 384         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 385
 386         /* Now initialize the hardware */
 387         if (igb_hardware_init(hw) != 0) {
 388                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 389                 rte_free(eth_dev->data->mac_addrs);
 390                 eth_dev->data->mac_addrs = NULL;
 391                 error = -ENODEV;
 392                 goto err_late;
 393         }
 394         hw->mac.get_link_status = 1;
 395
 396         /* Indicate SOL/IDER usage */
 397         if (e1000_check_reset_block(hw) < 0) {
 398                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 399                                         "SOL/IDER session");
 400         }
 401
 402         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 403                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 404                      pci_dev->id.device_id);
 405
 406         rte_intr_callback_register(&(pci_dev->intr_handle),
 407                 eth_igb_interrupt_handler, (void *)eth_dev);
 408
 409         /* enable uio intr after callback register */
 410         rte_intr_enable(&(pci_dev->intr_handle));
 411
 412         /* enable support intr */
 413         igb_intr_enable(eth_dev);
 414
 415         return 0;
 416
 417 err_late:
 418         igb_hw_control_release(hw);
 419
 420         return (error);
 421 }
 422
 423 /*
 424  * Virtual Function device init
 425  */
 426 static int
 427 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 428                 struct rte_eth_dev *eth_dev)
 429 {
 430         struct rte_pci_device *pci_dev;
 431         struct e1000_hw *hw =
 432                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 433         int diag;
 434
 435         PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 436
 437         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 438         pci_dev = eth_dev->pci_dev;
 439
 440         hw->device_id = pci_dev->id.device_id;
 441         hw->vendor_id = pci_dev->id.vendor_id;
 442         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 443
 444         /* Initialize the shared code */
 445         diag = e1000_setup_init_funcs(hw, TRUE);
 446         if (diag != 0) {
 447                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 448                         diag);
 449                 return -EIO;
 450         }
 451
 452         /* init_mailbox_params */
 453         hw->mbx.ops.init_params(hw);
 454
 455         /* Disable the interrupts for VF */
 456         igbvf_intr_disable(hw);
 457
 458         diag = hw->mac.ops.reset_hw(hw);
 459
 460         /* Allocate memory for storing MAC addresses */
 461         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 462                 hw->mac.rar_entry_count, 0);
 463         if (eth_dev->data->mac_addrs == NULL) {
 464                 PMD_INIT_LOG(ERR,
 465                         "Failed to allocate %d bytes needed to store MAC "
 466                         "addresses",
 467                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 468                 return -ENOMEM;
 469         }
 470         /* Copy the permanent MAC address */
 471         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 472                         &eth_dev->data->mac_addrs[0]);
 473
 474         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
 475                         "mac.type=%s\n",
 476                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 477                         pci_dev->id.device_id,
 478                         "igb_mac_82576_vf");
 479
 480         return 0;
 481 }
 482
 483 static struct eth_driver rte_igb_pmd = {
 484         {
 485                 .name = "rte_igb_pmd",
 486                 .id_table = pci_id_igb_map,
 487 #ifdef RTE_EAL_UNBIND_PORTS
 488                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 489 #endif
 490         },
 491         .eth_dev_init = eth_igb_dev_init,
 492         .dev_private_size = sizeof(struct e1000_adapter),
 493 };
 494
 495 /*
 496  * virtual function driver struct
 497  */
 498 static struct eth_driver rte_igbvf_pmd = {
 499         {
 500                 .name = "rte_igbvf_pmd",
 501                 .id_table = pci_id_igbvf_map,
 502 #ifdef RTE_EAL_UNBIND_PORTS
 503                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 504 #endif
 505         },
 506         .eth_dev_init = eth_igbvf_dev_init,
 507         .dev_private_size = sizeof(struct e1000_adapter),
 508 };
 509
 510 int
 511 rte_igb_pmd_init(void)
 512 {
 513         rte_eth_driver_register(&rte_igb_pmd);
 514         return 0;
 515 }
 516
 517 /*
 518  * VF Driver initialization routine.
 519  * Invoked one at EAL init time.
 520  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 521  */
 522 int
 523 rte_igbvf_pmd_init(void)
 524 {
 525         DEBUGFUNC("rte_igbvf_pmd_init");
 526
 527         rte_eth_driver_register(&rte_igbvf_pmd);
 528         return (0);
 529 }
 530
 531 static int
 532 eth_igb_configure(struct rte_eth_dev *dev)
 533 {
 534         struct e1000_interrupt *intr =
 535                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 536
 537         PMD_INIT_LOG(DEBUG, ">>");
 538
 539         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 540
 541         PMD_INIT_LOG(DEBUG, "<<");
 542
 543         return (0);
 544 }
 545
 546 static int
 547 eth_igb_start(struct rte_eth_dev *dev)
 548 {
 549         struct e1000_hw *hw =
 550                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 551         int ret, i, mask;
 552
 553         PMD_INIT_LOG(DEBUG, ">>");
 554
 555         /* Power up the phy. Needed to make the link go Up */
 556         e1000_power_up_phy(hw);
 557
 558         /*
 559          * Packet Buffer Allocation (PBA)
 560          * Writing PBA sets the receive portion of the buffer
 561          * the remainder is used for the transmit buffer.
 562          */
 563         if (hw->mac.type == e1000_82575) {
 564                 uint32_t pba;
 565
 566                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 567                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 568         }
 569
 570         /* Put the address into the Receive Address Array */
 571         e1000_rar_set(hw, hw->mac.addr, 0);
 572
 573         /* Initialize the hardware */
 574         if (igb_hardware_init(hw)) {
 575                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 576                 return (-EIO);
 577         }
 578
 579         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 580
 581         /* Configure for OS presence */
 582         igb_init_manageability(hw);
 583
 584         eth_igb_tx_init(dev);
 585
 586         /* This can fail when allocating mbufs for descriptor rings */
 587         ret = eth_igb_rx_init(dev);
 588         if (ret) {
 589                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 590                 igb_dev_clear_queues(dev);
 591                 return ret;
 592         }
 593
 594         e1000_clear_hw_cntrs_base_generic(hw);
 595
 596         /*
 597          * VLAN Offload Settings
 598          */
 599         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 600                         ETH_VLAN_EXTEND_MASK;
 601         eth_igb_vlan_offload_set(dev, mask);
 602
 603         /*
 604          * Configure the Interrupt Moderation register (EITR) with the maximum
 605          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 606          * spurious [DMA] memory updates of RX and TX ring descriptors.
 607          *
 608          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 609          * spurious memory updates per second should be expected.
 610          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 611          *
 612          * Because interrupts are not used at all, the MSI-X is not activated
 613          * and interrupt moderation is controlled by EITR[0].
 614          *
 615          * Note that having [almost] disabled memory updates of RX and TX ring
 616          * descriptors through the Interrupt Moderation mechanism, memory
 617          * updates of ring descriptors are now moderated by the configurable
 618          * value of Write-Back Threshold registers.
 619          */
 620         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 621                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 622                 uint32_t ivar;
 623
 624                 /* Enable all RX & TX queues in the IVAR registers */
 625                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 626                 for (i = 0; i < 8; i++)
 627                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 628
 629                 /* Configure EITR with the maximum possible value (0xFFFF) */
 630                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 631         }
 632
 633         /* Setup link speed and duplex */
 634         switch (dev->data->dev_conf.link_speed) {
 635         case ETH_LINK_SPEED_AUTONEG:
 636                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 637                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 638                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 639                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 640                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 641                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 642                 else
 643                         goto error_invalid_config;
 644                 break;
 645         case ETH_LINK_SPEED_10:
 646                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 647                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 648                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 649                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 650                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 651                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 652                 else
 653                         goto error_invalid_config;
 654                 break;
 655         case ETH_LINK_SPEED_100:
 656                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 657                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 658                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 659                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 660                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 661                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 662                 else
 663                         goto error_invalid_config;
 664                 break;
 665         case ETH_LINK_SPEED_1000:
 666                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 667                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 668                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 669                 else
 670                         goto error_invalid_config;
 671                 break;
 672         case ETH_LINK_SPEED_10000:
 673         default:
 674                 goto error_invalid_config;
 675         }
 676         e1000_setup_link(hw);
 677
 678         /* check if lsc interrupt feature is enabled */
 679         if (dev->data->dev_conf.intr_conf.lsc != 0)
 680                 ret = eth_igb_lsc_interrupt_setup(dev);
 681
 682         /* resume enabled intr since hw reset */
 683         igb_intr_enable(dev);
 684
 685         PMD_INIT_LOG(DEBUG, "<<");
 686
 687         return (0);
 688
 689 error_invalid_config:
 690         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 691                         dev->data->dev_conf.link_speed,
 692                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 693         igb_dev_clear_queues(dev);
 694         return (-EINVAL);
 695 }
 696
 697 /*********************************************************************
 698  *
 699  *  This routine disables all traffic on the adapter by issuing a
 700  *  global reset on the MAC.
 701  *
 702  **********************************************************************/
 703 static void
 704 eth_igb_stop(struct rte_eth_dev *dev)
 705 {
 706         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 707         struct rte_eth_link link;
 708
 709         igb_intr_disable(hw);
 710         e1000_reset_hw(hw);
 711         E1000_WRITE_REG(hw, E1000_WUC, 0);
 712
 713         /* Power down the phy. Needed to make the link go Down */
 714         e1000_power_down_phy(hw);
 715
 716         igb_dev_clear_queues(dev);
 717
 718         /* clear the recorded link status */
 719         memset(&link, 0, sizeof(link));
 720         rte_igb_dev_atomic_write_link_status(dev, &link);
 721 }
 722
 723 static void
 724 eth_igb_close(struct rte_eth_dev *dev)
 725 {
 726         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 727         struct rte_eth_link link;
 728
 729         eth_igb_stop(dev);
 730         e1000_phy_hw_reset(hw);
 731         igb_release_manageability(hw);
 732         igb_hw_control_release(hw);
 733
 734         igb_dev_clear_queues(dev);
 735
 736         memset(&link, 0, sizeof(link));
 737         rte_igb_dev_atomic_write_link_status(dev, &link);
 738 }
 739
 740 static int
 741 igb_get_rx_buffer_size(struct e1000_hw *hw)
 742 {
 743         uint32_t rx_buf_size;
 744         if (hw->mac.type == e1000_82576) {
 745                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 746         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 747                 /* PBS needs to be translated according to a lookup table */
 748                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 749                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 750                 rx_buf_size = (rx_buf_size << 10);
 751         } else if (hw->mac.type == e1000_i210) {
 752                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 753         } else {
 754                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 755         }
 756
 757         return rx_buf_size;
 758 }
 759
 760 /*********************************************************************
 761  *
 762  *  Initialize the hardware
 763  *
 764  **********************************************************************/
 765 static int
 766 igb_hardware_init(struct e1000_hw *hw)
 767 {
 768         uint32_t rx_buf_size;
 769         int diag;
 770
 771         /* Let the firmware know the OS is in control */
 772         igb_hw_control_acquire(hw);
 773
 774         /*
 775          * These parameters control the automatic generation (Tx) and
 776          * response (Rx) to Ethernet PAUSE frames.
 777          * - High water mark should allow for at least two standard size (1518)
 778          *   frames to be received after sending an XOFF.
 779          * - Low water mark works best when it is very near the high water mark.
 780          *   This allows the receiver to restart by sending XON when it has
 781          *   drained a bit. Here we use an arbitary value of 1500 which will
 782          *   restart after one full frame is pulled from the buffer. There
 783          *   could be several smaller frames in the buffer and if so they will
 784          *   not trigger the XON until their total number reduces the buffer
 785          *   by 1500.
 786          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 787          */
 788         rx_buf_size = igb_get_rx_buffer_size(hw);
 789
 790         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
 791         hw->fc.low_water = hw->fc.high_water - 1500;
 792         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
 793         hw->fc.send_xon = 1;
 794
 795         /* Set Flow control, use the tunable location if sane */
 796         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
 797                 hw->fc.requested_mode = igb_fc_setting;
 798         else
 799                 hw->fc.requested_mode = e1000_fc_none;
 800
 801         /* Issue a global reset */
 802         e1000_reset_hw(hw);
 803         E1000_WRITE_REG(hw, E1000_WUC, 0);
 804
 805         diag = e1000_init_hw(hw);
 806         if (diag < 0)
 807                 return (diag);
 808
 809         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 810         e1000_get_phy_info(hw);
 811         e1000_check_for_link(hw);
 812
 813         return (0);
 814 }
 815
 816 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
 817 static void
 818 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 819 {
 820         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 821         struct e1000_hw_stats *stats =
 822                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 823         int pause_frames;
 824
 825         if(hw->phy.media_type == e1000_media_type_copper ||
 826             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 827                 stats->symerrs +=
 828                     E1000_READ_REG(hw,E1000_SYMERRS);
 829                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 830         }
 831
 832         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 833         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 834         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 835         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 836
 837         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 838         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 839         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 840         stats->dc += E1000_READ_REG(hw, E1000_DC);
 841         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 842         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 843         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 844         /*
 845         ** For watchdog management we need to know if we have been
 846         ** paused during the last interval, so capture that here.
 847         */
 848         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 849         stats->xoffrxc += pause_frames;
 850         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 851         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 852         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 853         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 854         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 855         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 856         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 857         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 858         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 859         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 860         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 861         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 862
 863         /* For the 64-bit byte counters the low dword must be read first. */
 864         /* Both registers clear on the read of the high dword */
 865
 866         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 867         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 868         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 869         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 870
 871         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 872         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 873         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 874         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 875         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 876
 877         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 878         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 879
 880         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 881         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 882         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 883         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 884         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 885         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 886         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 887         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 888         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 889         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 890
 891         /* Interrupt Counts */
 892
 893         stats->iac += E1000_READ_REG(hw, E1000_IAC);
 894         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 895         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 896         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 897         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 898         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 899         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 900         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 901         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 902
 903         /* Host to Card Statistics */
 904
 905         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
 906         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
 907         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
 908         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
 909         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
 910         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
 911         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
 912         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
 913         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
 914         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
 915         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
 916         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
 917         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
 918         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
 919
 920         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 921         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 922         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 923         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 924         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 925         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 926
 927         if (rte_stats == NULL)
 928                 return;
 929
 930         /* Rx Errors */
 931         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 932             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 933
 934         /* Tx Errors */
 935         rte_stats->oerrors = stats->ecol + stats->latecol;
 936
 937         rte_stats->ipackets = stats->gprc;
 938         rte_stats->opackets = stats->gptc;
 939         rte_stats->ibytes   = stats->gorc;
 940         rte_stats->obytes   = stats->gotc;
 941 }
 942
 943 static void
 944 eth_igb_stats_reset(struct rte_eth_dev *dev)
 945 {
 946         struct e1000_hw_stats *hw_stats =
 947                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 948
 949         /* HW registers are cleared on read */
 950         eth_igb_stats_get(dev, NULL);
 951
 952         /* Reset software totals */
 953         memset(hw_stats, 0, sizeof(*hw_stats));
 954 }
 955
 956 static void
 957 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 958 {
 959         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 960         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
 961                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 962
 963         /* Good Rx packets, include VF loopback */
 964         UPDATE_VF_STAT(E1000_VFGPRC,
 965             hw_stats->last_gprc, hw_stats->gprc);
 966
 967         /* Good Rx octets, include VF loopback */
 968         UPDATE_VF_STAT(E1000_VFGORC,
 969             hw_stats->last_gorc, hw_stats->gorc);
 970
 971         /* Good Tx packets, include VF loopback */
 972         UPDATE_VF_STAT(E1000_VFGPTC,
 973             hw_stats->last_gptc, hw_stats->gptc);
 974
 975         /* Good Tx octets, include VF loopback */
 976         UPDATE_VF_STAT(E1000_VFGOTC,
 977             hw_stats->last_gotc, hw_stats->gotc);
 978
 979         /* Rx Multicst packets */
 980         UPDATE_VF_STAT(E1000_VFMPRC,
 981             hw_stats->last_mprc, hw_stats->mprc);
 982
 983         /* Good Rx loopback packets */
 984         UPDATE_VF_STAT(E1000_VFGPRLBC,
 985             hw_stats->last_gprlbc, hw_stats->gprlbc);
 986
 987         /* Good Rx loopback octets */
 988         UPDATE_VF_STAT(E1000_VFGORLBC,
 989             hw_stats->last_gorlbc, hw_stats->gorlbc);
 990
 991         /* Good Tx loopback packets */
 992         UPDATE_VF_STAT(E1000_VFGPTLBC,
 993             hw_stats->last_gptlbc, hw_stats->gptlbc);
 994
 995         /* Good Tx loopback octets */
 996         UPDATE_VF_STAT(E1000_VFGOTLBC,
 997             hw_stats->last_gotlbc, hw_stats->gotlbc);
 998
 999         if (rte_stats == NULL)
1000                 return;
1001
1002         memset(rte_stats, 0, sizeof(*rte_stats));
1003         rte_stats->ipackets = hw_stats->gprc;
1004         rte_stats->ibytes = hw_stats->gorc;
1005         rte_stats->opackets = hw_stats->gptc;
1006         rte_stats->obytes = hw_stats->gotc;
1007         rte_stats->imcasts = hw_stats->mprc;
1008         rte_stats->ilbpackets = hw_stats->gprlbc;
1009         rte_stats->ilbbytes = hw_stats->gorlbc;
1010         rte_stats->olbpackets = hw_stats->gptlbc;
1011         rte_stats->olbbytes = hw_stats->gotlbc;
1012
1013 }
1014
1015 static void
1016 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1017 {
1018         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1019                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1020
1021         /* Sync HW register to the last stats */
1022         eth_igbvf_stats_get(dev, NULL);
1023
1024         /* reset HW current stats*/
1025         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1026                offsetof(struct e1000_vf_stats, gprc));
1027
1028 }
1029
1030 static void
1031 eth_igb_infos_get(struct rte_eth_dev *dev,
1032                     struct rte_eth_dev_info *dev_info)
1033 {
1034         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1035
1036         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1037         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1038         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1039
1040         switch (hw->mac.type) {
1041         case e1000_82575:
1042                 dev_info->max_rx_queues = 4;
1043                 dev_info->max_tx_queues = 4;
1044                 break;
1045
1046         case e1000_82576:
1047                 dev_info->max_rx_queues = 16;
1048                 dev_info->max_tx_queues = 16;
1049                 break;
1050
1051         case e1000_82580:
1052                 dev_info->max_rx_queues = 8;
1053                 dev_info->max_tx_queues = 8;
1054                 break;
1055
1056         case e1000_i350:
1057                 dev_info->max_rx_queues = 8;
1058                 dev_info->max_tx_queues = 8;
1059                 break;
1060
1061         case e1000_i210:
1062                 dev_info->max_rx_queues = 4;
1063                 dev_info->max_tx_queues = 4;
1064                 break;
1065
1066         case e1000_vfadapt:
1067                 dev_info->max_rx_queues = 2;
1068                 dev_info->max_tx_queues = 2;
1069                 break;
1070
1071         case e1000_vfadapt_i350:
1072                 dev_info->max_rx_queues = 1;
1073                 dev_info->max_tx_queues = 1;
1074                 break;
1075
1076         default:
1077                 /* Should not happen */
1078                 dev_info->max_rx_queues = 0;
1079                 dev_info->max_tx_queues = 0;
1080         }
1081 }
1082
1083 /* return 0 means link status changed, -1 means not changed */
1084 static int
1085 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1086 {
1087         struct e1000_hw *hw =
1088                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1089         struct rte_eth_link link, old;
1090         int link_check, count;
1091
1092         link_check = 0;
1093         hw->mac.get_link_status = 1;
1094
1095         /* possible wait-to-complete in up to 9 seconds */
1096         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1097                 /* Read the real link status */
1098                 switch (hw->phy.media_type) {
1099                 case e1000_media_type_copper:
1100                         /* Do the work to read phy */
1101                         e1000_check_for_link(hw);
1102                         link_check = !hw->mac.get_link_status;
1103                         break;
1104
1105                 case e1000_media_type_fiber:
1106                         e1000_check_for_link(hw);
1107                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1108                                       E1000_STATUS_LU);
1109                         break;
1110
1111                 case e1000_media_type_internal_serdes:
1112                         e1000_check_for_link(hw);
1113                         link_check = hw->mac.serdes_has_link;
1114                         break;
1115
1116                 /* VF device is type_unknown */
1117                 case e1000_media_type_unknown:
1118                         eth_igbvf_link_update(hw);
1119                         link_check = !hw->mac.get_link_status;
1120                         break;
1121
1122                 default:
1123                         break;
1124                 }
1125                 if (link_check || wait_to_complete == 0)
1126                         break;
1127                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1128         }
1129         memset(&link, 0, sizeof(link));
1130         rte_igb_dev_atomic_read_link_status(dev, &link);
1131         old = link;
1132
1133         /* Now we check if a transition has happened */
1134         if (link_check) {
1135                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1136                                           &link.link_duplex);
1137                 link.link_status = 1;
1138         } else if (!link_check) {
1139                 link.link_speed = 0;
1140                 link.link_duplex = 0;
1141                 link.link_status = 0;
1142         }
1143         rte_igb_dev_atomic_write_link_status(dev, &link);
1144
1145         /* not changed */
1146         if (old.link_status == link.link_status)
1147                 return -1;
1148
1149         /* changed */
1150         return 0;
1151 }
1152
1153 /*
1154  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1155  * For ASF and Pass Through versions of f/w this means
1156  * that the driver is loaded.
1157  */
1158 static void
1159 igb_hw_control_acquire(struct e1000_hw *hw)
1160 {
1161         uint32_t ctrl_ext;
1162
1163         /* Let firmware know the driver has taken over */
1164         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1165         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1166 }
1167
1168 /*
1169  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1170  * For ASF and Pass Through versions of f/w this means that the
1171  * driver is no longer loaded.
1172  */
1173 static void
1174 igb_hw_control_release(struct e1000_hw *hw)
1175 {
1176         uint32_t ctrl_ext;
1177
1178         /* Let firmware taken over control of h/w */
1179         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1180         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1181                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1182 }
1183
1184 /*
1185  * Bit of a misnomer, what this really means is
1186  * to enable OS management of the system... aka
1187  * to disable special hardware management features.
1188  */
1189 static void
1190 igb_init_manageability(struct e1000_hw *hw)
1191 {
1192         if (e1000_enable_mng_pass_thru(hw)) {
1193                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1194                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1195
1196                 /* disable hardware interception of ARP */
1197                 manc &= ~(E1000_MANC_ARP_EN);
1198
1199                 /* enable receiving management packets to the host */
1200                 manc |= E1000_MANC_EN_MNG2HOST;
1201                 manc2h |= 1 << 5;  /* Mng Port 623 */
1202                 manc2h |= 1 << 6;  /* Mng Port 664 */
1203                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1204                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1205         }
1206 }
1207
1208 static void
1209 igb_release_manageability(struct e1000_hw *hw)
1210 {
1211         if (e1000_enable_mng_pass_thru(hw)) {
1212                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1213
1214                 manc |= E1000_MANC_ARP_EN;
1215                 manc &= ~E1000_MANC_EN_MNG2HOST;
1216
1217                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1218         }
1219 }
1220
1221 static void
1222 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1223 {
1224         struct e1000_hw *hw =
1225                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1226         uint32_t rctl;
1227
1228         rctl = E1000_READ_REG(hw, E1000_RCTL);
1229         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1230         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1231 }
1232
1233 static void
1234 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1235 {
1236         struct e1000_hw *hw =
1237                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1238         uint32_t rctl;
1239
1240         rctl = E1000_READ_REG(hw, E1000_RCTL);
1241         rctl &= (~E1000_RCTL_UPE);
1242         if (dev->data->all_multicast == 1)
1243                 rctl |= E1000_RCTL_MPE;
1244         else
1245                 rctl &= (~E1000_RCTL_MPE);
1246         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1247 }
1248
1249 static void
1250 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1251 {
1252         struct e1000_hw *hw =
1253                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1254         uint32_t rctl;
1255
1256         rctl = E1000_READ_REG(hw, E1000_RCTL);
1257         rctl |= E1000_RCTL_MPE;
1258         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1259 }
1260
1261 static void
1262 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1263 {
1264         struct e1000_hw *hw =
1265                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1266         uint32_t rctl;
1267
1268         if (dev->data->promiscuous == 1)
1269                 return; /* must remain in all_multicast mode */
1270         rctl = E1000_READ_REG(hw, E1000_RCTL);
1271         rctl &= (~E1000_RCTL_MPE);
1272         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1273 }
1274
1275 static int
1276 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1277 {
1278         struct e1000_hw *hw =
1279                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1280         struct e1000_vfta * shadow_vfta =
1281                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1282         uint32_t vfta;
1283         uint32_t vid_idx;
1284         uint32_t vid_bit;
1285
1286         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1287                               E1000_VFTA_ENTRY_MASK);
1288         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1289         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1290         if (on)
1291                 vfta |= vid_bit;
1292         else
1293                 vfta &= ~vid_bit;
1294         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1295
1296         /* update local VFTA copy */
1297         shadow_vfta->vfta[vid_idx] = vfta;
1298
1299         return 0;
1300 }
1301
1302 static void
1303 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1304 {
1305         struct e1000_hw *hw =
1306                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1307         uint32_t reg = ETHER_TYPE_VLAN ;
1308
1309         reg |= (tpid << 16);
1310         E1000_WRITE_REG(hw, E1000_VET, reg);
1311 }
1312
1313 static void
1314 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1315 {
1316         struct e1000_hw *hw =
1317                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1318         uint32_t reg;
1319
1320         /* Filter Table Disable */
1321         reg = E1000_READ_REG(hw, E1000_RCTL);
1322         reg &= ~E1000_RCTL_CFIEN;
1323         reg &= ~E1000_RCTL_VFE;
1324         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1325 }
1326
1327 static void
1328 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1329 {
1330         struct e1000_hw *hw =
1331                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1332         struct e1000_vfta * shadow_vfta =
1333                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1334         uint32_t reg;
1335         int i;
1336
1337         /* Filter Table Enable, CFI not used for packet acceptance */
1338         reg = E1000_READ_REG(hw, E1000_RCTL);
1339         reg &= ~E1000_RCTL_CFIEN;
1340         reg |= E1000_RCTL_VFE;
1341         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1342
1343         /* restore VFTA table */
1344         for (i = 0; i < IGB_VFTA_SIZE; i++)
1345                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1346 }
1347
1348 static void
1349 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1350 {
1351         struct e1000_hw *hw =
1352                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1353         uint32_t reg;
1354
1355         /* VLAN Mode Disable */
1356         reg = E1000_READ_REG(hw, E1000_CTRL);
1357         reg &= ~E1000_CTRL_VME;
1358         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1359
1360         /* Update maximum frame size */
1361         E1000_WRITE_REG(hw, E1000_RLPML,
1362                 dev->data->dev_conf.rxmode.max_rx_pkt_len + VLAN_TAG_SIZE);
1363 }
1364
1365 static void
1366 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1367 {
1368         struct e1000_hw *hw =
1369                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1370         uint32_t reg;
1371
1372         /* VLAN Mode Enable */
1373         reg = E1000_READ_REG(hw, E1000_CTRL);
1374         reg |= E1000_CTRL_VME;
1375         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1376
1377         /* Update maximum frame size */
1378         E1000_WRITE_REG(hw, E1000_RLPML,
1379                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1380
1381 }
1382
1383 static void
1384 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1385 {
1386         struct e1000_hw *hw =
1387                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1388         uint32_t reg;
1389
1390         /* CTRL_EXT: Extended VLAN */
1391         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1392         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1393         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1394
1395 }
1396
1397 static void
1398 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1399 {
1400         struct e1000_hw *hw =
1401                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1402         uint32_t reg;
1403
1404         /* CTRL_EXT: Extended VLAN */
1405         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1406         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1407         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1408 }
1409
1410 static void
1411 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1412 {
1413         if(mask & ETH_VLAN_STRIP_MASK){
1414                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1415                         igb_vlan_hw_strip_enable(dev);
1416                 else
1417                         igb_vlan_hw_strip_disable(dev);
1418         }
1419
1420         if(mask & ETH_VLAN_FILTER_MASK){
1421                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1422                         igb_vlan_hw_filter_enable(dev);
1423                 else
1424                         igb_vlan_hw_filter_disable(dev);
1425         }
1426
1427         if(mask & ETH_VLAN_EXTEND_MASK){
1428                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1429                         igb_vlan_hw_extend_enable(dev);
1430                 else
1431                         igb_vlan_hw_extend_disable(dev);
1432         }
1433 }
1434
1435
1436 /**
1437  * It enables the interrupt mask and then enable the interrupt.
1438  *
1439  * @param dev
1440  *  Pointer to struct rte_eth_dev.
1441  *
1442  * @return
1443  *  - On success, zero.
1444  *  - On failure, a negative value.
1445  */
1446 static int
1447 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1448 {
1449         struct e1000_interrupt *intr =
1450                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1451
1452         intr->mask |= E1000_ICR_LSC;
1453
1454         return 0;
1455 }
1456
1457 /*
1458  * It reads ICR and gets interrupt causes, check it and set a bit flag
1459  * to update link status.
1460  *
1461  * @param dev
1462  *  Pointer to struct rte_eth_dev.
1463  *
1464  * @return
1465  *  - On success, zero.
1466  *  - On failure, a negative value.
1467  */
1468 static int
1469 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1470 {
1471         uint32_t icr;
1472         struct e1000_hw *hw =
1473                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1474         struct e1000_interrupt *intr =
1475                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1476
1477         igb_intr_disable(hw);
1478
1479         /* read-on-clear nic registers here */
1480         icr = E1000_READ_REG(hw, E1000_ICR);
1481
1482         intr->flags = 0;
1483         if (icr & E1000_ICR_LSC) {
1484                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1485         }
1486
1487         return 0;
1488 }
1489
1490 /*
1491  * It executes link_update after knowing an interrupt is prsent.
1492  *
1493  * @param dev
1494  *  Pointer to struct rte_eth_dev.
1495  *
1496  * @return
1497  *  - On success, zero.
1498  *  - On failure, a negative value.
1499  */
1500 static int
1501 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1502 {
1503         struct e1000_hw *hw =
1504                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1505         struct e1000_interrupt *intr =
1506                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1507         uint32_t tctl, rctl;
1508         struct rte_eth_link link;
1509         int ret;
1510
1511
1512         igb_intr_enable(dev);
1513         rte_intr_enable(&(dev->pci_dev->intr_handle));
1514
1515         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1516                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1517
1518                 /* set get_link_status to check register later */
1519                 hw->mac.get_link_status = 1;
1520                 ret = eth_igb_link_update(dev, 0);
1521
1522                 /* check if link has changed */
1523                 if (ret < 0)
1524                         return 0;
1525
1526                 memset(&link, 0, sizeof(link));
1527                 rte_igb_dev_atomic_read_link_status(dev, &link);
1528                 if (link.link_status) {
1529                         PMD_INIT_LOG(INFO,
1530                                 " Port %d: Link Up - speed %u Mbps - %s\n",
1531                                 dev->data->port_id, (unsigned)link.link_speed,
1532                                 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1533                                         "full-duplex" : "half-duplex");
1534                 } else {
1535                         PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1536                                                 dev->data->port_id);
1537                 }
1538                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1539                                         dev->pci_dev->addr.domain,
1540                                         dev->pci_dev->addr.bus,
1541                                         dev->pci_dev->addr.devid,
1542                                         dev->pci_dev->addr.function);
1543                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1544                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1545                 if (link.link_status) {
1546                         /* enable Tx/Rx */
1547                         tctl |= E1000_TCTL_EN;
1548                         rctl |= E1000_RCTL_EN;
1549                 } else {
1550                         /* disable Tx/Rx */
1551                         tctl &= ~E1000_TCTL_EN;
1552                         rctl &= ~E1000_RCTL_EN;
1553                 }
1554                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1555                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1556                 E1000_WRITE_FLUSH(hw);
1557                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1558         }
1559
1560         return 0;
1561 }
1562
1563 /**
1564  * Interrupt handler which shall be registered at first.
1565  *
1566  * @param handle
1567  *  Pointer to interrupt handle.
1568  * @param param
1569  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1570  *
1571  * @return
1572  *  void
1573  */
1574 static void
1575 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1576                                                         void *param)
1577 {
1578         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1579
1580         eth_igb_interrupt_get_status(dev);
1581         eth_igb_interrupt_action(dev);
1582 }
1583
1584 static int
1585 eth_igb_led_on(struct rte_eth_dev *dev)
1586 {
1587         struct e1000_hw *hw;
1588
1589         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1590         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1591 }
1592
1593 static int
1594 eth_igb_led_off(struct rte_eth_dev *dev)
1595 {
1596         struct e1000_hw *hw;
1597
1598         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1600 }
1601
1602 static int
1603 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1604 {
1605         struct e1000_hw *hw;
1606         int err;
1607         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1608                 e1000_fc_none,
1609                 e1000_fc_rx_pause,
1610                 e1000_fc_tx_pause,
1611                 e1000_fc_full
1612         };
1613         uint32_t rx_buf_size;
1614         uint32_t max_high_water;
1615
1616         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1617         rx_buf_size = igb_get_rx_buffer_size(hw);
1618         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1619
1620         /* At least reserve one Ethernet frame for watermark */
1621         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1622         if ((fc_conf->high_water > max_high_water) ||
1623                 (fc_conf->high_water < fc_conf->low_water)) {
1624                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1625                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1626                 return (-EINVAL);
1627         }
1628
1629         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1630         hw->fc.pause_time     = fc_conf->pause_time;
1631         hw->fc.high_water     = fc_conf->high_water;
1632         hw->fc.low_water      = fc_conf->low_water;
1633         hw->fc.send_xon       = fc_conf->send_xon;
1634
1635         err = e1000_setup_link_generic(hw);
1636         if (err == E1000_SUCCESS) {
1637                 return 0;
1638         }
1639
1640         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1641         return (-EIO);
1642 }
1643
1644 static void
1645 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1646                 uint32_t index, __rte_unused uint32_t pool)
1647 {
1648         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1649
1650         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1651 }
1652
1653 static void
1654 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1655 {
1656         uint8_t addr[ETHER_ADDR_LEN];
1657         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1658
1659         memset(addr, 0, sizeof(addr));
1660
1661         e1000_rar_set(hw, addr, index);
1662 }
1663
1664 /*
1665  * Virtual Function operations
1666  */
1667 static void
1668 igbvf_intr_disable(struct e1000_hw *hw)
1669 {
1670         PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1671
1672         /* Clear interrupt mask to stop from interrupts being generated */
1673         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
1674
1675         E1000_WRITE_FLUSH(hw);
1676 }
1677
1678 static void
1679 igbvf_stop_adapter(struct rte_eth_dev *dev)
1680 {
1681         u32 reg_val;
1682         u16 i;
1683         struct rte_eth_dev_info dev_info;
1684         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685
1686         memset(&dev_info, 0, sizeof(dev_info));
1687         eth_igb_infos_get(dev, &dev_info);
1688
1689         /* Clear interrupt mask to stop from interrupts being generated */
1690         igbvf_intr_disable(hw);
1691
1692         /* Clear any pending interrupts, flush previous writes */
1693         E1000_READ_REG(hw, E1000_EICR);
1694
1695         /* Disable the transmit unit.  Each queue must be disabled. */
1696         for (i = 0; i < dev_info.max_tx_queues; i++)
1697                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1698
1699         /* Disable the receive unit by stopping each queue */
1700         for (i = 0; i < dev_info.max_rx_queues; i++) {
1701                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1702                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1703                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1704                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1705                         ;
1706         }
1707
1708         /* flush all queues disables */
1709         E1000_WRITE_FLUSH(hw);
1710         msec_delay(2);
1711 }
1712
1713 static int eth_igbvf_link_update(struct e1000_hw *hw)
1714 {
1715         struct e1000_mbx_info *mbx = &hw->mbx;
1716         struct e1000_mac_info *mac = &hw->mac;
1717         int ret_val = E1000_SUCCESS;
1718
1719         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1720
1721         /*
1722          * We only want to run this if there has been a rst asserted.
1723          * in this case that could mean a link change, device reset,
1724          * or a virtual function reset
1725          */
1726
1727         /* If we were hit with a reset or timeout drop the link */
1728         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1729                 mac->get_link_status = TRUE;
1730
1731         if (!mac->get_link_status)
1732                 goto out;
1733
1734         /* if link status is down no point in checking to see if pf is up */
1735         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1736                 goto out;
1737
1738         /* if we passed all the tests above then the link is up and we no
1739          * longer need to check for link */
1740         mac->get_link_status = FALSE;
1741
1742 out:
1743         return ret_val;
1744 }
1745
1746
1747 static int
1748 igbvf_dev_configure(struct rte_eth_dev *dev)
1749 {
1750         struct rte_eth_conf* conf = &dev->data->dev_conf;
1751
1752         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1753                 dev->data->port_id);
1754
1755         /*
1756          * VF has no ability to enable/disable HW CRC
1757          * Keep the persistent behavior the same as Host PF
1758          */
1759 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1760         if (!conf->rxmode.hw_strip_crc) {
1761                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1762                 conf->rxmode.hw_strip_crc = 1;
1763         }
1764 #else
1765         if (conf->rxmode.hw_strip_crc) {
1766                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1767                 conf->rxmode.hw_strip_crc = 0;
1768         }
1769 #endif
1770
1771         return 0;
1772 }
1773
1774 static int
1775 igbvf_dev_start(struct rte_eth_dev *dev)
1776 {
1777         struct e1000_hw *hw =
1778                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1779         int ret;
1780
1781         PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1782
1783         hw->mac.ops.reset_hw(hw);
1784
1785         /* Set all vfta */
1786         igbvf_set_vfta_all(dev,1);
1787
1788         eth_igbvf_tx_init(dev);
1789
1790         /* This can fail when allocating mbufs for descriptor rings */
1791         ret = eth_igbvf_rx_init(dev);
1792         if (ret) {
1793                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1794                 igb_dev_clear_queues(dev);
1795                 return ret;
1796         }
1797
1798         return 0;
1799 }
1800
1801 static void
1802 igbvf_dev_stop(struct rte_eth_dev *dev)
1803 {
1804         PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1805
1806         igbvf_stop_adapter(dev);
1807
1808         /*
1809           * Clear what we set, but we still keep shadow_vfta to
1810           * restore after device starts
1811           */
1812         igbvf_set_vfta_all(dev,0);
1813
1814         igb_dev_clear_queues(dev);
1815 }
1816
1817 static void
1818 igbvf_dev_close(struct rte_eth_dev *dev)
1819 {
1820         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1821
1822         PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1823
1824         e1000_reset_hw(hw);
1825
1826         igbvf_dev_stop(dev);
1827 }
1828
1829 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1830 {
1831         struct e1000_mbx_info *mbx = &hw->mbx;
1832         uint32_t msgbuf[2];
1833
1834         /* After set vlan, vlan strip will also be enabled in igb driver*/
1835         msgbuf[0] = E1000_VF_SET_VLAN;
1836         msgbuf[1] = vid;
1837         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1838         if (on)
1839                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1840
1841         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1842 }
1843
1844 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1845 {
1846         struct e1000_hw *hw =
1847                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1848         struct e1000_vfta * shadow_vfta =
1849                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1850         int i = 0, j = 0, vfta = 0, mask = 1;
1851
1852         for (i = 0; i < IGB_VFTA_SIZE; i++){
1853                 vfta = shadow_vfta->vfta[i];
1854                 if(vfta){
1855                         mask = 1;
1856                         for (j = 0; j < 32; j++){
1857                                 if(vfta & mask)
1858                                         igbvf_set_vfta(hw,
1859                                                 (uint16_t)((i<<5)+j), on);
1860                                 mask<<=1;
1861                         }
1862                 }
1863         }
1864
1865 }
1866
1867 static int
1868 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1869 {
1870         struct e1000_hw *hw =
1871                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         struct e1000_vfta * shadow_vfta =
1873                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1874         uint32_t vid_idx = 0;
1875         uint32_t vid_bit = 0;
1876         int ret = 0;
1877
1878         PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
1879
1880         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
1881         ret = igbvf_set_vfta(hw, vlan_id, !!on);
1882         if(ret){
1883                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
1884                 return ret;
1885         }
1886         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1887         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1888
1889         /*Save what we set and retore it after device reset*/
1890         if (on)
1891                 shadow_vfta->vfta[vid_idx] |= vid_bit;
1892         else
1893                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
1894
1895         return 0;
1896 }
1897