lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #include <sys/queue.h>
  36 #include <stdio.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40
  41 #include <rte_common.h>
  42 #include <rte_interrupts.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_tailq.h>
  52 #include <rte_eal.h>
  53 #include <rte_atomic.h>
  54 #include <rte_malloc.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 static int  eth_igb_configure(struct rte_eth_dev *dev);
  61 static int  eth_igb_start(struct rte_eth_dev *dev);
  62 static void eth_igb_stop(struct rte_eth_dev *dev);
  63 static void eth_igb_close(struct rte_eth_dev *dev);
  64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  68 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  69                                 int wait_to_complete);
  70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  71                                 struct rte_eth_stats *rte_stats);
  72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  74                                 struct rte_eth_dev_info *dev_info);
  75 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  76                                 struct rte_eth_fc_conf *fc_conf);
  77 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  78 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  79 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  80 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  81                                                         void *param);
  82 static int  igb_hardware_init(struct e1000_hw *hw);
  83 static void igb_hw_control_acquire(struct e1000_hw *hw);
  84 static void igb_hw_control_release(struct e1000_hw *hw);
  85 static void igb_init_manageability(struct e1000_hw *hw);
  86 static void igb_release_manageability(struct e1000_hw *hw);
  87
  88 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  89                 uint16_t vlan_id, int on);
  90 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
  91 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  92
  93 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  94 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  95 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  96 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  97 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
  98 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
  99
 100 static int eth_igb_led_on(struct rte_eth_dev *dev);
 101 static int eth_igb_led_off(struct rte_eth_dev *dev);
 102
 103 static void igb_intr_disable(struct e1000_hw *hw);
 104 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 105 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 106                 struct ether_addr *mac_addr,
 107                 uint32_t index, uint32_t pool);
 108 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 109
 110 static void igbvf_intr_disable(struct e1000_hw *hw);
 111 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 112 static int igbvf_dev_start(struct rte_eth_dev *dev);
 113 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 114 static void igbvf_dev_close(struct rte_eth_dev *dev);
 115 static int eth_igbvf_link_update(struct e1000_hw *hw);
 116 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 117 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 118 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 119                 uint16_t vlan_id, int on);
 120 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 121 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 122 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 123                  struct rte_eth_rss_reta *reta_conf);
 124 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 125                 struct rte_eth_rss_reta *reta_conf);
 126
 127 /*
 128  * Define VF Stats MACRO for Non "cleared on read" register
 129  */
 130 #define UPDATE_VF_STAT(reg, last, cur)            \
 131 {                                                 \
 132         u32 latest = E1000_READ_REG(hw, reg);     \
 133         cur += latest - last;                     \
 134         last = latest;                            \
 135 }
 136
 137
 138 #define IGB_FC_PAUSE_TIME 0x0680
 139 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 140 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 141
 142 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 143
 144 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 145
 146 /*
 147  * The set of PCI devices this driver supports
 148  */
 149 static struct rte_pci_id pci_id_igb_map[] = {
 150
 151 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 152 #include "rte_pci_dev_ids.h"
 153
 154 {.device_id = 0},
 155 };
 156
 157 /*
 158  * The set of PCI devices this driver supports (for 82576&I350 VF)
 159  */
 160 static struct rte_pci_id pci_id_igbvf_map[] = {
 161
 162 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 163 #include "rte_pci_dev_ids.h"
 164
 165 {.device_id = 0},
 166 };
 167
 168 static struct eth_dev_ops eth_igb_ops = {
 169         .dev_configure        = eth_igb_configure,
 170         .dev_start            = eth_igb_start,
 171         .dev_stop             = eth_igb_stop,
 172         .dev_close            = eth_igb_close,
 173         .promiscuous_enable   = eth_igb_promiscuous_enable,
 174         .promiscuous_disable  = eth_igb_promiscuous_disable,
 175         .allmulticast_enable  = eth_igb_allmulticast_enable,
 176         .allmulticast_disable = eth_igb_allmulticast_disable,
 177         .link_update          = eth_igb_link_update,
 178         .stats_get            = eth_igb_stats_get,
 179         .stats_reset          = eth_igb_stats_reset,
 180         .dev_infos_get        = eth_igb_infos_get,
 181         .vlan_filter_set      = eth_igb_vlan_filter_set,
 182         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 183         .vlan_offload_set     = eth_igb_vlan_offload_set,
 184         .rx_queue_setup       = eth_igb_rx_queue_setup,
 185         .rx_queue_release     = eth_igb_rx_queue_release,
 186         .rx_queue_count       = eth_igb_rx_queue_count,
 187         .tx_queue_setup       = eth_igb_tx_queue_setup,
 188         .tx_queue_release     = eth_igb_tx_queue_release,
 189         .dev_led_on           = eth_igb_led_on,
 190         .dev_led_off          = eth_igb_led_off,
 191         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 192         .mac_addr_add         = eth_igb_rar_set,
 193         .mac_addr_remove      = eth_igb_rar_clear,
 194         .reta_update          = eth_igb_rss_reta_update,
 195         .reta_query           = eth_igb_rss_reta_query,
 196 };
 197
 198 /*
 199  * dev_ops for virtual function, bare necessities for basic vf
 200  * operation have been implemented
 201  */
 202 static struct eth_dev_ops igbvf_eth_dev_ops = {
 203         .dev_configure        = igbvf_dev_configure,
 204         .dev_start            = igbvf_dev_start,
 205         .dev_stop             = igbvf_dev_stop,
 206         .dev_close            = igbvf_dev_close,
 207         .link_update          = eth_igb_link_update,
 208         .stats_get            = eth_igbvf_stats_get,
 209         .stats_reset          = eth_igbvf_stats_reset,
 210         .vlan_filter_set      = igbvf_vlan_filter_set,
 211         .dev_infos_get        = eth_igb_infos_get,
 212         .rx_queue_setup       = eth_igb_rx_queue_setup,
 213         .rx_queue_release     = eth_igb_rx_queue_release,
 214         .tx_queue_setup       = eth_igb_tx_queue_setup,
 215         .tx_queue_release     = eth_igb_tx_queue_release,
 216 };
 217
 218 /**
 219  * Atomically reads the link status information from global
 220  * structure rte_eth_dev.
 221  *
 222  * @param dev
 223  *   - Pointer to the structure rte_eth_dev to read from.
 224  *   - Pointer to the buffer to be saved with the link status.
 225  *
 226  * @return
 227  *   - On success, zero.
 228  *   - On failure, negative value.
 229  */
 230 static inline int
 231 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 232                                 struct rte_eth_link *link)
 233 {
 234         struct rte_eth_link *dst = link;
 235         struct rte_eth_link *src = &(dev->data->dev_link);
 236
 237         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 238                                         *(uint64_t *)src) == 0)
 239                 return -1;
 240
 241         return 0;
 242 }
 243
 244 /**
 245  * Atomically writes the link status information into global
 246  * structure rte_eth_dev.
 247  *
 248  * @param dev
 249  *   - Pointer to the structure rte_eth_dev to read from.
 250  *   - Pointer to the buffer to be saved with the link status.
 251  *
 252  * @return
 253  *   - On success, zero.
 254  *   - On failure, negative value.
 255  */
 256 static inline int
 257 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 258                                 struct rte_eth_link *link)
 259 {
 260         struct rte_eth_link *dst = &(dev->data->dev_link);
 261         struct rte_eth_link *src = link;
 262
 263         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 264                                         *(uint64_t *)src) == 0)
 265                 return -1;
 266
 267         return 0;
 268 }
 269
 270 static inline void
 271 igb_intr_enable(struct rte_eth_dev *dev)
 272 {
 273         struct e1000_interrupt *intr =
 274                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 275         struct e1000_hw *hw =
 276                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 277
 278         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 279         E1000_WRITE_FLUSH(hw);
 280 }
 281
 282 static void
 283 igb_intr_disable(struct e1000_hw *hw)
 284 {
 285         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 286         E1000_WRITE_FLUSH(hw);
 287 }
 288
 289 static inline int32_t
 290 igb_pf_reset_hw(struct e1000_hw *hw)
 291 {
 292         uint32_t ctrl_ext;
 293         int32_t status;
 294
 295         status = e1000_reset_hw(hw);
 296
 297         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 298         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 299         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 300         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 301         E1000_WRITE_FLUSH(hw);
 302
 303         return status;
 304 }
 305
 306 static void
 307 igb_identify_hardware(struct rte_eth_dev *dev)
 308 {
 309         struct e1000_hw *hw =
 310                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 311
 312         hw->vendor_id = dev->pci_dev->id.vendor_id;
 313         hw->device_id = dev->pci_dev->id.device_id;
 314         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 315         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 316
 317         e1000_set_mac_type(hw);
 318
 319         /* need to check if it is a vf device below */
 320 }
 321
 322 static int
 323 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 324                    struct rte_eth_dev *eth_dev)
 325 {
 326         int error = 0;
 327         struct rte_pci_device *pci_dev;
 328         struct e1000_hw *hw =
 329                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 330         struct e1000_vfta * shadow_vfta =
 331                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 332         uint32_t ctrl_ext;
 333
 334         pci_dev = eth_dev->pci_dev;
 335         eth_dev->dev_ops = &eth_igb_ops;
 336         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 337         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 338
 339         /* for secondary processes, we don't initialise any further as primary
 340          * has already done this work. Only check we don't need a different
 341          * RX function */
 342         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 343                 if (eth_dev->data->scattered_rx)
 344                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 345                 return 0;
 346         }
 347
 348         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 349
 350         igb_identify_hardware(eth_dev);
 351         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 352                 error = -EIO;
 353                 goto err_late;
 354         }
 355
 356         e1000_get_bus_info(hw);
 357
 358         hw->mac.autoneg = 1;
 359         hw->phy.autoneg_wait_to_complete = 0;
 360         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 361
 362         /* Copper options */
 363         if (hw->phy.media_type == e1000_media_type_copper) {
 364                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 365                 hw->phy.disable_polarity_correction = 0;
 366                 hw->phy.ms_type = e1000_ms_hw_default;
 367         }
 368
 369         /*
 370          * Start from a known state, this is important in reading the nvm
 371          * and mac from that.
 372          */
 373         igb_pf_reset_hw(hw);
 374
 375         /* Make sure we have a good EEPROM before we read from it */
 376         if (e1000_validate_nvm_checksum(hw) < 0) {
 377                 /*
 378                  * Some PCI-E parts fail the first check due to
 379                  * the link being in sleep state, call it again,
 380                  * if it fails a second time its a real issue.
 381                  */
 382                 if (e1000_validate_nvm_checksum(hw) < 0) {
 383                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 384                         error = -EIO;
 385                         goto err_late;
 386                 }
 387         }
 388
 389         /* Read the permanent MAC address out of the EEPROM */
 390         if (e1000_read_mac_addr(hw) != 0) {
 391                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 392                 error = -EIO;
 393                 goto err_late;
 394         }
 395
 396         /* Allocate memory for storing MAC addresses */
 397         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 398                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 399         if (eth_dev->data->mac_addrs == NULL) {
 400                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 401                                                 "store MAC addresses",
 402                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 403                 error = -ENOMEM;
 404                 goto err_late;
 405         }
 406
 407         /* Copy the permanent MAC address */
 408         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 409
 410         /* initialize the vfta */
 411         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 412
 413         /* Now initialize the hardware */
 414         if (igb_hardware_init(hw) != 0) {
 415                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 416                 rte_free(eth_dev->data->mac_addrs);
 417                 eth_dev->data->mac_addrs = NULL;
 418                 error = -ENODEV;
 419                 goto err_late;
 420         }
 421         hw->mac.get_link_status = 1;
 422
 423         /* Indicate SOL/IDER usage */
 424         if (e1000_check_reset_block(hw) < 0) {
 425                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 426                                         "SOL/IDER session");
 427         }
 428
 429         /* initialize PF if max_vfs not zero */
 430         igb_pf_host_init(eth_dev);
 431
 432         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 433         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 434         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 435         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 436         E1000_WRITE_FLUSH(hw);
 437
 438         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 439                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 440                      pci_dev->id.device_id);
 441
 442         rte_intr_callback_register(&(pci_dev->intr_handle),
 443                 eth_igb_interrupt_handler, (void *)eth_dev);
 444
 445         /* enable uio intr after callback register */
 446         rte_intr_enable(&(pci_dev->intr_handle));
 447
 448         /* enable support intr */
 449         igb_intr_enable(eth_dev);
 450
 451         return 0;
 452
 453 err_late:
 454         igb_hw_control_release(hw);
 455
 456         return (error);
 457 }
 458
 459 /*
 460  * Virtual Function device init
 461  */
 462 static int
 463 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 464                 struct rte_eth_dev *eth_dev)
 465 {
 466         struct rte_pci_device *pci_dev;
 467         struct e1000_hw *hw =
 468                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 469         int diag;
 470
 471         PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 472
 473         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 474         pci_dev = eth_dev->pci_dev;
 475
 476         hw->device_id = pci_dev->id.device_id;
 477         hw->vendor_id = pci_dev->id.vendor_id;
 478         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 479
 480         /* Initialize the shared code */
 481         diag = e1000_setup_init_funcs(hw, TRUE);
 482         if (diag != 0) {
 483                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 484                         diag);
 485                 return -EIO;
 486         }
 487
 488         /* init_mailbox_params */
 489         hw->mbx.ops.init_params(hw);
 490
 491         /* Disable the interrupts for VF */
 492         igbvf_intr_disable(hw);
 493
 494         diag = hw->mac.ops.reset_hw(hw);
 495
 496         /* Allocate memory for storing MAC addresses */
 497         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 498                 hw->mac.rar_entry_count, 0);
 499         if (eth_dev->data->mac_addrs == NULL) {
 500                 PMD_INIT_LOG(ERR,
 501                         "Failed to allocate %d bytes needed to store MAC "
 502                         "addresses",
 503                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 504                 return -ENOMEM;
 505         }
 506
 507         /* Copy the permanent MAC address */
 508         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 509                         &eth_dev->data->mac_addrs[0]);
 510
 511         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
 512                         "mac.type=%s\n",
 513                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 514                         pci_dev->id.device_id,
 515                         "igb_mac_82576_vf");
 516
 517         return 0;
 518 }
 519
 520 static struct eth_driver rte_igb_pmd = {
 521         {
 522                 .name = "rte_igb_pmd",
 523                 .id_table = pci_id_igb_map,
 524 #ifdef RTE_EAL_UNBIND_PORTS
 525                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 526 #endif
 527         },
 528         .eth_dev_init = eth_igb_dev_init,
 529         .dev_private_size = sizeof(struct e1000_adapter),
 530 };
 531
 532 /*
 533  * virtual function driver struct
 534  */
 535 static struct eth_driver rte_igbvf_pmd = {
 536         {
 537                 .name = "rte_igbvf_pmd",
 538                 .id_table = pci_id_igbvf_map,
 539 #ifdef RTE_EAL_UNBIND_PORTS
 540                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 541 #endif
 542         },
 543         .eth_dev_init = eth_igbvf_dev_init,
 544         .dev_private_size = sizeof(struct e1000_adapter),
 545 };
 546
 547 int
 548 rte_igb_pmd_init(void)
 549 {
 550         rte_eth_driver_register(&rte_igb_pmd);
 551         return 0;
 552 }
 553
 554 /*
 555  * VF Driver initialization routine.
 556  * Invoked one at EAL init time.
 557  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 558  */
 559 int
 560 rte_igbvf_pmd_init(void)
 561 {
 562         DEBUGFUNC("rte_igbvf_pmd_init");
 563
 564         rte_eth_driver_register(&rte_igbvf_pmd);
 565         return (0);
 566 }
 567
 568 static int
 569 eth_igb_configure(struct rte_eth_dev *dev)
 570 {
 571         struct e1000_interrupt *intr =
 572                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 573
 574         PMD_INIT_LOG(DEBUG, ">>");
 575
 576         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 577
 578         PMD_INIT_LOG(DEBUG, "<<");
 579
 580         return (0);
 581 }
 582
 583 static int
 584 eth_igb_start(struct rte_eth_dev *dev)
 585 {
 586         struct e1000_hw *hw =
 587                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 588         int ret, i, mask;
 589         uint32_t ctrl_ext;
 590
 591         PMD_INIT_LOG(DEBUG, ">>");
 592
 593         /* Power up the phy. Needed to make the link go Up */
 594         e1000_power_up_phy(hw);
 595
 596         /*
 597          * Packet Buffer Allocation (PBA)
 598          * Writing PBA sets the receive portion of the buffer
 599          * the remainder is used for the transmit buffer.
 600          */
 601         if (hw->mac.type == e1000_82575) {
 602                 uint32_t pba;
 603
 604                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 605                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 606         }
 607
 608         /* Put the address into the Receive Address Array */
 609         e1000_rar_set(hw, hw->mac.addr, 0);
 610
 611         /* Initialize the hardware */
 612         if (igb_hardware_init(hw)) {
 613                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 614                 return (-EIO);
 615         }
 616
 617         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 618
 619         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 620         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 621         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 622         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 623         E1000_WRITE_FLUSH(hw);
 624
 625         /* configure PF module if SRIOV enabled */
 626         igb_pf_host_configure(dev);
 627
 628         /* Configure for OS presence */
 629         igb_init_manageability(hw);
 630
 631         eth_igb_tx_init(dev);
 632
 633         /* This can fail when allocating mbufs for descriptor rings */
 634         ret = eth_igb_rx_init(dev);
 635         if (ret) {
 636                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 637                 igb_dev_clear_queues(dev);
 638                 return ret;
 639         }
 640
 641         e1000_clear_hw_cntrs_base_generic(hw);
 642
 643         /*
 644          * VLAN Offload Settings
 645          */
 646         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 647                         ETH_VLAN_EXTEND_MASK;
 648         eth_igb_vlan_offload_set(dev, mask);
 649
 650         /*
 651          * Configure the Interrupt Moderation register (EITR) with the maximum
 652          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 653          * spurious [DMA] memory updates of RX and TX ring descriptors.
 654          *
 655          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 656          * spurious memory updates per second should be expected.
 657          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 658          *
 659          * Because interrupts are not used at all, the MSI-X is not activated
 660          * and interrupt moderation is controlled by EITR[0].
 661          *
 662          * Note that having [almost] disabled memory updates of RX and TX ring
 663          * descriptors through the Interrupt Moderation mechanism, memory
 664          * updates of ring descriptors are now moderated by the configurable
 665          * value of Write-Back Threshold registers.
 666          */
 667         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 668                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 669                 uint32_t ivar;
 670
 671                 /* Enable all RX & TX queues in the IVAR registers */
 672                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 673                 for (i = 0; i < 8; i++)
 674                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 675
 676                 /* Configure EITR with the maximum possible value (0xFFFF) */
 677                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 678         }
 679
 680         /* Setup link speed and duplex */
 681         switch (dev->data->dev_conf.link_speed) {
 682         case ETH_LINK_SPEED_AUTONEG:
 683                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 684                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 685                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 686                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 687                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 688                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 689                 else
 690                         goto error_invalid_config;
 691                 break;
 692         case ETH_LINK_SPEED_10:
 693                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 694                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 695                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 696                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 697                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 698                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 699                 else
 700                         goto error_invalid_config;
 701                 break;
 702         case ETH_LINK_SPEED_100:
 703                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 704                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 705                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 706                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 707                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 708                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 709                 else
 710                         goto error_invalid_config;
 711                 break;
 712         case ETH_LINK_SPEED_1000:
 713                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 714                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 715                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 716                 else
 717                         goto error_invalid_config;
 718                 break;
 719         case ETH_LINK_SPEED_10000:
 720         default:
 721                 goto error_invalid_config;
 722         }
 723         e1000_setup_link(hw);
 724
 725         /* check if lsc interrupt feature is enabled */
 726         if (dev->data->dev_conf.intr_conf.lsc != 0)
 727                 ret = eth_igb_lsc_interrupt_setup(dev);
 728
 729         /* resume enabled intr since hw reset */
 730         igb_intr_enable(dev);
 731
 732         PMD_INIT_LOG(DEBUG, "<<");
 733
 734         return (0);
 735
 736 error_invalid_config:
 737         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 738                         dev->data->dev_conf.link_speed,
 739                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 740         igb_dev_clear_queues(dev);
 741         return (-EINVAL);
 742 }
 743
 744 /*********************************************************************
 745  *
 746  *  This routine disables all traffic on the adapter by issuing a
 747  *  global reset on the MAC.
 748  *
 749  **********************************************************************/
 750 static void
 751 eth_igb_stop(struct rte_eth_dev *dev)
 752 {
 753         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 754         struct rte_eth_link link;
 755
 756         igb_intr_disable(hw);
 757         igb_pf_reset_hw(hw);
 758         E1000_WRITE_REG(hw, E1000_WUC, 0);
 759
 760         /* Power down the phy. Needed to make the link go Down */
 761         e1000_power_down_phy(hw);
 762
 763         igb_dev_clear_queues(dev);
 764
 765         /* clear the recorded link status */
 766         memset(&link, 0, sizeof(link));
 767         rte_igb_dev_atomic_write_link_status(dev, &link);
 768 }
 769
 770 static void
 771 eth_igb_close(struct rte_eth_dev *dev)
 772 {
 773         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 774         struct rte_eth_link link;
 775
 776         eth_igb_stop(dev);
 777         e1000_phy_hw_reset(hw);
 778         igb_release_manageability(hw);
 779         igb_hw_control_release(hw);
 780
 781         igb_dev_clear_queues(dev);
 782
 783         memset(&link, 0, sizeof(link));
 784         rte_igb_dev_atomic_write_link_status(dev, &link);
 785 }
 786
 787 static int
 788 igb_get_rx_buffer_size(struct e1000_hw *hw)
 789 {
 790         uint32_t rx_buf_size;
 791         if (hw->mac.type == e1000_82576) {
 792                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 793         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 794                 /* PBS needs to be translated according to a lookup table */
 795                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 796                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 797                 rx_buf_size = (rx_buf_size << 10);
 798         } else if (hw->mac.type == e1000_i210) {
 799                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 800         } else {
 801                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 802         }
 803
 804         return rx_buf_size;
 805 }
 806
 807 /*********************************************************************
 808  *
 809  *  Initialize the hardware
 810  *
 811  **********************************************************************/
 812 static int
 813 igb_hardware_init(struct e1000_hw *hw)
 814 {
 815         uint32_t rx_buf_size;
 816         int diag;
 817
 818         /* Let the firmware know the OS is in control */
 819         igb_hw_control_acquire(hw);
 820
 821         /*
 822          * These parameters control the automatic generation (Tx) and
 823          * response (Rx) to Ethernet PAUSE frames.
 824          * - High water mark should allow for at least two standard size (1518)
 825          *   frames to be received after sending an XOFF.
 826          * - Low water mark works best when it is very near the high water mark.
 827          *   This allows the receiver to restart by sending XON when it has
 828          *   drained a bit. Here we use an arbitary value of 1500 which will
 829          *   restart after one full frame is pulled from the buffer. There
 830          *   could be several smaller frames in the buffer and if so they will
 831          *   not trigger the XON until their total number reduces the buffer
 832          *   by 1500.
 833          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 834          */
 835         rx_buf_size = igb_get_rx_buffer_size(hw);
 836
 837         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
 838         hw->fc.low_water = hw->fc.high_water - 1500;
 839         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
 840         hw->fc.send_xon = 1;
 841
 842         /* Set Flow control, use the tunable location if sane */
 843         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
 844                 hw->fc.requested_mode = igb_fc_setting;
 845         else
 846                 hw->fc.requested_mode = e1000_fc_none;
 847
 848         /* Issue a global reset */
 849         igb_pf_reset_hw(hw);
 850         E1000_WRITE_REG(hw, E1000_WUC, 0);
 851
 852         diag = e1000_init_hw(hw);
 853         if (diag < 0)
 854                 return (diag);
 855
 856         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 857         e1000_get_phy_info(hw);
 858         e1000_check_for_link(hw);
 859
 860         return (0);
 861 }
 862
 863 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
 864 static void
 865 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 866 {
 867         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 868         struct e1000_hw_stats *stats =
 869                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 870         int pause_frames;
 871
 872         if(hw->phy.media_type == e1000_media_type_copper ||
 873             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 874                 stats->symerrs +=
 875                     E1000_READ_REG(hw,E1000_SYMERRS);
 876                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 877         }
 878
 879         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 880         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 881         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 882         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 883
 884         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 885         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 886         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 887         stats->dc += E1000_READ_REG(hw, E1000_DC);
 888         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 889         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 890         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 891         /*
 892         ** For watchdog management we need to know if we have been
 893         ** paused during the last interval, so capture that here.
 894         */
 895         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 896         stats->xoffrxc += pause_frames;
 897         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 898         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 899         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 900         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 901         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 902         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 903         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 904         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 905         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 906         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 907         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 908         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 909
 910         /* For the 64-bit byte counters the low dword must be read first. */
 911         /* Both registers clear on the read of the high dword */
 912
 913         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 914         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 915         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 916         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 917
 918         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 919         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 920         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 921         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 922         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 923
 924         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 925         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 926
 927         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 928         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 929         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 930         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 931         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 932         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 933         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 934         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 935         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 936         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 937
 938         /* Interrupt Counts */
 939
 940         stats->iac += E1000_READ_REG(hw, E1000_IAC);
 941         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 942         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 943         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 944         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 945         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 946         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 947         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 948         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 949
 950         /* Host to Card Statistics */
 951
 952         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
 953         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
 954         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
 955         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
 956         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
 957         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
 958         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
 959         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
 960         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
 961         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
 962         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
 963         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
 964         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
 965         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
 966
 967         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 968         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 969         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 970         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 971         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 972         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 973
 974         if (rte_stats == NULL)
 975                 return;
 976
 977         /* Rx Errors */
 978         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 979             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 980
 981         /* Tx Errors */
 982         rte_stats->oerrors = stats->ecol + stats->latecol;
 983
 984         rte_stats->ipackets = stats->gprc;
 985         rte_stats->opackets = stats->gptc;
 986         rte_stats->ibytes   = stats->gorc;
 987         rte_stats->obytes   = stats->gotc;
 988 }
 989
 990 static void
 991 eth_igb_stats_reset(struct rte_eth_dev *dev)
 992 {
 993         struct e1000_hw_stats *hw_stats =
 994                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 995
 996         /* HW registers are cleared on read */
 997         eth_igb_stats_get(dev, NULL);
 998
 999         /* Reset software totals */
1000         memset(hw_stats, 0, sizeof(*hw_stats));
1001 }
1002
1003 static void
1004 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1005 {
1006         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1007         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1008                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1009
1010         /* Good Rx packets, include VF loopback */
1011         UPDATE_VF_STAT(E1000_VFGPRC,
1012             hw_stats->last_gprc, hw_stats->gprc);
1013
1014         /* Good Rx octets, include VF loopback */
1015         UPDATE_VF_STAT(E1000_VFGORC,
1016             hw_stats->last_gorc, hw_stats->gorc);
1017
1018         /* Good Tx packets, include VF loopback */
1019         UPDATE_VF_STAT(E1000_VFGPTC,
1020             hw_stats->last_gptc, hw_stats->gptc);
1021
1022         /* Good Tx octets, include VF loopback */
1023         UPDATE_VF_STAT(E1000_VFGOTC,
1024             hw_stats->last_gotc, hw_stats->gotc);
1025
1026         /* Rx Multicst packets */
1027         UPDATE_VF_STAT(E1000_VFMPRC,
1028             hw_stats->last_mprc, hw_stats->mprc);
1029
1030         /* Good Rx loopback packets */
1031         UPDATE_VF_STAT(E1000_VFGPRLBC,
1032             hw_stats->last_gprlbc, hw_stats->gprlbc);
1033
1034         /* Good Rx loopback octets */
1035         UPDATE_VF_STAT(E1000_VFGORLBC,
1036             hw_stats->last_gorlbc, hw_stats->gorlbc);
1037
1038         /* Good Tx loopback packets */
1039         UPDATE_VF_STAT(E1000_VFGPTLBC,
1040             hw_stats->last_gptlbc, hw_stats->gptlbc);
1041
1042         /* Good Tx loopback octets */
1043         UPDATE_VF_STAT(E1000_VFGOTLBC,
1044             hw_stats->last_gotlbc, hw_stats->gotlbc);
1045
1046         if (rte_stats == NULL)
1047                 return;
1048
1049         memset(rte_stats, 0, sizeof(*rte_stats));
1050         rte_stats->ipackets = hw_stats->gprc;
1051         rte_stats->ibytes = hw_stats->gorc;
1052         rte_stats->opackets = hw_stats->gptc;
1053         rte_stats->obytes = hw_stats->gotc;
1054         rte_stats->imcasts = hw_stats->mprc;
1055         rte_stats->ilbpackets = hw_stats->gprlbc;
1056         rte_stats->ilbbytes = hw_stats->gorlbc;
1057         rte_stats->olbpackets = hw_stats->gptlbc;
1058         rte_stats->olbbytes = hw_stats->gotlbc;
1059
1060 }
1061
1062 static void
1063 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1064 {
1065         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1066                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1067
1068         /* Sync HW register to the last stats */
1069         eth_igbvf_stats_get(dev, NULL);
1070
1071         /* reset HW current stats*/
1072         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1073                offsetof(struct e1000_vf_stats, gprc));
1074
1075 }
1076
1077 static void
1078 eth_igb_infos_get(struct rte_eth_dev *dev,
1079                     struct rte_eth_dev_info *dev_info)
1080 {
1081         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1082
1083         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1084         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1085         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1086
1087         switch (hw->mac.type) {
1088         case e1000_82575:
1089                 dev_info->max_rx_queues = 4;
1090                 dev_info->max_tx_queues = 4;
1091                 break;
1092
1093         case e1000_82576:
1094                 dev_info->max_rx_queues = 16;
1095                 dev_info->max_tx_queues = 16;
1096                 break;
1097
1098         case e1000_82580:
1099                 dev_info->max_rx_queues = 8;
1100                 dev_info->max_tx_queues = 8;
1101                 break;
1102
1103         case e1000_i350:
1104                 dev_info->max_rx_queues = 8;
1105                 dev_info->max_tx_queues = 8;
1106                 break;
1107
1108         case e1000_i210:
1109                 dev_info->max_rx_queues = 4;
1110                 dev_info->max_tx_queues = 4;
1111                 break;
1112
1113         case e1000_vfadapt:
1114                 dev_info->max_rx_queues = 2;
1115                 dev_info->max_tx_queues = 2;
1116                 break;
1117
1118         case e1000_vfadapt_i350:
1119                 dev_info->max_rx_queues = 1;
1120                 dev_info->max_tx_queues = 1;
1121                 break;
1122
1123         default:
1124                 /* Should not happen */
1125                 dev_info->max_rx_queues = 0;
1126                 dev_info->max_tx_queues = 0;
1127         }
1128 }
1129
1130 /* return 0 means link status changed, -1 means not changed */
1131 static int
1132 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1133 {
1134         struct e1000_hw *hw =
1135                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1136         struct rte_eth_link link, old;
1137         int link_check, count;
1138
1139         link_check = 0;
1140         hw->mac.get_link_status = 1;
1141
1142         /* possible wait-to-complete in up to 9 seconds */
1143         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1144                 /* Read the real link status */
1145                 switch (hw->phy.media_type) {
1146                 case e1000_media_type_copper:
1147                         /* Do the work to read phy */
1148                         e1000_check_for_link(hw);
1149                         link_check = !hw->mac.get_link_status;
1150                         break;
1151
1152                 case e1000_media_type_fiber:
1153                         e1000_check_for_link(hw);
1154                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1155                                       E1000_STATUS_LU);
1156                         break;
1157
1158                 case e1000_media_type_internal_serdes:
1159                         e1000_check_for_link(hw);
1160                         link_check = hw->mac.serdes_has_link;
1161                         break;
1162
1163                 /* VF device is type_unknown */
1164                 case e1000_media_type_unknown:
1165                         eth_igbvf_link_update(hw);
1166                         link_check = !hw->mac.get_link_status;
1167                         break;
1168
1169                 default:
1170                         break;
1171                 }
1172                 if (link_check || wait_to_complete == 0)
1173                         break;
1174                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1175         }
1176         memset(&link, 0, sizeof(link));
1177         rte_igb_dev_atomic_read_link_status(dev, &link);
1178         old = link;
1179
1180         /* Now we check if a transition has happened */
1181         if (link_check) {
1182                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1183                                           &link.link_duplex);
1184                 link.link_status = 1;
1185         } else if (!link_check) {
1186                 link.link_speed = 0;
1187                 link.link_duplex = 0;
1188                 link.link_status = 0;
1189         }
1190         rte_igb_dev_atomic_write_link_status(dev, &link);
1191
1192         /* not changed */
1193         if (old.link_status == link.link_status)
1194                 return -1;
1195
1196         /* changed */
1197         return 0;
1198 }
1199
1200 /*
1201  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1202  * For ASF and Pass Through versions of f/w this means
1203  * that the driver is loaded.
1204  */
1205 static void
1206 igb_hw_control_acquire(struct e1000_hw *hw)
1207 {
1208         uint32_t ctrl_ext;
1209
1210         /* Let firmware know the driver has taken over */
1211         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1212         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1213 }
1214
1215 /*
1216  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1217  * For ASF and Pass Through versions of f/w this means that the
1218  * driver is no longer loaded.
1219  */
1220 static void
1221 igb_hw_control_release(struct e1000_hw *hw)
1222 {
1223         uint32_t ctrl_ext;
1224
1225         /* Let firmware taken over control of h/w */
1226         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1227         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1228                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1229 }
1230
1231 /*
1232  * Bit of a misnomer, what this really means is
1233  * to enable OS management of the system... aka
1234  * to disable special hardware management features.
1235  */
1236 static void
1237 igb_init_manageability(struct e1000_hw *hw)
1238 {
1239         if (e1000_enable_mng_pass_thru(hw)) {
1240                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1241                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1242
1243                 /* disable hardware interception of ARP */
1244                 manc &= ~(E1000_MANC_ARP_EN);
1245
1246                 /* enable receiving management packets to the host */
1247                 manc |= E1000_MANC_EN_MNG2HOST;
1248                 manc2h |= 1 << 5;  /* Mng Port 623 */
1249                 manc2h |= 1 << 6;  /* Mng Port 664 */
1250                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1251                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1252         }
1253 }
1254
1255 static void
1256 igb_release_manageability(struct e1000_hw *hw)
1257 {
1258         if (e1000_enable_mng_pass_thru(hw)) {
1259                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1260
1261                 manc |= E1000_MANC_ARP_EN;
1262                 manc &= ~E1000_MANC_EN_MNG2HOST;
1263
1264                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1265         }
1266 }
1267
1268 static void
1269 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1270 {
1271         struct e1000_hw *hw =
1272                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1273         uint32_t rctl;
1274
1275         rctl = E1000_READ_REG(hw, E1000_RCTL);
1276         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1277         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1278 }
1279
1280 static void
1281 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1282 {
1283         struct e1000_hw *hw =
1284                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1285         uint32_t rctl;
1286
1287         rctl = E1000_READ_REG(hw, E1000_RCTL);
1288         rctl &= (~E1000_RCTL_UPE);
1289         if (dev->data->all_multicast == 1)
1290                 rctl |= E1000_RCTL_MPE;
1291         else
1292                 rctl &= (~E1000_RCTL_MPE);
1293         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1294 }
1295
1296 static void
1297 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1298 {
1299         struct e1000_hw *hw =
1300                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1301         uint32_t rctl;
1302
1303         rctl = E1000_READ_REG(hw, E1000_RCTL);
1304         rctl |= E1000_RCTL_MPE;
1305         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1306 }
1307
1308 static void
1309 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1310 {
1311         struct e1000_hw *hw =
1312                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1313         uint32_t rctl;
1314
1315         if (dev->data->promiscuous == 1)
1316                 return; /* must remain in all_multicast mode */
1317         rctl = E1000_READ_REG(hw, E1000_RCTL);
1318         rctl &= (~E1000_RCTL_MPE);
1319         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1320 }
1321
1322 static int
1323 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1324 {
1325         struct e1000_hw *hw =
1326                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1327         struct e1000_vfta * shadow_vfta =
1328                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1329         uint32_t vfta;
1330         uint32_t vid_idx;
1331         uint32_t vid_bit;
1332
1333         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1334                               E1000_VFTA_ENTRY_MASK);
1335         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1336         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1337         if (on)
1338                 vfta |= vid_bit;
1339         else
1340                 vfta &= ~vid_bit;
1341         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1342
1343         /* update local VFTA copy */
1344         shadow_vfta->vfta[vid_idx] = vfta;
1345
1346         return 0;
1347 }
1348
1349 static void
1350 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1351 {
1352         struct e1000_hw *hw =
1353                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1354         uint32_t reg = ETHER_TYPE_VLAN ;
1355
1356         reg |= (tpid << 16);
1357         E1000_WRITE_REG(hw, E1000_VET, reg);
1358 }
1359
1360 static void
1361 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1362 {
1363         struct e1000_hw *hw =
1364                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1365         uint32_t reg;
1366
1367         /* Filter Table Disable */
1368         reg = E1000_READ_REG(hw, E1000_RCTL);
1369         reg &= ~E1000_RCTL_CFIEN;
1370         reg &= ~E1000_RCTL_VFE;
1371         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1372 }
1373
1374 static void
1375 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1376 {
1377         struct e1000_hw *hw =
1378                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1379         struct e1000_vfta * shadow_vfta =
1380                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1381         uint32_t reg;
1382         int i;
1383
1384         /* Filter Table Enable, CFI not used for packet acceptance */
1385         reg = E1000_READ_REG(hw, E1000_RCTL);
1386         reg &= ~E1000_RCTL_CFIEN;
1387         reg |= E1000_RCTL_VFE;
1388         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1389
1390         /* restore VFTA table */
1391         for (i = 0; i < IGB_VFTA_SIZE; i++)
1392                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1393 }
1394
1395 static void
1396 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1397 {
1398         struct e1000_hw *hw =
1399                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400         uint32_t reg;
1401
1402         /* VLAN Mode Disable */
1403         reg = E1000_READ_REG(hw, E1000_CTRL);
1404         reg &= ~E1000_CTRL_VME;
1405         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1406 }
1407
1408 static void
1409 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1410 {
1411         struct e1000_hw *hw =
1412                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1413         uint32_t reg;
1414
1415         /* VLAN Mode Enable */
1416         reg = E1000_READ_REG(hw, E1000_CTRL);
1417         reg |= E1000_CTRL_VME;
1418         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1419 }
1420
1421 static void
1422 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1423 {
1424         struct e1000_hw *hw =
1425                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426         uint32_t reg;
1427
1428         /* CTRL_EXT: Extended VLAN */
1429         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1430         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1431         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1432
1433         /* Update maximum packet length */
1434         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1435                 E1000_WRITE_REG(hw, E1000_RLPML,
1436                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1437                                                 VLAN_TAG_SIZE);
1438 }
1439
1440 static void
1441 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1442 {
1443         struct e1000_hw *hw =
1444                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445         uint32_t reg;
1446
1447         /* CTRL_EXT: Extended VLAN */
1448         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1449         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1450         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1451
1452         /* Update maximum packet length */
1453         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1454                 E1000_WRITE_REG(hw, E1000_RLPML,
1455                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1456                                                 2 * VLAN_TAG_SIZE);
1457 }
1458
1459 static void
1460 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1461 {
1462         if(mask & ETH_VLAN_STRIP_MASK){
1463                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1464                         igb_vlan_hw_strip_enable(dev);
1465                 else
1466                         igb_vlan_hw_strip_disable(dev);
1467         }
1468
1469         if(mask & ETH_VLAN_FILTER_MASK){
1470                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1471                         igb_vlan_hw_filter_enable(dev);
1472                 else
1473                         igb_vlan_hw_filter_disable(dev);
1474         }
1475
1476         if(mask & ETH_VLAN_EXTEND_MASK){
1477                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1478                         igb_vlan_hw_extend_enable(dev);
1479                 else
1480                         igb_vlan_hw_extend_disable(dev);
1481         }
1482 }
1483
1484
1485 /**
1486  * It enables the interrupt mask and then enable the interrupt.
1487  *
1488  * @param dev
1489  *  Pointer to struct rte_eth_dev.
1490  *
1491  * @return
1492  *  - On success, zero.
1493  *  - On failure, a negative value.
1494  */
1495 static int
1496 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1497 {
1498         struct e1000_interrupt *intr =
1499                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1500
1501         intr->mask |= E1000_ICR_LSC;
1502
1503         return 0;
1504 }
1505
1506 /*
1507  * It reads ICR and gets interrupt causes, check it and set a bit flag
1508  * to update link status.
1509  *
1510  * @param dev
1511  *  Pointer to struct rte_eth_dev.
1512  *
1513  * @return
1514  *  - On success, zero.
1515  *  - On failure, a negative value.
1516  */
1517 static int
1518 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1519 {
1520         uint32_t icr;
1521         struct e1000_hw *hw =
1522                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1523         struct e1000_interrupt *intr =
1524                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1525
1526         igb_intr_disable(hw);
1527
1528         /* read-on-clear nic registers here */
1529         icr = E1000_READ_REG(hw, E1000_ICR);
1530
1531         intr->flags = 0;
1532         if (icr & E1000_ICR_LSC) {
1533                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1534         }
1535
1536         if (icr & E1000_ICR_VMMB)
1537                 intr->flags |= E1000_FLAG_MAILBOX;
1538
1539         return 0;
1540 }
1541
1542 /*
1543  * It executes link_update after knowing an interrupt is prsent.
1544  *
1545  * @param dev
1546  *  Pointer to struct rte_eth_dev.
1547  *
1548  * @return
1549  *  - On success, zero.
1550  *  - On failure, a negative value.
1551  */
1552 static int
1553 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1554 {
1555         struct e1000_hw *hw =
1556                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1557         struct e1000_interrupt *intr =
1558                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1559         uint32_t tctl, rctl;
1560         struct rte_eth_link link;
1561         int ret;
1562
1563         if (intr->flags & E1000_FLAG_MAILBOX) {
1564                 igb_pf_mbx_process(dev);
1565                 intr->flags &= ~E1000_FLAG_MAILBOX;
1566         }
1567
1568         igb_intr_enable(dev);
1569         rte_intr_enable(&(dev->pci_dev->intr_handle));
1570
1571         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1572                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1573
1574                 /* set get_link_status to check register later */
1575                 hw->mac.get_link_status = 1;
1576                 ret = eth_igb_link_update(dev, 0);
1577
1578                 /* check if link has changed */
1579                 if (ret < 0)
1580                         return 0;
1581
1582                 memset(&link, 0, sizeof(link));
1583                 rte_igb_dev_atomic_read_link_status(dev, &link);
1584                 if (link.link_status) {
1585                         PMD_INIT_LOG(INFO,
1586                                 " Port %d: Link Up - speed %u Mbps - %s\n",
1587                                 dev->data->port_id, (unsigned)link.link_speed,
1588                                 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1589                                         "full-duplex" : "half-duplex");
1590                 } else {
1591                         PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1592                                                 dev->data->port_id);
1593                 }
1594                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1595                                         dev->pci_dev->addr.domain,
1596                                         dev->pci_dev->addr.bus,
1597                                         dev->pci_dev->addr.devid,
1598                                         dev->pci_dev->addr.function);
1599                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1600                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1601                 if (link.link_status) {
1602                         /* enable Tx/Rx */
1603                         tctl |= E1000_TCTL_EN;
1604                         rctl |= E1000_RCTL_EN;
1605                 } else {
1606                         /* disable Tx/Rx */
1607                         tctl &= ~E1000_TCTL_EN;
1608                         rctl &= ~E1000_RCTL_EN;
1609                 }
1610                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1611                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1612                 E1000_WRITE_FLUSH(hw);
1613                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1614         }
1615
1616         return 0;
1617 }
1618
1619 /**
1620  * Interrupt handler which shall be registered at first.
1621  *
1622  * @param handle
1623  *  Pointer to interrupt handle.
1624  * @param param
1625  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1626  *
1627  * @return
1628  *  void
1629  */
1630 static void
1631 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1632                                                         void *param)
1633 {
1634         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1635
1636         eth_igb_interrupt_get_status(dev);
1637         eth_igb_interrupt_action(dev);
1638 }
1639
1640 static int
1641 eth_igb_led_on(struct rte_eth_dev *dev)
1642 {
1643         struct e1000_hw *hw;
1644
1645         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1647 }
1648
1649 static int
1650 eth_igb_led_off(struct rte_eth_dev *dev)
1651 {
1652         struct e1000_hw *hw;
1653
1654         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1656 }
1657
1658 static int
1659 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1660 {
1661         struct e1000_hw *hw;
1662         int err;
1663         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1664                 e1000_fc_none,
1665                 e1000_fc_rx_pause,
1666                 e1000_fc_tx_pause,
1667                 e1000_fc_full
1668         };
1669         uint32_t rx_buf_size;
1670         uint32_t max_high_water;
1671
1672         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1673         rx_buf_size = igb_get_rx_buffer_size(hw);
1674         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1675
1676         /* At least reserve one Ethernet frame for watermark */
1677         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1678         if ((fc_conf->high_water > max_high_water) ||
1679                 (fc_conf->high_water < fc_conf->low_water)) {
1680                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1681                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1682                 return (-EINVAL);
1683         }
1684
1685         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1686         hw->fc.pause_time     = fc_conf->pause_time;
1687         hw->fc.high_water     = fc_conf->high_water;
1688         hw->fc.low_water      = fc_conf->low_water;
1689         hw->fc.send_xon       = fc_conf->send_xon;
1690
1691         err = e1000_setup_link_generic(hw);
1692         if (err == E1000_SUCCESS) {
1693                 return 0;
1694         }
1695
1696         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1697         return (-EIO);
1698 }
1699
1700 #define E1000_RAH_POOLSEL_SHIFT      (18)
1701 static void
1702 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1703                 uint32_t index, __rte_unused uint32_t pool)
1704 {
1705         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1706         uint32_t rah;
1707
1708         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1709         rah = E1000_READ_REG(hw, E1000_RAH(index));
1710         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
1711         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
1712 }
1713
1714 static void
1715 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1716 {
1717         uint8_t addr[ETHER_ADDR_LEN];
1718         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719
1720         memset(addr, 0, sizeof(addr));
1721
1722         e1000_rar_set(hw, addr, index);
1723 }
1724
1725 /*
1726  * Virtual Function operations
1727  */
1728 static void
1729 igbvf_intr_disable(struct e1000_hw *hw)
1730 {
1731         PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1732
1733         /* Clear interrupt mask to stop from interrupts being generated */
1734         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
1735
1736         E1000_WRITE_FLUSH(hw);
1737 }
1738
1739 static void
1740 igbvf_stop_adapter(struct rte_eth_dev *dev)
1741 {
1742         u32 reg_val;
1743         u16 i;
1744         struct rte_eth_dev_info dev_info;
1745         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1746
1747         memset(&dev_info, 0, sizeof(dev_info));
1748         eth_igb_infos_get(dev, &dev_info);
1749
1750         /* Clear interrupt mask to stop from interrupts being generated */
1751         igbvf_intr_disable(hw);
1752
1753         /* Clear any pending interrupts, flush previous writes */
1754         E1000_READ_REG(hw, E1000_EICR);
1755
1756         /* Disable the transmit unit.  Each queue must be disabled. */
1757         for (i = 0; i < dev_info.max_tx_queues; i++)
1758                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1759
1760         /* Disable the receive unit by stopping each queue */
1761         for (i = 0; i < dev_info.max_rx_queues; i++) {
1762                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1763                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1764                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1765                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1766                         ;
1767         }
1768
1769         /* flush all queues disables */
1770         E1000_WRITE_FLUSH(hw);
1771         msec_delay(2);
1772 }
1773
1774 static int eth_igbvf_link_update(struct e1000_hw *hw)
1775 {
1776         struct e1000_mbx_info *mbx = &hw->mbx;
1777         struct e1000_mac_info *mac = &hw->mac;
1778         int ret_val = E1000_SUCCESS;
1779
1780         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1781
1782         /*
1783          * We only want to run this if there has been a rst asserted.
1784          * in this case that could mean a link change, device reset,
1785          * or a virtual function reset
1786          */
1787
1788         /* If we were hit with a reset or timeout drop the link */
1789         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1790                 mac->get_link_status = TRUE;
1791
1792         if (!mac->get_link_status)
1793                 goto out;
1794
1795         /* if link status is down no point in checking to see if pf is up */
1796         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1797                 goto out;
1798
1799         /* if we passed all the tests above then the link is up and we no
1800          * longer need to check for link */
1801         mac->get_link_status = FALSE;
1802
1803 out:
1804         return ret_val;
1805 }
1806
1807
1808 static int
1809 igbvf_dev_configure(struct rte_eth_dev *dev)
1810 {
1811         struct rte_eth_conf* conf = &dev->data->dev_conf;
1812
1813         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1814                 dev->data->port_id);
1815
1816         /*
1817          * VF has no ability to enable/disable HW CRC
1818          * Keep the persistent behavior the same as Host PF
1819          */
1820 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1821         if (!conf->rxmode.hw_strip_crc) {
1822                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1823                 conf->rxmode.hw_strip_crc = 1;
1824         }
1825 #else
1826         if (conf->rxmode.hw_strip_crc) {
1827                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1828                 conf->rxmode.hw_strip_crc = 0;
1829         }
1830 #endif
1831
1832         return 0;
1833 }
1834
1835 static int
1836 igbvf_dev_start(struct rte_eth_dev *dev)
1837 {
1838         struct e1000_hw *hw =
1839                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840         int ret;
1841
1842         PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1843
1844         hw->mac.ops.reset_hw(hw);
1845
1846         /* Set all vfta */
1847         igbvf_set_vfta_all(dev,1);
1848
1849         eth_igbvf_tx_init(dev);
1850
1851         /* This can fail when allocating mbufs for descriptor rings */
1852         ret = eth_igbvf_rx_init(dev);
1853         if (ret) {
1854                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1855                 igb_dev_clear_queues(dev);
1856                 return ret;
1857         }
1858
1859         return 0;
1860 }
1861
1862 static void
1863 igbvf_dev_stop(struct rte_eth_dev *dev)
1864 {
1865         PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1866
1867         igbvf_stop_adapter(dev);
1868
1869         /*
1870           * Clear what we set, but we still keep shadow_vfta to
1871           * restore after device starts
1872           */
1873         igbvf_set_vfta_all(dev,0);
1874
1875         igb_dev_clear_queues(dev);
1876 }
1877
1878 static void
1879 igbvf_dev_close(struct rte_eth_dev *dev)
1880 {
1881         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1882
1883         PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1884
1885         e1000_reset_hw(hw);
1886
1887         igbvf_dev_stop(dev);
1888 }
1889
1890 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1891 {
1892         struct e1000_mbx_info *mbx = &hw->mbx;
1893         uint32_t msgbuf[2];
1894
1895         /* After set vlan, vlan strip will also be enabled in igb driver*/
1896         msgbuf[0] = E1000_VF_SET_VLAN;
1897         msgbuf[1] = vid;
1898         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1899         if (on)
1900                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1901
1902         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1903 }
1904
1905 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1906 {
1907         struct e1000_hw *hw =
1908                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1909         struct e1000_vfta * shadow_vfta =
1910                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1911         int i = 0, j = 0, vfta = 0, mask = 1;
1912
1913         for (i = 0; i < IGB_VFTA_SIZE; i++){
1914                 vfta = shadow_vfta->vfta[i];
1915                 if(vfta){
1916                         mask = 1;
1917                         for (j = 0; j < 32; j++){
1918                                 if(vfta & mask)
1919                                         igbvf_set_vfta(hw,
1920                                                 (uint16_t)((i<<5)+j), on);
1921                                 mask<<=1;
1922                         }
1923                 }
1924         }
1925
1926 }
1927
1928 static int
1929 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1930 {
1931         struct e1000_hw *hw =
1932                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1933         struct e1000_vfta * shadow_vfta =
1934                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1935         uint32_t vid_idx = 0;
1936         uint32_t vid_bit = 0;
1937         int ret = 0;
1938
1939         PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
1940
1941         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
1942         ret = igbvf_set_vfta(hw, vlan_id, !!on);
1943         if(ret){
1944                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
1945                 return ret;
1946         }
1947         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1948         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1949
1950         /*Save what we set and retore it after device reset*/
1951         if (on)
1952                 shadow_vfta->vfta[vid_idx] |= vid_bit;
1953         else
1954                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
1955
1956         return 0;
1957 }
1958
1959 static int
1960 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
1961                                 struct rte_eth_rss_reta *reta_conf)
1962 {
1963         uint8_t i,j,mask;
1964         uint32_t reta;
1965         struct e1000_hw *hw =
1966                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1967
1968         /*
1969          * Update Redirection Table RETA[n],n=0...31,The redirection table has
1970          * 128-entries in 32 registers
1971          */
1972         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1973                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
1974                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1975                 else
1976                         mask = (uint8_t)((reta_conf->mask_hi >>
1977                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
1978                 if (mask != 0) {
1979                         reta = 0;
1980                         /* If all 4 entries were set,don't need read RETA register */
1981                         if (mask != 0xF)
1982                                 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
1983
1984                         for (j = 0; j < 4; j++) {
1985                                 if (mask & (0x1 << j)) {
1986                                         if (mask != 0xF)
1987                                                 reta &= ~(0xFF << 8 * j);
1988                                         reta |= reta_conf->reta[i + j] << 8 * j;
1989                                 }
1990                         }
1991                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
1992                 }
1993         }
1994
1995         return 0;
1996 }
1997
1998 static int
1999 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2000                                 struct rte_eth_rss_reta *reta_conf)
2001 {
2002         uint8_t i,j,mask;
2003         uint32_t reta;
2004         struct e1000_hw *hw =
2005                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006
2007         /*
2008          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2009          * 128-entries in 32 registers
2010          */
2011         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2012                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2013                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2014                 else
2015                         mask = (uint8_t)((reta_conf->mask_hi >>
2016                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2017
2018                 if (mask != 0) {
2019                         reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2020                         for (j = 0; j < 4; j++) {
2021                                 if (mask & (0x1 << j))
2022                                         reta_conf->reta[i + j] =
2023                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2024                         }
2025                 }
2026         }
2027
2028         return 0;
2029 }