lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 static int  eth_igb_configure(struct rte_eth_dev *dev);
  61 static int  eth_igb_start(struct rte_eth_dev *dev);
  62 static void eth_igb_stop(struct rte_eth_dev *dev);
  63 static void eth_igb_close(struct rte_eth_dev *dev);
  64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  68 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  69                                 int wait_to_complete);
  70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  71                                 struct rte_eth_stats *rte_stats);
  72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  74                                 struct rte_eth_dev_info *dev_info);
  75 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
  76                                 struct rte_eth_fc_conf *fc_conf);
  77 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  78                                 struct rte_eth_fc_conf *fc_conf);
  79 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  80 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  81 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  82 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  83                                                         void *param);
  84 static int  igb_hardware_init(struct e1000_hw *hw);
  85 static void igb_hw_control_acquire(struct e1000_hw *hw);
  86 static void igb_hw_control_release(struct e1000_hw *hw);
  87 static void igb_init_manageability(struct e1000_hw *hw);
  88 static void igb_release_manageability(struct e1000_hw *hw);
  89
  90 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  91
  92 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  93                 uint16_t vlan_id, int on);
  94 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
  95 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  96
  97 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  98 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  99 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 100 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 101 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 102 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 103
 104 static int eth_igb_led_on(struct rte_eth_dev *dev);
 105 static int eth_igb_led_off(struct rte_eth_dev *dev);
 106
 107 static void igb_intr_disable(struct e1000_hw *hw);
 108 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 109 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 110                 struct ether_addr *mac_addr,
 111                 uint32_t index, uint32_t pool);
 112 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 113
 114 static void igbvf_intr_disable(struct e1000_hw *hw);
 115 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 116 static int igbvf_dev_start(struct rte_eth_dev *dev);
 117 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 118 static void igbvf_dev_close(struct rte_eth_dev *dev);
 119 static int eth_igbvf_link_update(struct e1000_hw *hw);
 120 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 121 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 122 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 123                 uint16_t vlan_id, int on);
 124 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 125 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 126 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 127                  struct rte_eth_rss_reta *reta_conf);
 128 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 129                 struct rte_eth_rss_reta *reta_conf);
 130
 131 static int eth_igb_add_syn_filter(struct rte_eth_dev *dev,
 132                         struct rte_syn_filter *filter, uint16_t rx_queue);
 133 static int eth_igb_remove_syn_filter(struct rte_eth_dev *dev);
 134 static int eth_igb_get_syn_filter(struct rte_eth_dev *dev,
 135                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 136 static int eth_igb_add_ethertype_filter(struct rte_eth_dev *dev,
 137                         uint16_t index,
 138                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 139 static int eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev,
 140                         uint16_t index);
 141 static int eth_igb_get_ethertype_filter(struct rte_eth_dev *dev,
 142                         uint16_t index,
 143                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 144 static int eth_igb_add_2tuple_filter(struct rte_eth_dev *dev,
 145                         uint16_t index,
 146                         struct rte_2tuple_filter *filter, uint16_t rx_queue);
 147 static int eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 148                         uint16_t index);
 149 static int eth_igb_get_2tuple_filter(struct rte_eth_dev *dev,
 150                         uint16_t index,
 151                         struct rte_2tuple_filter *filter, uint16_t *rx_queue);
 152 static int eth_igb_add_flex_filter(struct rte_eth_dev *dev,
 153                         uint16_t index,
 154                         struct rte_flex_filter *filter, uint16_t rx_queue);
 155 static int eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
 156                         uint16_t index);
 157 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 158                         uint16_t index,
 159                         struct rte_flex_filter *filter, uint16_t *rx_queue);
 160 static int eth_igb_add_5tuple_filter(struct rte_eth_dev *dev,
 161                         uint16_t index,
 162                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 163 static int eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
 164                         uint16_t index);
 165 static int eth_igb_get_5tuple_filter(struct rte_eth_dev *dev,
 166                         uint16_t index,
 167                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 168
 169 /*
 170  * Define VF Stats MACRO for Non "cleared on read" register
 171  */
 172 #define UPDATE_VF_STAT(reg, last, cur)            \
 173 {                                                 \
 174         u32 latest = E1000_READ_REG(hw, reg);     \
 175         cur += latest - last;                     \
 176         last = latest;                            \
 177 }
 178
 179
 180 #define IGB_FC_PAUSE_TIME 0x0680
 181 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 182 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 183
 184 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 185
 186 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 187
 188 /*
 189  * The set of PCI devices this driver supports
 190  */
 191 static struct rte_pci_id pci_id_igb_map[] = {
 192
 193 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 194 #include "rte_pci_dev_ids.h"
 195
 196 {.device_id = 0},
 197 };
 198
 199 /*
 200  * The set of PCI devices this driver supports (for 82576&I350 VF)
 201  */
 202 static struct rte_pci_id pci_id_igbvf_map[] = {
 203
 204 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 205 #include "rte_pci_dev_ids.h"
 206
 207 {.device_id = 0},
 208 };
 209
 210 static struct eth_dev_ops eth_igb_ops = {
 211         .dev_configure        = eth_igb_configure,
 212         .dev_start            = eth_igb_start,
 213         .dev_stop             = eth_igb_stop,
 214         .dev_close            = eth_igb_close,
 215         .promiscuous_enable   = eth_igb_promiscuous_enable,
 216         .promiscuous_disable  = eth_igb_promiscuous_disable,
 217         .allmulticast_enable  = eth_igb_allmulticast_enable,
 218         .allmulticast_disable = eth_igb_allmulticast_disable,
 219         .link_update          = eth_igb_link_update,
 220         .stats_get            = eth_igb_stats_get,
 221         .stats_reset          = eth_igb_stats_reset,
 222         .dev_infos_get        = eth_igb_infos_get,
 223         .mtu_set              = eth_igb_mtu_set,
 224         .vlan_filter_set      = eth_igb_vlan_filter_set,
 225         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 226         .vlan_offload_set     = eth_igb_vlan_offload_set,
 227         .rx_queue_setup       = eth_igb_rx_queue_setup,
 228         .rx_queue_release     = eth_igb_rx_queue_release,
 229         .rx_queue_count       = eth_igb_rx_queue_count,
 230         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 231         .tx_queue_setup       = eth_igb_tx_queue_setup,
 232         .tx_queue_release     = eth_igb_tx_queue_release,
 233         .dev_led_on           = eth_igb_led_on,
 234         .dev_led_off          = eth_igb_led_off,
 235         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 236         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 237         .mac_addr_add         = eth_igb_rar_set,
 238         .mac_addr_remove      = eth_igb_rar_clear,
 239         .reta_update          = eth_igb_rss_reta_update,
 240         .reta_query           = eth_igb_rss_reta_query,
 241         .rss_hash_update      = eth_igb_rss_hash_update,
 242         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 243         .add_syn_filter          = eth_igb_add_syn_filter,
 244         .remove_syn_filter       = eth_igb_remove_syn_filter,
 245         .get_syn_filter          = eth_igb_get_syn_filter,
 246         .add_ethertype_filter    = eth_igb_add_ethertype_filter,
 247         .remove_ethertype_filter = eth_igb_remove_ethertype_filter,
 248         .get_ethertype_filter    = eth_igb_get_ethertype_filter,
 249         .add_2tuple_filter       = eth_igb_add_2tuple_filter,
 250         .remove_2tuple_filter    = eth_igb_remove_2tuple_filter,
 251         .get_2tuple_filter       = eth_igb_get_2tuple_filter,
 252         .add_flex_filter         = eth_igb_add_flex_filter,
 253         .remove_flex_filter      = eth_igb_remove_flex_filter,
 254         .get_flex_filter         = eth_igb_get_flex_filter,
 255         .add_5tuple_filter       = eth_igb_add_5tuple_filter,
 256         .remove_5tuple_filter    = eth_igb_remove_5tuple_filter,
 257         .get_5tuple_filter       = eth_igb_get_5tuple_filter,
 258 };
 259
 260 /*
 261  * dev_ops for virtual function, bare necessities for basic vf
 262  * operation have been implemented
 263  */
 264 static struct eth_dev_ops igbvf_eth_dev_ops = {
 265         .dev_configure        = igbvf_dev_configure,
 266         .dev_start            = igbvf_dev_start,
 267         .dev_stop             = igbvf_dev_stop,
 268         .dev_close            = igbvf_dev_close,
 269         .link_update          = eth_igb_link_update,
 270         .stats_get            = eth_igbvf_stats_get,
 271         .stats_reset          = eth_igbvf_stats_reset,
 272         .vlan_filter_set      = igbvf_vlan_filter_set,
 273         .dev_infos_get        = eth_igb_infos_get,
 274         .rx_queue_setup       = eth_igb_rx_queue_setup,
 275         .rx_queue_release     = eth_igb_rx_queue_release,
 276         .tx_queue_setup       = eth_igb_tx_queue_setup,
 277         .tx_queue_release     = eth_igb_tx_queue_release,
 278 };
 279
 280 /**
 281  * Atomically reads the link status information from global
 282  * structure rte_eth_dev.
 283  *
 284  * @param dev
 285  *   - Pointer to the structure rte_eth_dev to read from.
 286  *   - Pointer to the buffer to be saved with the link status.
 287  *
 288  * @return
 289  *   - On success, zero.
 290  *   - On failure, negative value.
 291  */
 292 static inline int
 293 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 294                                 struct rte_eth_link *link)
 295 {
 296         struct rte_eth_link *dst = link;
 297         struct rte_eth_link *src = &(dev->data->dev_link);
 298
 299         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 300                                         *(uint64_t *)src) == 0)
 301                 return -1;
 302
 303         return 0;
 304 }
 305
 306 /**
 307  * Atomically writes the link status information into global
 308  * structure rte_eth_dev.
 309  *
 310  * @param dev
 311  *   - Pointer to the structure rte_eth_dev to read from.
 312  *   - Pointer to the buffer to be saved with the link status.
 313  *
 314  * @return
 315  *   - On success, zero.
 316  *   - On failure, negative value.
 317  */
 318 static inline int
 319 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 320                                 struct rte_eth_link *link)
 321 {
 322         struct rte_eth_link *dst = &(dev->data->dev_link);
 323         struct rte_eth_link *src = link;
 324
 325         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 326                                         *(uint64_t *)src) == 0)
 327                 return -1;
 328
 329         return 0;
 330 }
 331
 332 static inline void
 333 igb_intr_enable(struct rte_eth_dev *dev)
 334 {
 335         struct e1000_interrupt *intr =
 336                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 337         struct e1000_hw *hw =
 338                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 339
 340         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 341         E1000_WRITE_FLUSH(hw);
 342 }
 343
 344 static void
 345 igb_intr_disable(struct e1000_hw *hw)
 346 {
 347         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 348         E1000_WRITE_FLUSH(hw);
 349 }
 350
 351 static inline int32_t
 352 igb_pf_reset_hw(struct e1000_hw *hw)
 353 {
 354         uint32_t ctrl_ext;
 355         int32_t status;
 356
 357         status = e1000_reset_hw(hw);
 358
 359         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 360         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 361         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 362         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 363         E1000_WRITE_FLUSH(hw);
 364
 365         return status;
 366 }
 367
 368 static void
 369 igb_identify_hardware(struct rte_eth_dev *dev)
 370 {
 371         struct e1000_hw *hw =
 372                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 373
 374         hw->vendor_id = dev->pci_dev->id.vendor_id;
 375         hw->device_id = dev->pci_dev->id.device_id;
 376         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 377         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 378
 379         e1000_set_mac_type(hw);
 380
 381         /* need to check if it is a vf device below */
 382 }
 383
 384 static int
 385 igb_reset_swfw_lock(struct e1000_hw *hw)
 386 {
 387         int ret_val;
 388
 389         /*
 390          * Do mac ops initialization manually here, since we will need
 391          * some function pointers set by this call.
 392          */
 393         ret_val = e1000_init_mac_params(hw);
 394         if (ret_val)
 395                 return ret_val;
 396
 397         /*
 398          * SMBI lock should not fail in this early stage. If this is the case,
 399          * it is due to an improper exit of the application.
 400          * So force the release of the faulty lock.
 401          */
 402         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 403                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 404         }
 405         e1000_put_hw_semaphore_generic(hw);
 406
 407         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 408                 uint16_t mask;
 409
 410                 /*
 411                  * Phy lock should not fail in this early stage. If this is the case,
 412                  * it is due to an improper exit of the application.
 413                  * So force the release of the faulty lock.
 414                  */
 415                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 416                 if (hw->bus.func > E1000_FUNC_1)
 417                         mask <<= 2;
 418                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 419                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 420                                     hw->bus.func);
 421                 }
 422                 hw->mac.ops.release_swfw_sync(hw, mask);
 423
 424                 /*
 425                  * This one is more tricky since it is common to all ports; but
 426                  * swfw_sync retries last long enough (1s) to be almost sure that if
 427                  * lock can not be taken it is due to an improper lock of the
 428                  * semaphore.
 429                  */
 430                 mask = E1000_SWFW_EEP_SM;
 431                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 432                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 433                 }
 434                 hw->mac.ops.release_swfw_sync(hw, mask);
 435         }
 436
 437         return E1000_SUCCESS;
 438 }
 439
 440 static int
 441 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 442                    struct rte_eth_dev *eth_dev)
 443 {
 444         int error = 0;
 445         struct rte_pci_device *pci_dev;
 446         struct e1000_hw *hw =
 447                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 448         struct e1000_vfta * shadow_vfta =
 449                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 450         uint32_t ctrl_ext;
 451
 452         pci_dev = eth_dev->pci_dev;
 453         eth_dev->dev_ops = &eth_igb_ops;
 454         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 455         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 456
 457         /* for secondary processes, we don't initialise any further as primary
 458          * has already done this work. Only check we don't need a different
 459          * RX function */
 460         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 461                 if (eth_dev->data->scattered_rx)
 462                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 463                 return 0;
 464         }
 465
 466         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 467
 468         igb_identify_hardware(eth_dev);
 469         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 470                 error = -EIO;
 471                 goto err_late;
 472         }
 473
 474         e1000_get_bus_info(hw);
 475
 476         /* Reset any pending lock */
 477         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 478                 error = -EIO;
 479                 goto err_late;
 480         }
 481
 482         /* Finish initialization */
 483         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 484                 error = -EIO;
 485                 goto err_late;
 486         }
 487
 488         hw->mac.autoneg = 1;
 489         hw->phy.autoneg_wait_to_complete = 0;
 490         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 491
 492         /* Copper options */
 493         if (hw->phy.media_type == e1000_media_type_copper) {
 494                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 495                 hw->phy.disable_polarity_correction = 0;
 496                 hw->phy.ms_type = e1000_ms_hw_default;
 497         }
 498
 499         /*
 500          * Start from a known state, this is important in reading the nvm
 501          * and mac from that.
 502          */
 503         igb_pf_reset_hw(hw);
 504
 505         /* Make sure we have a good EEPROM before we read from it */
 506         if (e1000_validate_nvm_checksum(hw) < 0) {
 507                 /*
 508                  * Some PCI-E parts fail the first check due to
 509                  * the link being in sleep state, call it again,
 510                  * if it fails a second time its a real issue.
 511                  */
 512                 if (e1000_validate_nvm_checksum(hw) < 0) {
 513                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 514                         error = -EIO;
 515                         goto err_late;
 516                 }
 517         }
 518
 519         /* Read the permanent MAC address out of the EEPROM */
 520         if (e1000_read_mac_addr(hw) != 0) {
 521                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 522                 error = -EIO;
 523                 goto err_late;
 524         }
 525
 526         /* Allocate memory for storing MAC addresses */
 527         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 528                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 529         if (eth_dev->data->mac_addrs == NULL) {
 530                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 531                                                 "store MAC addresses",
 532                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 533                 error = -ENOMEM;
 534                 goto err_late;
 535         }
 536
 537         /* Copy the permanent MAC address */
 538         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 539
 540         /* initialize the vfta */
 541         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 542
 543         /* Now initialize the hardware */
 544         if (igb_hardware_init(hw) != 0) {
 545                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 546                 rte_free(eth_dev->data->mac_addrs);
 547                 eth_dev->data->mac_addrs = NULL;
 548                 error = -ENODEV;
 549                 goto err_late;
 550         }
 551         hw->mac.get_link_status = 1;
 552
 553         /* Indicate SOL/IDER usage */
 554         if (e1000_check_reset_block(hw) < 0) {
 555                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 556                                         "SOL/IDER session");
 557         }
 558
 559         /* initialize PF if max_vfs not zero */
 560         igb_pf_host_init(eth_dev);
 561
 562         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 563         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 564         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 565         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 566         E1000_WRITE_FLUSH(hw);
 567
 568         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
 569                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 570                      pci_dev->id.device_id);
 571
 572         rte_intr_callback_register(&(pci_dev->intr_handle),
 573                 eth_igb_interrupt_handler, (void *)eth_dev);
 574
 575         /* enable uio intr after callback register */
 576         rte_intr_enable(&(pci_dev->intr_handle));
 577
 578         /* enable support intr */
 579         igb_intr_enable(eth_dev);
 580
 581         return 0;
 582
 583 err_late:
 584         igb_hw_control_release(hw);
 585
 586         return (error);
 587 }
 588
 589 /*
 590  * Virtual Function device init
 591  */
 592 static int
 593 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 594                 struct rte_eth_dev *eth_dev)
 595 {
 596         struct rte_pci_device *pci_dev;
 597         struct e1000_hw *hw =
 598                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 599         int diag;
 600
 601         PMD_INIT_FUNC_TRACE();
 602
 603         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 604         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 605         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 606
 607         /* for secondary processes, we don't initialise any further as primary
 608          * has already done this work. Only check we don't need a different
 609          * RX function */
 610         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 611                 if (eth_dev->data->scattered_rx)
 612                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 613                 return 0;
 614         }
 615
 616         pci_dev = eth_dev->pci_dev;
 617
 618         hw->device_id = pci_dev->id.device_id;
 619         hw->vendor_id = pci_dev->id.vendor_id;
 620         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 621
 622         /* Initialize the shared code (base driver) */
 623         diag = e1000_setup_init_funcs(hw, TRUE);
 624         if (diag != 0) {
 625                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 626                         diag);
 627                 return -EIO;
 628         }
 629
 630         /* init_mailbox_params */
 631         hw->mbx.ops.init_params(hw);
 632
 633         /* Disable the interrupts for VF */
 634         igbvf_intr_disable(hw);
 635
 636         diag = hw->mac.ops.reset_hw(hw);
 637
 638         /* Allocate memory for storing MAC addresses */
 639         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 640                 hw->mac.rar_entry_count, 0);
 641         if (eth_dev->data->mac_addrs == NULL) {
 642                 PMD_INIT_LOG(ERR,
 643                         "Failed to allocate %d bytes needed to store MAC "
 644                         "addresses",
 645                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 646                 return -ENOMEM;
 647         }
 648
 649         /* Copy the permanent MAC address */
 650         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 651                         &eth_dev->data->mac_addrs[0]);
 652
 653         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 654                      "mac.type=%s",
 655                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 656                      pci_dev->id.device_id, "igb_mac_82576_vf");
 657
 658         return 0;
 659 }
 660
 661 static struct eth_driver rte_igb_pmd = {
 662         {
 663                 .name = "rte_igb_pmd",
 664                 .id_table = pci_id_igb_map,
 665                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 666         },
 667         .eth_dev_init = eth_igb_dev_init,
 668         .dev_private_size = sizeof(struct e1000_adapter),
 669 };
 670
 671 /*
 672  * virtual function driver struct
 673  */
 674 static struct eth_driver rte_igbvf_pmd = {
 675         {
 676                 .name = "rte_igbvf_pmd",
 677                 .id_table = pci_id_igbvf_map,
 678                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 679         },
 680         .eth_dev_init = eth_igbvf_dev_init,
 681         .dev_private_size = sizeof(struct e1000_adapter),
 682 };
 683
 684 static int
 685 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 686 {
 687         rte_eth_driver_register(&rte_igb_pmd);
 688         return 0;
 689 }
 690
 691 static void
 692 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 693 {
 694         struct e1000_hw *hw =
 695                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 696         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 697         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 698         rctl |= E1000_RCTL_VFE;
 699         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 700 }
 701
 702 /*
 703  * VF Driver initialization routine.
 704  * Invoked one at EAL init time.
 705  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 706  */
 707 static int
 708 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 709 {
 710         PMD_INIT_FUNC_TRACE();
 711
 712         rte_eth_driver_register(&rte_igbvf_pmd);
 713         return (0);
 714 }
 715
 716 static int
 717 eth_igb_configure(struct rte_eth_dev *dev)
 718 {
 719         struct e1000_interrupt *intr =
 720                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 721
 722         PMD_INIT_FUNC_TRACE();
 723         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 724         PMD_INIT_FUNC_TRACE();
 725
 726         return (0);
 727 }
 728
 729 static int
 730 eth_igb_start(struct rte_eth_dev *dev)
 731 {
 732         struct e1000_hw *hw =
 733                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 734         int ret, i, mask;
 735         uint32_t ctrl_ext;
 736
 737         PMD_INIT_FUNC_TRACE();
 738
 739         /* Power up the phy. Needed to make the link go Up */
 740         e1000_power_up_phy(hw);
 741
 742         /*
 743          * Packet Buffer Allocation (PBA)
 744          * Writing PBA sets the receive portion of the buffer
 745          * the remainder is used for the transmit buffer.
 746          */
 747         if (hw->mac.type == e1000_82575) {
 748                 uint32_t pba;
 749
 750                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 751                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 752         }
 753
 754         /* Put the address into the Receive Address Array */
 755         e1000_rar_set(hw, hw->mac.addr, 0);
 756
 757         /* Initialize the hardware */
 758         if (igb_hardware_init(hw)) {
 759                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 760                 return (-EIO);
 761         }
 762
 763         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 764
 765         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 766         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 767         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 768         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 769         E1000_WRITE_FLUSH(hw);
 770
 771         /* configure PF module if SRIOV enabled */
 772         igb_pf_host_configure(dev);
 773
 774         /* Configure for OS presence */
 775         igb_init_manageability(hw);
 776
 777         eth_igb_tx_init(dev);
 778
 779         /* This can fail when allocating mbufs for descriptor rings */
 780         ret = eth_igb_rx_init(dev);
 781         if (ret) {
 782                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 783                 igb_dev_clear_queues(dev);
 784                 return ret;
 785         }
 786
 787         e1000_clear_hw_cntrs_base_generic(hw);
 788
 789         /*
 790          * VLAN Offload Settings
 791          */
 792         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 793                         ETH_VLAN_EXTEND_MASK;
 794         eth_igb_vlan_offload_set(dev, mask);
 795
 796         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 797                 /* Enable VLAN filter since VMDq always use VLAN filter */
 798                 igb_vmdq_vlan_hw_filter_enable(dev);
 799         }
 800
 801         /*
 802          * Configure the Interrupt Moderation register (EITR) with the maximum
 803          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 804          * spurious [DMA] memory updates of RX and TX ring descriptors.
 805          *
 806          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 807          * spurious memory updates per second should be expected.
 808          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 809          *
 810          * Because interrupts are not used at all, the MSI-X is not activated
 811          * and interrupt moderation is controlled by EITR[0].
 812          *
 813          * Note that having [almost] disabled memory updates of RX and TX ring
 814          * descriptors through the Interrupt Moderation mechanism, memory
 815          * updates of ring descriptors are now moderated by the configurable
 816          * value of Write-Back Threshold registers.
 817          */
 818         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 819                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
 820                 (hw->mac.type == e1000_i211)) {
 821                 uint32_t ivar;
 822
 823                 /* Enable all RX & TX queues in the IVAR registers */
 824                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 825                 for (i = 0; i < 8; i++)
 826                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 827
 828                 /* Configure EITR with the maximum possible value (0xFFFF) */
 829                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 830         }
 831
 832         /* Setup link speed and duplex */
 833         switch (dev->data->dev_conf.link_speed) {
 834         case ETH_LINK_SPEED_AUTONEG:
 835                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 836                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 837                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 838                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 839                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 840                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 841                 else
 842                         goto error_invalid_config;
 843                 break;
 844         case ETH_LINK_SPEED_10:
 845                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 846                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 847                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 848                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 849                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 850                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 851                 else
 852                         goto error_invalid_config;
 853                 break;
 854         case ETH_LINK_SPEED_100:
 855                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 856                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 857                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 858                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 859                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 860                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 861                 else
 862                         goto error_invalid_config;
 863                 break;
 864         case ETH_LINK_SPEED_1000:
 865                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 866                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 867                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 868                 else
 869                         goto error_invalid_config;
 870                 break;
 871         case ETH_LINK_SPEED_10000:
 872         default:
 873                 goto error_invalid_config;
 874         }
 875         e1000_setup_link(hw);
 876
 877         /* check if lsc interrupt feature is enabled */
 878         if (dev->data->dev_conf.intr_conf.lsc != 0)
 879                 ret = eth_igb_lsc_interrupt_setup(dev);
 880
 881         /* resume enabled intr since hw reset */
 882         igb_intr_enable(dev);
 883
 884         PMD_INIT_LOG(DEBUG, "<<");
 885
 886         return (0);
 887
 888 error_invalid_config:
 889         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 890                      dev->data->dev_conf.link_speed,
 891                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 892         igb_dev_clear_queues(dev);
 893         return (-EINVAL);
 894 }
 895
 896 /*********************************************************************
 897  *
 898  *  This routine disables all traffic on the adapter by issuing a
 899  *  global reset on the MAC.
 900  *
 901  **********************************************************************/
 902 static void
 903 eth_igb_stop(struct rte_eth_dev *dev)
 904 {
 905         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 906         struct rte_eth_link link;
 907
 908         igb_intr_disable(hw);
 909         igb_pf_reset_hw(hw);
 910         E1000_WRITE_REG(hw, E1000_WUC, 0);
 911
 912         /* Set bit for Go Link disconnect */
 913         if (hw->mac.type >= e1000_82580) {
 914                 uint32_t phpm_reg;
 915
 916                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 917                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 918                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 919         }
 920
 921         /* Power down the phy. Needed to make the link go Down */
 922         e1000_power_down_phy(hw);
 923
 924         igb_dev_clear_queues(dev);
 925
 926         /* clear the recorded link status */
 927         memset(&link, 0, sizeof(link));
 928         rte_igb_dev_atomic_write_link_status(dev, &link);
 929 }
 930
 931 static void
 932 eth_igb_close(struct rte_eth_dev *dev)
 933 {
 934         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 935         struct rte_eth_link link;
 936
 937         eth_igb_stop(dev);
 938         e1000_phy_hw_reset(hw);
 939         igb_release_manageability(hw);
 940         igb_hw_control_release(hw);
 941
 942         /* Clear bit for Go Link disconnect */
 943         if (hw->mac.type >= e1000_82580) {
 944                 uint32_t phpm_reg;
 945
 946                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 947                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
 948                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 949         }
 950
 951         igb_dev_clear_queues(dev);
 952
 953         memset(&link, 0, sizeof(link));
 954         rte_igb_dev_atomic_write_link_status(dev, &link);
 955 }
 956
 957 static int
 958 igb_get_rx_buffer_size(struct e1000_hw *hw)
 959 {
 960         uint32_t rx_buf_size;
 961         if (hw->mac.type == e1000_82576) {
 962                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 963         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 964                 /* PBS needs to be translated according to a lookup table */
 965                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 966                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 967                 rx_buf_size = (rx_buf_size << 10);
 968         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
 969                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 970         } else {
 971                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 972         }
 973
 974         return rx_buf_size;
 975 }
 976
 977 /*********************************************************************
 978  *
 979  *  Initialize the hardware
 980  *
 981  **********************************************************************/
 982 static int
 983 igb_hardware_init(struct e1000_hw *hw)
 984 {
 985         uint32_t rx_buf_size;
 986         int diag;
 987
 988         /* Let the firmware know the OS is in control */
 989         igb_hw_control_acquire(hw);
 990
 991         /*
 992          * These parameters control the automatic generation (Tx) and
 993          * response (Rx) to Ethernet PAUSE frames.
 994          * - High water mark should allow for at least two standard size (1518)
 995          *   frames to be received after sending an XOFF.
 996          * - Low water mark works best when it is very near the high water mark.
 997          *   This allows the receiver to restart by sending XON when it has
 998          *   drained a bit. Here we use an arbitrary value of 1500 which will
 999          *   restart after one full frame is pulled from the buffer. There
1000          *   could be several smaller frames in the buffer and if so they will
1001          *   not trigger the XON until their total number reduces the buffer
1002          *   by 1500.
1003          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1004          */
1005         rx_buf_size = igb_get_rx_buffer_size(hw);
1006
1007         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1008         hw->fc.low_water = hw->fc.high_water - 1500;
1009         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1010         hw->fc.send_xon = 1;
1011
1012         /* Set Flow control, use the tunable location if sane */
1013         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1014                 hw->fc.requested_mode = igb_fc_setting;
1015         else
1016                 hw->fc.requested_mode = e1000_fc_none;
1017
1018         /* Issue a global reset */
1019         igb_pf_reset_hw(hw);
1020         E1000_WRITE_REG(hw, E1000_WUC, 0);
1021
1022         diag = e1000_init_hw(hw);
1023         if (diag < 0)
1024                 return (diag);
1025
1026         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1027         e1000_get_phy_info(hw);
1028         e1000_check_for_link(hw);
1029
1030         return (0);
1031 }
1032
1033 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1034 static void
1035 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1036 {
1037         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1038         struct e1000_hw_stats *stats =
1039                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1040         int pause_frames;
1041
1042         if(hw->phy.media_type == e1000_media_type_copper ||
1043             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1044                 stats->symerrs +=
1045                     E1000_READ_REG(hw,E1000_SYMERRS);
1046                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1047         }
1048
1049         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1050         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1051         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1052         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1053
1054         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1055         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1056         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1057         stats->dc += E1000_READ_REG(hw, E1000_DC);
1058         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1059         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1060         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1061         /*
1062         ** For watchdog management we need to know if we have been
1063         ** paused during the last interval, so capture that here.
1064         */
1065         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1066         stats->xoffrxc += pause_frames;
1067         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1068         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1069         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1070         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1071         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1072         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1073         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1074         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1075         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1076         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1077         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1078         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1079
1080         /* For the 64-bit byte counters the low dword must be read first. */
1081         /* Both registers clear on the read of the high dword */
1082
1083         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1084         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1085         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1086         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1087
1088         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1089         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1090         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1091         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1092         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1093
1094         stats->tor += E1000_READ_REG(hw, E1000_TORH);
1095         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1096
1097         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1098         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1099         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1100         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1101         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1102         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1103         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1104         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1105         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1106         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1107
1108         /* Interrupt Counts */
1109
1110         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1111         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1112         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1113         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1114         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1115         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1116         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1117         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1118         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1119
1120         /* Host to Card Statistics */
1121
1122         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1123         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1124         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1125         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1126         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1127         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1128         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1129         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1130         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1131         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1132         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1133         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1134         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1135         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1136
1137         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1138         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1139         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1140         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1141         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1142         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1143
1144         if (rte_stats == NULL)
1145                 return;
1146
1147         /* Rx Errors */
1148         rte_stats->ibadcrc = stats->crcerrs;
1149         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1150         rte_stats->imissed = stats->mpc;
1151         rte_stats->ierrors = rte_stats->ibadcrc +
1152                              rte_stats->ibadlen +
1153                              rte_stats->imissed +
1154                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1155
1156         /* Tx Errors */
1157         rte_stats->oerrors = stats->ecol + stats->latecol;
1158
1159         /* XON/XOFF pause frames */
1160         rte_stats->tx_pause_xon  = stats->xontxc;
1161         rte_stats->rx_pause_xon  = stats->xonrxc;
1162         rte_stats->tx_pause_xoff = stats->xofftxc;
1163         rte_stats->rx_pause_xoff = stats->xoffrxc;
1164
1165         rte_stats->ipackets = stats->gprc;
1166         rte_stats->opackets = stats->gptc;
1167         rte_stats->ibytes   = stats->gorc;
1168         rte_stats->obytes   = stats->gotc;
1169 }
1170
1171 static void
1172 eth_igb_stats_reset(struct rte_eth_dev *dev)
1173 {
1174         struct e1000_hw_stats *hw_stats =
1175                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1176
1177         /* HW registers are cleared on read */
1178         eth_igb_stats_get(dev, NULL);
1179
1180         /* Reset software totals */
1181         memset(hw_stats, 0, sizeof(*hw_stats));
1182 }
1183
1184 static void
1185 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1186 {
1187         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1188         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1189                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1190
1191         /* Good Rx packets, include VF loopback */
1192         UPDATE_VF_STAT(E1000_VFGPRC,
1193             hw_stats->last_gprc, hw_stats->gprc);
1194
1195         /* Good Rx octets, include VF loopback */
1196         UPDATE_VF_STAT(E1000_VFGORC,
1197             hw_stats->last_gorc, hw_stats->gorc);
1198
1199         /* Good Tx packets, include VF loopback */
1200         UPDATE_VF_STAT(E1000_VFGPTC,
1201             hw_stats->last_gptc, hw_stats->gptc);
1202
1203         /* Good Tx octets, include VF loopback */
1204         UPDATE_VF_STAT(E1000_VFGOTC,
1205             hw_stats->last_gotc, hw_stats->gotc);
1206
1207         /* Rx Multicst packets */
1208         UPDATE_VF_STAT(E1000_VFMPRC,
1209             hw_stats->last_mprc, hw_stats->mprc);
1210
1211         /* Good Rx loopback packets */
1212         UPDATE_VF_STAT(E1000_VFGPRLBC,
1213             hw_stats->last_gprlbc, hw_stats->gprlbc);
1214
1215         /* Good Rx loopback octets */
1216         UPDATE_VF_STAT(E1000_VFGORLBC,
1217             hw_stats->last_gorlbc, hw_stats->gorlbc);
1218
1219         /* Good Tx loopback packets */
1220         UPDATE_VF_STAT(E1000_VFGPTLBC,
1221             hw_stats->last_gptlbc, hw_stats->gptlbc);
1222
1223         /* Good Tx loopback octets */
1224         UPDATE_VF_STAT(E1000_VFGOTLBC,
1225             hw_stats->last_gotlbc, hw_stats->gotlbc);
1226
1227         if (rte_stats == NULL)
1228                 return;
1229
1230         memset(rte_stats, 0, sizeof(*rte_stats));
1231         rte_stats->ipackets = hw_stats->gprc;
1232         rte_stats->ibytes = hw_stats->gorc;
1233         rte_stats->opackets = hw_stats->gptc;
1234         rte_stats->obytes = hw_stats->gotc;
1235         rte_stats->imcasts = hw_stats->mprc;
1236         rte_stats->ilbpackets = hw_stats->gprlbc;
1237         rte_stats->ilbbytes = hw_stats->gorlbc;
1238         rte_stats->olbpackets = hw_stats->gptlbc;
1239         rte_stats->olbbytes = hw_stats->gotlbc;
1240
1241 }
1242
1243 static void
1244 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1245 {
1246         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1247                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1248
1249         /* Sync HW register to the last stats */
1250         eth_igbvf_stats_get(dev, NULL);
1251
1252         /* reset HW current stats*/
1253         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1254                offsetof(struct e1000_vf_stats, gprc));
1255
1256 }
1257
1258 static void
1259 eth_igb_infos_get(struct rte_eth_dev *dev,
1260                     struct rte_eth_dev_info *dev_info)
1261 {
1262         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1263
1264         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1265         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1266         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1267         dev_info->rx_offload_capa =
1268                 DEV_RX_OFFLOAD_VLAN_STRIP |
1269                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1270                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1271                 DEV_RX_OFFLOAD_TCP_CKSUM;
1272         dev_info->tx_offload_capa =
1273                 DEV_TX_OFFLOAD_VLAN_INSERT |
1274                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1275                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1276                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1277                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1278
1279         switch (hw->mac.type) {
1280         case e1000_82575:
1281                 dev_info->max_rx_queues = 4;
1282                 dev_info->max_tx_queues = 4;
1283                 dev_info->max_vmdq_pools = 0;
1284                 break;
1285
1286         case e1000_82576:
1287                 dev_info->max_rx_queues = 16;
1288                 dev_info->max_tx_queues = 16;
1289                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1290                 break;
1291
1292         case e1000_82580:
1293                 dev_info->max_rx_queues = 8;
1294                 dev_info->max_tx_queues = 8;
1295                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1296                 break;
1297
1298         case e1000_i350:
1299                 dev_info->max_rx_queues = 8;
1300                 dev_info->max_tx_queues = 8;
1301                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1302                 break;
1303
1304         case e1000_i354:
1305                 dev_info->max_rx_queues = 8;
1306                 dev_info->max_tx_queues = 8;
1307                 break;
1308
1309         case e1000_i210:
1310                 dev_info->max_rx_queues = 4;
1311                 dev_info->max_tx_queues = 4;
1312                 dev_info->max_vmdq_pools = 0;
1313                 break;
1314
1315         case e1000_i211:
1316                 dev_info->max_rx_queues = 2;
1317                 dev_info->max_tx_queues = 2;
1318                 dev_info->max_vmdq_pools = 0;
1319                 break;
1320
1321         case e1000_vfadapt:
1322                 dev_info->max_rx_queues = 2;
1323                 dev_info->max_tx_queues = 2;
1324                 dev_info->max_vmdq_pools = 0;
1325                 break;
1326
1327         case e1000_vfadapt_i350:
1328                 dev_info->max_rx_queues = 1;
1329                 dev_info->max_tx_queues = 1;
1330                 dev_info->max_vmdq_pools = 0;
1331                 break;
1332
1333         default:
1334                 /* Should not happen */
1335                 dev_info->max_rx_queues = 0;
1336                 dev_info->max_tx_queues = 0;
1337                 dev_info->max_vmdq_pools = 0;
1338         }
1339 }
1340
1341 /* return 0 means link status changed, -1 means not changed */
1342 static int
1343 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1344 {
1345         struct e1000_hw *hw =
1346                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1347         struct rte_eth_link link, old;
1348         int link_check, count;
1349
1350         link_check = 0;
1351         hw->mac.get_link_status = 1;
1352
1353         /* possible wait-to-complete in up to 9 seconds */
1354         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1355                 /* Read the real link status */
1356                 switch (hw->phy.media_type) {
1357                 case e1000_media_type_copper:
1358                         /* Do the work to read phy */
1359                         e1000_check_for_link(hw);
1360                         link_check = !hw->mac.get_link_status;
1361                         break;
1362
1363                 case e1000_media_type_fiber:
1364                         e1000_check_for_link(hw);
1365                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1366                                       E1000_STATUS_LU);
1367                         break;
1368
1369                 case e1000_media_type_internal_serdes:
1370                         e1000_check_for_link(hw);
1371                         link_check = hw->mac.serdes_has_link;
1372                         break;
1373
1374                 /* VF device is type_unknown */
1375                 case e1000_media_type_unknown:
1376                         eth_igbvf_link_update(hw);
1377                         link_check = !hw->mac.get_link_status;
1378                         break;
1379
1380                 default:
1381                         break;
1382                 }
1383                 if (link_check || wait_to_complete == 0)
1384                         break;
1385                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1386         }
1387         memset(&link, 0, sizeof(link));
1388         rte_igb_dev_atomic_read_link_status(dev, &link);
1389         old = link;
1390
1391         /* Now we check if a transition has happened */
1392         if (link_check) {
1393                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1394                                           &link.link_duplex);
1395                 link.link_status = 1;
1396         } else if (!link_check) {
1397                 link.link_speed = 0;
1398                 link.link_duplex = 0;
1399                 link.link_status = 0;
1400         }
1401         rte_igb_dev_atomic_write_link_status(dev, &link);
1402
1403         /* not changed */
1404         if (old.link_status == link.link_status)
1405                 return -1;
1406
1407         /* changed */
1408         return 0;
1409 }
1410
1411 /*
1412  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1413  * For ASF and Pass Through versions of f/w this means
1414  * that the driver is loaded.
1415  */
1416 static void
1417 igb_hw_control_acquire(struct e1000_hw *hw)
1418 {
1419         uint32_t ctrl_ext;
1420
1421         /* Let firmware know the driver has taken over */
1422         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1423         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1424 }
1425
1426 /*
1427  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1428  * For ASF and Pass Through versions of f/w this means that the
1429  * driver is no longer loaded.
1430  */
1431 static void
1432 igb_hw_control_release(struct e1000_hw *hw)
1433 {
1434         uint32_t ctrl_ext;
1435
1436         /* Let firmware taken over control of h/w */
1437         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1438         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1439                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1440 }
1441
1442 /*
1443  * Bit of a misnomer, what this really means is
1444  * to enable OS management of the system... aka
1445  * to disable special hardware management features.
1446  */
1447 static void
1448 igb_init_manageability(struct e1000_hw *hw)
1449 {
1450         if (e1000_enable_mng_pass_thru(hw)) {
1451                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1452                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1453
1454                 /* disable hardware interception of ARP */
1455                 manc &= ~(E1000_MANC_ARP_EN);
1456
1457                 /* enable receiving management packets to the host */
1458                 manc |= E1000_MANC_EN_MNG2HOST;
1459                 manc2h |= 1 << 5;  /* Mng Port 623 */
1460                 manc2h |= 1 << 6;  /* Mng Port 664 */
1461                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1462                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1463         }
1464 }
1465
1466 static void
1467 igb_release_manageability(struct e1000_hw *hw)
1468 {
1469         if (e1000_enable_mng_pass_thru(hw)) {
1470                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1471
1472                 manc |= E1000_MANC_ARP_EN;
1473                 manc &= ~E1000_MANC_EN_MNG2HOST;
1474
1475                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1476         }
1477 }
1478
1479 static void
1480 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1481 {
1482         struct e1000_hw *hw =
1483                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1484         uint32_t rctl;
1485
1486         rctl = E1000_READ_REG(hw, E1000_RCTL);
1487         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1488         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1489 }
1490
1491 static void
1492 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1493 {
1494         struct e1000_hw *hw =
1495                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1496         uint32_t rctl;
1497
1498         rctl = E1000_READ_REG(hw, E1000_RCTL);
1499         rctl &= (~E1000_RCTL_UPE);
1500         if (dev->data->all_multicast == 1)
1501                 rctl |= E1000_RCTL_MPE;
1502         else
1503                 rctl &= (~E1000_RCTL_MPE);
1504         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1505 }
1506
1507 static void
1508 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1509 {
1510         struct e1000_hw *hw =
1511                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1512         uint32_t rctl;
1513
1514         rctl = E1000_READ_REG(hw, E1000_RCTL);
1515         rctl |= E1000_RCTL_MPE;
1516         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1517 }
1518
1519 static void
1520 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1521 {
1522         struct e1000_hw *hw =
1523                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524         uint32_t rctl;
1525
1526         if (dev->data->promiscuous == 1)
1527                 return; /* must remain in all_multicast mode */
1528         rctl = E1000_READ_REG(hw, E1000_RCTL);
1529         rctl &= (~E1000_RCTL_MPE);
1530         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1531 }
1532
1533 static int
1534 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1535 {
1536         struct e1000_hw *hw =
1537                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1538         struct e1000_vfta * shadow_vfta =
1539                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1540         uint32_t vfta;
1541         uint32_t vid_idx;
1542         uint32_t vid_bit;
1543
1544         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1545                               E1000_VFTA_ENTRY_MASK);
1546         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1547         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1548         if (on)
1549                 vfta |= vid_bit;
1550         else
1551                 vfta &= ~vid_bit;
1552         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1553
1554         /* update local VFTA copy */
1555         shadow_vfta->vfta[vid_idx] = vfta;
1556
1557         return 0;
1558 }
1559
1560 static void
1561 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1562 {
1563         struct e1000_hw *hw =
1564                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1565         uint32_t reg = ETHER_TYPE_VLAN ;
1566
1567         reg |= (tpid << 16);
1568         E1000_WRITE_REG(hw, E1000_VET, reg);
1569 }
1570
1571 static void
1572 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1573 {
1574         struct e1000_hw *hw =
1575                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1576         uint32_t reg;
1577
1578         /* Filter Table Disable */
1579         reg = E1000_READ_REG(hw, E1000_RCTL);
1580         reg &= ~E1000_RCTL_CFIEN;
1581         reg &= ~E1000_RCTL_VFE;
1582         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1583 }
1584
1585 static void
1586 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1587 {
1588         struct e1000_hw *hw =
1589                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1590         struct e1000_vfta * shadow_vfta =
1591                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1592         uint32_t reg;
1593         int i;
1594
1595         /* Filter Table Enable, CFI not used for packet acceptance */
1596         reg = E1000_READ_REG(hw, E1000_RCTL);
1597         reg &= ~E1000_RCTL_CFIEN;
1598         reg |= E1000_RCTL_VFE;
1599         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1600
1601         /* restore VFTA table */
1602         for (i = 0; i < IGB_VFTA_SIZE; i++)
1603                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1604 }
1605
1606 static void
1607 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1608 {
1609         struct e1000_hw *hw =
1610                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1611         uint32_t reg;
1612
1613         /* VLAN Mode Disable */
1614         reg = E1000_READ_REG(hw, E1000_CTRL);
1615         reg &= ~E1000_CTRL_VME;
1616         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1617 }
1618
1619 static void
1620 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1621 {
1622         struct e1000_hw *hw =
1623                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1624         uint32_t reg;
1625
1626         /* VLAN Mode Enable */
1627         reg = E1000_READ_REG(hw, E1000_CTRL);
1628         reg |= E1000_CTRL_VME;
1629         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1630 }
1631
1632 static void
1633 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1634 {
1635         struct e1000_hw *hw =
1636                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1637         uint32_t reg;
1638
1639         /* CTRL_EXT: Extended VLAN */
1640         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1641         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1642         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1643
1644         /* Update maximum packet length */
1645         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1646                 E1000_WRITE_REG(hw, E1000_RLPML,
1647                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1648                                                 VLAN_TAG_SIZE);
1649 }
1650
1651 static void
1652 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1653 {
1654         struct e1000_hw *hw =
1655                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656         uint32_t reg;
1657
1658         /* CTRL_EXT: Extended VLAN */
1659         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1660         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1661         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1662
1663         /* Update maximum packet length */
1664         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1665                 E1000_WRITE_REG(hw, E1000_RLPML,
1666                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1667                                                 2 * VLAN_TAG_SIZE);
1668 }
1669
1670 static void
1671 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1672 {
1673         if(mask & ETH_VLAN_STRIP_MASK){
1674                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1675                         igb_vlan_hw_strip_enable(dev);
1676                 else
1677                         igb_vlan_hw_strip_disable(dev);
1678         }
1679
1680         if(mask & ETH_VLAN_FILTER_MASK){
1681                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1682                         igb_vlan_hw_filter_enable(dev);
1683                 else
1684                         igb_vlan_hw_filter_disable(dev);
1685         }
1686
1687         if(mask & ETH_VLAN_EXTEND_MASK){
1688                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1689                         igb_vlan_hw_extend_enable(dev);
1690                 else
1691                         igb_vlan_hw_extend_disable(dev);
1692         }
1693 }
1694
1695
1696 /**
1697  * It enables the interrupt mask and then enable the interrupt.
1698  *
1699  * @param dev
1700  *  Pointer to struct rte_eth_dev.
1701  *
1702  * @return
1703  *  - On success, zero.
1704  *  - On failure, a negative value.
1705  */
1706 static int
1707 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1708 {
1709         struct e1000_interrupt *intr =
1710                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1711
1712         intr->mask |= E1000_ICR_LSC;
1713
1714         return 0;
1715 }
1716
1717 /*
1718  * It reads ICR and gets interrupt causes, check it and set a bit flag
1719  * to update link status.
1720  *
1721  * @param dev
1722  *  Pointer to struct rte_eth_dev.
1723  *
1724  * @return
1725  *  - On success, zero.
1726  *  - On failure, a negative value.
1727  */
1728 static int
1729 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1730 {
1731         uint32_t icr;
1732         struct e1000_hw *hw =
1733                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1734         struct e1000_interrupt *intr =
1735                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1736
1737         igb_intr_disable(hw);
1738
1739         /* read-on-clear nic registers here */
1740         icr = E1000_READ_REG(hw, E1000_ICR);
1741
1742         intr->flags = 0;
1743         if (icr & E1000_ICR_LSC) {
1744                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1745         }
1746
1747         if (icr & E1000_ICR_VMMB)
1748                 intr->flags |= E1000_FLAG_MAILBOX;
1749
1750         return 0;
1751 }
1752
1753 /*
1754  * It executes link_update after knowing an interrupt is prsent.
1755  *
1756  * @param dev
1757  *  Pointer to struct rte_eth_dev.
1758  *
1759  * @return
1760  *  - On success, zero.
1761  *  - On failure, a negative value.
1762  */
1763 static int
1764 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1765 {
1766         struct e1000_hw *hw =
1767                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1768         struct e1000_interrupt *intr =
1769                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1770         uint32_t tctl, rctl;
1771         struct rte_eth_link link;
1772         int ret;
1773
1774         if (intr->flags & E1000_FLAG_MAILBOX) {
1775                 igb_pf_mbx_process(dev);
1776                 intr->flags &= ~E1000_FLAG_MAILBOX;
1777         }
1778
1779         igb_intr_enable(dev);
1780         rte_intr_enable(&(dev->pci_dev->intr_handle));
1781
1782         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1783                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1784
1785                 /* set get_link_status to check register later */
1786                 hw->mac.get_link_status = 1;
1787                 ret = eth_igb_link_update(dev, 0);
1788
1789                 /* check if link has changed */
1790                 if (ret < 0)
1791                         return 0;
1792
1793                 memset(&link, 0, sizeof(link));
1794                 rte_igb_dev_atomic_read_link_status(dev, &link);
1795                 if (link.link_status) {
1796                         PMD_INIT_LOG(INFO,
1797                                      " Port %d: Link Up - speed %u Mbps - %s",
1798                                      dev->data->port_id,
1799                                      (unsigned)link.link_speed,
1800                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1801                                      "full-duplex" : "half-duplex");
1802                 } else {
1803                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
1804                                      dev->data->port_id);
1805                 }
1806                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1807                              dev->pci_dev->addr.domain,
1808                              dev->pci_dev->addr.bus,
1809                              dev->pci_dev->addr.devid,
1810                              dev->pci_dev->addr.function);
1811                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1812                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1813                 if (link.link_status) {
1814                         /* enable Tx/Rx */
1815                         tctl |= E1000_TCTL_EN;
1816                         rctl |= E1000_RCTL_EN;
1817                 } else {
1818                         /* disable Tx/Rx */
1819                         tctl &= ~E1000_TCTL_EN;
1820                         rctl &= ~E1000_RCTL_EN;
1821                 }
1822                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1823                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1824                 E1000_WRITE_FLUSH(hw);
1825                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1826         }
1827
1828         return 0;
1829 }
1830
1831 /**
1832  * Interrupt handler which shall be registered at first.
1833  *
1834  * @param handle
1835  *  Pointer to interrupt handle.
1836  * @param param
1837  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1838  *
1839  * @return
1840  *  void
1841  */
1842 static void
1843 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1844                                                         void *param)
1845 {
1846         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1847
1848         eth_igb_interrupt_get_status(dev);
1849         eth_igb_interrupt_action(dev);
1850 }
1851
1852 static int
1853 eth_igb_led_on(struct rte_eth_dev *dev)
1854 {
1855         struct e1000_hw *hw;
1856
1857         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1859 }
1860
1861 static int
1862 eth_igb_led_off(struct rte_eth_dev *dev)
1863 {
1864         struct e1000_hw *hw;
1865
1866         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1867         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1868 }
1869
1870 static int
1871 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1872 {
1873         struct e1000_hw *hw;
1874         uint32_t ctrl;
1875         int tx_pause;
1876         int rx_pause;
1877
1878         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879         fc_conf->pause_time = hw->fc.pause_time;
1880         fc_conf->high_water = hw->fc.high_water;
1881         fc_conf->low_water = hw->fc.low_water;
1882         fc_conf->send_xon = hw->fc.send_xon;
1883         fc_conf->autoneg = hw->mac.autoneg;
1884
1885         /*
1886          * Return rx_pause and tx_pause status according to actual setting of
1887          * the TFCE and RFCE bits in the CTRL register.
1888          */
1889         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1890         if (ctrl & E1000_CTRL_TFCE)
1891                 tx_pause = 1;
1892         else
1893                 tx_pause = 0;
1894
1895         if (ctrl & E1000_CTRL_RFCE)
1896                 rx_pause = 1;
1897         else
1898                 rx_pause = 0;
1899
1900         if (rx_pause && tx_pause)
1901                 fc_conf->mode = RTE_FC_FULL;
1902         else if (rx_pause)
1903                 fc_conf->mode = RTE_FC_RX_PAUSE;
1904         else if (tx_pause)
1905                 fc_conf->mode = RTE_FC_TX_PAUSE;
1906         else
1907                 fc_conf->mode = RTE_FC_NONE;
1908
1909         return 0;
1910 }
1911
1912 static int
1913 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1914 {
1915         struct e1000_hw *hw;
1916         int err;
1917         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1918                 e1000_fc_none,
1919                 e1000_fc_rx_pause,
1920                 e1000_fc_tx_pause,
1921                 e1000_fc_full
1922         };
1923         uint32_t rx_buf_size;
1924         uint32_t max_high_water;
1925         uint32_t rctl;
1926
1927         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928         if (fc_conf->autoneg != hw->mac.autoneg)
1929                 return -ENOTSUP;
1930         rx_buf_size = igb_get_rx_buffer_size(hw);
1931         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1932
1933         /* At least reserve one Ethernet frame for watermark */
1934         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1935         if ((fc_conf->high_water > max_high_water) ||
1936             (fc_conf->high_water < fc_conf->low_water)) {
1937                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1938                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
1939                 return (-EINVAL);
1940         }
1941
1942         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1943         hw->fc.pause_time     = fc_conf->pause_time;
1944         hw->fc.high_water     = fc_conf->high_water;
1945         hw->fc.low_water      = fc_conf->low_water;
1946         hw->fc.send_xon       = fc_conf->send_xon;
1947
1948         err = e1000_setup_link_generic(hw);
1949         if (err == E1000_SUCCESS) {
1950
1951                 /* check if we want to forward MAC frames - driver doesn't have native
1952                  * capability to do that, so we'll write the registers ourselves */
1953
1954                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1955
1956                 /* set or clear MFLCN.PMCF bit depending on configuration */
1957                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1958                         rctl |= E1000_RCTL_PMCF;
1959                 else
1960                         rctl &= ~E1000_RCTL_PMCF;
1961
1962                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1963                 E1000_WRITE_FLUSH(hw);
1964
1965                 return 0;
1966         }
1967
1968         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1969         return (-EIO);
1970 }
1971
1972 #define E1000_RAH_POOLSEL_SHIFT      (18)
1973 static void
1974 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1975                 uint32_t index, __rte_unused uint32_t pool)
1976 {
1977         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1978         uint32_t rah;
1979
1980         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1981         rah = E1000_READ_REG(hw, E1000_RAH(index));
1982         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
1983         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
1984 }
1985
1986 static void
1987 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1988 {
1989         uint8_t addr[ETHER_ADDR_LEN];
1990         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991
1992         memset(addr, 0, sizeof(addr));
1993
1994         e1000_rar_set(hw, addr, index);
1995 }
1996
1997 /*
1998  * Virtual Function operations
1999  */
2000 static void
2001 igbvf_intr_disable(struct e1000_hw *hw)
2002 {
2003         PMD_INIT_FUNC_TRACE();
2004
2005         /* Clear interrupt mask to stop from interrupts being generated */
2006         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2007
2008         E1000_WRITE_FLUSH(hw);
2009 }
2010
2011 static void
2012 igbvf_stop_adapter(struct rte_eth_dev *dev)
2013 {
2014         u32 reg_val;
2015         u16 i;
2016         struct rte_eth_dev_info dev_info;
2017         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2018
2019         memset(&dev_info, 0, sizeof(dev_info));
2020         eth_igb_infos_get(dev, &dev_info);
2021
2022         /* Clear interrupt mask to stop from interrupts being generated */
2023         igbvf_intr_disable(hw);
2024
2025         /* Clear any pending interrupts, flush previous writes */
2026         E1000_READ_REG(hw, E1000_EICR);
2027
2028         /* Disable the transmit unit.  Each queue must be disabled. */
2029         for (i = 0; i < dev_info.max_tx_queues; i++)
2030                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2031
2032         /* Disable the receive unit by stopping each queue */
2033         for (i = 0; i < dev_info.max_rx_queues; i++) {
2034                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2035                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2036                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2037                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2038                         ;
2039         }
2040
2041         /* flush all queues disables */
2042         E1000_WRITE_FLUSH(hw);
2043         msec_delay(2);
2044 }
2045
2046 static int eth_igbvf_link_update(struct e1000_hw *hw)
2047 {
2048         struct e1000_mbx_info *mbx = &hw->mbx;
2049         struct e1000_mac_info *mac = &hw->mac;
2050         int ret_val = E1000_SUCCESS;
2051
2052         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2053
2054         /*
2055          * We only want to run this if there has been a rst asserted.
2056          * in this case that could mean a link change, device reset,
2057          * or a virtual function reset
2058          */
2059
2060         /* If we were hit with a reset or timeout drop the link */
2061         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2062                 mac->get_link_status = TRUE;
2063
2064         if (!mac->get_link_status)
2065                 goto out;
2066
2067         /* if link status is down no point in checking to see if pf is up */
2068         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2069                 goto out;
2070
2071         /* if we passed all the tests above then the link is up and we no
2072          * longer need to check for link */
2073         mac->get_link_status = FALSE;
2074
2075 out:
2076         return ret_val;
2077 }
2078
2079
2080 static int
2081 igbvf_dev_configure(struct rte_eth_dev *dev)
2082 {
2083         struct rte_eth_conf* conf = &dev->data->dev_conf;
2084
2085         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2086                      dev->data->port_id);
2087
2088         /*
2089          * VF has no ability to enable/disable HW CRC
2090          * Keep the persistent behavior the same as Host PF
2091          */
2092 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2093         if (!conf->rxmode.hw_strip_crc) {
2094                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2095                 conf->rxmode.hw_strip_crc = 1;
2096         }
2097 #else
2098         if (conf->rxmode.hw_strip_crc) {
2099                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2100                 conf->rxmode.hw_strip_crc = 0;
2101         }
2102 #endif
2103
2104         return 0;
2105 }
2106
2107 static int
2108 igbvf_dev_start(struct rte_eth_dev *dev)
2109 {
2110         struct e1000_hw *hw =
2111                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2112         int ret;
2113
2114         PMD_INIT_FUNC_TRACE();
2115
2116         hw->mac.ops.reset_hw(hw);
2117
2118         /* Set all vfta */
2119         igbvf_set_vfta_all(dev,1);
2120
2121         eth_igbvf_tx_init(dev);
2122
2123         /* This can fail when allocating mbufs for descriptor rings */
2124         ret = eth_igbvf_rx_init(dev);
2125         if (ret) {
2126                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2127                 igb_dev_clear_queues(dev);
2128                 return ret;
2129         }
2130
2131         return 0;
2132 }
2133
2134 static void
2135 igbvf_dev_stop(struct rte_eth_dev *dev)
2136 {
2137         PMD_INIT_FUNC_TRACE();
2138
2139         igbvf_stop_adapter(dev);
2140
2141         /*
2142           * Clear what we set, but we still keep shadow_vfta to
2143           * restore after device starts
2144           */
2145         igbvf_set_vfta_all(dev,0);
2146
2147         igb_dev_clear_queues(dev);
2148 }
2149
2150 static void
2151 igbvf_dev_close(struct rte_eth_dev *dev)
2152 {
2153         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2154
2155         PMD_INIT_FUNC_TRACE();
2156
2157         e1000_reset_hw(hw);
2158
2159         igbvf_dev_stop(dev);
2160 }
2161
2162 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2163 {
2164         struct e1000_mbx_info *mbx = &hw->mbx;
2165         uint32_t msgbuf[2];
2166
2167         /* After set vlan, vlan strip will also be enabled in igb driver*/
2168         msgbuf[0] = E1000_VF_SET_VLAN;
2169         msgbuf[1] = vid;
2170         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2171         if (on)
2172                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2173
2174         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2175 }
2176
2177 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2178 {
2179         struct e1000_hw *hw =
2180                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2181         struct e1000_vfta * shadow_vfta =
2182                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2183         int i = 0, j = 0, vfta = 0, mask = 1;
2184
2185         for (i = 0; i < IGB_VFTA_SIZE; i++){
2186                 vfta = shadow_vfta->vfta[i];
2187                 if(vfta){
2188                         mask = 1;
2189                         for (j = 0; j < 32; j++){
2190                                 if(vfta & mask)
2191                                         igbvf_set_vfta(hw,
2192                                                 (uint16_t)((i<<5)+j), on);
2193                                 mask<<=1;
2194                         }
2195                 }
2196         }
2197
2198 }
2199
2200 static int
2201 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2202 {
2203         struct e1000_hw *hw =
2204                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2205         struct e1000_vfta * shadow_vfta =
2206                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2207         uint32_t vid_idx = 0;
2208         uint32_t vid_bit = 0;
2209         int ret = 0;
2210
2211         PMD_INIT_FUNC_TRACE();
2212
2213         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2214         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2215         if(ret){
2216                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2217                 return ret;
2218         }
2219         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2220         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2221
2222         /*Save what we set and retore it after device reset*/
2223         if (on)
2224                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2225         else
2226                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2227
2228         return 0;
2229 }
2230
2231 static int
2232 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2233                                 struct rte_eth_rss_reta *reta_conf)
2234 {
2235         uint8_t i,j,mask;
2236         uint32_t reta;
2237         struct e1000_hw *hw =
2238                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239
2240         /*
2241          * Update Redirection Table RETA[n],n=0...31,The redirection table has
2242          * 128-entries in 32 registers
2243          */
2244         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2245                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2246                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2247                 else
2248                         mask = (uint8_t)((reta_conf->mask_hi >>
2249                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2250                 if (mask != 0) {
2251                         reta = 0;
2252                         /* If all 4 entries were set,don't need read RETA register */
2253                         if (mask != 0xF)
2254                                 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2255
2256                         for (j = 0; j < 4; j++) {
2257                                 if (mask & (0x1 << j)) {
2258                                         if (mask != 0xF)
2259                                                 reta &= ~(0xFF << 8 * j);
2260                                         reta |= reta_conf->reta[i + j] << 8 * j;
2261                                 }
2262                         }
2263                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2264                 }
2265         }
2266
2267         return 0;
2268 }
2269
2270 static int
2271 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2272                                 struct rte_eth_rss_reta *reta_conf)
2273 {
2274         uint8_t i,j,mask;
2275         uint32_t reta;
2276         struct e1000_hw *hw =
2277                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2278
2279         /*
2280          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2281          * 128-entries in 32 registers
2282          */
2283         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2284                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2285                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2286                 else
2287                         mask = (uint8_t)((reta_conf->mask_hi >>
2288                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2289
2290                 if (mask != 0) {
2291                         reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2292                         for (j = 0; j < 4; j++) {
2293                                 if (mask & (0x1 << j))
2294                                         reta_conf->reta[i + j] =
2295                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2296                         }
2297                 }
2298         }
2299
2300         return 0;
2301 }
2302
2303 #define MAC_TYPE_FILTER_SUP(type)    do {\
2304         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2305                 (type) != e1000_82576)\
2306                 return -ENOSYS;\
2307 } while (0)
2308
2309 /*
2310  * add the syn filter
2311  *
2312  * @param
2313  * dev: Pointer to struct rte_eth_dev.
2314  * filter: ponter to the filter that will be added.
2315  * rx_queue: the queue id the filter assigned to.
2316  *
2317  * @return
2318  *    - On success, zero.
2319  *    - On failure, a negative value.
2320  */
2321 static int
2322 eth_igb_add_syn_filter(struct rte_eth_dev *dev,
2323                         struct rte_syn_filter *filter, uint16_t rx_queue)
2324 {
2325         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2326         uint32_t synqf, rfctl;
2327
2328         MAC_TYPE_FILTER_SUP(hw->mac.type);
2329
2330         if (rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2331                 return -EINVAL;
2332
2333         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2334         if (synqf & E1000_SYN_FILTER_ENABLE)
2335                 return -EINVAL;
2336
2337         synqf = (uint32_t)(((rx_queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2338                 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2339
2340         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2341         if (filter->hig_pri)
2342                 rfctl |= E1000_RFCTL_SYNQFP;
2343         else
2344                 rfctl &= ~E1000_RFCTL_SYNQFP;
2345
2346         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2347         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2348         return 0;
2349 }
2350
2351 /*
2352  * remove the syn filter
2353  *
2354  * @param
2355  * dev: Pointer to struct rte_eth_dev.
2356  *
2357  * @return
2358  *    - On success, zero.
2359  *    - On failure, a negative value.
2360  */
2361 static int
2362 eth_igb_remove_syn_filter(struct rte_eth_dev *dev)
2363 {
2364         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2365
2366         MAC_TYPE_FILTER_SUP(hw->mac.type);
2367
2368         E1000_WRITE_REG(hw, E1000_SYNQF(0), 0);
2369         return 0;
2370 }
2371
2372 /*
2373  * get the syn filter's info
2374  *
2375  * @param
2376  * dev: Pointer to struct rte_eth_dev.
2377  * filter: ponter to the filter that returns.
2378  * *rx_queue: pointer to the queue id the filter assigned to.
2379  *
2380  * @return
2381  *    - On success, zero.
2382  *    - On failure, a negative value.
2383  */
2384 static int
2385 eth_igb_get_syn_filter(struct rte_eth_dev *dev,
2386                         struct rte_syn_filter *filter, uint16_t *rx_queue)
2387 {
2388         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389         uint32_t synqf, rfctl;
2390
2391         MAC_TYPE_FILTER_SUP(hw->mac.type);
2392         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2393         if (synqf & E1000_SYN_FILTER_ENABLE) {
2394                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2395                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2396                 *rx_queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2397                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2398                 return 0;
2399         }
2400         return -ENOENT;
2401 }
2402
2403 /*
2404  * add an ethertype filter
2405  *
2406  * @param
2407  * dev: Pointer to struct rte_eth_dev.
2408  * index: the index the filter allocates.
2409  * filter: ponter to the filter that will be added.
2410  * rx_queue: the queue id the filter assigned to.
2411  *
2412  * @return
2413  *    - On success, zero.
2414  *    - On failure, a negative value.
2415  */
2416 static int
2417 eth_igb_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2418                         struct rte_ethertype_filter *filter, uint16_t rx_queue)
2419 {
2420         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2421         uint32_t etqf;
2422
2423         MAC_TYPE_FILTER_SUP(hw->mac.type);
2424
2425         if (index >= E1000_MAX_ETQF_FILTERS || rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2426                 return -EINVAL;
2427
2428         etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2429         if (etqf & E1000_ETQF_FILTER_ENABLE)
2430                 return -EINVAL;  /* filter index is in use. */
2431         else
2432                 etqf = 0;
2433
2434         etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
2435         etqf |= (uint32_t)(filter->ethertype & E1000_ETQF_ETHERTYPE);
2436         etqf |= rx_queue << E1000_ETQF_QUEUE_SHIFT;
2437
2438         if (filter->priority_en) {
2439                 PMD_INIT_LOG(ERR, "vlan and priority (%d) is not supported"
2440                         " in E1000.", filter->priority);
2441                 return -EINVAL;
2442         }
2443
2444         E1000_WRITE_REG(hw, E1000_ETQF(index), etqf);
2445         return 0;
2446 }
2447
2448 /*
2449  * remove an ethertype filter
2450  *
2451  * @param
2452  * dev: Pointer to struct rte_eth_dev.
2453  * index: the index the filter allocates.
2454  *
2455  * @return
2456  *    - On success, zero.
2457  *    - On failure, a negative value.
2458  */
2459 static int
2460 eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev, uint16_t index)
2461 {
2462         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2463
2464         MAC_TYPE_FILTER_SUP(hw->mac.type);
2465
2466         if (index >= E1000_MAX_ETQF_FILTERS)
2467                 return -EINVAL;
2468
2469         E1000_WRITE_REG(hw, E1000_ETQF(index), 0);
2470         return 0;
2471 }
2472
2473 /*
2474  * get an ethertype filter
2475  *
2476  * @param
2477  * dev: Pointer to struct rte_eth_dev.
2478  * index: the index the filter allocates.
2479  * filter: ponter to the filter that will be gotten.
2480  * *rx_queue: the ponited of the queue id the filter assigned to.
2481  *
2482  * @return
2483  *    - On success, zero.
2484  *    - On failure, a negative value.
2485  */
2486 static int
2487 eth_igb_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2488                         struct rte_ethertype_filter *filter, uint16_t *rx_queue)
2489 {
2490         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2491         uint32_t etqf;
2492
2493         MAC_TYPE_FILTER_SUP(hw->mac.type);
2494
2495         if (index >= E1000_MAX_ETQF_FILTERS)
2496                 return -EINVAL;
2497
2498         etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2499         if (etqf & E1000_ETQF_FILTER_ENABLE) {
2500                 filter->ethertype = etqf & E1000_ETQF_ETHERTYPE;
2501                 filter->priority_en = 0;
2502                 *rx_queue = (etqf & E1000_ETQF_QUEUE) >> E1000_ETQF_QUEUE_SHIFT;
2503                 return 0;
2504         }
2505         return -ENOENT;
2506 }
2507
2508 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2509         if ((type) != e1000_82580 && (type) != e1000_i350)\
2510                 return -ENOSYS; \
2511 } while (0)
2512
2513 /*
2514  * add a 2tuple filter
2515  *
2516  * @param
2517  * dev: Pointer to struct rte_eth_dev.
2518  * index: the index the filter allocates.
2519  * filter: ponter to the filter that will be added.
2520  * rx_queue: the queue id the filter assigned to.
2521  *
2522  * @return
2523  *    - On success, zero.
2524  *    - On failure, a negative value.
2525  */
2526 static int
2527 eth_igb_add_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2528                         struct rte_2tuple_filter *filter, uint16_t rx_queue)
2529 {
2530         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2531         uint32_t ttqf, imir = 0;
2532         uint32_t imir_ext = 0;
2533
2534         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2535
2536         if (index >= E1000_MAX_TTQF_FILTERS ||
2537                 rx_queue >= IGB_MAX_RX_QUEUE_NUM ||
2538                 filter->priority > E1000_2TUPLE_MAX_PRI)
2539                 return -EINVAL;  /* filter index is out of range. */
2540         if  (filter->tcp_flags > TCP_FLAG_ALL)
2541                 return -EINVAL;  /* flags is invalid. */
2542
2543         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2544         if (ttqf & E1000_TTQF_QUEUE_ENABLE)
2545                 return -EINVAL;  /* filter index is in use. */
2546
2547         imir = (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2548         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2549                 imir |= E1000_IMIR_PORT_BP;
2550         else
2551                 imir &= ~E1000_IMIR_PORT_BP;
2552
2553         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2554
2555         ttqf = 0;
2556         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2557         ttqf |= (uint32_t)(rx_queue << E1000_TTQF_QUEUE_SHIFT);
2558         ttqf |= (uint32_t)(filter->protocol & E1000_TTQF_PROTOCOL_MASK);
2559         if (filter->protocol_mask == 1)
2560                 ttqf |= E1000_TTQF_MASK_ENABLE;
2561         else
2562                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2563
2564         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2565         /* tcp flags bits setting. */
2566         if (filter->tcp_flags & TCP_FLAG_ALL) {
2567                 if (filter->tcp_flags & TCP_UGR_FLAG)
2568                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2569                 if (filter->tcp_flags & TCP_ACK_FLAG)
2570                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2571                 if (filter->tcp_flags & TCP_PSH_FLAG)
2572                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2573                 if (filter->tcp_flags & TCP_RST_FLAG)
2574                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2575                 if (filter->tcp_flags & TCP_SYN_FLAG)
2576                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2577                 if (filter->tcp_flags & TCP_FIN_FLAG)
2578                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2579                 imir_ext &= ~E1000_IMIR_EXT_CTRL_BP;
2580         } else
2581                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2582         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2583         E1000_WRITE_REG(hw, E1000_TTQF(index), ttqf);
2584         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2585         return 0;
2586 }
2587
2588 /*
2589  * remove a 2tuple filter
2590  *
2591  * @param
2592  * dev: Pointer to struct rte_eth_dev.
2593  * index: the index the filter allocates.
2594  *
2595  * @return
2596  *    - On success, zero.
2597  *    - On failure, a negative value.
2598  */
2599 static int
2600 eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2601                         uint16_t index)
2602 {
2603         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2604
2605         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2606
2607         if (index >= E1000_MAX_TTQF_FILTERS)
2608                 return -EINVAL;  /* filter index is out of range */
2609
2610         E1000_WRITE_REG(hw, E1000_TTQF(index), 0);
2611         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2612         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2613         return 0;
2614 }
2615
2616 /*
2617  * get a 2tuple filter
2618  *
2619  * @param
2620  * dev: Pointer to struct rte_eth_dev.
2621  * index: the index the filter allocates.
2622  * filter: ponter to the filter that returns.
2623  * *rx_queue: pointer of the queue id the filter assigned to.
2624  *
2625  * @return
2626  *    - On success, zero.
2627  *    - On failure, a negative value.
2628  */
2629 static int
2630 eth_igb_get_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2631                         struct rte_2tuple_filter *filter, uint16_t *rx_queue)
2632 {
2633         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2634         uint32_t imir, ttqf, imir_ext;
2635
2636         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2637
2638         if (index >= E1000_MAX_TTQF_FILTERS)
2639                 return -EINVAL;  /* filter index is out of range. */
2640
2641         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2642         if (ttqf & E1000_TTQF_QUEUE_ENABLE) {
2643                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2644                 filter->protocol = ttqf & E1000_TTQF_PROTOCOL_MASK;
2645                 filter->protocol_mask = (ttqf & E1000_TTQF_MASK_ENABLE) ? 1 : 0;
2646                 *rx_queue = (ttqf & E1000_TTQF_RX_QUEUE_MASK) >>
2647                                 E1000_TTQF_QUEUE_SHIFT;
2648                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2649                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2650                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2651                         E1000_IMIR_PRIORITY_SHIFT;
2652
2653                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2654                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2655                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2656                                 filter->tcp_flags |= TCP_UGR_FLAG;
2657                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2658                                 filter->tcp_flags |= TCP_ACK_FLAG;
2659                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2660                                 filter->tcp_flags |= TCP_PSH_FLAG;
2661                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2662                                 filter->tcp_flags |= TCP_RST_FLAG;
2663                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2664                                 filter->tcp_flags |= TCP_SYN_FLAG;
2665                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2666                                 filter->tcp_flags |= TCP_FIN_FLAG;
2667                 } else
2668                         filter->tcp_flags = 0;
2669                 return 0;
2670         }
2671         return -ENOENT;
2672 }
2673
2674 /*
2675  * add a flex filter
2676  *
2677  * @param
2678  * dev: Pointer to struct rte_eth_dev.
2679  * index: the index the filter allocates.
2680  * filter: ponter to the filter that will be added.
2681  * rx_queue: the queue id the filter assigned to.
2682  *
2683  * @return
2684  *    - On success, zero.
2685  *     - On failure, a negative value.
2686  */
2687 static int
2688 eth_igb_add_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2689                         struct rte_flex_filter *filter, uint16_t rx_queue)
2690 {
2691         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2692         uint32_t wufc, en_bits = 0;
2693         uint32_t queueing = 0;
2694         uint32_t reg_off = 0;
2695         uint8_t i, j = 0;
2696
2697         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2698
2699         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2700                 return -EINVAL;  /* filter index is out of range. */
2701
2702         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN ||
2703                 filter->len % 8 != 0 ||
2704                 filter->priority > E1000_MAX_FLEX_FILTER_PRI)
2705                 return -EINVAL;
2706
2707         wufc = E1000_READ_REG(hw, E1000_WUFC);
2708         en_bits = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2709         if ((wufc & en_bits) == en_bits)
2710                 return -EINVAL;  /* the filter is in use. */
2711
2712         E1000_WRITE_REG(hw, E1000_WUFC,
2713                 wufc | E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index));
2714
2715         j = 0;
2716         if (index < E1000_MAX_FHFT)
2717                 reg_off = E1000_FHFT(index);
2718         else
2719                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2720
2721         for (i = 0; i < 16; i++) {
2722                 E1000_WRITE_REG(hw, reg_off + i*4*4, filter->dwords[j]);
2723                 E1000_WRITE_REG(hw, reg_off + (i*4+1)*4, filter->dwords[++j]);
2724                 E1000_WRITE_REG(hw, reg_off + (i*4+2)*4,
2725                                 (uint32_t)filter->mask[i]);
2726                 ++j;
2727         }
2728         queueing |= filter->len |
2729                 (rx_queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2730                 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2731         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET, queueing);
2732         return 0;
2733 }
2734
2735 /*
2736  * remove a flex filter
2737  *
2738  * @param
2739  * dev: Pointer to struct rte_eth_dev.
2740  * index: the index the filter allocates.
2741  *
2742  * @return
2743  *    - On success, zero.
2744  *    - On failure, a negative value.
2745  */
2746 static int
2747 eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
2748                                 uint16_t index)
2749 {
2750         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2751         uint32_t wufc, reg_off = 0;
2752         uint8_t i;
2753
2754         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2755
2756         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2757                 return -EINVAL;  /* filter index is out of range. */
2758
2759         wufc = E1000_READ_REG(hw, E1000_WUFC);
2760         E1000_WRITE_REG(hw, E1000_WUFC, wufc & (~(E1000_WUFC_FLX0 << index)));
2761
2762         if (index < E1000_MAX_FHFT)
2763                 reg_off = E1000_FHFT(index);
2764         else
2765                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2766
2767         for (i = 0; i < 64; i++)
2768                 E1000_WRITE_REG(hw, reg_off + i*4, 0);
2769         return 0;
2770 }
2771
2772 /*
2773  * get a flex filter
2774  *
2775  * @param
2776  * dev: Pointer to struct rte_eth_dev.
2777  * index: the index the filter allocates.
2778  * filter: ponter to the filter that returns.
2779  * *rx_queue: the pointer of the queue id the filter assigned to.
2780  *
2781  * @return
2782  *    - On success, zero.
2783  *    - On failure, a negative value.
2784  */
2785 static int
2786 eth_igb_get_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2787                         struct rte_flex_filter *filter, uint16_t *rx_queue)
2788 {
2789         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2790         uint32_t wufc, queueing, wufc_en = 0;
2791         uint8_t i, j;
2792
2793         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2794
2795         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2796                 return -EINVAL;  /* filter index is out of range. */
2797
2798         wufc = E1000_READ_REG(hw, E1000_WUFC);
2799         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2800
2801         if ((wufc & wufc_en) == wufc_en) {
2802                 uint32_t reg_off = 0;
2803                 j = 0;
2804                 if (index < E1000_MAX_FHFT)
2805                         reg_off = E1000_FHFT(index);
2806                 else
2807                         reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2808
2809                 for (i = 0; i < 16; i++, j = i * 2) {
2810                         filter->dwords[j] =
2811                                 E1000_READ_REG(hw, reg_off + i*4*4);
2812                         filter->dwords[j+1] =
2813                                 E1000_READ_REG(hw, reg_off + (i*4+1)*4);
2814                         filter->mask[i] =
2815                                 E1000_READ_REG(hw, reg_off + (i*4+2)*4);
2816                 }
2817                 queueing = E1000_READ_REG(hw,
2818                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2819                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2820                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2821                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
2822                 *rx_queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2823                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2824                 return 0;
2825         }
2826         return -ENOENT;
2827 }
2828
2829 /*
2830  * add a 5tuple filter
2831  *
2832  * @param
2833  * dev: Pointer to struct rte_eth_dev.
2834  * index: the index the filter allocates.
2835  * filter: ponter to the filter that will be added.
2836  * rx_queue: the queue id the filter assigned to.
2837  *
2838  * @return
2839  *    - On success, zero.
2840  *    - On failure, a negative value.
2841  */
2842 static int
2843 eth_igb_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2844                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
2845 {
2846         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2847         uint32_t ftqf, spqf = 0;
2848         uint32_t imir = 0;
2849         uint32_t imir_ext = 0;
2850
2851         if (hw->mac.type != e1000_82576)
2852                 return -ENOSYS;
2853
2854         if (index >= E1000_MAX_FTQF_FILTERS ||
2855                 rx_queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2856                 return -EINVAL;  /* filter index is out of range. */
2857
2858         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2859         if (ftqf & E1000_FTQF_QUEUE_ENABLE)
2860                 return -EINVAL;  /* filter index is in use. */
2861
2862         ftqf = 0;
2863         ftqf |= filter->protocol & E1000_FTQF_PROTOCOL_MASK;
2864         if (filter->src_ip_mask == 1) /* 1b means not compare. */
2865                 ftqf |= E1000_FTQF_SOURCE_ADDR_MASK;
2866         if (filter->dst_ip_mask == 1)
2867                 ftqf |= E1000_FTQF_DEST_ADDR_MASK;
2868         if (filter->src_port_mask == 1)
2869                 ftqf |= E1000_FTQF_SOURCE_PORT_MASK;
2870         if (filter->protocol_mask == 1)
2871                 ftqf |= E1000_FTQF_PROTOCOL_COMP_MASK;
2872         ftqf |= (rx_queue << E1000_FTQF_QUEUE_SHIFT) & E1000_FTQF_QUEUE_MASK;
2873         ftqf |= E1000_FTQF_VF_MASK_EN;
2874         ftqf |= E1000_FTQF_QUEUE_ENABLE;
2875         E1000_WRITE_REG(hw, E1000_FTQF(index), ftqf);
2876         E1000_WRITE_REG(hw, E1000_DAQF(index), filter->dst_ip);
2877         E1000_WRITE_REG(hw, E1000_SAQF(index), filter->src_ip);
2878
2879         spqf |= filter->src_port & E1000_SPQF_SRCPORT;
2880         E1000_WRITE_REG(hw, E1000_SPQF(index), spqf);
2881
2882         imir |= (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2883         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2884                 imir |= E1000_IMIR_PORT_BP;
2885         else
2886                 imir &= ~E1000_IMIR_PORT_BP;
2887         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2888
2889         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2890         /* tcp flags bits setting. */
2891         if (filter->tcp_flags & TCP_FLAG_ALL) {
2892                 if (filter->tcp_flags & TCP_UGR_FLAG)
2893                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2894                 if (filter->tcp_flags & TCP_ACK_FLAG)
2895                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2896                 if (filter->tcp_flags & TCP_PSH_FLAG)
2897                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2898                 if (filter->tcp_flags & TCP_RST_FLAG)
2899                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2900                 if (filter->tcp_flags & TCP_SYN_FLAG)
2901                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2902                 if (filter->tcp_flags & TCP_FIN_FLAG)
2903                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2904         } else
2905                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2906         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2907         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2908         return 0;
2909 }
2910
2911 /*
2912  * remove a 5tuple filter
2913  *
2914  * @param
2915  * dev: Pointer to struct rte_eth_dev.
2916  * index: the index the filter allocates
2917  *
2918  * @return
2919  *    - On success, zero.
2920  *    - On failure, a negative value.
2921  */
2922 static int
2923 eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
2924                                 uint16_t index)
2925 {
2926         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2927
2928         if (hw->mac.type != e1000_82576)
2929                 return -ENOSYS;
2930
2931         if (index >= E1000_MAX_FTQF_FILTERS)
2932                 return -EINVAL;  /* filter index is out of range. */
2933
2934         E1000_WRITE_REG(hw, E1000_FTQF(index), 0);
2935         E1000_WRITE_REG(hw, E1000_DAQF(index), 0);
2936         E1000_WRITE_REG(hw, E1000_SAQF(index), 0);
2937         E1000_WRITE_REG(hw, E1000_SPQF(index), 0);
2938         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2939         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2940         return 0;
2941 }
2942
2943 /*
2944  * get a 5tuple filter
2945  *
2946  * @param
2947  * dev: Pointer to struct rte_eth_dev.
2948  * index: the index the filter allocates
2949  * filter: ponter to the filter that returns
2950  * *rx_queue: pointer of the queue id the filter assigned to
2951  *
2952  * @return
2953  *    - On success, zero.
2954  *    - On failure, a negative value.
2955  */
2956 static int
2957 eth_igb_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2958                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
2959 {
2960         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2961         uint32_t spqf, ftqf, imir, imir_ext;
2962
2963         if (hw->mac.type != e1000_82576)
2964                 return -ENOSYS;
2965
2966         if (index >= E1000_MAX_FTQF_FILTERS)
2967                 return -EINVAL;  /* filter index is out of range. */
2968
2969         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2970         if (ftqf & E1000_FTQF_QUEUE_ENABLE) {
2971                 filter->src_ip_mask =
2972                         (ftqf & E1000_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
2973                 filter->dst_ip_mask =
2974                         (ftqf & E1000_FTQF_DEST_ADDR_MASK) ? 1 : 0;
2975                 filter->src_port_mask =
2976                         (ftqf & E1000_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
2977                 filter->protocol_mask =
2978                         (ftqf & E1000_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
2979                 filter->protocol =
2980                         (uint8_t)ftqf & E1000_FTQF_PROTOCOL_MASK;
2981                 *rx_queue = (uint16_t)((ftqf & E1000_FTQF_QUEUE_MASK) >>
2982                                 E1000_FTQF_QUEUE_SHIFT);
2983
2984                 spqf = E1000_READ_REG(hw, E1000_SPQF(index));
2985                 filter->src_port = spqf & E1000_SPQF_SRCPORT;
2986
2987                 filter->dst_ip = E1000_READ_REG(hw, E1000_DAQF(index));
2988                 filter->src_ip = E1000_READ_REG(hw, E1000_SAQF(index));
2989
2990                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2991                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2992                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2993                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2994                         E1000_IMIR_PRIORITY_SHIFT;
2995
2996                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2997                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2998                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2999                                 filter->tcp_flags |= TCP_UGR_FLAG;
3000                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
3001                                 filter->tcp_flags |= TCP_ACK_FLAG;
3002                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
3003                                 filter->tcp_flags |= TCP_PSH_FLAG;
3004                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
3005                                 filter->tcp_flags |= TCP_RST_FLAG;
3006                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
3007                                 filter->tcp_flags |= TCP_SYN_FLAG;
3008                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
3009                                 filter->tcp_flags |= TCP_FIN_FLAG;
3010                 } else
3011                         filter->tcp_flags = 0;
3012                 return 0;
3013         }
3014         return -ENOENT;
3015 }
3016
3017 static int
3018 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3019 {
3020         uint32_t rctl;
3021         struct e1000_hw *hw;
3022         struct rte_eth_dev_info dev_info;
3023         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3024                                      VLAN_TAG_SIZE);
3025
3026         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3027
3028 #ifdef RTE_LIBRTE_82571_SUPPORT
3029         /* XXX: not bigger than max_rx_pktlen */
3030         if (hw->mac.type == e1000_82571)
3031                 return -ENOTSUP;
3032 #endif
3033         eth_igb_infos_get(dev, &dev_info);
3034
3035         /* check that mtu is within the allowed range */
3036         if ((mtu < ETHER_MIN_MTU) ||
3037             (frame_size > dev_info.max_rx_pktlen))
3038                 return -EINVAL;
3039
3040         /* refuse mtu that requires the support of scattered packets when this
3041          * feature has not been enabled before. */
3042         if (!dev->data->scattered_rx &&
3043             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3044                 return -EINVAL;
3045
3046         rctl = E1000_READ_REG(hw, E1000_RCTL);
3047
3048         /* switch to jumbo mode if needed */
3049         if (frame_size > ETHER_MAX_LEN) {
3050                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3051                 rctl |= E1000_RCTL_LPE;
3052         } else {
3053                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3054                 rctl &= ~E1000_RCTL_LPE;
3055         }
3056         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3057
3058         /* update max frame size */
3059         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3060
3061         E1000_WRITE_REG(hw, E1000_RLPML,
3062                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3063
3064         return 0;
3065 }
3066
3067 static struct rte_driver pmd_igb_drv = {
3068         .type = PMD_PDEV,
3069         .init = rte_igb_pmd_init,
3070 };
3071
3072 static struct rte_driver pmd_igbvf_drv = {
3073         .type = PMD_PDEV,
3074         .init = rte_igbvf_pmd_init,
3075 };
3076
3077 PMD_REGISTER_DRIVER(pmd_igb_drv);
3078 PMD_REGISTER_DRIVER(pmd_igbvf_drv);