lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #include <sys/queue.h>
  36 #include <stdio.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40
  41 #include <rte_common.h>
  42 #include <rte_interrupts.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_tailq.h>
  52 #include <rte_eal.h>
  53 #include <rte_atomic.h>
  54 #include <rte_malloc.h>
  55
  56 #include "e1000_logs.h"
  57 #include "igb/e1000_api.h"
  58 #include "igb/e1000_hw.h"
  59 #include "e1000_ethdev.h"
  60
  61 static int  eth_igb_configure(struct rte_eth_dev *dev, uint16_t nb_rx_q,
  62                 uint16_t nb_tx_q);
  63 static int  eth_igb_start(struct rte_eth_dev *dev);
  64 static void eth_igb_stop(struct rte_eth_dev *dev);
  65 static void eth_igb_close(struct rte_eth_dev *dev);
  66 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  67 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  68 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  69 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  70 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  71                                 int wait_to_complete);
  72 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  73                                 struct rte_eth_stats *rte_stats);
  74 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  75 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  76                                 struct rte_eth_dev_info *dev_info);
  77 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  78                                 struct rte_eth_fc_conf *fc_conf);
  79 static int eth_igb_interrupt_setup(struct rte_eth_dev *dev);
  80 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  81 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  82 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  83                                                         void *param);
  84 static int  igb_hardware_init(struct e1000_hw *hw);
  85 static void igb_hw_control_acquire(struct e1000_hw *hw);
  86 static void igb_hw_control_release(struct e1000_hw *hw);
  87 static void igb_init_manageability(struct e1000_hw *hw);
  88 static void igb_release_manageability(struct e1000_hw *hw);
  89 static void igb_vlan_hw_support_enable(struct rte_eth_dev *dev);
  90 static void igb_vlan_hw_support_disable(struct rte_eth_dev *dev);
  91 static void eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  92                                       uint16_t vlan_id,
  93                                       int on);
  94 static int eth_igb_led_on(struct rte_eth_dev *dev);
  95 static int eth_igb_led_off(struct rte_eth_dev *dev);
  96
  97 static void igb_intr_disable(struct e1000_hw *hw);
  98 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
  99 static void eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 100                 uint32_t index, uint32_t pool);
 101 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 102
 103 static void igbvf_intr_disable(struct e1000_hw *hw);
 104 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 105 static int igbvf_dev_start(struct rte_eth_dev *dev);
 106 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 107 static void igbvf_dev_close(struct rte_eth_dev *dev);
 108 static int eth_igbvf_link_update(struct e1000_hw *hw);
 109 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 110 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 111 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 112                 uint16_t vlan_id, int on);
 113 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 114 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 115
 116 /*
 117  * Define VF Stats MACRO for Non "cleared on read" register
 118  */
 119 #define UPDATE_VF_STAT(reg, last, cur)            \
 120 {                                                 \
 121         u32 latest = E1000_READ_REG(hw, reg);     \
 122         cur += latest - last;                     \
 123         last = latest;                            \
 124 }
 125
 126
 127 #define IGB_FC_PAUSE_TIME 0x0680
 128 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 129 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 130
 131 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 132
 133 /*
 134  * The set of PCI devices this driver supports
 135  */
 136 static struct rte_pci_id pci_id_igb_map[] = {
 137
 138 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 139 #include "rte_pci_dev_ids.h"
 140
 141 {.device_id = 0},
 142 };
 143
 144 /*
 145  * The set of PCI devices this driver supports (for 82576&I350 VF)
 146  */
 147 static struct rte_pci_id pci_id_igbvf_map[] = {
 148
 149 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 150 #include "rte_pci_dev_ids.h"
 151
 152 {.device_id = 0},
 153 };
 154
 155 static struct eth_dev_ops eth_igb_ops = {
 156         .dev_configure        = eth_igb_configure,
 157         .dev_start            = eth_igb_start,
 158         .dev_stop             = eth_igb_stop,
 159         .dev_close            = eth_igb_close,
 160         .promiscuous_enable   = eth_igb_promiscuous_enable,
 161         .promiscuous_disable  = eth_igb_promiscuous_disable,
 162         .allmulticast_enable  = eth_igb_allmulticast_enable,
 163         .allmulticast_disable = eth_igb_allmulticast_disable,
 164         .link_update          = eth_igb_link_update,
 165         .stats_get            = eth_igb_stats_get,
 166         .stats_reset          = eth_igb_stats_reset,
 167         .dev_infos_get        = eth_igb_infos_get,
 168         .vlan_filter_set      = eth_igb_vlan_filter_set,
 169         .rx_queue_setup       = eth_igb_rx_queue_setup,
 170         .tx_queue_setup       = eth_igb_tx_queue_setup,
 171         .dev_led_on           = eth_igb_led_on,
 172         .dev_led_off          = eth_igb_led_off,
 173         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 174         .mac_addr_add         = eth_igb_rar_set,
 175         .mac_addr_remove      = eth_igb_rar_clear,
 176 };
 177
 178 /*
 179  * dev_ops for virtual function, bare necessities for basic vf
 180  * operation have been implemented
 181  */
 182 static struct eth_dev_ops igbvf_eth_dev_ops = {
 183         .dev_configure        = igbvf_dev_configure,
 184         .dev_start            = igbvf_dev_start,
 185         .dev_stop             = igbvf_dev_stop,
 186         .dev_close            = igbvf_dev_close,
 187         .link_update          = eth_igb_link_update,
 188         .stats_get            = eth_igbvf_stats_get,
 189         .stats_reset          = eth_igbvf_stats_reset,
 190         .vlan_filter_set      = igbvf_vlan_filter_set,
 191         .dev_infos_get        = eth_igb_infos_get,
 192         .rx_queue_setup       = eth_igb_rx_queue_setup,
 193         .rx_queue_release     = eth_igb_rx_queue_release,
 194         .tx_queue_setup       = eth_igb_tx_queue_setup,
 195         .tx_queue_release     = eth_igb_tx_queue_release,
 196 };
 197
 198 /**
 199  * Atomically reads the link status information from global
 200  * structure rte_eth_dev.
 201  *
 202  * @param dev
 203  *   - Pointer to the structure rte_eth_dev to read from.
 204  *   - Pointer to the buffer to be saved with the link status.
 205  *
 206  * @return
 207  *   - On success, zero.
 208  *   - On failure, negative value.
 209  */
 210 static inline int
 211 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 212                                 struct rte_eth_link *link)
 213 {
 214         struct rte_eth_link *dst = link;
 215         struct rte_eth_link *src = &(dev->data->dev_link);
 216
 217         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 218                                         *(uint64_t *)src) == 0)
 219                 return -1;
 220
 221         return 0;
 222 }
 223
 224 /**
 225  * Atomically writes the link status information into global
 226  * structure rte_eth_dev.
 227  *
 228  * @param dev
 229  *   - Pointer to the structure rte_eth_dev to read from.
 230  *   - Pointer to the buffer to be saved with the link status.
 231  *
 232  * @return
 233  *   - On success, zero.
 234  *   - On failure, negative value.
 235  */
 236 static inline int
 237 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 238                                 struct rte_eth_link *link)
 239 {
 240         struct rte_eth_link *dst = &(dev->data->dev_link);
 241         struct rte_eth_link *src = link;
 242
 243         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 244                                         *(uint64_t *)src) == 0)
 245                 return -1;
 246
 247         return 0;
 248 }
 249
 250 static void
 251 igb_identify_hardware(struct rte_eth_dev *dev)
 252 {
 253         struct e1000_hw *hw =
 254                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 255
 256         hw->vendor_id = dev->pci_dev->id.vendor_id;
 257         hw->device_id = dev->pci_dev->id.device_id;
 258         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 259         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 260
 261         e1000_set_mac_type(hw);
 262
 263         /* need to check if it is a vf device below */
 264 }
 265
 266 static int
 267 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 268                    struct rte_eth_dev *eth_dev)
 269 {
 270         int error = 0;
 271         struct rte_pci_device *pci_dev;
 272         struct e1000_hw *hw =
 273                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 274         struct e1000_vfta * shadow_vfta =
 275                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 276
 277         pci_dev = eth_dev->pci_dev;
 278         eth_dev->dev_ops = &eth_igb_ops;
 279         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 280         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 281
 282         /* for secondary processes, we don't initialise any further as primary
 283          * has already done this work. Only check we don't need a different
 284          * RX function */
 285         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 286                 if (eth_dev->data->scattered_rx)
 287                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 288                 return 0;
 289         }
 290
 291         hw->hw_addr= (void *)pci_dev->mem_resource.addr;
 292
 293         igb_identify_hardware(eth_dev);
 294
 295         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 296                 error = -EIO;
 297                 goto err_late;
 298         }
 299
 300         e1000_get_bus_info(hw);
 301
 302         hw->mac.autoneg = 1;
 303         hw->phy.autoneg_wait_to_complete = 0;
 304         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 305
 306         /* Copper options */
 307         if (hw->phy.media_type == e1000_media_type_copper) {
 308                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 309                 hw->phy.disable_polarity_correction = 0;
 310                 hw->phy.ms_type = e1000_ms_hw_default;
 311         }
 312
 313         /*
 314          * Start from a known state, this is important in reading the nvm
 315          * and mac from that.
 316          */
 317         e1000_reset_hw(hw);
 318
 319         /* Make sure we have a good EEPROM before we read from it */
 320         if (e1000_validate_nvm_checksum(hw) < 0) {
 321                 /*
 322                  * Some PCI-E parts fail the first check due to
 323                  * the link being in sleep state, call it again,
 324                  * if it fails a second time its a real issue.
 325                  */
 326                 if (e1000_validate_nvm_checksum(hw) < 0) {
 327                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 328                         error = -EIO;
 329                         goto err_late;
 330                 }
 331         }
 332
 333         /* Read the permanent MAC address out of the EEPROM */
 334         if (e1000_read_mac_addr(hw) != 0) {
 335                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 336                 error = -EIO;
 337                 goto err_late;
 338         }
 339
 340         /* Allocate memory for storing MAC addresses */
 341         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 342                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 343         if (eth_dev->data->mac_addrs == NULL) {
 344                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 345                                                 "store MAC addresses",
 346                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 347                 error = -ENOMEM;
 348                 goto err_late;
 349         }
 350
 351         /* Copy the permanent MAC address */
 352         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 353
 354         /* initialize the vfta */
 355         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 356
 357         /* Now initialize the hardware */
 358         if (igb_hardware_init(hw) != 0) {
 359                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 360                 rte_free(eth_dev->data->mac_addrs);
 361                 eth_dev->data->mac_addrs = NULL;
 362                 error = -ENODEV;
 363                 goto err_late;
 364         }
 365         hw->mac.get_link_status = 1;
 366
 367         /* Indicate SOL/IDER usage */
 368         if (e1000_check_reset_block(hw) < 0) {
 369                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 370                                         "SOL/IDER session");
 371         }
 372
 373         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 374                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 375                      pci_dev->id.device_id);
 376
 377         rte_intr_callback_register(&(pci_dev->intr_handle),
 378                 eth_igb_interrupt_handler, (void *)eth_dev);
 379
 380         return 0;
 381
 382 err_late:
 383         igb_hw_control_release(hw);
 384
 385         return (error);
 386 }
 387
 388 /*
 389  * Virtual Function device init
 390  */
 391 static int
 392 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 393                 struct rte_eth_dev *eth_dev)
 394 {
 395         struct rte_pci_device *pci_dev;
 396         struct e1000_hw *hw =
 397                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 398         int diag;
 399
 400         PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 401
 402         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 403         pci_dev = eth_dev->pci_dev;
 404
 405         hw->device_id = pci_dev->id.device_id;
 406         hw->vendor_id = pci_dev->id.vendor_id;
 407         hw->hw_addr = (void *)pci_dev->mem_resource.addr;
 408
 409         /* Initialize the shared code */
 410         diag = e1000_setup_init_funcs(hw, TRUE);
 411         if (diag != 0) {
 412                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 413                         diag);
 414                 return -EIO;
 415         }
 416
 417         /* init_mailbox_params */
 418         hw->mbx.ops.init_params(hw);
 419
 420         /* Disable the interrupts for VF */
 421         igbvf_intr_disable(hw);
 422
 423         diag = hw->mac.ops.reset_hw(hw);
 424
 425         /* Allocate memory for storing MAC addresses */
 426         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 427                 hw->mac.rar_entry_count, 0);
 428         if (eth_dev->data->mac_addrs == NULL) {
 429                 PMD_INIT_LOG(ERR,
 430                         "Failed to allocate %d bytes needed to store MAC "
 431                         "addresses",
 432                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 433                 return -ENOMEM;
 434         }
 435         /* Copy the permanent MAC address */
 436         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 437                         &eth_dev->data->mac_addrs[0]);
 438
 439         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
 440                         "mac.type=%s\n",
 441                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 442                         pci_dev->id.device_id,
 443                         "igb_mac_82576_vf");
 444
 445         return 0;
 446 }
 447
 448 static struct eth_driver rte_igb_pmd = {
 449         {
 450                 .name = "rte_igb_pmd",
 451                 .id_table = pci_id_igb_map,
 452                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 453         },
 454         .eth_dev_init = eth_igb_dev_init,
 455         .dev_private_size = sizeof(struct e1000_adapter),
 456 };
 457
 458 /*
 459  * virtual function driver struct
 460  */
 461 static struct eth_driver rte_igbvf_pmd = {
 462         {
 463                 .name = "rte_igbvf_pmd",
 464                 .id_table = pci_id_igbvf_map,
 465                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 466         },
 467         .eth_dev_init = eth_igbvf_dev_init,
 468         .dev_private_size = sizeof(struct e1000_adapter),
 469 };
 470
 471 int
 472 rte_igb_pmd_init(void)
 473 {
 474         rte_eth_driver_register(&rte_igb_pmd);
 475         return 0;
 476 }
 477
 478 /*
 479  * VF Driver initialization routine.
 480  * Invoked one at EAL init time.
 481  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 482  */
 483 int
 484 rte_igbvf_pmd_init(void)
 485 {
 486         DEBUGFUNC("rte_igbvf_pmd_init");
 487
 488         rte_eth_driver_register(&rte_igbvf_pmd);
 489         return (0);
 490 }
 491
 492 static int
 493 eth_igb_configure(struct rte_eth_dev *dev, uint16_t nb_rx_q, uint16_t nb_tx_q)
 494 {
 495         struct e1000_interrupt *intr =
 496                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 497         int diag;
 498
 499         PMD_INIT_LOG(DEBUG, ">>");
 500
 501         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 502
 503         /* Allocate the array of pointers to RX structures */
 504         diag = igb_dev_rx_queue_alloc(dev, nb_rx_q);
 505         if (diag != 0) {
 506                 PMD_INIT_LOG(ERR, "ethdev port_id=%u allocation of array of %u"
 507                                         " pointers to RX queues failed",
 508                                         dev->data->port_id, nb_rx_q);
 509                 return diag;
 510         }
 511
 512         /* Allocate the array of pointers to TX structures */
 513         diag = igb_dev_tx_queue_alloc(dev, nb_tx_q);
 514         if (diag != 0) {
 515                 PMD_INIT_LOG(ERR, "ethdev port_id=%u allocation of array of %u"
 516                                         " pointers to TX queues failed",
 517                                         dev->data->port_id, nb_tx_q);
 518
 519                 return diag;
 520         }
 521
 522         PMD_INIT_LOG(DEBUG, "<<");
 523
 524         return (0);
 525 }
 526
 527 static int
 528 eth_igb_start(struct rte_eth_dev *dev)
 529 {
 530         struct e1000_hw *hw =
 531                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 532         int ret, i;
 533
 534         PMD_INIT_LOG(DEBUG, ">>");
 535
 536         igb_intr_disable(hw);
 537
 538         /* Power up the phy. Needed to make the link go Up */
 539         e1000_power_up_phy(hw);
 540
 541         /*
 542          * Packet Buffer Allocation (PBA)
 543          * Writing PBA sets the receive portion of the buffer
 544          * the remainder is used for the transmit buffer.
 545          */
 546         if (hw->mac.type == e1000_82575) {
 547                 uint32_t pba;
 548
 549                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 550                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 551         }
 552
 553         /* Put the address into the Receive Address Array */
 554         e1000_rar_set(hw, hw->mac.addr, 0);
 555
 556         /* Initialize the hardware */
 557         if (igb_hardware_init(hw)) {
 558                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 559                 return (-1);
 560         }
 561
 562         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 563
 564         /* Configure for OS presence */
 565         igb_init_manageability(hw);
 566
 567         eth_igb_tx_init(dev);
 568
 569         /* This can fail when allocating mbufs for descriptor rings */
 570         ret = eth_igb_rx_init(dev);
 571         if (ret) {
 572                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 573                 return ret;
 574         }
 575
 576         e1000_clear_hw_cntrs_base_generic(hw);
 577
 578         /*
 579          * If VLAN filtering is enabled, set up VLAN tag offload and filtering
 580          * and restore the VFTA.
 581          */
 582         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
 583                 igb_vlan_hw_support_enable(dev);
 584         else
 585                 igb_vlan_hw_support_disable(dev);
 586
 587         /*
 588          * Configure the Interrupt Moderation register (EITR) with the maximum
 589          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 590          * spurious [DMA] memory updates of RX and TX ring descriptors.
 591          *
 592          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 593          * spurious memory updates per second should be expected.
 594          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 595          *
 596          * Because interrupts are not used at all, the MSI-X is not activated
 597          * and interrupt moderation is controlled by EITR[0].
 598          *
 599          * Note that having [almost] disabled memory updates of RX and TX ring
 600          * descriptors through the Interrupt Moderation mechanism, memory
 601          * updates of ring descriptors are now moderated by the configurable
 602          * value of Write-Back Threshold registers.
 603          */
 604         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 605                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 606                 uint32_t ivar;
 607
 608                 /* Enable all RX & TX queues in the IVAR registers */
 609                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 610                 for (i = 0; i < 8; i++)
 611                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 612
 613                 /* Configure EITR with the maximum possible value (0xFFFF) */
 614                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 615         }
 616
 617         /* Don't reset the phy next time init gets called */
 618         hw->phy.reset_disable = 1;
 619
 620         /* Setup link speed and duplex */
 621         switch (dev->data->dev_conf.link_speed) {
 622         case ETH_LINK_SPEED_AUTONEG:
 623                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 624                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 625                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 626                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 627                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 628                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 629                 else
 630                         goto error_invalid_config;
 631                 break;
 632         case ETH_LINK_SPEED_10:
 633                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 634                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 635                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 636                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 637                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 638                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 639                 else
 640                         goto error_invalid_config;
 641                 break;
 642         case ETH_LINK_SPEED_100:
 643                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 644                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 645                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 646                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 647                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 648                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 649                 else
 650                         goto error_invalid_config;
 651                 break;
 652         case ETH_LINK_SPEED_1000:
 653                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 654                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 655                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 656                 else
 657                         goto error_invalid_config;
 658                 break;
 659         case ETH_LINK_SPEED_10000:
 660         default:
 661                 goto error_invalid_config;
 662         }
 663         e1000_setup_link(hw);
 664
 665         PMD_INIT_LOG(DEBUG, "<<");
 666
 667         /* check if lsc interrupt feature is enabled */
 668         if (dev->data->dev_conf.intr_conf.lsc != 0)
 669                 return eth_igb_interrupt_setup(dev);
 670
 671         return (0);
 672
 673 error_invalid_config:
 674         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 675                         dev->data->dev_conf.link_speed,
 676                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 677         return -1;
 678 }
 679
 680 /*********************************************************************
 681  *
 682  *  This routine disables all traffic on the adapter by issuing a
 683  *  global reset on the MAC.
 684  *
 685  **********************************************************************/
 686 static void
 687 eth_igb_stop(struct rte_eth_dev *dev)
 688 {
 689         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 690         struct rte_eth_link link;
 691
 692         igb_intr_disable(hw);
 693         e1000_reset_hw(hw);
 694         E1000_WRITE_REG(hw, E1000_WUC, 0);
 695
 696         /* Power down the phy. Needed to make the link go Down */
 697         e1000_power_down_phy(hw);
 698
 699         igb_dev_clear_queues(dev);
 700
 701         /* clear the recorded link status */
 702         memset(&link, 0, sizeof(link));
 703         rte_igb_dev_atomic_write_link_status(dev, &link);
 704 }
 705
 706 static void
 707 eth_igb_close(struct rte_eth_dev *dev)
 708 {
 709         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 710         struct rte_eth_link link;
 711
 712         eth_igb_stop(dev);
 713         e1000_phy_hw_reset(hw);
 714         igb_release_manageability(hw);
 715         igb_hw_control_release(hw);
 716
 717         igb_dev_clear_queues(dev);
 718
 719         memset(&link, 0, sizeof(link));
 720         rte_igb_dev_atomic_write_link_status(dev, &link);
 721 }
 722
 723 static int
 724 igb_get_rx_buffer_size(struct e1000_hw *hw)
 725 {
 726         uint32_t rx_buf_size;
 727         if (hw->mac.type == e1000_82576) {
 728                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 729         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 730                 /* PBS needs to be translated according to a lookup table */
 731                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 732                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 733                 rx_buf_size = (rx_buf_size << 10);
 734         } else if (hw->mac.type == e1000_i210) {
 735                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 736         } else {
 737                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 738         }
 739
 740         return rx_buf_size;
 741 }
 742
 743 /*********************************************************************
 744  *
 745  *  Initialize the hardware
 746  *
 747  **********************************************************************/
 748 static int
 749 igb_hardware_init(struct e1000_hw *hw)
 750 {
 751         uint32_t rx_buf_size;
 752         int diag;
 753
 754         /* Let the firmware know the OS is in control */
 755         igb_hw_control_acquire(hw);
 756
 757         /*
 758          * These parameters control the automatic generation (Tx) and
 759          * response (Rx) to Ethernet PAUSE frames.
 760          * - High water mark should allow for at least two standard size (1518)
 761          *   frames to be received after sending an XOFF.
 762          * - Low water mark works best when it is very near the high water mark.
 763          *   This allows the receiver to restart by sending XON when it has
 764          *   drained a bit. Here we use an arbitary value of 1500 which will
 765          *   restart after one full frame is pulled from the buffer. There
 766          *   could be several smaller frames in the buffer and if so they will
 767          *   not trigger the XON until their total number reduces the buffer
 768          *   by 1500.
 769          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 770          */
 771         rx_buf_size = igb_get_rx_buffer_size(hw);
 772
 773         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
 774         hw->fc.low_water = hw->fc.high_water - 1500;
 775         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
 776         hw->fc.send_xon = 1;
 777
 778         /* Set Flow control, use the tunable location if sane */
 779         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
 780                 hw->fc.requested_mode = igb_fc_setting;
 781         else
 782                 hw->fc.requested_mode = e1000_fc_none;
 783
 784         /* Issue a global reset */
 785         e1000_reset_hw(hw);
 786         E1000_WRITE_REG(hw, E1000_WUC, 0);
 787
 788         diag = e1000_init_hw(hw);
 789         if (diag < 0)
 790                 return (diag);
 791
 792         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 793         e1000_get_phy_info(hw);
 794         e1000_check_for_link(hw);
 795
 796         return (0);
 797 }
 798
 799 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
 800 static void
 801 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 802 {
 803         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 804         struct e1000_hw_stats *stats =
 805                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 806         int pause_frames;
 807
 808         if(hw->phy.media_type == e1000_media_type_copper ||
 809             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 810                 stats->symerrs +=
 811                     E1000_READ_REG(hw,E1000_SYMERRS);
 812                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 813         }
 814
 815         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 816         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 817         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 818         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 819
 820         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 821         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 822         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 823         stats->dc += E1000_READ_REG(hw, E1000_DC);
 824         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 825         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 826         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 827         /*
 828         ** For watchdog management we need to know if we have been
 829         ** paused during the last interval, so capture that here.
 830         */
 831         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 832         stats->xoffrxc += pause_frames;
 833         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 834         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 835         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 836         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 837         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 838         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 839         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 840         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 841         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 842         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 843         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 844         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 845
 846         /* For the 64-bit byte counters the low dword must be read first. */
 847         /* Both registers clear on the read of the high dword */
 848
 849         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 850         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 851         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 852         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 853
 854         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 855         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 856         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 857         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 858         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 859
 860         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 861         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 862
 863         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 864         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 865         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 866         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 867         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 868         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 869         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 870         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 871         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 872         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 873
 874         /* Interrupt Counts */
 875
 876         stats->iac += E1000_READ_REG(hw, E1000_IAC);
 877         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 878         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 879         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 880         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 881         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 882         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 883         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 884         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 885
 886         /* Host to Card Statistics */
 887
 888         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
 889         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
 890         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
 891         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
 892         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
 893         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
 894         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
 895         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
 896         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
 897         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
 898         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
 899         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
 900         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
 901         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
 902
 903         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 904         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 905         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 906         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 907         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 908         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 909
 910         if (rte_stats == NULL)
 911                 return;
 912
 913         /* Rx Errors */
 914         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 915             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 916
 917         /* Tx Errors */
 918         rte_stats->oerrors = stats->ecol + stats->latecol;
 919
 920         rte_stats->ipackets = stats->gprc;
 921         rte_stats->opackets = stats->gptc;
 922         rte_stats->ibytes   = stats->gorc;
 923         rte_stats->obytes   = stats->gotc;
 924 }
 925
 926 static void
 927 eth_igb_stats_reset(struct rte_eth_dev *dev)
 928 {
 929         struct e1000_hw_stats *hw_stats =
 930                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 931
 932         /* HW registers are cleared on read */
 933         eth_igb_stats_get(dev, NULL);
 934
 935         /* Reset software totals */
 936         memset(hw_stats, 0, sizeof(*hw_stats));
 937 }
 938
 939 static void
 940 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 941 {
 942         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 943         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
 944                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 945
 946         /* Good Rx packets, include VF loopback */
 947         UPDATE_VF_STAT(E1000_VFGPRC,
 948             hw_stats->last_gprc, hw_stats->gprc);
 949
 950         /* Good Rx octets, include VF loopback */
 951         UPDATE_VF_STAT(E1000_VFGORC,
 952             hw_stats->last_gorc, hw_stats->gorc);
 953
 954         /* Good Tx packets, include VF loopback */
 955         UPDATE_VF_STAT(E1000_VFGPTC,
 956             hw_stats->last_gptc, hw_stats->gptc);
 957
 958         /* Good Tx octets, include VF loopback */
 959         UPDATE_VF_STAT(E1000_VFGOTC,
 960             hw_stats->last_gotc, hw_stats->gotc);
 961
 962         /* Rx Multicst packets */
 963         UPDATE_VF_STAT(E1000_VFMPRC,
 964             hw_stats->last_mprc, hw_stats->mprc);
 965
 966         /* Good Rx loopback packets */
 967         UPDATE_VF_STAT(E1000_VFGPRLBC,
 968             hw_stats->last_gprlbc, hw_stats->gprlbc);
 969
 970         /* Good Rx loopback octets */
 971         UPDATE_VF_STAT(E1000_VFGORLBC,
 972             hw_stats->last_gorlbc, hw_stats->gorlbc);
 973
 974         /* Good Tx loopback packets */
 975         UPDATE_VF_STAT(E1000_VFGPTLBC,
 976             hw_stats->last_gptlbc, hw_stats->gptlbc);
 977
 978         /* Good Tx loopback octets */
 979         UPDATE_VF_STAT(E1000_VFGOTLBC,
 980             hw_stats->last_gotlbc, hw_stats->gotlbc);
 981
 982         if (rte_stats == NULL)
 983                 return;
 984
 985         memset(rte_stats, 0, sizeof(*rte_stats));
 986         rte_stats->ipackets = hw_stats->gprc;
 987         rte_stats->ibytes = hw_stats->gorc;
 988         rte_stats->opackets = hw_stats->gptc;
 989         rte_stats->obytes = hw_stats->gotc;
 990         rte_stats->imcasts = hw_stats->mprc;
 991         rte_stats->ilbpackets = hw_stats->gprlbc;
 992         rte_stats->ilbbytes = hw_stats->gorlbc;
 993         rte_stats->olbpackets = hw_stats->gptlbc;
 994         rte_stats->olbbytes = hw_stats->gotlbc;
 995
 996 }
 997
 998 static void
 999 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1000 {
1001         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1002                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1003
1004         /* Sync HW register to the last stats */
1005         eth_igbvf_stats_get(dev, NULL);
1006
1007         /* reset HW current stats*/
1008         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1009                offsetof(struct e1000_vf_stats, gprc));
1010
1011 }
1012
1013 static void
1014 eth_igb_infos_get(struct rte_eth_dev *dev,
1015                     struct rte_eth_dev_info *dev_info)
1016 {
1017         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1018
1019         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1020         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1021         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1022
1023         switch (hw->mac.type) {
1024         case e1000_82575:
1025                 dev_info->max_rx_queues = 4;
1026                 dev_info->max_tx_queues = 4;
1027                 break;
1028
1029         case e1000_82576:
1030                 dev_info->max_rx_queues = 16;
1031                 dev_info->max_tx_queues = 16;
1032                 break;
1033
1034         case e1000_82580:
1035                 dev_info->max_rx_queues = 8;
1036                 dev_info->max_tx_queues = 8;
1037                 break;
1038
1039         case e1000_i350:
1040                 dev_info->max_rx_queues = 8;
1041                 dev_info->max_tx_queues = 8;
1042                 break;
1043
1044         case e1000_i210:
1045                 dev_info->max_rx_queues = 4;
1046                 dev_info->max_tx_queues = 4;
1047                 break;
1048
1049         case e1000_vfadapt:
1050                 dev_info->max_rx_queues = 2;
1051                 dev_info->max_tx_queues = 2;
1052                 break;
1053
1054         case e1000_vfadapt_i350:
1055                 dev_info->max_rx_queues = 1;
1056                 dev_info->max_tx_queues = 1;
1057                 break;
1058
1059         default:
1060                 /* Should not happen */
1061                 dev_info->max_rx_queues = 0;
1062                 dev_info->max_tx_queues = 0;
1063         }
1064 }
1065
1066 /* return 0 means link status changed, -1 means not changed */
1067 static int
1068 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1069 {
1070         struct e1000_hw *hw =
1071                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1072         struct rte_eth_link link, old;
1073         int link_check, count;
1074
1075         link_check = 0;
1076         hw->mac.get_link_status = 1;
1077
1078         /* possible wait-to-complete in up to 9 seconds */
1079         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1080                 /* Read the real link status */
1081                 switch (hw->phy.media_type) {
1082                 case e1000_media_type_copper:
1083                         /* Do the work to read phy */
1084                         e1000_check_for_link(hw);
1085                         link_check = !hw->mac.get_link_status;
1086                         break;
1087
1088                 case e1000_media_type_fiber:
1089                         e1000_check_for_link(hw);
1090                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1091                                       E1000_STATUS_LU);
1092                         break;
1093
1094                 case e1000_media_type_internal_serdes:
1095                         e1000_check_for_link(hw);
1096                         link_check = hw->mac.serdes_has_link;
1097                         break;
1098
1099                 /* VF device is type_unknown */
1100                 case e1000_media_type_unknown:
1101                         eth_igbvf_link_update(hw);
1102                         link_check = !hw->mac.get_link_status;
1103                         break;
1104
1105                 default:
1106                         break;
1107                 }
1108                 if (link_check || wait_to_complete == 0)
1109                         break;
1110                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1111         }
1112         memset(&link, 0, sizeof(link));
1113         rte_igb_dev_atomic_read_link_status(dev, &link);
1114         old = link;
1115
1116         /* Now we check if a transition has happened */
1117         if (link_check) {
1118                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1119                                           &link.link_duplex);
1120                 link.link_status = 1;
1121         } else if (!link_check) {
1122                 link.link_speed = 0;
1123                 link.link_duplex = 0;
1124                 link.link_status = 0;
1125         }
1126         rte_igb_dev_atomic_write_link_status(dev, &link);
1127
1128         /* not changed */
1129         if (old.link_status == link.link_status)
1130                 return -1;
1131
1132         /* changed */
1133         return 0;
1134 }
1135
1136 /*
1137  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1138  * For ASF and Pass Through versions of f/w this means
1139  * that the driver is loaded.
1140  */
1141 static void
1142 igb_hw_control_acquire(struct e1000_hw *hw)
1143 {
1144         uint32_t ctrl_ext;
1145
1146         /* Let firmware know the driver has taken over */
1147         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1148         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1149 }
1150
1151 /*
1152  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1153  * For ASF and Pass Through versions of f/w this means that the
1154  * driver is no longer loaded.
1155  */
1156 static void
1157 igb_hw_control_release(struct e1000_hw *hw)
1158 {
1159         uint32_t ctrl_ext;
1160
1161         /* Let firmware taken over control of h/w */
1162         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1163         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1164                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1165 }
1166
1167 /*
1168  * Bit of a misnomer, what this really means is
1169  * to enable OS management of the system... aka
1170  * to disable special hardware management features.
1171  */
1172 static void
1173 igb_init_manageability(struct e1000_hw *hw)
1174 {
1175         if (e1000_enable_mng_pass_thru(hw)) {
1176                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1177                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1178
1179                 /* disable hardware interception of ARP */
1180                 manc &= ~(E1000_MANC_ARP_EN);
1181
1182                 /* enable receiving management packets to the host */
1183                 manc |= E1000_MANC_EN_MNG2HOST;
1184                 manc2h |= 1 << 5;  /* Mng Port 623 */
1185                 manc2h |= 1 << 6;  /* Mng Port 664 */
1186                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1187                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1188         }
1189 }
1190
1191 static void
1192 igb_release_manageability(struct e1000_hw *hw)
1193 {
1194         if (e1000_enable_mng_pass_thru(hw)) {
1195                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1196
1197                 manc |= E1000_MANC_ARP_EN;
1198                 manc &= ~E1000_MANC_EN_MNG2HOST;
1199
1200                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1201         }
1202 }
1203
1204 static void
1205 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1206 {
1207         struct e1000_hw *hw =
1208                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1209         uint32_t rctl;
1210
1211         rctl = E1000_READ_REG(hw, E1000_RCTL);
1212         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1213         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1214 }
1215
1216 static void
1217 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1218 {
1219         struct e1000_hw *hw =
1220                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1221         uint32_t rctl;
1222
1223         rctl = E1000_READ_REG(hw, E1000_RCTL);
1224         rctl &= (~E1000_RCTL_UPE);
1225         if (dev->data->all_multicast == 1)
1226                 rctl |= E1000_RCTL_MPE;
1227         else
1228                 rctl &= (~E1000_RCTL_MPE);
1229         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1230 }
1231
1232 static void
1233 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1234 {
1235         struct e1000_hw *hw =
1236                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1237         uint32_t rctl;
1238
1239         rctl = E1000_READ_REG(hw, E1000_RCTL);
1240         rctl |= E1000_RCTL_MPE;
1241         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1242 }
1243
1244 static void
1245 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1246 {
1247         struct e1000_hw *hw =
1248                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1249         uint32_t rctl;
1250
1251         if (dev->data->promiscuous == 1)
1252                 return; /* must remain in all_multicast mode */
1253         rctl = E1000_READ_REG(hw, E1000_RCTL);
1254         rctl &= (~E1000_RCTL_MPE);
1255         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1256 }
1257
1258 static void
1259 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1260 {
1261         struct e1000_hw *hw =
1262                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1263         struct e1000_vfta * shadow_vfta =
1264                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1265         uint32_t vfta;
1266         uint32_t vid_idx;
1267         uint32_t vid_bit;
1268
1269         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1270                               E1000_VFTA_ENTRY_MASK);
1271         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1272         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1273         if (on)
1274                 vfta |= vid_bit;
1275         else
1276                 vfta &= ~vid_bit;
1277         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1278
1279         /* update local VFTA copy */
1280         shadow_vfta->vfta[vid_idx] = vfta;
1281 }
1282
1283 static void
1284 igb_vlan_hw_support_enable(struct rte_eth_dev *dev)
1285 {
1286         struct e1000_hw *hw =
1287                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1288         struct e1000_vfta * shadow_vfta =
1289                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1290         uint32_t reg;
1291         int i;
1292
1293         /* VLAN Mode Enable */
1294         reg = E1000_READ_REG(hw, E1000_CTRL);
1295         reg |= E1000_CTRL_VME;
1296         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1297
1298         /* Filter Table Enable */
1299         reg = E1000_READ_REG(hw, E1000_RCTL);
1300         reg &= ~E1000_RCTL_CFIEN;
1301         reg |= E1000_RCTL_VFE;
1302         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1303
1304         /* Update maximum frame size */
1305         reg = E1000_READ_REG(hw, E1000_RLPML);
1306         reg += VLAN_TAG_SIZE;
1307         E1000_WRITE_REG(hw, E1000_RLPML, reg);
1308
1309         /* restore VFTA table */
1310         for (i = 0; i < E1000_VFTA_SIZE; i++)
1311                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1312 }
1313
1314 static void
1315 igb_vlan_hw_support_disable(struct rte_eth_dev *dev)
1316 {
1317         struct e1000_hw *hw =
1318                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1319         uint32_t reg;
1320
1321         /* VLAN Mode disable */
1322         reg = E1000_READ_REG(hw, E1000_CTRL);
1323         reg &= ~E1000_CTRL_VME;
1324         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1325 }
1326
1327 static void
1328 igb_intr_disable(struct e1000_hw *hw)
1329 {
1330         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1331         E1000_WRITE_FLUSH(hw);
1332 }
1333
1334 /**
1335  * It enables the interrupt mask and then enable the interrupt.
1336  *
1337  * @param dev
1338  *  Pointer to struct rte_eth_dev.
1339  *
1340  * @return
1341  *  - On success, zero.
1342  *  - On failure, a negative value.
1343  */
1344 static int
1345 eth_igb_interrupt_setup(struct rte_eth_dev *dev)
1346 {
1347         struct e1000_hw *hw =
1348                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349
1350         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1351         E1000_WRITE_FLUSH(hw);
1352         rte_intr_enable(&(dev->pci_dev->intr_handle));
1353
1354         return 0;
1355 }
1356
1357 /*
1358  * It reads ICR and gets interrupt causes, check it and set a bit flag
1359  * to update link status.
1360  *
1361  * @param dev
1362  *  Pointer to struct rte_eth_dev.
1363  *
1364  * @return
1365  *  - On success, zero.
1366  *  - On failure, a negative value.
1367  */
1368 static int
1369 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1370 {
1371         uint32_t icr;
1372         struct e1000_hw *hw =
1373                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1374         struct e1000_interrupt *intr =
1375                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1376
1377         /* read-on-clear nic registers here */
1378         icr = E1000_READ_REG(hw, E1000_ICR);
1379         if (icr & E1000_ICR_LSC) {
1380                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1381         }
1382
1383         return 0;
1384 }
1385
1386 /*
1387  * It executes link_update after knowing an interrupt is prsent.
1388  *
1389  * @param dev
1390  *  Pointer to struct rte_eth_dev.
1391  *
1392  * @return
1393  *  - On success, zero.
1394  *  - On failure, a negative value.
1395  */
1396 static int
1397 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1398 {
1399         struct e1000_hw *hw =
1400                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1401         struct e1000_interrupt *intr =
1402                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1403         uint32_t tctl, rctl;
1404         struct rte_eth_link link;
1405         int ret;
1406
1407         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1408                 return -1;
1409
1410         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1411         rte_intr_enable(&(dev->pci_dev->intr_handle));
1412
1413         /* set get_link_status to check register later */
1414         hw->mac.get_link_status = 1;
1415         ret = eth_igb_link_update(dev, 0);
1416
1417         /* check if link has changed */
1418         if (ret < 0)
1419                 return 0;
1420
1421         memset(&link, 0, sizeof(link));
1422         rte_igb_dev_atomic_read_link_status(dev, &link);
1423         if (link.link_status) {
1424                 PMD_INIT_LOG(INFO,
1425                         " Port %d: Link Up - speed %u Mbps - %s\n",
1426                         dev->data->port_id, (unsigned)link.link_speed,
1427                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1428                                 "full-duplex" : "half-duplex");
1429         } else {
1430                 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1431                                         dev->data->port_id);
1432         }
1433         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1434                                 dev->pci_dev->addr.domain,
1435                                 dev->pci_dev->addr.bus,
1436                                 dev->pci_dev->addr.devid,
1437                                 dev->pci_dev->addr.function);
1438         tctl = E1000_READ_REG(hw, E1000_TCTL);
1439         rctl = E1000_READ_REG(hw, E1000_RCTL);
1440         if (link.link_status) {
1441                 /* enable Tx/Rx */
1442                 tctl |= E1000_TCTL_EN;
1443                 rctl |= E1000_RCTL_EN;
1444         } else {
1445                 /* disable Tx/Rx */
1446                 tctl &= ~E1000_TCTL_EN;
1447                 rctl &= ~E1000_RCTL_EN;
1448         }
1449         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1450         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1451         E1000_WRITE_FLUSH(hw);
1452
1453         return 0;
1454 }
1455
1456 /**
1457  * Interrupt handler which shall be registered at first.
1458  *
1459  * @param handle
1460  *  Pointer to interrupt handle.
1461  * @param param
1462  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1463  *
1464  * @return
1465  *  void
1466  */
1467 static void
1468 eth_igb_interrupt_handler(struct rte_intr_handle *handle, void *param)
1469 {
1470         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1471
1472         eth_igb_interrupt_get_status(dev);
1473         eth_igb_interrupt_action(dev);
1474         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1475 }
1476
1477 static int
1478 eth_igb_led_on(struct rte_eth_dev *dev)
1479 {
1480         struct e1000_hw *hw;
1481
1482         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1483         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1484 }
1485
1486 static int
1487 eth_igb_led_off(struct rte_eth_dev *dev)
1488 {
1489         struct e1000_hw *hw;
1490
1491         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1492         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1493 }
1494
1495 static int
1496 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1497 {
1498         struct e1000_hw *hw;
1499         int err;
1500         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1501                 e1000_fc_none,
1502                 e1000_fc_rx_pause,
1503                 e1000_fc_tx_pause,
1504                 e1000_fc_full
1505         };
1506         uint32_t rx_buf_size;
1507         uint32_t max_high_water;
1508
1509         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1510         rx_buf_size = igb_get_rx_buffer_size(hw);
1511         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1512
1513         /* At least reserve one Ethernet frame for watermark */
1514         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1515         if ((fc_conf->high_water > max_high_water) ||
1516                 (fc_conf->high_water < fc_conf->low_water)) {
1517                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1518                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1519                 return (-EINVAL);
1520         }
1521
1522         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1523         hw->fc.pause_time     = fc_conf->pause_time;
1524         hw->fc.high_water     = fc_conf->high_water;
1525         hw->fc.low_water      = fc_conf->low_water;
1526         hw->fc.send_xon       = fc_conf->send_xon;
1527
1528         err = e1000_setup_link_generic(hw);
1529         if (err == E1000_SUCCESS) {
1530                 return 0;
1531         }
1532
1533         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1534         return (-EIO);
1535 }
1536
1537 static void
1538 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1539                 uint32_t index, __rte_unused uint32_t pool)
1540 {
1541         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1542
1543         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1544 }
1545
1546 static void
1547 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1548 {
1549         uint8_t addr[ETHER_ADDR_LEN];
1550         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1551
1552         memset(addr, 0, sizeof(addr));
1553
1554         e1000_rar_set(hw, addr, index);
1555 }
1556
1557 /*
1558  * Virtual Function operations
1559  */
1560 static void
1561 igbvf_intr_disable(struct e1000_hw *hw)
1562 {
1563         PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1564
1565         /* Clear interrupt mask to stop from interrupts being generated */
1566         E1000_WRITE_REG(hw, E1000_EIMC, ~0);
1567
1568         E1000_WRITE_FLUSH(hw);
1569 }
1570
1571 static void
1572 igbvf_stop_adapter(struct rte_eth_dev *dev)
1573 {
1574         u32 reg_val;
1575         u16 i;
1576         struct rte_eth_dev_info dev_info;
1577         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1578
1579         memset(&dev_info, 0, sizeof(dev_info));
1580         eth_igb_infos_get(dev, &dev_info);
1581
1582         /* Clear interrupt mask to stop from interrupts being generated */
1583         E1000_WRITE_REG(hw, E1000_EIMC, ~0);
1584
1585         /* Clear any pending interrupts, flush previous writes */
1586         E1000_READ_REG(hw, E1000_EICR);
1587
1588         /* Disable the transmit unit.  Each queue must be disabled. */
1589         for (i = 0; i < dev_info.max_tx_queues; i++)
1590                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1591
1592         /* Disable the receive unit by stopping each queue */
1593         for (i = 0; i < dev_info.max_rx_queues; i++) {
1594                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1595                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1596                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1597                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1598                         ;
1599         }
1600
1601         /* flush all queues disables */
1602         E1000_WRITE_FLUSH(hw);
1603         msec_delay(2);
1604 }
1605
1606 static int eth_igbvf_link_update(struct e1000_hw *hw)
1607 {
1608         struct e1000_mbx_info *mbx = &hw->mbx;
1609         struct e1000_mac_info *mac = &hw->mac;
1610         int ret_val = E1000_SUCCESS;
1611
1612         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1613
1614         /*
1615          * We only want to run this if there has been a rst asserted.
1616          * in this case that could mean a link change, device reset,
1617          * or a virtual function reset
1618          */
1619
1620         /* If we were hit with a reset or timeout drop the link */
1621         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1622                 mac->get_link_status = TRUE;
1623
1624         if (!mac->get_link_status)
1625                 goto out;
1626
1627         /* if link status is down no point in checking to see if pf is up */
1628         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1629                 goto out;
1630
1631         /* if we passed all the tests above then the link is up and we no
1632          * longer need to check for link */
1633         mac->get_link_status = FALSE;
1634
1635 out:
1636         return ret_val;
1637 }
1638
1639
1640 static int
1641 igbvf_dev_configure(struct rte_eth_dev *dev)
1642 {
1643         struct rte_eth_conf* conf = &dev->data->dev_conf;
1644
1645         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1646                 dev->data->port_id);
1647
1648         /*
1649          * VF has no ability to enable/disable HW CRC
1650          * Keep the persistent behavior the same as Host PF
1651          */
1652 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1653         if (!conf->rxmode.hw_strip_crc) {
1654                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1655                 conf->rxmode.hw_strip_crc = 1;
1656         }
1657 #else
1658         if (conf->rxmode.hw_strip_crc) {
1659                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1660                 conf->rxmode.hw_strip_crc = 0;
1661         }
1662 #endif
1663
1664         return 0;
1665 }
1666
1667 static int
1668 igbvf_dev_start(struct rte_eth_dev *dev)
1669 {
1670         int ret;
1671
1672         PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1673
1674         /* Set all vfta */
1675         igbvf_set_vfta_all(dev,1);
1676
1677         eth_igbvf_tx_init(dev);
1678
1679         /* This can fail when allocating mbufs for descriptor rings */
1680         ret = eth_igbvf_rx_init(dev);
1681         if (ret) {
1682                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1683                 igb_dev_clear_queues(dev);
1684                 return ret;
1685         }
1686
1687         return 0;
1688 }
1689
1690 static void
1691 igbvf_dev_stop(struct rte_eth_dev *dev)
1692 {
1693         PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1694
1695         igbvf_stop_adapter(dev);
1696
1697         /*
1698           * Clear what we set, but we still keep shadow_vfta to
1699           * restore after device starts
1700           */
1701         igbvf_set_vfta_all(dev,0);
1702
1703         igb_dev_clear_queues(dev);
1704 }
1705
1706 static void
1707 igbvf_dev_close(struct rte_eth_dev *dev)
1708 {
1709         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1710
1711         PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1712
1713         e1000_reset_hw(hw);
1714
1715         igbvf_dev_stop(dev);
1716 }
1717
1718 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1719 {
1720         struct e1000_mbx_info *mbx = &hw->mbx;
1721         uint32_t msgbuf[2];
1722
1723         /* After set vlan, vlan strip will also be enabled in igb driver*/
1724         msgbuf[0] = E1000_VF_SET_VLAN;
1725         msgbuf[1] = vid;
1726         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1727         if (on)
1728                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1729
1730         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1731 }
1732
1733 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1734 {
1735         struct e1000_hw *hw =
1736                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1737         struct e1000_vfta * shadow_vfta =
1738                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1739         int i = 0, j = 0, vfta = 0, mask = 1;
1740
1741         for (i = 0; i < IGB_VFTA_SIZE; i++){
1742                 vfta = shadow_vfta->vfta[i];
1743                 if(vfta){
1744                         mask = 1;
1745                         for (j = 0; j < 32; j++){
1746                                 if(vfta & mask)
1747                                         igbvf_set_vfta(hw, (i<<5)+j, on);
1748                                 mask<<=1;
1749                         }
1750                 }
1751         }
1752
1753 }
1754
1755 static int
1756 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1757 {
1758         struct e1000_hw *hw =
1759                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1760         struct e1000_vfta * shadow_vfta =
1761                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1762         uint32_t vid_idx = 0;
1763         uint32_t vid_bit = 0;
1764         int ret = 0;
1765
1766         PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
1767
1768         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
1769         ret = igbvf_set_vfta(hw, vlan_id, !!on);
1770         if(ret){
1771                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
1772                 return ret;
1773         }
1774         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1775         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1776
1777         /*Save what we set and retore it after device reset*/
1778         if (on)
1779                 shadow_vfta->vfta[vid_idx] |= vid_bit;
1780         else
1781                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
1782
1783         return 0;
1784 }
1785