lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #include <sys/queue.h>
  36 #include <stdio.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40
  41 #include <rte_common.h>
  42 #include <rte_interrupts.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_tailq.h>
  52 #include <rte_eal.h>
  53 #include <rte_atomic.h>
  54 #include <rte_malloc.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 static int  eth_igb_configure(struct rte_eth_dev *dev, uint16_t nb_rx_q,
  61                 uint16_t nb_tx_q);
  62 static int  eth_igb_start(struct rte_eth_dev *dev);
  63 static void eth_igb_stop(struct rte_eth_dev *dev);
  64 static void eth_igb_close(struct rte_eth_dev *dev);
  65 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  66 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  67 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  68 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  69 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  70                                 int wait_to_complete);
  71 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  72                                 struct rte_eth_stats *rte_stats);
  73 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  74 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  75                                 struct rte_eth_dev_info *dev_info);
  76 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  77                                 struct rte_eth_fc_conf *fc_conf);
  78 static int eth_igb_interrupt_setup(struct rte_eth_dev *dev);
  79 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  80 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  81 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  82                                                         void *param);
  83 static int  igb_hardware_init(struct e1000_hw *hw);
  84 static void igb_hw_control_acquire(struct e1000_hw *hw);
  85 static void igb_hw_control_release(struct e1000_hw *hw);
  86 static void igb_init_manageability(struct e1000_hw *hw);
  87 static void igb_release_manageability(struct e1000_hw *hw);
  88 static void igb_vlan_hw_support_enable(struct rte_eth_dev *dev);
  89 static void igb_vlan_hw_support_disable(struct rte_eth_dev *dev);
  90 static void eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  91                                       uint16_t vlan_id,
  92                                       int on);
  93 static int eth_igb_led_on(struct rte_eth_dev *dev);
  94 static int eth_igb_led_off(struct rte_eth_dev *dev);
  95
  96 static void igb_intr_disable(struct e1000_hw *hw);
  97 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
  98 static void eth_igb_rar_set(struct rte_eth_dev *dev,
  99                 struct ether_addr *mac_addr,
 100                 uint32_t index, uint32_t pool);
 101 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 102
 103 static void igbvf_intr_disable(struct e1000_hw *hw);
 104 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 105 static int igbvf_dev_start(struct rte_eth_dev *dev);
 106 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 107 static void igbvf_dev_close(struct rte_eth_dev *dev);
 108 static int eth_igbvf_link_update(struct e1000_hw *hw);
 109 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 110 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 111 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 112                 uint16_t vlan_id, int on);
 113 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 114 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 115
 116 /*
 117  * Define VF Stats MACRO for Non "cleared on read" register
 118  */
 119 #define UPDATE_VF_STAT(reg, last, cur)            \
 120 {                                                 \
 121         u32 latest = E1000_READ_REG(hw, reg);     \
 122         cur += latest - last;                     \
 123         last = latest;                            \
 124 }
 125
 126
 127 #define IGB_FC_PAUSE_TIME 0x0680
 128 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 129 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 130
 131 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 132
 133 /*
 134  * The set of PCI devices this driver supports
 135  */
 136 static struct rte_pci_id pci_id_igb_map[] = {
 137
 138 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 139 #include "rte_pci_dev_ids.h"
 140
 141 {.device_id = 0},
 142 };
 143
 144 /*
 145  * The set of PCI devices this driver supports (for 82576&I350 VF)
 146  */
 147 static struct rte_pci_id pci_id_igbvf_map[] = {
 148
 149 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 150 #include "rte_pci_dev_ids.h"
 151
 152 {.device_id = 0},
 153 };
 154
 155 static struct eth_dev_ops eth_igb_ops = {
 156         .dev_configure        = eth_igb_configure,
 157         .dev_start            = eth_igb_start,
 158         .dev_stop             = eth_igb_stop,
 159         .dev_close            = eth_igb_close,
 160         .promiscuous_enable   = eth_igb_promiscuous_enable,
 161         .promiscuous_disable  = eth_igb_promiscuous_disable,
 162         .allmulticast_enable  = eth_igb_allmulticast_enable,
 163         .allmulticast_disable = eth_igb_allmulticast_disable,
 164         .link_update          = eth_igb_link_update,
 165         .stats_get            = eth_igb_stats_get,
 166         .stats_reset          = eth_igb_stats_reset,
 167         .dev_infos_get        = eth_igb_infos_get,
 168         .vlan_filter_set      = eth_igb_vlan_filter_set,
 169         .rx_queue_setup       = eth_igb_rx_queue_setup,
 170         .tx_queue_setup       = eth_igb_tx_queue_setup,
 171         .dev_led_on           = eth_igb_led_on,
 172         .dev_led_off          = eth_igb_led_off,
 173         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 174         .mac_addr_add         = eth_igb_rar_set,
 175         .mac_addr_remove      = eth_igb_rar_clear,
 176 };
 177
 178 /*
 179  * dev_ops for virtual function, bare necessities for basic vf
 180  * operation have been implemented
 181  */
 182 static struct eth_dev_ops igbvf_eth_dev_ops = {
 183         .dev_configure        = igbvf_dev_configure,
 184         .dev_start            = igbvf_dev_start,
 185         .dev_stop             = igbvf_dev_stop,
 186         .dev_close            = igbvf_dev_close,
 187         .link_update          = eth_igb_link_update,
 188         .stats_get            = eth_igbvf_stats_get,
 189         .stats_reset          = eth_igbvf_stats_reset,
 190         .vlan_filter_set      = igbvf_vlan_filter_set,
 191         .dev_infos_get        = eth_igb_infos_get,
 192         .rx_queue_setup       = eth_igb_rx_queue_setup,
 193         .rx_queue_release     = eth_igb_rx_queue_release,
 194         .tx_queue_setup       = eth_igb_tx_queue_setup,
 195         .tx_queue_release     = eth_igb_tx_queue_release,
 196 };
 197
 198 /**
 199  * Atomically reads the link status information from global
 200  * structure rte_eth_dev.
 201  *
 202  * @param dev
 203  *   - Pointer to the structure rte_eth_dev to read from.
 204  *   - Pointer to the buffer to be saved with the link status.
 205  *
 206  * @return
 207  *   - On success, zero.
 208  *   - On failure, negative value.
 209  */
 210 static inline int
 211 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 212                                 struct rte_eth_link *link)
 213 {
 214         struct rte_eth_link *dst = link;
 215         struct rte_eth_link *src = &(dev->data->dev_link);
 216
 217         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 218                                         *(uint64_t *)src) == 0)
 219                 return -1;
 220
 221         return 0;
 222 }
 223
 224 /**
 225  * Atomically writes the link status information into global
 226  * structure rte_eth_dev.
 227  *
 228  * @param dev
 229  *   - Pointer to the structure rte_eth_dev to read from.
 230  *   - Pointer to the buffer to be saved with the link status.
 231  *
 232  * @return
 233  *   - On success, zero.
 234  *   - On failure, negative value.
 235  */
 236 static inline int
 237 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 238                                 struct rte_eth_link *link)
 239 {
 240         struct rte_eth_link *dst = &(dev->data->dev_link);
 241         struct rte_eth_link *src = link;
 242
 243         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 244                                         *(uint64_t *)src) == 0)
 245                 return -1;
 246
 247         return 0;
 248 }
 249
 250 static void
 251 igb_identify_hardware(struct rte_eth_dev *dev)
 252 {
 253         struct e1000_hw *hw =
 254                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 255
 256         hw->vendor_id = dev->pci_dev->id.vendor_id;
 257         hw->device_id = dev->pci_dev->id.device_id;
 258         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 259         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 260
 261         e1000_set_mac_type(hw);
 262
 263         /* need to check if it is a vf device below */
 264 }
 265
 266 static int
 267 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 268                    struct rte_eth_dev *eth_dev)
 269 {
 270         int error = 0;
 271         struct rte_pci_device *pci_dev;
 272         struct e1000_hw *hw =
 273                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 274         struct e1000_vfta * shadow_vfta =
 275                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 276
 277         pci_dev = eth_dev->pci_dev;
 278         eth_dev->dev_ops = &eth_igb_ops;
 279         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 280         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 281
 282         /* for secondary processes, we don't initialise any further as primary
 283          * has already done this work. Only check we don't need a different
 284          * RX function */
 285         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 286                 if (eth_dev->data->scattered_rx)
 287                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 288                 return 0;
 289         }
 290
 291         hw->hw_addr= (void *)pci_dev->mem_resource.addr;
 292
 293         igb_identify_hardware(eth_dev);
 294
 295         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 296                 error = -EIO;
 297                 goto err_late;
 298         }
 299
 300         e1000_get_bus_info(hw);
 301
 302         hw->mac.autoneg = 1;
 303         hw->phy.autoneg_wait_to_complete = 0;
 304         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 305
 306         /* Copper options */
 307         if (hw->phy.media_type == e1000_media_type_copper) {
 308                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 309                 hw->phy.disable_polarity_correction = 0;
 310                 hw->phy.ms_type = e1000_ms_hw_default;
 311         }
 312
 313         /*
 314          * Start from a known state, this is important in reading the nvm
 315          * and mac from that.
 316          */
 317         e1000_reset_hw(hw);
 318
 319         /* Make sure we have a good EEPROM before we read from it */
 320         if (e1000_validate_nvm_checksum(hw) < 0) {
 321                 /*
 322                  * Some PCI-E parts fail the first check due to
 323                  * the link being in sleep state, call it again,
 324                  * if it fails a second time its a real issue.
 325                  */
 326                 if (e1000_validate_nvm_checksum(hw) < 0) {
 327                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 328                         error = -EIO;
 329                         goto err_late;
 330                 }
 331         }
 332
 333         /* Read the permanent MAC address out of the EEPROM */
 334         if (e1000_read_mac_addr(hw) != 0) {
 335                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 336                 error = -EIO;
 337                 goto err_late;
 338         }
 339
 340         /* Allocate memory for storing MAC addresses */
 341         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 342                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 343         if (eth_dev->data->mac_addrs == NULL) {
 344                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 345                                                 "store MAC addresses",
 346                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 347                 error = -ENOMEM;
 348                 goto err_late;
 349         }
 350
 351         /* Copy the permanent MAC address */
 352         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 353
 354         /* initialize the vfta */
 355         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 356
 357         /* Now initialize the hardware */
 358         if (igb_hardware_init(hw) != 0) {
 359                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 360                 rte_free(eth_dev->data->mac_addrs);
 361                 eth_dev->data->mac_addrs = NULL;
 362                 error = -ENODEV;
 363                 goto err_late;
 364         }
 365         hw->mac.get_link_status = 1;
 366
 367         /* Indicate SOL/IDER usage */
 368         if (e1000_check_reset_block(hw) < 0) {
 369                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 370                                         "SOL/IDER session");
 371         }
 372
 373         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 374                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 375                      pci_dev->id.device_id);
 376
 377         rte_intr_callback_register(&(pci_dev->intr_handle),
 378                 eth_igb_interrupt_handler, (void *)eth_dev);
 379
 380         return 0;
 381
 382 err_late:
 383         igb_hw_control_release(hw);
 384
 385         return (error);
 386 }
 387
 388 /*
 389  * Virtual Function device init
 390  */
 391 static int
 392 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 393                 struct rte_eth_dev *eth_dev)
 394 {
 395         struct rte_pci_device *pci_dev;
 396         struct e1000_hw *hw =
 397                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 398         int diag;
 399
 400         PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 401
 402         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 403         pci_dev = eth_dev->pci_dev;
 404
 405         hw->device_id = pci_dev->id.device_id;
 406         hw->vendor_id = pci_dev->id.vendor_id;
 407         hw->hw_addr = (void *)pci_dev->mem_resource.addr;
 408
 409         /* Initialize the shared code */
 410         diag = e1000_setup_init_funcs(hw, TRUE);
 411         if (diag != 0) {
 412                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 413                         diag);
 414                 return -EIO;
 415         }
 416
 417         /* init_mailbox_params */
 418         hw->mbx.ops.init_params(hw);
 419
 420         /* Disable the interrupts for VF */
 421         igbvf_intr_disable(hw);
 422
 423         diag = hw->mac.ops.reset_hw(hw);
 424
 425         /* Allocate memory for storing MAC addresses */
 426         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 427                 hw->mac.rar_entry_count, 0);
 428         if (eth_dev->data->mac_addrs == NULL) {
 429                 PMD_INIT_LOG(ERR,
 430                         "Failed to allocate %d bytes needed to store MAC "
 431                         "addresses",
 432                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 433                 return -ENOMEM;
 434         }
 435         /* Copy the permanent MAC address */
 436         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 437                         &eth_dev->data->mac_addrs[0]);
 438
 439         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
 440                         "mac.type=%s\n",
 441                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 442                         pci_dev->id.device_id,
 443                         "igb_mac_82576_vf");
 444
 445         return 0;
 446 }
 447
 448 static struct eth_driver rte_igb_pmd = {
 449         {
 450                 .name = "rte_igb_pmd",
 451                 .id_table = pci_id_igb_map,
 452                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 453         },
 454         .eth_dev_init = eth_igb_dev_init,
 455         .dev_private_size = sizeof(struct e1000_adapter),
 456 };
 457
 458 /*
 459  * virtual function driver struct
 460  */
 461 static struct eth_driver rte_igbvf_pmd = {
 462         {
 463                 .name = "rte_igbvf_pmd",
 464                 .id_table = pci_id_igbvf_map,
 465                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 466         },
 467         .eth_dev_init = eth_igbvf_dev_init,
 468         .dev_private_size = sizeof(struct e1000_adapter),
 469 };
 470
 471 int
 472 rte_igb_pmd_init(void)
 473 {
 474         rte_eth_driver_register(&rte_igb_pmd);
 475         return 0;
 476 }
 477
 478 /*
 479  * VF Driver initialization routine.
 480  * Invoked one at EAL init time.
 481  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 482  */
 483 int
 484 rte_igbvf_pmd_init(void)
 485 {
 486         DEBUGFUNC("rte_igbvf_pmd_init");
 487
 488         rte_eth_driver_register(&rte_igbvf_pmd);
 489         return (0);
 490 }
 491
 492 static int
 493 eth_igb_configure(struct rte_eth_dev *dev, uint16_t nb_rx_q, uint16_t nb_tx_q)
 494 {
 495         struct e1000_interrupt *intr =
 496                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 497         int diag;
 498
 499         PMD_INIT_LOG(DEBUG, ">>");
 500
 501         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 502
 503         /* Allocate the array of pointers to RX structures */
 504         diag = igb_dev_rx_queue_alloc(dev, nb_rx_q);
 505         if (diag != 0) {
 506                 PMD_INIT_LOG(ERR, "ethdev port_id=%u allocation of array of %u"
 507                                         " pointers to RX queues failed",
 508                                         dev->data->port_id, nb_rx_q);
 509                 return diag;
 510         }
 511
 512         /* Allocate the array of pointers to TX structures */
 513         diag = igb_dev_tx_queue_alloc(dev, nb_tx_q);
 514         if (diag != 0) {
 515                 PMD_INIT_LOG(ERR, "ethdev port_id=%u allocation of array of %u"
 516                                         " pointers to TX queues failed",
 517                                         dev->data->port_id, nb_tx_q);
 518
 519                 return diag;
 520         }
 521
 522         PMD_INIT_LOG(DEBUG, "<<");
 523
 524         return (0);
 525 }
 526
 527 static int
 528 eth_igb_start(struct rte_eth_dev *dev)
 529 {
 530         struct e1000_hw *hw =
 531                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 532         int ret, i;
 533
 534         PMD_INIT_LOG(DEBUG, ">>");
 535
 536         igb_intr_disable(hw);
 537
 538         /* Power up the phy. Needed to make the link go Up */
 539         e1000_power_up_phy(hw);
 540
 541         /*
 542          * Packet Buffer Allocation (PBA)
 543          * Writing PBA sets the receive portion of the buffer
 544          * the remainder is used for the transmit buffer.
 545          */
 546         if (hw->mac.type == e1000_82575) {
 547                 uint32_t pba;
 548
 549                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 550                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 551         }
 552
 553         /* Put the address into the Receive Address Array */
 554         e1000_rar_set(hw, hw->mac.addr, 0);
 555
 556         /* Initialize the hardware */
 557         if (igb_hardware_init(hw)) {
 558                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 559                 return (-1);
 560         }
 561
 562         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 563
 564         /* Configure for OS presence */
 565         igb_init_manageability(hw);
 566
 567         eth_igb_tx_init(dev);
 568
 569         /* This can fail when allocating mbufs for descriptor rings */
 570         ret = eth_igb_rx_init(dev);
 571         if (ret) {
 572                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 573                 return ret;
 574         }
 575
 576         e1000_clear_hw_cntrs_base_generic(hw);
 577
 578         /*
 579          * If VLAN filtering is enabled, set up VLAN tag offload and filtering
 580          * and restore the VFTA.
 581          */
 582         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
 583                 igb_vlan_hw_support_enable(dev);
 584         else
 585                 igb_vlan_hw_support_disable(dev);
 586
 587         /*
 588          * Configure the Interrupt Moderation register (EITR) with the maximum
 589          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 590          * spurious [DMA] memory updates of RX and TX ring descriptors.
 591          *
 592          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 593          * spurious memory updates per second should be expected.
 594          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 595          *
 596          * Because interrupts are not used at all, the MSI-X is not activated
 597          * and interrupt moderation is controlled by EITR[0].
 598          *
 599          * Note that having [almost] disabled memory updates of RX and TX ring
 600          * descriptors through the Interrupt Moderation mechanism, memory
 601          * updates of ring descriptors are now moderated by the configurable
 602          * value of Write-Back Threshold registers.
 603          */
 604         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 605                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 606                 uint32_t ivar;
 607
 608                 /* Enable all RX & TX queues in the IVAR registers */
 609                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 610                 for (i = 0; i < 8; i++)
 611                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 612
 613                 /* Configure EITR with the maximum possible value (0xFFFF) */
 614                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 615         }
 616
 617         /* Setup link speed and duplex */
 618         switch (dev->data->dev_conf.link_speed) {
 619         case ETH_LINK_SPEED_AUTONEG:
 620                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 621                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 622                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 623                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 624                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 625                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 626                 else
 627                         goto error_invalid_config;
 628                 break;
 629         case ETH_LINK_SPEED_10:
 630                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 631                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 632                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 633                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 634                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 635                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 636                 else
 637                         goto error_invalid_config;
 638                 break;
 639         case ETH_LINK_SPEED_100:
 640                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 641                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 642                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 643                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 644                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 645                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 646                 else
 647                         goto error_invalid_config;
 648                 break;
 649         case ETH_LINK_SPEED_1000:
 650                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 651                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 652                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 653                 else
 654                         goto error_invalid_config;
 655                 break;
 656         case ETH_LINK_SPEED_10000:
 657         default:
 658                 goto error_invalid_config;
 659         }
 660         e1000_setup_link(hw);
 661
 662         /* check if lsc interrupt feature is enabled */
 663         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 664                 ret = eth_igb_interrupt_setup(dev);
 665                 if (ret) {
 666                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 667                         igb_dev_clear_queues(dev);
 668                         return ret;
 669                 }
 670         }
 671
 672         PMD_INIT_LOG(DEBUG, "<<");
 673
 674         return (0);
 675
 676 error_invalid_config:
 677         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 678                         dev->data->dev_conf.link_speed,
 679                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 680         return -1;
 681 }
 682
 683 /*********************************************************************
 684  *
 685  *  This routine disables all traffic on the adapter by issuing a
 686  *  global reset on the MAC.
 687  *
 688  **********************************************************************/
 689 static void
 690 eth_igb_stop(struct rte_eth_dev *dev)
 691 {
 692         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 693         struct rte_eth_link link;
 694
 695         igb_intr_disable(hw);
 696         e1000_reset_hw(hw);
 697         E1000_WRITE_REG(hw, E1000_WUC, 0);
 698
 699         /* Power down the phy. Needed to make the link go Down */
 700         e1000_power_down_phy(hw);
 701
 702         igb_dev_clear_queues(dev);
 703
 704         /* clear the recorded link status */
 705         memset(&link, 0, sizeof(link));
 706         rte_igb_dev_atomic_write_link_status(dev, &link);
 707 }
 708
 709 static void
 710 eth_igb_close(struct rte_eth_dev *dev)
 711 {
 712         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 713         struct rte_eth_link link;
 714
 715         eth_igb_stop(dev);
 716         e1000_phy_hw_reset(hw);
 717         igb_release_manageability(hw);
 718         igb_hw_control_release(hw);
 719
 720         igb_dev_clear_queues(dev);
 721
 722         memset(&link, 0, sizeof(link));
 723         rte_igb_dev_atomic_write_link_status(dev, &link);
 724 }
 725
 726 static int
 727 igb_get_rx_buffer_size(struct e1000_hw *hw)
 728 {
 729         uint32_t rx_buf_size;
 730         if (hw->mac.type == e1000_82576) {
 731                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 732         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 733                 /* PBS needs to be translated according to a lookup table */
 734                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 735                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 736                 rx_buf_size = (rx_buf_size << 10);
 737         } else if (hw->mac.type == e1000_i210) {
 738                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 739         } else {
 740                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 741         }
 742
 743         return rx_buf_size;
 744 }
 745
 746 /*********************************************************************
 747  *
 748  *  Initialize the hardware
 749  *
 750  **********************************************************************/
 751 static int
 752 igb_hardware_init(struct e1000_hw *hw)
 753 {
 754         uint32_t rx_buf_size;
 755         int diag;
 756
 757         /* Let the firmware know the OS is in control */
 758         igb_hw_control_acquire(hw);
 759
 760         /*
 761          * These parameters control the automatic generation (Tx) and
 762          * response (Rx) to Ethernet PAUSE frames.
 763          * - High water mark should allow for at least two standard size (1518)
 764          *   frames to be received after sending an XOFF.
 765          * - Low water mark works best when it is very near the high water mark.
 766          *   This allows the receiver to restart by sending XON when it has
 767          *   drained a bit. Here we use an arbitary value of 1500 which will
 768          *   restart after one full frame is pulled from the buffer. There
 769          *   could be several smaller frames in the buffer and if so they will
 770          *   not trigger the XON until their total number reduces the buffer
 771          *   by 1500.
 772          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 773          */
 774         rx_buf_size = igb_get_rx_buffer_size(hw);
 775
 776         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
 777         hw->fc.low_water = hw->fc.high_water - 1500;
 778         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
 779         hw->fc.send_xon = 1;
 780
 781         /* Set Flow control, use the tunable location if sane */
 782         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
 783                 hw->fc.requested_mode = igb_fc_setting;
 784         else
 785                 hw->fc.requested_mode = e1000_fc_none;
 786
 787         /* Issue a global reset */
 788         e1000_reset_hw(hw);
 789         E1000_WRITE_REG(hw, E1000_WUC, 0);
 790
 791         diag = e1000_init_hw(hw);
 792         if (diag < 0)
 793                 return (diag);
 794
 795         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 796         e1000_get_phy_info(hw);
 797         e1000_check_for_link(hw);
 798
 799         return (0);
 800 }
 801
 802 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
 803 static void
 804 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 805 {
 806         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 807         struct e1000_hw_stats *stats =
 808                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 809         int pause_frames;
 810
 811         if(hw->phy.media_type == e1000_media_type_copper ||
 812             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 813                 stats->symerrs +=
 814                     E1000_READ_REG(hw,E1000_SYMERRS);
 815                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 816         }
 817
 818         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 819         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 820         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 821         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 822
 823         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 824         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 825         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 826         stats->dc += E1000_READ_REG(hw, E1000_DC);
 827         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 828         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 829         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 830         /*
 831         ** For watchdog management we need to know if we have been
 832         ** paused during the last interval, so capture that here.
 833         */
 834         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 835         stats->xoffrxc += pause_frames;
 836         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 837         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 838         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 839         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 840         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 841         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 842         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 843         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 844         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 845         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 846         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 847         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 848
 849         /* For the 64-bit byte counters the low dword must be read first. */
 850         /* Both registers clear on the read of the high dword */
 851
 852         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 853         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 854         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 855         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 856
 857         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 858         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 859         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 860         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 861         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 862
 863         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 864         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 865
 866         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 867         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 868         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 869         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 870         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 871         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 872         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 873         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 874         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 875         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 876
 877         /* Interrupt Counts */
 878
 879         stats->iac += E1000_READ_REG(hw, E1000_IAC);
 880         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 881         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 882         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 883         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 884         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 885         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 886         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 887         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 888
 889         /* Host to Card Statistics */
 890
 891         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
 892         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
 893         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
 894         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
 895         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
 896         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
 897         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
 898         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
 899         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
 900         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
 901         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
 902         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
 903         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
 904         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
 905
 906         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 907         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 908         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 909         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 910         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 911         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 912
 913         if (rte_stats == NULL)
 914                 return;
 915
 916         /* Rx Errors */
 917         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 918             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 919
 920         /* Tx Errors */
 921         rte_stats->oerrors = stats->ecol + stats->latecol;
 922
 923         rte_stats->ipackets = stats->gprc;
 924         rte_stats->opackets = stats->gptc;
 925         rte_stats->ibytes   = stats->gorc;
 926         rte_stats->obytes   = stats->gotc;
 927 }
 928
 929 static void
 930 eth_igb_stats_reset(struct rte_eth_dev *dev)
 931 {
 932         struct e1000_hw_stats *hw_stats =
 933                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 934
 935         /* HW registers are cleared on read */
 936         eth_igb_stats_get(dev, NULL);
 937
 938         /* Reset software totals */
 939         memset(hw_stats, 0, sizeof(*hw_stats));
 940 }
 941
 942 static void
 943 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 944 {
 945         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 946         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
 947                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 948
 949         /* Good Rx packets, include VF loopback */
 950         UPDATE_VF_STAT(E1000_VFGPRC,
 951             hw_stats->last_gprc, hw_stats->gprc);
 952
 953         /* Good Rx octets, include VF loopback */
 954         UPDATE_VF_STAT(E1000_VFGORC,
 955             hw_stats->last_gorc, hw_stats->gorc);
 956
 957         /* Good Tx packets, include VF loopback */
 958         UPDATE_VF_STAT(E1000_VFGPTC,
 959             hw_stats->last_gptc, hw_stats->gptc);
 960
 961         /* Good Tx octets, include VF loopback */
 962         UPDATE_VF_STAT(E1000_VFGOTC,
 963             hw_stats->last_gotc, hw_stats->gotc);
 964
 965         /* Rx Multicst packets */
 966         UPDATE_VF_STAT(E1000_VFMPRC,
 967             hw_stats->last_mprc, hw_stats->mprc);
 968
 969         /* Good Rx loopback packets */
 970         UPDATE_VF_STAT(E1000_VFGPRLBC,
 971             hw_stats->last_gprlbc, hw_stats->gprlbc);
 972
 973         /* Good Rx loopback octets */
 974         UPDATE_VF_STAT(E1000_VFGORLBC,
 975             hw_stats->last_gorlbc, hw_stats->gorlbc);
 976
 977         /* Good Tx loopback packets */
 978         UPDATE_VF_STAT(E1000_VFGPTLBC,
 979             hw_stats->last_gptlbc, hw_stats->gptlbc);
 980
 981         /* Good Tx loopback octets */
 982         UPDATE_VF_STAT(E1000_VFGOTLBC,
 983             hw_stats->last_gotlbc, hw_stats->gotlbc);
 984
 985         if (rte_stats == NULL)
 986                 return;
 987
 988         memset(rte_stats, 0, sizeof(*rte_stats));
 989         rte_stats->ipackets = hw_stats->gprc;
 990         rte_stats->ibytes = hw_stats->gorc;
 991         rte_stats->opackets = hw_stats->gptc;
 992         rte_stats->obytes = hw_stats->gotc;
 993         rte_stats->imcasts = hw_stats->mprc;
 994         rte_stats->ilbpackets = hw_stats->gprlbc;
 995         rte_stats->ilbbytes = hw_stats->gorlbc;
 996         rte_stats->olbpackets = hw_stats->gptlbc;
 997         rte_stats->olbbytes = hw_stats->gotlbc;
 998
 999 }
1000
1001 static void
1002 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1003 {
1004         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1005                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1006
1007         /* Sync HW register to the last stats */
1008         eth_igbvf_stats_get(dev, NULL);
1009
1010         /* reset HW current stats*/
1011         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1012                offsetof(struct e1000_vf_stats, gprc));
1013
1014 }
1015
1016 static void
1017 eth_igb_infos_get(struct rte_eth_dev *dev,
1018                     struct rte_eth_dev_info *dev_info)
1019 {
1020         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1021
1022         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1023         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1024         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1025
1026         switch (hw->mac.type) {
1027         case e1000_82575:
1028                 dev_info->max_rx_queues = 4;
1029                 dev_info->max_tx_queues = 4;
1030                 break;
1031
1032         case e1000_82576:
1033                 dev_info->max_rx_queues = 16;
1034                 dev_info->max_tx_queues = 16;
1035                 break;
1036
1037         case e1000_82580:
1038                 dev_info->max_rx_queues = 8;
1039                 dev_info->max_tx_queues = 8;
1040                 break;
1041
1042         case e1000_i350:
1043                 dev_info->max_rx_queues = 8;
1044                 dev_info->max_tx_queues = 8;
1045                 break;
1046
1047         case e1000_i210:
1048                 dev_info->max_rx_queues = 4;
1049                 dev_info->max_tx_queues = 4;
1050                 break;
1051
1052         case e1000_vfadapt:
1053                 dev_info->max_rx_queues = 2;
1054                 dev_info->max_tx_queues = 2;
1055                 break;
1056
1057         case e1000_vfadapt_i350:
1058                 dev_info->max_rx_queues = 1;
1059                 dev_info->max_tx_queues = 1;
1060                 break;
1061
1062         default:
1063                 /* Should not happen */
1064                 dev_info->max_rx_queues = 0;
1065                 dev_info->max_tx_queues = 0;
1066         }
1067 }
1068
1069 /* return 0 means link status changed, -1 means not changed */
1070 static int
1071 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1072 {
1073         struct e1000_hw *hw =
1074                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1075         struct rte_eth_link link, old;
1076         int link_check, count;
1077
1078         link_check = 0;
1079         hw->mac.get_link_status = 1;
1080
1081         /* possible wait-to-complete in up to 9 seconds */
1082         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1083                 /* Read the real link status */
1084                 switch (hw->phy.media_type) {
1085                 case e1000_media_type_copper:
1086                         /* Do the work to read phy */
1087                         e1000_check_for_link(hw);
1088                         link_check = !hw->mac.get_link_status;
1089                         break;
1090
1091                 case e1000_media_type_fiber:
1092                         e1000_check_for_link(hw);
1093                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1094                                       E1000_STATUS_LU);
1095                         break;
1096
1097                 case e1000_media_type_internal_serdes:
1098                         e1000_check_for_link(hw);
1099                         link_check = hw->mac.serdes_has_link;
1100                         break;
1101
1102                 /* VF device is type_unknown */
1103                 case e1000_media_type_unknown:
1104                         eth_igbvf_link_update(hw);
1105                         link_check = !hw->mac.get_link_status;
1106                         break;
1107
1108                 default:
1109                         break;
1110                 }
1111                 if (link_check || wait_to_complete == 0)
1112                         break;
1113                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1114         }
1115         memset(&link, 0, sizeof(link));
1116         rte_igb_dev_atomic_read_link_status(dev, &link);
1117         old = link;
1118
1119         /* Now we check if a transition has happened */
1120         if (link_check) {
1121                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1122                                           &link.link_duplex);
1123                 link.link_status = 1;
1124         } else if (!link_check) {
1125                 link.link_speed = 0;
1126                 link.link_duplex = 0;
1127                 link.link_status = 0;
1128         }
1129         rte_igb_dev_atomic_write_link_status(dev, &link);
1130
1131         /* not changed */
1132         if (old.link_status == link.link_status)
1133                 return -1;
1134
1135         /* changed */
1136         return 0;
1137 }
1138
1139 /*
1140  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1141  * For ASF and Pass Through versions of f/w this means
1142  * that the driver is loaded.
1143  */
1144 static void
1145 igb_hw_control_acquire(struct e1000_hw *hw)
1146 {
1147         uint32_t ctrl_ext;
1148
1149         /* Let firmware know the driver has taken over */
1150         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1151         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1152 }
1153
1154 /*
1155  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1156  * For ASF and Pass Through versions of f/w this means that the
1157  * driver is no longer loaded.
1158  */
1159 static void
1160 igb_hw_control_release(struct e1000_hw *hw)
1161 {
1162         uint32_t ctrl_ext;
1163
1164         /* Let firmware taken over control of h/w */
1165         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1166         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1167                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1168 }
1169
1170 /*
1171  * Bit of a misnomer, what this really means is
1172  * to enable OS management of the system... aka
1173  * to disable special hardware management features.
1174  */
1175 static void
1176 igb_init_manageability(struct e1000_hw *hw)
1177 {
1178         if (e1000_enable_mng_pass_thru(hw)) {
1179                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1180                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1181
1182                 /* disable hardware interception of ARP */
1183                 manc &= ~(E1000_MANC_ARP_EN);
1184
1185                 /* enable receiving management packets to the host */
1186                 manc |= E1000_MANC_EN_MNG2HOST;
1187                 manc2h |= 1 << 5;  /* Mng Port 623 */
1188                 manc2h |= 1 << 6;  /* Mng Port 664 */
1189                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1190                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1191         }
1192 }
1193
1194 static void
1195 igb_release_manageability(struct e1000_hw *hw)
1196 {
1197         if (e1000_enable_mng_pass_thru(hw)) {
1198                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1199
1200                 manc |= E1000_MANC_ARP_EN;
1201                 manc &= ~E1000_MANC_EN_MNG2HOST;
1202
1203                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1204         }
1205 }
1206
1207 static void
1208 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1209 {
1210         struct e1000_hw *hw =
1211                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1212         uint32_t rctl;
1213
1214         rctl = E1000_READ_REG(hw, E1000_RCTL);
1215         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1216         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1217 }
1218
1219 static void
1220 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1221 {
1222         struct e1000_hw *hw =
1223                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224         uint32_t rctl;
1225
1226         rctl = E1000_READ_REG(hw, E1000_RCTL);
1227         rctl &= (~E1000_RCTL_UPE);
1228         if (dev->data->all_multicast == 1)
1229                 rctl |= E1000_RCTL_MPE;
1230         else
1231                 rctl &= (~E1000_RCTL_MPE);
1232         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1233 }
1234
1235 static void
1236 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1237 {
1238         struct e1000_hw *hw =
1239                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1240         uint32_t rctl;
1241
1242         rctl = E1000_READ_REG(hw, E1000_RCTL);
1243         rctl |= E1000_RCTL_MPE;
1244         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1245 }
1246
1247 static void
1248 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1249 {
1250         struct e1000_hw *hw =
1251                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1252         uint32_t rctl;
1253
1254         if (dev->data->promiscuous == 1)
1255                 return; /* must remain in all_multicast mode */
1256         rctl = E1000_READ_REG(hw, E1000_RCTL);
1257         rctl &= (~E1000_RCTL_MPE);
1258         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1259 }
1260
1261 static void
1262 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1263 {
1264         struct e1000_hw *hw =
1265                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1266         struct e1000_vfta * shadow_vfta =
1267                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1268         uint32_t vfta;
1269         uint32_t vid_idx;
1270         uint32_t vid_bit;
1271
1272         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1273                               E1000_VFTA_ENTRY_MASK);
1274         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1275         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1276         if (on)
1277                 vfta |= vid_bit;
1278         else
1279                 vfta &= ~vid_bit;
1280         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1281
1282         /* update local VFTA copy */
1283         shadow_vfta->vfta[vid_idx] = vfta;
1284 }
1285
1286 static void
1287 igb_vlan_hw_support_enable(struct rte_eth_dev *dev)
1288 {
1289         struct e1000_hw *hw =
1290                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1291         struct e1000_vfta * shadow_vfta =
1292                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1293         uint32_t reg;
1294         int i;
1295
1296         /* VLAN Mode Enable */
1297         reg = E1000_READ_REG(hw, E1000_CTRL);
1298         reg |= E1000_CTRL_VME;
1299         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1300
1301         /* Filter Table Enable */
1302         reg = E1000_READ_REG(hw, E1000_RCTL);
1303         reg &= ~E1000_RCTL_CFIEN;
1304         reg |= E1000_RCTL_VFE;
1305         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1306
1307         /* Update maximum frame size */
1308         reg = E1000_READ_REG(hw, E1000_RLPML);
1309         reg += VLAN_TAG_SIZE;
1310         E1000_WRITE_REG(hw, E1000_RLPML, reg);
1311
1312         /* restore VFTA table */
1313         for (i = 0; i < E1000_VFTA_SIZE; i++)
1314                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1315 }
1316
1317 static void
1318 igb_vlan_hw_support_disable(struct rte_eth_dev *dev)
1319 {
1320         struct e1000_hw *hw =
1321                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1322         uint32_t reg;
1323
1324         /* VLAN Mode disable */
1325         reg = E1000_READ_REG(hw, E1000_CTRL);
1326         reg &= ~E1000_CTRL_VME;
1327         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1328 }
1329
1330 static void
1331 igb_intr_disable(struct e1000_hw *hw)
1332 {
1333         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1334         E1000_WRITE_FLUSH(hw);
1335 }
1336
1337 /**
1338  * It enables the interrupt mask and then enable the interrupt.
1339  *
1340  * @param dev
1341  *  Pointer to struct rte_eth_dev.
1342  *
1343  * @return
1344  *  - On success, zero.
1345  *  - On failure, a negative value.
1346  */
1347 static int
1348 eth_igb_interrupt_setup(struct rte_eth_dev *dev)
1349 {
1350         struct e1000_hw *hw =
1351                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352
1353         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1354         E1000_WRITE_FLUSH(hw);
1355         rte_intr_enable(&(dev->pci_dev->intr_handle));
1356
1357         return 0;
1358 }
1359
1360 /*
1361  * It reads ICR and gets interrupt causes, check it and set a bit flag
1362  * to update link status.
1363  *
1364  * @param dev
1365  *  Pointer to struct rte_eth_dev.
1366  *
1367  * @return
1368  *  - On success, zero.
1369  *  - On failure, a negative value.
1370  */
1371 static int
1372 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1373 {
1374         uint32_t icr;
1375         struct e1000_hw *hw =
1376                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1377         struct e1000_interrupt *intr =
1378                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1379
1380         /* read-on-clear nic registers here */
1381         icr = E1000_READ_REG(hw, E1000_ICR);
1382         if (icr & E1000_ICR_LSC) {
1383                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1384         }
1385
1386         return 0;
1387 }
1388
1389 /*
1390  * It executes link_update after knowing an interrupt is prsent.
1391  *
1392  * @param dev
1393  *  Pointer to struct rte_eth_dev.
1394  *
1395  * @return
1396  *  - On success, zero.
1397  *  - On failure, a negative value.
1398  */
1399 static int
1400 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1401 {
1402         struct e1000_hw *hw =
1403                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1404         struct e1000_interrupt *intr =
1405                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1406         uint32_t tctl, rctl;
1407         struct rte_eth_link link;
1408         int ret;
1409
1410         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1411                 return -1;
1412
1413         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1414         rte_intr_enable(&(dev->pci_dev->intr_handle));
1415
1416         /* set get_link_status to check register later */
1417         hw->mac.get_link_status = 1;
1418         ret = eth_igb_link_update(dev, 0);
1419
1420         /* check if link has changed */
1421         if (ret < 0)
1422                 return 0;
1423
1424         memset(&link, 0, sizeof(link));
1425         rte_igb_dev_atomic_read_link_status(dev, &link);
1426         if (link.link_status) {
1427                 PMD_INIT_LOG(INFO,
1428                         " Port %d: Link Up - speed %u Mbps - %s\n",
1429                         dev->data->port_id, (unsigned)link.link_speed,
1430                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1431                                 "full-duplex" : "half-duplex");
1432         } else {
1433                 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1434                                         dev->data->port_id);
1435         }
1436         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1437                                 dev->pci_dev->addr.domain,
1438                                 dev->pci_dev->addr.bus,
1439                                 dev->pci_dev->addr.devid,
1440                                 dev->pci_dev->addr.function);
1441         tctl = E1000_READ_REG(hw, E1000_TCTL);
1442         rctl = E1000_READ_REG(hw, E1000_RCTL);
1443         if (link.link_status) {
1444                 /* enable Tx/Rx */
1445                 tctl |= E1000_TCTL_EN;
1446                 rctl |= E1000_RCTL_EN;
1447         } else {
1448                 /* disable Tx/Rx */
1449                 tctl &= ~E1000_TCTL_EN;
1450                 rctl &= ~E1000_RCTL_EN;
1451         }
1452         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1453         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1454         E1000_WRITE_FLUSH(hw);
1455
1456         return 0;
1457 }
1458
1459 /**
1460  * Interrupt handler which shall be registered at first.
1461  *
1462  * @param handle
1463  *  Pointer to interrupt handle.
1464  * @param param
1465  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1466  *
1467  * @return
1468  *  void
1469  */
1470 static void
1471 eth_igb_interrupt_handler(struct rte_intr_handle *handle, void *param)
1472 {
1473         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1474
1475         eth_igb_interrupt_get_status(dev);
1476         eth_igb_interrupt_action(dev);
1477         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1478 }
1479
1480 static int
1481 eth_igb_led_on(struct rte_eth_dev *dev)
1482 {
1483         struct e1000_hw *hw;
1484
1485         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1486         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1487 }
1488
1489 static int
1490 eth_igb_led_off(struct rte_eth_dev *dev)
1491 {
1492         struct e1000_hw *hw;
1493
1494         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1495         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1496 }
1497
1498 static int
1499 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1500 {
1501         struct e1000_hw *hw;
1502         int err;
1503         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1504                 e1000_fc_none,
1505                 e1000_fc_rx_pause,
1506                 e1000_fc_tx_pause,
1507                 e1000_fc_full
1508         };
1509         uint32_t rx_buf_size;
1510         uint32_t max_high_water;
1511
1512         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1513         rx_buf_size = igb_get_rx_buffer_size(hw);
1514         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1515
1516         /* At least reserve one Ethernet frame for watermark */
1517         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1518         if ((fc_conf->high_water > max_high_water) ||
1519                 (fc_conf->high_water < fc_conf->low_water)) {
1520                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1521                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1522                 return (-EINVAL);
1523         }
1524
1525         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1526         hw->fc.pause_time     = fc_conf->pause_time;
1527         hw->fc.high_water     = fc_conf->high_water;
1528         hw->fc.low_water      = fc_conf->low_water;
1529         hw->fc.send_xon       = fc_conf->send_xon;
1530
1531         err = e1000_setup_link_generic(hw);
1532         if (err == E1000_SUCCESS) {
1533                 return 0;
1534         }
1535
1536         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1537         return (-EIO);
1538 }
1539
1540 static void
1541 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1542                 uint32_t index, __rte_unused uint32_t pool)
1543 {
1544         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1545
1546         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1547 }
1548
1549 static void
1550 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1551 {
1552         uint8_t addr[ETHER_ADDR_LEN];
1553         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1554
1555         memset(addr, 0, sizeof(addr));
1556
1557         e1000_rar_set(hw, addr, index);
1558 }
1559
1560 /*
1561  * Virtual Function operations
1562  */
1563 static void
1564 igbvf_intr_disable(struct e1000_hw *hw)
1565 {
1566         PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1567
1568         /* Clear interrupt mask to stop from interrupts being generated */
1569         E1000_WRITE_REG(hw, E1000_EIMC, ~0);
1570
1571         E1000_WRITE_FLUSH(hw);
1572 }
1573
1574 static void
1575 igbvf_stop_adapter(struct rte_eth_dev *dev)
1576 {
1577         u32 reg_val;
1578         u16 i;
1579         struct rte_eth_dev_info dev_info;
1580         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1581
1582         memset(&dev_info, 0, sizeof(dev_info));
1583         eth_igb_infos_get(dev, &dev_info);
1584
1585         /* Clear interrupt mask to stop from interrupts being generated */
1586         E1000_WRITE_REG(hw, E1000_EIMC, ~0);
1587
1588         /* Clear any pending interrupts, flush previous writes */
1589         E1000_READ_REG(hw, E1000_EICR);
1590
1591         /* Disable the transmit unit.  Each queue must be disabled. */
1592         for (i = 0; i < dev_info.max_tx_queues; i++)
1593                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1594
1595         /* Disable the receive unit by stopping each queue */
1596         for (i = 0; i < dev_info.max_rx_queues; i++) {
1597                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1598                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1599                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1600                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1601                         ;
1602         }
1603
1604         /* flush all queues disables */
1605         E1000_WRITE_FLUSH(hw);
1606         msec_delay(2);
1607 }
1608
1609 static int eth_igbvf_link_update(struct e1000_hw *hw)
1610 {
1611         struct e1000_mbx_info *mbx = &hw->mbx;
1612         struct e1000_mac_info *mac = &hw->mac;
1613         int ret_val = E1000_SUCCESS;
1614
1615         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1616
1617         /*
1618          * We only want to run this if there has been a rst asserted.
1619          * in this case that could mean a link change, device reset,
1620          * or a virtual function reset
1621          */
1622
1623         /* If we were hit with a reset or timeout drop the link */
1624         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1625                 mac->get_link_status = TRUE;
1626
1627         if (!mac->get_link_status)
1628                 goto out;
1629
1630         /* if link status is down no point in checking to see if pf is up */
1631         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1632                 goto out;
1633
1634         /* if we passed all the tests above then the link is up and we no
1635          * longer need to check for link */
1636         mac->get_link_status = FALSE;
1637
1638 out:
1639         return ret_val;
1640 }
1641
1642
1643 static int
1644 igbvf_dev_configure(struct rte_eth_dev *dev)
1645 {
1646         struct rte_eth_conf* conf = &dev->data->dev_conf;
1647
1648         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1649                 dev->data->port_id);
1650
1651         /*
1652          * VF has no ability to enable/disable HW CRC
1653          * Keep the persistent behavior the same as Host PF
1654          */
1655 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1656         if (!conf->rxmode.hw_strip_crc) {
1657                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1658                 conf->rxmode.hw_strip_crc = 1;
1659         }
1660 #else
1661         if (conf->rxmode.hw_strip_crc) {
1662                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1663                 conf->rxmode.hw_strip_crc = 0;
1664         }
1665 #endif
1666
1667         return 0;
1668 }
1669
1670 static int
1671 igbvf_dev_start(struct rte_eth_dev *dev)
1672 {
1673         int ret;
1674
1675         PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1676
1677         /* Set all vfta */
1678         igbvf_set_vfta_all(dev,1);
1679
1680         eth_igbvf_tx_init(dev);
1681
1682         /* This can fail when allocating mbufs for descriptor rings */
1683         ret = eth_igbvf_rx_init(dev);
1684         if (ret) {
1685                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1686                 igb_dev_clear_queues(dev);
1687                 return ret;
1688         }
1689
1690         return 0;
1691 }
1692
1693 static void
1694 igbvf_dev_stop(struct rte_eth_dev *dev)
1695 {
1696         PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1697
1698         igbvf_stop_adapter(dev);
1699
1700         /*
1701           * Clear what we set, but we still keep shadow_vfta to
1702           * restore after device starts
1703           */
1704         igbvf_set_vfta_all(dev,0);
1705
1706         igb_dev_clear_queues(dev);
1707 }
1708
1709 static void
1710 igbvf_dev_close(struct rte_eth_dev *dev)
1711 {
1712         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1713
1714         PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1715
1716         e1000_reset_hw(hw);
1717
1718         igbvf_dev_stop(dev);
1719 }
1720
1721 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1722 {
1723         struct e1000_mbx_info *mbx = &hw->mbx;
1724         uint32_t msgbuf[2];
1725
1726         /* After set vlan, vlan strip will also be enabled in igb driver*/
1727         msgbuf[0] = E1000_VF_SET_VLAN;
1728         msgbuf[1] = vid;
1729         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1730         if (on)
1731                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1732
1733         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1734 }
1735
1736 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1737 {
1738         struct e1000_hw *hw =
1739                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1740         struct e1000_vfta * shadow_vfta =
1741                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1742         int i = 0, j = 0, vfta = 0, mask = 1;
1743
1744         for (i = 0; i < IGB_VFTA_SIZE; i++){
1745                 vfta = shadow_vfta->vfta[i];
1746                 if(vfta){
1747                         mask = 1;
1748                         for (j = 0; j < 32; j++){
1749                                 if(vfta & mask)
1750                                         igbvf_set_vfta(hw, (i<<5)+j, on);
1751                                 mask<<=1;
1752                         }
1753                 }
1754         }
1755
1756 }
1757
1758 static int
1759 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1760 {
1761         struct e1000_hw *hw =
1762                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1763         struct e1000_vfta * shadow_vfta =
1764                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1765         uint32_t vid_idx = 0;
1766         uint32_t vid_bit = 0;
1767         int ret = 0;
1768
1769         PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
1770
1771         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
1772         ret = igbvf_set_vfta(hw, vlan_id, !!on);
1773         if(ret){
1774                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
1775                 return ret;
1776         }
1777         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1778         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1779
1780         /*Save what we set and retore it after device reset*/
1781         if (on)
1782                 shadow_vfta->vfta[vid_idx] |= vid_bit;
1783         else
1784                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
1785
1786         return 0;
1787 }
1788