lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54
  55 #include "e1000_logs.h"
  56 #include "e1000/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 static int  eth_igb_configure(struct rte_eth_dev *dev);
  60 static int  eth_igb_start(struct rte_eth_dev *dev);
  61 static void eth_igb_stop(struct rte_eth_dev *dev);
  62 static void eth_igb_close(struct rte_eth_dev *dev);
  63 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  64 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  65 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  66 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  67 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  68                                 int wait_to_complete);
  69 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  70                                 struct rte_eth_stats *rte_stats);
  71 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  72 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  73                                 struct rte_eth_dev_info *dev_info);
  74 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  75                                 struct rte_eth_fc_conf *fc_conf);
  76 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  77 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  78 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  79 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  80                                                         void *param);
  81 static int  igb_hardware_init(struct e1000_hw *hw);
  82 static void igb_hw_control_acquire(struct e1000_hw *hw);
  83 static void igb_hw_control_release(struct e1000_hw *hw);
  84 static void igb_init_manageability(struct e1000_hw *hw);
  85 static void igb_release_manageability(struct e1000_hw *hw);
  86
  87 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  88                 uint16_t vlan_id, int on);
  89 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
  90 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  91
  92 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  93 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  94 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  95 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  96 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
  97 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
  98
  99 static int eth_igb_led_on(struct rte_eth_dev *dev);
 100 static int eth_igb_led_off(struct rte_eth_dev *dev);
 101
 102 static void igb_intr_disable(struct e1000_hw *hw);
 103 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 104 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 105                 struct ether_addr *mac_addr,
 106                 uint32_t index, uint32_t pool);
 107 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 108
 109 static void igbvf_intr_disable(struct e1000_hw *hw);
 110 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 111 static int igbvf_dev_start(struct rte_eth_dev *dev);
 112 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 113 static void igbvf_dev_close(struct rte_eth_dev *dev);
 114 static int eth_igbvf_link_update(struct e1000_hw *hw);
 115 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 116 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 117 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 118                 uint16_t vlan_id, int on);
 119 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 120 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 121 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 122                  struct rte_eth_rss_reta *reta_conf);
 123 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 124                 struct rte_eth_rss_reta *reta_conf);
 125
 126 /*
 127  * Define VF Stats MACRO for Non "cleared on read" register
 128  */
 129 #define UPDATE_VF_STAT(reg, last, cur)            \
 130 {                                                 \
 131         u32 latest = E1000_READ_REG(hw, reg);     \
 132         cur += latest - last;                     \
 133         last = latest;                            \
 134 }
 135
 136
 137 #define IGB_FC_PAUSE_TIME 0x0680
 138 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 139 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 140
 141 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 142
 143 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 144
 145 /*
 146  * The set of PCI devices this driver supports
 147  */
 148 static struct rte_pci_id pci_id_igb_map[] = {
 149
 150 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 151 #include "rte_pci_dev_ids.h"
 152
 153 {.device_id = 0},
 154 };
 155
 156 /*
 157  * The set of PCI devices this driver supports (for 82576&I350 VF)
 158  */
 159 static struct rte_pci_id pci_id_igbvf_map[] = {
 160
 161 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 162 #include "rte_pci_dev_ids.h"
 163
 164 {.device_id = 0},
 165 };
 166
 167 static struct eth_dev_ops eth_igb_ops = {
 168         .dev_configure        = eth_igb_configure,
 169         .dev_start            = eth_igb_start,
 170         .dev_stop             = eth_igb_stop,
 171         .dev_close            = eth_igb_close,
 172         .promiscuous_enable   = eth_igb_promiscuous_enable,
 173         .promiscuous_disable  = eth_igb_promiscuous_disable,
 174         .allmulticast_enable  = eth_igb_allmulticast_enable,
 175         .allmulticast_disable = eth_igb_allmulticast_disable,
 176         .link_update          = eth_igb_link_update,
 177         .stats_get            = eth_igb_stats_get,
 178         .stats_reset          = eth_igb_stats_reset,
 179         .dev_infos_get        = eth_igb_infos_get,
 180         .vlan_filter_set      = eth_igb_vlan_filter_set,
 181         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 182         .vlan_offload_set     = eth_igb_vlan_offload_set,
 183         .rx_queue_setup       = eth_igb_rx_queue_setup,
 184         .rx_queue_release     = eth_igb_rx_queue_release,
 185         .rx_queue_count       = eth_igb_rx_queue_count,
 186         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 187         .tx_queue_setup       = eth_igb_tx_queue_setup,
 188         .tx_queue_release     = eth_igb_tx_queue_release,
 189         .dev_led_on           = eth_igb_led_on,
 190         .dev_led_off          = eth_igb_led_off,
 191         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 192         .mac_addr_add         = eth_igb_rar_set,
 193         .mac_addr_remove      = eth_igb_rar_clear,
 194         .reta_update          = eth_igb_rss_reta_update,
 195         .reta_query           = eth_igb_rss_reta_query,
 196 };
 197
 198 /*
 199  * dev_ops for virtual function, bare necessities for basic vf
 200  * operation have been implemented
 201  */
 202 static struct eth_dev_ops igbvf_eth_dev_ops = {
 203         .dev_configure        = igbvf_dev_configure,
 204         .dev_start            = igbvf_dev_start,
 205         .dev_stop             = igbvf_dev_stop,
 206         .dev_close            = igbvf_dev_close,
 207         .link_update          = eth_igb_link_update,
 208         .stats_get            = eth_igbvf_stats_get,
 209         .stats_reset          = eth_igbvf_stats_reset,
 210         .vlan_filter_set      = igbvf_vlan_filter_set,
 211         .dev_infos_get        = eth_igb_infos_get,
 212         .rx_queue_setup       = eth_igb_rx_queue_setup,
 213         .rx_queue_release     = eth_igb_rx_queue_release,
 214         .tx_queue_setup       = eth_igb_tx_queue_setup,
 215         .tx_queue_release     = eth_igb_tx_queue_release,
 216 };
 217
 218 /**
 219  * Atomically reads the link status information from global
 220  * structure rte_eth_dev.
 221  *
 222  * @param dev
 223  *   - Pointer to the structure rte_eth_dev to read from.
 224  *   - Pointer to the buffer to be saved with the link status.
 225  *
 226  * @return
 227  *   - On success, zero.
 228  *   - On failure, negative value.
 229  */
 230 static inline int
 231 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 232                                 struct rte_eth_link *link)
 233 {
 234         struct rte_eth_link *dst = link;
 235         struct rte_eth_link *src = &(dev->data->dev_link);
 236
 237         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 238                                         *(uint64_t *)src) == 0)
 239                 return -1;
 240
 241         return 0;
 242 }
 243
 244 /**
 245  * Atomically writes the link status information into global
 246  * structure rte_eth_dev.
 247  *
 248  * @param dev
 249  *   - Pointer to the structure rte_eth_dev to read from.
 250  *   - Pointer to the buffer to be saved with the link status.
 251  *
 252  * @return
 253  *   - On success, zero.
 254  *   - On failure, negative value.
 255  */
 256 static inline int
 257 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 258                                 struct rte_eth_link *link)
 259 {
 260         struct rte_eth_link *dst = &(dev->data->dev_link);
 261         struct rte_eth_link *src = link;
 262
 263         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 264                                         *(uint64_t *)src) == 0)
 265                 return -1;
 266
 267         return 0;
 268 }
 269
 270 static inline void
 271 igb_intr_enable(struct rte_eth_dev *dev)
 272 {
 273         struct e1000_interrupt *intr =
 274                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 275         struct e1000_hw *hw =
 276                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 277
 278         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 279         E1000_WRITE_FLUSH(hw);
 280 }
 281
 282 static void
 283 igb_intr_disable(struct e1000_hw *hw)
 284 {
 285         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 286         E1000_WRITE_FLUSH(hw);
 287 }
 288
 289 static inline int32_t
 290 igb_pf_reset_hw(struct e1000_hw *hw)
 291 {
 292         uint32_t ctrl_ext;
 293         int32_t status;
 294
 295         status = e1000_reset_hw(hw);
 296
 297         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 298         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 299         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 300         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 301         E1000_WRITE_FLUSH(hw);
 302
 303         return status;
 304 }
 305
 306 static void
 307 igb_identify_hardware(struct rte_eth_dev *dev)
 308 {
 309         struct e1000_hw *hw =
 310                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 311
 312         hw->vendor_id = dev->pci_dev->id.vendor_id;
 313         hw->device_id = dev->pci_dev->id.device_id;
 314         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 315         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 316
 317         e1000_set_mac_type(hw);
 318
 319         /* need to check if it is a vf device below */
 320 }
 321
 322 static int
 323 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 324                    struct rte_eth_dev *eth_dev)
 325 {
 326         int error = 0;
 327         struct rte_pci_device *pci_dev;
 328         struct e1000_hw *hw =
 329                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 330         struct e1000_vfta * shadow_vfta =
 331                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 332         uint32_t ctrl_ext;
 333
 334         pci_dev = eth_dev->pci_dev;
 335         eth_dev->dev_ops = &eth_igb_ops;
 336         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 337         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 338
 339         /* for secondary processes, we don't initialise any further as primary
 340          * has already done this work. Only check we don't need a different
 341          * RX function */
 342         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 343                 if (eth_dev->data->scattered_rx)
 344                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 345                 return 0;
 346         }
 347
 348         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 349
 350         igb_identify_hardware(eth_dev);
 351         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 352                 error = -EIO;
 353                 goto err_late;
 354         }
 355
 356         e1000_get_bus_info(hw);
 357
 358         hw->mac.autoneg = 1;
 359         hw->phy.autoneg_wait_to_complete = 0;
 360         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 361
 362         /* Copper options */
 363         if (hw->phy.media_type == e1000_media_type_copper) {
 364                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 365                 hw->phy.disable_polarity_correction = 0;
 366                 hw->phy.ms_type = e1000_ms_hw_default;
 367         }
 368
 369         /*
 370          * Start from a known state, this is important in reading the nvm
 371          * and mac from that.
 372          */
 373         igb_pf_reset_hw(hw);
 374
 375         /* Make sure we have a good EEPROM before we read from it */
 376         if (e1000_validate_nvm_checksum(hw) < 0) {
 377                 /*
 378                  * Some PCI-E parts fail the first check due to
 379                  * the link being in sleep state, call it again,
 380                  * if it fails a second time its a real issue.
 381                  */
 382                 if (e1000_validate_nvm_checksum(hw) < 0) {
 383                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 384                         error = -EIO;
 385                         goto err_late;
 386                 }
 387         }
 388
 389         /* Read the permanent MAC address out of the EEPROM */
 390         if (e1000_read_mac_addr(hw) != 0) {
 391                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 392                 error = -EIO;
 393                 goto err_late;
 394         }
 395
 396         /* Allocate memory for storing MAC addresses */
 397         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 398                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 399         if (eth_dev->data->mac_addrs == NULL) {
 400                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 401                                                 "store MAC addresses",
 402                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 403                 error = -ENOMEM;
 404                 goto err_late;
 405         }
 406
 407         /* Copy the permanent MAC address */
 408         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 409
 410         /* initialize the vfta */
 411         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 412
 413         /* Now initialize the hardware */
 414         if (igb_hardware_init(hw) != 0) {
 415                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 416                 rte_free(eth_dev->data->mac_addrs);
 417                 eth_dev->data->mac_addrs = NULL;
 418                 error = -ENODEV;
 419                 goto err_late;
 420         }
 421         hw->mac.get_link_status = 1;
 422
 423         /* Indicate SOL/IDER usage */
 424         if (e1000_check_reset_block(hw) < 0) {
 425                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 426                                         "SOL/IDER session");
 427         }
 428
 429         /* initialize PF if max_vfs not zero */
 430         igb_pf_host_init(eth_dev);
 431
 432         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 433         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 434         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 435         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 436         E1000_WRITE_FLUSH(hw);
 437
 438         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 439                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 440                      pci_dev->id.device_id);
 441
 442         rte_intr_callback_register(&(pci_dev->intr_handle),
 443                 eth_igb_interrupt_handler, (void *)eth_dev);
 444
 445         /* enable uio intr after callback register */
 446         rte_intr_enable(&(pci_dev->intr_handle));
 447
 448         /* enable support intr */
 449         igb_intr_enable(eth_dev);
 450
 451         return 0;
 452
 453 err_late:
 454         igb_hw_control_release(hw);
 455
 456         return (error);
 457 }
 458
 459 /*
 460  * Virtual Function device init
 461  */
 462 static int
 463 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 464                 struct rte_eth_dev *eth_dev)
 465 {
 466         struct rte_pci_device *pci_dev;
 467         struct e1000_hw *hw =
 468                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 469         int diag;
 470
 471         PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 472
 473         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 474         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 475         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 476
 477         /* for secondary processes, we don't initialise any further as primary
 478          * has already done this work. Only check we don't need a different
 479          * RX function */
 480         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 481                 if (eth_dev->data->scattered_rx)
 482                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 483                 return 0;
 484         }
 485
 486         pci_dev = eth_dev->pci_dev;
 487
 488         hw->device_id = pci_dev->id.device_id;
 489         hw->vendor_id = pci_dev->id.vendor_id;
 490         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 491
 492         /* Initialize the shared code */
 493         diag = e1000_setup_init_funcs(hw, TRUE);
 494         if (diag != 0) {
 495                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 496                         diag);
 497                 return -EIO;
 498         }
 499
 500         /* init_mailbox_params */
 501         hw->mbx.ops.init_params(hw);
 502
 503         /* Disable the interrupts for VF */
 504         igbvf_intr_disable(hw);
 505
 506         diag = hw->mac.ops.reset_hw(hw);
 507
 508         /* Allocate memory for storing MAC addresses */
 509         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 510                 hw->mac.rar_entry_count, 0);
 511         if (eth_dev->data->mac_addrs == NULL) {
 512                 PMD_INIT_LOG(ERR,
 513                         "Failed to allocate %d bytes needed to store MAC "
 514                         "addresses",
 515                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 516                 return -ENOMEM;
 517         }
 518
 519         /* Copy the permanent MAC address */
 520         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 521                         &eth_dev->data->mac_addrs[0]);
 522
 523         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
 524                         "mac.type=%s\n",
 525                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 526                         pci_dev->id.device_id,
 527                         "igb_mac_82576_vf");
 528
 529         return 0;
 530 }
 531
 532 static struct eth_driver rte_igb_pmd = {
 533         {
 534                 .name = "rte_igb_pmd",
 535                 .id_table = pci_id_igb_map,
 536                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 537         },
 538         .eth_dev_init = eth_igb_dev_init,
 539         .dev_private_size = sizeof(struct e1000_adapter),
 540 };
 541
 542 /*
 543  * virtual function driver struct
 544  */
 545 static struct eth_driver rte_igbvf_pmd = {
 546         {
 547                 .name = "rte_igbvf_pmd",
 548                 .id_table = pci_id_igbvf_map,
 549                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 550         },
 551         .eth_dev_init = eth_igbvf_dev_init,
 552         .dev_private_size = sizeof(struct e1000_adapter),
 553 };
 554
 555 int
 556 rte_igb_pmd_init(void)
 557 {
 558         rte_eth_driver_register(&rte_igb_pmd);
 559         return 0;
 560 }
 561
 562 static void
 563 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 564 {
 565         struct e1000_hw *hw =
 566                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 567         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 568         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 569         rctl |= E1000_RCTL_VFE;
 570         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 571 }
 572
 573 /*
 574  * VF Driver initialization routine.
 575  * Invoked one at EAL init time.
 576  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 577  */
 578 int
 579 rte_igbvf_pmd_init(void)
 580 {
 581         DEBUGFUNC("rte_igbvf_pmd_init");
 582
 583         rte_eth_driver_register(&rte_igbvf_pmd);
 584         return (0);
 585 }
 586
 587 static int
 588 eth_igb_configure(struct rte_eth_dev *dev)
 589 {
 590         struct e1000_interrupt *intr =
 591                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 592
 593         PMD_INIT_LOG(DEBUG, ">>");
 594
 595         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 596
 597         PMD_INIT_LOG(DEBUG, "<<");
 598
 599         return (0);
 600 }
 601
 602 static int
 603 eth_igb_start(struct rte_eth_dev *dev)
 604 {
 605         struct e1000_hw *hw =
 606                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 607         int ret, i, mask;
 608         uint32_t ctrl_ext;
 609
 610         PMD_INIT_LOG(DEBUG, ">>");
 611
 612         /* Power up the phy. Needed to make the link go Up */
 613         e1000_power_up_phy(hw);
 614
 615         /*
 616          * Packet Buffer Allocation (PBA)
 617          * Writing PBA sets the receive portion of the buffer
 618          * the remainder is used for the transmit buffer.
 619          */
 620         if (hw->mac.type == e1000_82575) {
 621                 uint32_t pba;
 622
 623                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 624                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 625         }
 626
 627         /* Put the address into the Receive Address Array */
 628         e1000_rar_set(hw, hw->mac.addr, 0);
 629
 630         /* Initialize the hardware */
 631         if (igb_hardware_init(hw)) {
 632                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 633                 return (-EIO);
 634         }
 635
 636         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 637
 638         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 639         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 640         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 641         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 642         E1000_WRITE_FLUSH(hw);
 643
 644         /* configure PF module if SRIOV enabled */
 645         igb_pf_host_configure(dev);
 646
 647         /* Configure for OS presence */
 648         igb_init_manageability(hw);
 649
 650         eth_igb_tx_init(dev);
 651
 652         /* This can fail when allocating mbufs for descriptor rings */
 653         ret = eth_igb_rx_init(dev);
 654         if (ret) {
 655                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 656                 igb_dev_clear_queues(dev);
 657                 return ret;
 658         }
 659
 660         e1000_clear_hw_cntrs_base_generic(hw);
 661
 662         /*
 663          * VLAN Offload Settings
 664          */
 665         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 666                         ETH_VLAN_EXTEND_MASK;
 667         eth_igb_vlan_offload_set(dev, mask);
 668
 669         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 670                 /* Enable VLAN filter since VMDq always use VLAN filter */
 671                 igb_vmdq_vlan_hw_filter_enable(dev);
 672         }
 673
 674         /*
 675          * Configure the Interrupt Moderation register (EITR) with the maximum
 676          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 677          * spurious [DMA] memory updates of RX and TX ring descriptors.
 678          *
 679          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 680          * spurious memory updates per second should be expected.
 681          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 682          *
 683          * Because interrupts are not used at all, the MSI-X is not activated
 684          * and interrupt moderation is controlled by EITR[0].
 685          *
 686          * Note that having [almost] disabled memory updates of RX and TX ring
 687          * descriptors through the Interrupt Moderation mechanism, memory
 688          * updates of ring descriptors are now moderated by the configurable
 689          * value of Write-Back Threshold registers.
 690          */
 691         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 692                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 693                 uint32_t ivar;
 694
 695                 /* Enable all RX & TX queues in the IVAR registers */
 696                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 697                 for (i = 0; i < 8; i++)
 698                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 699
 700                 /* Configure EITR with the maximum possible value (0xFFFF) */
 701                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 702         }
 703
 704         /* Setup link speed and duplex */
 705         switch (dev->data->dev_conf.link_speed) {
 706         case ETH_LINK_SPEED_AUTONEG:
 707                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 708                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 709                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 710                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 711                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 712                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 713                 else
 714                         goto error_invalid_config;
 715                 break;
 716         case ETH_LINK_SPEED_10:
 717                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 718                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 719                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 720                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 721                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 722                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 723                 else
 724                         goto error_invalid_config;
 725                 break;
 726         case ETH_LINK_SPEED_100:
 727                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 728                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 729                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 730                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 731                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 732                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 733                 else
 734                         goto error_invalid_config;
 735                 break;
 736         case ETH_LINK_SPEED_1000:
 737                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 738                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 739                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 740                 else
 741                         goto error_invalid_config;
 742                 break;
 743         case ETH_LINK_SPEED_10000:
 744         default:
 745                 goto error_invalid_config;
 746         }
 747         e1000_setup_link(hw);
 748
 749         /* check if lsc interrupt feature is enabled */
 750         if (dev->data->dev_conf.intr_conf.lsc != 0)
 751                 ret = eth_igb_lsc_interrupt_setup(dev);
 752
 753         /* resume enabled intr since hw reset */
 754         igb_intr_enable(dev);
 755
 756         PMD_INIT_LOG(DEBUG, "<<");
 757
 758         return (0);
 759
 760 error_invalid_config:
 761         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 762                         dev->data->dev_conf.link_speed,
 763                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 764         igb_dev_clear_queues(dev);
 765         return (-EINVAL);
 766 }
 767
 768 /*********************************************************************
 769  *
 770  *  This routine disables all traffic on the adapter by issuing a
 771  *  global reset on the MAC.
 772  *
 773  **********************************************************************/
 774 static void
 775 eth_igb_stop(struct rte_eth_dev *dev)
 776 {
 777         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 778         struct rte_eth_link link;
 779
 780         igb_intr_disable(hw);
 781         igb_pf_reset_hw(hw);
 782         E1000_WRITE_REG(hw, E1000_WUC, 0);
 783
 784         /* Set bit for Go Link disconnect */
 785         if (hw->mac.type >= e1000_82580) {
 786                 uint32_t phpm_reg;
 787
 788                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 789                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 790                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 791         }
 792
 793         /* Power down the phy. Needed to make the link go Down */
 794         e1000_power_down_phy(hw);
 795
 796         igb_dev_clear_queues(dev);
 797
 798         /* clear the recorded link status */
 799         memset(&link, 0, sizeof(link));
 800         rte_igb_dev_atomic_write_link_status(dev, &link);
 801 }
 802
 803 static void
 804 eth_igb_close(struct rte_eth_dev *dev)
 805 {
 806         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 807         struct rte_eth_link link;
 808
 809         eth_igb_stop(dev);
 810         e1000_phy_hw_reset(hw);
 811         igb_release_manageability(hw);
 812         igb_hw_control_release(hw);
 813
 814         /* Clear bit for Go Link disconnect */
 815         if (hw->mac.type >= e1000_82580) {
 816                 uint32_t phpm_reg;
 817
 818                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 819                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
 820                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 821         }
 822
 823         igb_dev_clear_queues(dev);
 824
 825         memset(&link, 0, sizeof(link));
 826         rte_igb_dev_atomic_write_link_status(dev, &link);
 827 }
 828
 829 static int
 830 igb_get_rx_buffer_size(struct e1000_hw *hw)
 831 {
 832         uint32_t rx_buf_size;
 833         if (hw->mac.type == e1000_82576) {
 834                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 835         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 836                 /* PBS needs to be translated according to a lookup table */
 837                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 838                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 839                 rx_buf_size = (rx_buf_size << 10);
 840         } else if (hw->mac.type == e1000_i210) {
 841                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 842         } else {
 843                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 844         }
 845
 846         return rx_buf_size;
 847 }
 848
 849 /*********************************************************************
 850  *
 851  *  Initialize the hardware
 852  *
 853  **********************************************************************/
 854 static int
 855 igb_hardware_init(struct e1000_hw *hw)
 856 {
 857         uint32_t rx_buf_size;
 858         int diag;
 859
 860         /* Let the firmware know the OS is in control */
 861         igb_hw_control_acquire(hw);
 862
 863         /*
 864          * These parameters control the automatic generation (Tx) and
 865          * response (Rx) to Ethernet PAUSE frames.
 866          * - High water mark should allow for at least two standard size (1518)
 867          *   frames to be received after sending an XOFF.
 868          * - Low water mark works best when it is very near the high water mark.
 869          *   This allows the receiver to restart by sending XON when it has
 870          *   drained a bit. Here we use an arbitary value of 1500 which will
 871          *   restart after one full frame is pulled from the buffer. There
 872          *   could be several smaller frames in the buffer and if so they will
 873          *   not trigger the XON until their total number reduces the buffer
 874          *   by 1500.
 875          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 876          */
 877         rx_buf_size = igb_get_rx_buffer_size(hw);
 878
 879         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
 880         hw->fc.low_water = hw->fc.high_water - 1500;
 881         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
 882         hw->fc.send_xon = 1;
 883
 884         /* Set Flow control, use the tunable location if sane */
 885         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
 886                 hw->fc.requested_mode = igb_fc_setting;
 887         else
 888                 hw->fc.requested_mode = e1000_fc_none;
 889
 890         /* Issue a global reset */
 891         igb_pf_reset_hw(hw);
 892         E1000_WRITE_REG(hw, E1000_WUC, 0);
 893
 894         diag = e1000_init_hw(hw);
 895         if (diag < 0)
 896                 return (diag);
 897
 898         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 899         e1000_get_phy_info(hw);
 900         e1000_check_for_link(hw);
 901
 902         return (0);
 903 }
 904
 905 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
 906 static void
 907 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 908 {
 909         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 910         struct e1000_hw_stats *stats =
 911                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 912         int pause_frames;
 913
 914         if(hw->phy.media_type == e1000_media_type_copper ||
 915             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 916                 stats->symerrs +=
 917                     E1000_READ_REG(hw,E1000_SYMERRS);
 918                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 919         }
 920
 921         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 922         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 923         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 924         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 925
 926         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 927         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 928         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 929         stats->dc += E1000_READ_REG(hw, E1000_DC);
 930         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 931         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 932         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 933         /*
 934         ** For watchdog management we need to know if we have been
 935         ** paused during the last interval, so capture that here.
 936         */
 937         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 938         stats->xoffrxc += pause_frames;
 939         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 940         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 941         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 942         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 943         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 944         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 945         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 946         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 947         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 948         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 949         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 950         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 951
 952         /* For the 64-bit byte counters the low dword must be read first. */
 953         /* Both registers clear on the read of the high dword */
 954
 955         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 956         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 957         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 958         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 959
 960         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 961         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 962         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 963         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 964         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 965
 966         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 967         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 968
 969         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 970         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 971         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 972         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 973         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 974         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 975         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 976         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 977         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 978         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 979
 980         /* Interrupt Counts */
 981
 982         stats->iac += E1000_READ_REG(hw, E1000_IAC);
 983         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 984         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 985         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 986         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 987         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 988         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 989         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 990         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 991
 992         /* Host to Card Statistics */
 993
 994         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
 995         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
 996         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
 997         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
 998         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
 999         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1000         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1001         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1002         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1003         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1004         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1005         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1006         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1007         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1008
1009         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1010         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1011         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1012         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1013         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1014         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1015
1016         if (rte_stats == NULL)
1017                 return;
1018
1019         /* Rx Errors */
1020         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
1021             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
1022
1023         /* Tx Errors */
1024         rte_stats->oerrors = stats->ecol + stats->latecol;
1025
1026         /* XON/XOFF pause frames */
1027         rte_stats->tx_pause_xon  = stats->xontxc;
1028         rte_stats->rx_pause_xon  = stats->xonrxc;
1029         rte_stats->tx_pause_xoff = stats->xofftxc;
1030         rte_stats->rx_pause_xoff = stats->xoffrxc;
1031
1032         rte_stats->ipackets = stats->gprc;
1033         rte_stats->opackets = stats->gptc;
1034         rte_stats->ibytes   = stats->gorc;
1035         rte_stats->obytes   = stats->gotc;
1036 }
1037
1038 static void
1039 eth_igb_stats_reset(struct rte_eth_dev *dev)
1040 {
1041         struct e1000_hw_stats *hw_stats =
1042                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1043
1044         /* HW registers are cleared on read */
1045         eth_igb_stats_get(dev, NULL);
1046
1047         /* Reset software totals */
1048         memset(hw_stats, 0, sizeof(*hw_stats));
1049 }
1050
1051 static void
1052 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1053 {
1054         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1055         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1056                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1057
1058         /* Good Rx packets, include VF loopback */
1059         UPDATE_VF_STAT(E1000_VFGPRC,
1060             hw_stats->last_gprc, hw_stats->gprc);
1061
1062         /* Good Rx octets, include VF loopback */
1063         UPDATE_VF_STAT(E1000_VFGORC,
1064             hw_stats->last_gorc, hw_stats->gorc);
1065
1066         /* Good Tx packets, include VF loopback */
1067         UPDATE_VF_STAT(E1000_VFGPTC,
1068             hw_stats->last_gptc, hw_stats->gptc);
1069
1070         /* Good Tx octets, include VF loopback */
1071         UPDATE_VF_STAT(E1000_VFGOTC,
1072             hw_stats->last_gotc, hw_stats->gotc);
1073
1074         /* Rx Multicst packets */
1075         UPDATE_VF_STAT(E1000_VFMPRC,
1076             hw_stats->last_mprc, hw_stats->mprc);
1077
1078         /* Good Rx loopback packets */
1079         UPDATE_VF_STAT(E1000_VFGPRLBC,
1080             hw_stats->last_gprlbc, hw_stats->gprlbc);
1081
1082         /* Good Rx loopback octets */
1083         UPDATE_VF_STAT(E1000_VFGORLBC,
1084             hw_stats->last_gorlbc, hw_stats->gorlbc);
1085
1086         /* Good Tx loopback packets */
1087         UPDATE_VF_STAT(E1000_VFGPTLBC,
1088             hw_stats->last_gptlbc, hw_stats->gptlbc);
1089
1090         /* Good Tx loopback octets */
1091         UPDATE_VF_STAT(E1000_VFGOTLBC,
1092             hw_stats->last_gotlbc, hw_stats->gotlbc);
1093
1094         if (rte_stats == NULL)
1095                 return;
1096
1097         memset(rte_stats, 0, sizeof(*rte_stats));
1098         rte_stats->ipackets = hw_stats->gprc;
1099         rte_stats->ibytes = hw_stats->gorc;
1100         rte_stats->opackets = hw_stats->gptc;
1101         rte_stats->obytes = hw_stats->gotc;
1102         rte_stats->imcasts = hw_stats->mprc;
1103         rte_stats->ilbpackets = hw_stats->gprlbc;
1104         rte_stats->ilbbytes = hw_stats->gorlbc;
1105         rte_stats->olbpackets = hw_stats->gptlbc;
1106         rte_stats->olbbytes = hw_stats->gotlbc;
1107
1108 }
1109
1110 static void
1111 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1112 {
1113         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1114                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1115
1116         /* Sync HW register to the last stats */
1117         eth_igbvf_stats_get(dev, NULL);
1118
1119         /* reset HW current stats*/
1120         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1121                offsetof(struct e1000_vf_stats, gprc));
1122
1123 }
1124
1125 static void
1126 eth_igb_infos_get(struct rte_eth_dev *dev,
1127                     struct rte_eth_dev_info *dev_info)
1128 {
1129         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1130
1131         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1132         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1133         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1134         dev_info->rx_offload_capa =
1135                 DEV_RX_OFFLOAD_VLAN_STRIP |
1136                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1137                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1138                 DEV_RX_OFFLOAD_TCP_CKSUM;
1139         dev_info->tx_offload_capa =
1140                 DEV_TX_OFFLOAD_VLAN_INSERT |
1141                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1142                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1143                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1144                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1145
1146         switch (hw->mac.type) {
1147         case e1000_82575:
1148                 dev_info->max_rx_queues = 4;
1149                 dev_info->max_tx_queues = 4;
1150                 dev_info->max_vmdq_pools = 0;
1151                 break;
1152
1153         case e1000_82576:
1154                 dev_info->max_rx_queues = 16;
1155                 dev_info->max_tx_queues = 16;
1156                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1157                 break;
1158
1159         case e1000_82580:
1160                 dev_info->max_rx_queues = 8;
1161                 dev_info->max_tx_queues = 8;
1162                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1163                 break;
1164
1165         case e1000_i350:
1166                 dev_info->max_rx_queues = 8;
1167                 dev_info->max_tx_queues = 8;
1168                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1169                 break;
1170
1171         case e1000_i354:
1172                 dev_info->max_rx_queues = 8;
1173                 dev_info->max_tx_queues = 8;
1174                 break;
1175
1176         case e1000_i210:
1177                 dev_info->max_rx_queues = 4;
1178                 dev_info->max_tx_queues = 4;
1179                 dev_info->max_vmdq_pools = 0;
1180                 break;
1181
1182         case e1000_vfadapt:
1183                 dev_info->max_rx_queues = 2;
1184                 dev_info->max_tx_queues = 2;
1185                 dev_info->max_vmdq_pools = 0;
1186                 break;
1187
1188         case e1000_vfadapt_i350:
1189                 dev_info->max_rx_queues = 1;
1190                 dev_info->max_tx_queues = 1;
1191                 dev_info->max_vmdq_pools = 0;
1192                 break;
1193
1194         default:
1195                 /* Should not happen */
1196                 dev_info->max_rx_queues = 0;
1197                 dev_info->max_tx_queues = 0;
1198                 dev_info->max_vmdq_pools = 0;
1199         }
1200 }
1201
1202 /* return 0 means link status changed, -1 means not changed */
1203 static int
1204 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1205 {
1206         struct e1000_hw *hw =
1207                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1208         struct rte_eth_link link, old;
1209         int link_check, count;
1210
1211         link_check = 0;
1212         hw->mac.get_link_status = 1;
1213
1214         /* possible wait-to-complete in up to 9 seconds */
1215         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1216                 /* Read the real link status */
1217                 switch (hw->phy.media_type) {
1218                 case e1000_media_type_copper:
1219                         /* Do the work to read phy */
1220                         e1000_check_for_link(hw);
1221                         link_check = !hw->mac.get_link_status;
1222                         break;
1223
1224                 case e1000_media_type_fiber:
1225                         e1000_check_for_link(hw);
1226                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1227                                       E1000_STATUS_LU);
1228                         break;
1229
1230                 case e1000_media_type_internal_serdes:
1231                         e1000_check_for_link(hw);
1232                         link_check = hw->mac.serdes_has_link;
1233                         break;
1234
1235                 /* VF device is type_unknown */
1236                 case e1000_media_type_unknown:
1237                         eth_igbvf_link_update(hw);
1238                         link_check = !hw->mac.get_link_status;
1239                         break;
1240
1241                 default:
1242                         break;
1243                 }
1244                 if (link_check || wait_to_complete == 0)
1245                         break;
1246                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1247         }
1248         memset(&link, 0, sizeof(link));
1249         rte_igb_dev_atomic_read_link_status(dev, &link);
1250         old = link;
1251
1252         /* Now we check if a transition has happened */
1253         if (link_check) {
1254                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1255                                           &link.link_duplex);
1256                 link.link_status = 1;
1257         } else if (!link_check) {
1258                 link.link_speed = 0;
1259                 link.link_duplex = 0;
1260                 link.link_status = 0;
1261         }
1262         rte_igb_dev_atomic_write_link_status(dev, &link);
1263
1264         /* not changed */
1265         if (old.link_status == link.link_status)
1266                 return -1;
1267
1268         /* changed */
1269         return 0;
1270 }
1271
1272 /*
1273  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1274  * For ASF and Pass Through versions of f/w this means
1275  * that the driver is loaded.
1276  */
1277 static void
1278 igb_hw_control_acquire(struct e1000_hw *hw)
1279 {
1280         uint32_t ctrl_ext;
1281
1282         /* Let firmware know the driver has taken over */
1283         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1284         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1285 }
1286
1287 /*
1288  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1289  * For ASF and Pass Through versions of f/w this means that the
1290  * driver is no longer loaded.
1291  */
1292 static void
1293 igb_hw_control_release(struct e1000_hw *hw)
1294 {
1295         uint32_t ctrl_ext;
1296
1297         /* Let firmware taken over control of h/w */
1298         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1299         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1300                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1301 }
1302
1303 /*
1304  * Bit of a misnomer, what this really means is
1305  * to enable OS management of the system... aka
1306  * to disable special hardware management features.
1307  */
1308 static void
1309 igb_init_manageability(struct e1000_hw *hw)
1310 {
1311         if (e1000_enable_mng_pass_thru(hw)) {
1312                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1313                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1314
1315                 /* disable hardware interception of ARP */
1316                 manc &= ~(E1000_MANC_ARP_EN);
1317
1318                 /* enable receiving management packets to the host */
1319                 manc |= E1000_MANC_EN_MNG2HOST;
1320                 manc2h |= 1 << 5;  /* Mng Port 623 */
1321                 manc2h |= 1 << 6;  /* Mng Port 664 */
1322                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1323                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1324         }
1325 }
1326
1327 static void
1328 igb_release_manageability(struct e1000_hw *hw)
1329 {
1330         if (e1000_enable_mng_pass_thru(hw)) {
1331                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1332
1333                 manc |= E1000_MANC_ARP_EN;
1334                 manc &= ~E1000_MANC_EN_MNG2HOST;
1335
1336                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1337         }
1338 }
1339
1340 static void
1341 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1342 {
1343         struct e1000_hw *hw =
1344                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1345         uint32_t rctl;
1346
1347         rctl = E1000_READ_REG(hw, E1000_RCTL);
1348         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1349         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1350 }
1351
1352 static void
1353 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1354 {
1355         struct e1000_hw *hw =
1356                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1357         uint32_t rctl;
1358
1359         rctl = E1000_READ_REG(hw, E1000_RCTL);
1360         rctl &= (~E1000_RCTL_UPE);
1361         if (dev->data->all_multicast == 1)
1362                 rctl |= E1000_RCTL_MPE;
1363         else
1364                 rctl &= (~E1000_RCTL_MPE);
1365         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1366 }
1367
1368 static void
1369 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1370 {
1371         struct e1000_hw *hw =
1372                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1373         uint32_t rctl;
1374
1375         rctl = E1000_READ_REG(hw, E1000_RCTL);
1376         rctl |= E1000_RCTL_MPE;
1377         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1378 }
1379
1380 static void
1381 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1382 {
1383         struct e1000_hw *hw =
1384                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1385         uint32_t rctl;
1386
1387         if (dev->data->promiscuous == 1)
1388                 return; /* must remain in all_multicast mode */
1389         rctl = E1000_READ_REG(hw, E1000_RCTL);
1390         rctl &= (~E1000_RCTL_MPE);
1391         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1392 }
1393
1394 static int
1395 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1396 {
1397         struct e1000_hw *hw =
1398                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1399         struct e1000_vfta * shadow_vfta =
1400                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1401         uint32_t vfta;
1402         uint32_t vid_idx;
1403         uint32_t vid_bit;
1404
1405         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1406                               E1000_VFTA_ENTRY_MASK);
1407         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1408         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1409         if (on)
1410                 vfta |= vid_bit;
1411         else
1412                 vfta &= ~vid_bit;
1413         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1414
1415         /* update local VFTA copy */
1416         shadow_vfta->vfta[vid_idx] = vfta;
1417
1418         return 0;
1419 }
1420
1421 static void
1422 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1423 {
1424         struct e1000_hw *hw =
1425                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426         uint32_t reg = ETHER_TYPE_VLAN ;
1427
1428         reg |= (tpid << 16);
1429         E1000_WRITE_REG(hw, E1000_VET, reg);
1430 }
1431
1432 static void
1433 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1434 {
1435         struct e1000_hw *hw =
1436                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1437         uint32_t reg;
1438
1439         /* Filter Table Disable */
1440         reg = E1000_READ_REG(hw, E1000_RCTL);
1441         reg &= ~E1000_RCTL_CFIEN;
1442         reg &= ~E1000_RCTL_VFE;
1443         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1444 }
1445
1446 static void
1447 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1448 {
1449         struct e1000_hw *hw =
1450                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1451         struct e1000_vfta * shadow_vfta =
1452                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1453         uint32_t reg;
1454         int i;
1455
1456         /* Filter Table Enable, CFI not used for packet acceptance */
1457         reg = E1000_READ_REG(hw, E1000_RCTL);
1458         reg &= ~E1000_RCTL_CFIEN;
1459         reg |= E1000_RCTL_VFE;
1460         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1461
1462         /* restore VFTA table */
1463         for (i = 0; i < IGB_VFTA_SIZE; i++)
1464                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1465 }
1466
1467 static void
1468 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1469 {
1470         struct e1000_hw *hw =
1471                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1472         uint32_t reg;
1473
1474         /* VLAN Mode Disable */
1475         reg = E1000_READ_REG(hw, E1000_CTRL);
1476         reg &= ~E1000_CTRL_VME;
1477         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1478 }
1479
1480 static void
1481 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1482 {
1483         struct e1000_hw *hw =
1484                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1485         uint32_t reg;
1486
1487         /* VLAN Mode Enable */
1488         reg = E1000_READ_REG(hw, E1000_CTRL);
1489         reg |= E1000_CTRL_VME;
1490         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1491 }
1492
1493 static void
1494 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1495 {
1496         struct e1000_hw *hw =
1497                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1498         uint32_t reg;
1499
1500         /* CTRL_EXT: Extended VLAN */
1501         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1502         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1503         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1504
1505         /* Update maximum packet length */
1506         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1507                 E1000_WRITE_REG(hw, E1000_RLPML,
1508                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1509                                                 VLAN_TAG_SIZE);
1510 }
1511
1512 static void
1513 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1514 {
1515         struct e1000_hw *hw =
1516                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517         uint32_t reg;
1518
1519         /* CTRL_EXT: Extended VLAN */
1520         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1521         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1522         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1523
1524         /* Update maximum packet length */
1525         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1526                 E1000_WRITE_REG(hw, E1000_RLPML,
1527                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1528                                                 2 * VLAN_TAG_SIZE);
1529 }
1530
1531 static void
1532 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1533 {
1534         if(mask & ETH_VLAN_STRIP_MASK){
1535                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1536                         igb_vlan_hw_strip_enable(dev);
1537                 else
1538                         igb_vlan_hw_strip_disable(dev);
1539         }
1540
1541         if(mask & ETH_VLAN_FILTER_MASK){
1542                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1543                         igb_vlan_hw_filter_enable(dev);
1544                 else
1545                         igb_vlan_hw_filter_disable(dev);
1546         }
1547
1548         if(mask & ETH_VLAN_EXTEND_MASK){
1549                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1550                         igb_vlan_hw_extend_enable(dev);
1551                 else
1552                         igb_vlan_hw_extend_disable(dev);
1553         }
1554 }
1555
1556
1557 /**
1558  * It enables the interrupt mask and then enable the interrupt.
1559  *
1560  * @param dev
1561  *  Pointer to struct rte_eth_dev.
1562  *
1563  * @return
1564  *  - On success, zero.
1565  *  - On failure, a negative value.
1566  */
1567 static int
1568 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1569 {
1570         struct e1000_interrupt *intr =
1571                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1572
1573         intr->mask |= E1000_ICR_LSC;
1574
1575         return 0;
1576 }
1577
1578 /*
1579  * It reads ICR and gets interrupt causes, check it and set a bit flag
1580  * to update link status.
1581  *
1582  * @param dev
1583  *  Pointer to struct rte_eth_dev.
1584  *
1585  * @return
1586  *  - On success, zero.
1587  *  - On failure, a negative value.
1588  */
1589 static int
1590 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1591 {
1592         uint32_t icr;
1593         struct e1000_hw *hw =
1594                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595         struct e1000_interrupt *intr =
1596                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1597
1598         igb_intr_disable(hw);
1599
1600         /* read-on-clear nic registers here */
1601         icr = E1000_READ_REG(hw, E1000_ICR);
1602
1603         intr->flags = 0;
1604         if (icr & E1000_ICR_LSC) {
1605                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1606         }
1607
1608         if (icr & E1000_ICR_VMMB)
1609                 intr->flags |= E1000_FLAG_MAILBOX;
1610
1611         return 0;
1612 }
1613
1614 /*
1615  * It executes link_update after knowing an interrupt is prsent.
1616  *
1617  * @param dev
1618  *  Pointer to struct rte_eth_dev.
1619  *
1620  * @return
1621  *  - On success, zero.
1622  *  - On failure, a negative value.
1623  */
1624 static int
1625 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1626 {
1627         struct e1000_hw *hw =
1628                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1629         struct e1000_interrupt *intr =
1630                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1631         uint32_t tctl, rctl;
1632         struct rte_eth_link link;
1633         int ret;
1634
1635         if (intr->flags & E1000_FLAG_MAILBOX) {
1636                 igb_pf_mbx_process(dev);
1637                 intr->flags &= ~E1000_FLAG_MAILBOX;
1638         }
1639
1640         igb_intr_enable(dev);
1641         rte_intr_enable(&(dev->pci_dev->intr_handle));
1642
1643         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1644                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1645
1646                 /* set get_link_status to check register later */
1647                 hw->mac.get_link_status = 1;
1648                 ret = eth_igb_link_update(dev, 0);
1649
1650                 /* check if link has changed */
1651                 if (ret < 0)
1652                         return 0;
1653
1654                 memset(&link, 0, sizeof(link));
1655                 rte_igb_dev_atomic_read_link_status(dev, &link);
1656                 if (link.link_status) {
1657                         PMD_INIT_LOG(INFO,
1658                                 " Port %d: Link Up - speed %u Mbps - %s\n",
1659                                 dev->data->port_id, (unsigned)link.link_speed,
1660                                 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1661                                         "full-duplex" : "half-duplex");
1662                 } else {
1663                         PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1664                                                 dev->data->port_id);
1665                 }
1666                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1667                                         dev->pci_dev->addr.domain,
1668                                         dev->pci_dev->addr.bus,
1669                                         dev->pci_dev->addr.devid,
1670                                         dev->pci_dev->addr.function);
1671                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1672                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1673                 if (link.link_status) {
1674                         /* enable Tx/Rx */
1675                         tctl |= E1000_TCTL_EN;
1676                         rctl |= E1000_RCTL_EN;
1677                 } else {
1678                         /* disable Tx/Rx */
1679                         tctl &= ~E1000_TCTL_EN;
1680                         rctl &= ~E1000_RCTL_EN;
1681                 }
1682                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1683                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1684                 E1000_WRITE_FLUSH(hw);
1685                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1686         }
1687
1688         return 0;
1689 }
1690
1691 /**
1692  * Interrupt handler which shall be registered at first.
1693  *
1694  * @param handle
1695  *  Pointer to interrupt handle.
1696  * @param param
1697  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1698  *
1699  * @return
1700  *  void
1701  */
1702 static void
1703 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1704                                                         void *param)
1705 {
1706         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1707
1708         eth_igb_interrupt_get_status(dev);
1709         eth_igb_interrupt_action(dev);
1710 }
1711
1712 static int
1713 eth_igb_led_on(struct rte_eth_dev *dev)
1714 {
1715         struct e1000_hw *hw;
1716
1717         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1718         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1719 }
1720
1721 static int
1722 eth_igb_led_off(struct rte_eth_dev *dev)
1723 {
1724         struct e1000_hw *hw;
1725
1726         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1727         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1728 }
1729
1730 static int
1731 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1732 {
1733         struct e1000_hw *hw;
1734         int err;
1735         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1736                 e1000_fc_none,
1737                 e1000_fc_rx_pause,
1738                 e1000_fc_tx_pause,
1739                 e1000_fc_full
1740         };
1741         uint32_t rx_buf_size;
1742         uint32_t max_high_water;
1743         uint32_t rctl;
1744
1745         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1746         rx_buf_size = igb_get_rx_buffer_size(hw);
1747         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1748
1749         /* At least reserve one Ethernet frame for watermark */
1750         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1751         if ((fc_conf->high_water > max_high_water) ||
1752                 (fc_conf->high_water < fc_conf->low_water)) {
1753                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1754                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1755                 return (-EINVAL);
1756         }
1757
1758         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1759         hw->fc.pause_time     = fc_conf->pause_time;
1760         hw->fc.high_water     = fc_conf->high_water;
1761         hw->fc.low_water      = fc_conf->low_water;
1762         hw->fc.send_xon       = fc_conf->send_xon;
1763
1764         err = e1000_setup_link_generic(hw);
1765         if (err == E1000_SUCCESS) {
1766
1767                 /* check if we want to forward MAC frames - driver doesn't have native
1768                  * capability to do that, so we'll write the registers ourselves */
1769
1770                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1771
1772                 /* set or clear MFLCN.PMCF bit depending on configuration */
1773                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1774                         rctl |= E1000_RCTL_PMCF;
1775                 else
1776                         rctl &= ~E1000_RCTL_PMCF;
1777
1778                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1779                 E1000_WRITE_FLUSH(hw);
1780
1781                 return 0;
1782         }
1783
1784         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1785         return (-EIO);
1786 }
1787
1788 #define E1000_RAH_POOLSEL_SHIFT      (18)
1789 static void
1790 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1791                 uint32_t index, __rte_unused uint32_t pool)
1792 {
1793         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1794         uint32_t rah;
1795
1796         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1797         rah = E1000_READ_REG(hw, E1000_RAH(index));
1798         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
1799         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
1800 }
1801
1802 static void
1803 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1804 {
1805         uint8_t addr[ETHER_ADDR_LEN];
1806         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1807
1808         memset(addr, 0, sizeof(addr));
1809
1810         e1000_rar_set(hw, addr, index);
1811 }
1812
1813 /*
1814  * Virtual Function operations
1815  */
1816 static void
1817 igbvf_intr_disable(struct e1000_hw *hw)
1818 {
1819         PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1820
1821         /* Clear interrupt mask to stop from interrupts being generated */
1822         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
1823
1824         E1000_WRITE_FLUSH(hw);
1825 }
1826
1827 static void
1828 igbvf_stop_adapter(struct rte_eth_dev *dev)
1829 {
1830         u32 reg_val;
1831         u16 i;
1832         struct rte_eth_dev_info dev_info;
1833         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1834
1835         memset(&dev_info, 0, sizeof(dev_info));
1836         eth_igb_infos_get(dev, &dev_info);
1837
1838         /* Clear interrupt mask to stop from interrupts being generated */
1839         igbvf_intr_disable(hw);
1840
1841         /* Clear any pending interrupts, flush previous writes */
1842         E1000_READ_REG(hw, E1000_EICR);
1843
1844         /* Disable the transmit unit.  Each queue must be disabled. */
1845         for (i = 0; i < dev_info.max_tx_queues; i++)
1846                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1847
1848         /* Disable the receive unit by stopping each queue */
1849         for (i = 0; i < dev_info.max_rx_queues; i++) {
1850                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1851                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1852                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1853                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1854                         ;
1855         }
1856
1857         /* flush all queues disables */
1858         E1000_WRITE_FLUSH(hw);
1859         msec_delay(2);
1860 }
1861
1862 static int eth_igbvf_link_update(struct e1000_hw *hw)
1863 {
1864         struct e1000_mbx_info *mbx = &hw->mbx;
1865         struct e1000_mac_info *mac = &hw->mac;
1866         int ret_val = E1000_SUCCESS;
1867
1868         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1869
1870         /*
1871          * We only want to run this if there has been a rst asserted.
1872          * in this case that could mean a link change, device reset,
1873          * or a virtual function reset
1874          */
1875
1876         /* If we were hit with a reset or timeout drop the link */
1877         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1878                 mac->get_link_status = TRUE;
1879
1880         if (!mac->get_link_status)
1881                 goto out;
1882
1883         /* if link status is down no point in checking to see if pf is up */
1884         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1885                 goto out;
1886
1887         /* if we passed all the tests above then the link is up and we no
1888          * longer need to check for link */
1889         mac->get_link_status = FALSE;
1890
1891 out:
1892         return ret_val;
1893 }
1894
1895
1896 static int
1897 igbvf_dev_configure(struct rte_eth_dev *dev)
1898 {
1899         struct rte_eth_conf* conf = &dev->data->dev_conf;
1900
1901         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1902                 dev->data->port_id);
1903
1904         /*
1905          * VF has no ability to enable/disable HW CRC
1906          * Keep the persistent behavior the same as Host PF
1907          */
1908 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1909         if (!conf->rxmode.hw_strip_crc) {
1910                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1911                 conf->rxmode.hw_strip_crc = 1;
1912         }
1913 #else
1914         if (conf->rxmode.hw_strip_crc) {
1915                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1916                 conf->rxmode.hw_strip_crc = 0;
1917         }
1918 #endif
1919
1920         return 0;
1921 }
1922
1923 static int
1924 igbvf_dev_start(struct rte_eth_dev *dev)
1925 {
1926         struct e1000_hw *hw =
1927                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928         int ret;
1929
1930         PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1931
1932         hw->mac.ops.reset_hw(hw);
1933
1934         /* Set all vfta */
1935         igbvf_set_vfta_all(dev,1);
1936
1937         eth_igbvf_tx_init(dev);
1938
1939         /* This can fail when allocating mbufs for descriptor rings */
1940         ret = eth_igbvf_rx_init(dev);
1941         if (ret) {
1942                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1943                 igb_dev_clear_queues(dev);
1944                 return ret;
1945         }
1946
1947         return 0;
1948 }
1949
1950 static void
1951 igbvf_dev_stop(struct rte_eth_dev *dev)
1952 {
1953         PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1954
1955         igbvf_stop_adapter(dev);
1956
1957         /*
1958           * Clear what we set, but we still keep shadow_vfta to
1959           * restore after device starts
1960           */
1961         igbvf_set_vfta_all(dev,0);
1962
1963         igb_dev_clear_queues(dev);
1964 }
1965
1966 static void
1967 igbvf_dev_close(struct rte_eth_dev *dev)
1968 {
1969         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1970
1971         PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1972
1973         e1000_reset_hw(hw);
1974
1975         igbvf_dev_stop(dev);
1976 }
1977
1978 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1979 {
1980         struct e1000_mbx_info *mbx = &hw->mbx;
1981         uint32_t msgbuf[2];
1982
1983         /* After set vlan, vlan strip will also be enabled in igb driver*/
1984         msgbuf[0] = E1000_VF_SET_VLAN;
1985         msgbuf[1] = vid;
1986         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1987         if (on)
1988                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1989
1990         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1991 }
1992
1993 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1994 {
1995         struct e1000_hw *hw =
1996                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1997         struct e1000_vfta * shadow_vfta =
1998                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1999         int i = 0, j = 0, vfta = 0, mask = 1;
2000
2001         for (i = 0; i < IGB_VFTA_SIZE; i++){
2002                 vfta = shadow_vfta->vfta[i];
2003                 if(vfta){
2004                         mask = 1;
2005                         for (j = 0; j < 32; j++){
2006                                 if(vfta & mask)
2007                                         igbvf_set_vfta(hw,
2008                                                 (uint16_t)((i<<5)+j), on);
2009                                 mask<<=1;
2010                         }
2011                 }
2012         }
2013
2014 }
2015
2016 static int
2017 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2018 {
2019         struct e1000_hw *hw =
2020                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2021         struct e1000_vfta * shadow_vfta =
2022                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2023         uint32_t vid_idx = 0;
2024         uint32_t vid_bit = 0;
2025         int ret = 0;
2026
2027         PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
2028
2029         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2030         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2031         if(ret){
2032                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2033                 return ret;
2034         }
2035         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2036         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2037
2038         /*Save what we set and retore it after device reset*/
2039         if (on)
2040                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2041         else
2042                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2043
2044         return 0;
2045 }
2046
2047 static int
2048 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2049                                 struct rte_eth_rss_reta *reta_conf)
2050 {
2051         uint8_t i,j,mask;
2052         uint32_t reta;
2053         struct e1000_hw *hw =
2054                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055
2056         /*
2057          * Update Redirection Table RETA[n],n=0...31,The redirection table has
2058          * 128-entries in 32 registers
2059          */
2060         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2061                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2062                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2063                 else
2064                         mask = (uint8_t)((reta_conf->mask_hi >>
2065                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2066                 if (mask != 0) {
2067                         reta = 0;
2068                         /* If all 4 entries were set,don't need read RETA register */
2069                         if (mask != 0xF)
2070                                 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2071
2072                         for (j = 0; j < 4; j++) {
2073                                 if (mask & (0x1 << j)) {
2074                                         if (mask != 0xF)
2075                                                 reta &= ~(0xFF << 8 * j);
2076                                         reta |= reta_conf->reta[i + j] << 8 * j;
2077                                 }
2078                         }
2079                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2080                 }
2081         }
2082
2083         return 0;
2084 }
2085
2086 static int
2087 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2088                                 struct rte_eth_rss_reta *reta_conf)
2089 {
2090         uint8_t i,j,mask;
2091         uint32_t reta;
2092         struct e1000_hw *hw =
2093                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2094
2095         /*
2096          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2097          * 128-entries in 32 registers
2098          */
2099         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2100                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2101                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2102                 else
2103                         mask = (uint8_t)((reta_conf->mask_hi >>
2104                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2105
2106                 if (mask != 0) {
2107                         reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2108                         for (j = 0; j < 4; j++) {
2109                                 if (mask & (0x1 << j))
2110                                         reta_conf->reta[i + j] =
2111                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2112                         }
2113                 }
2114         }
2115
2116         return 0;
2117 }