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34 #include <sys/queue.h>
45 #include <rte_interrupts.h>
46 #include <rte_byteorder.h>
47 #include <rte_common.h>
49 #include <rte_debug.h>
51 #include <rte_memory.h>
52 #include <rte_memcpy.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
55 #include <rte_tailq.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
73 #include "e1000_logs.h"
74 #include "e1000/e1000_api.h"
75 #include "e1000_ethdev.h"
77 static inline struct rte_mbuf *
78 rte_rxmbuf_alloc(struct rte_mempool *mp)
82 m = __rte_mbuf_raw_alloc(mp);
83 __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
87 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
88 (uint64_t) ((mb)->buf_physaddr + \
89 (uint64_t) ((char *)((mb)->pkt.data) - \
90 (char *)(mb)->buf_addr))
92 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
93 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
96 * Structure associated with each descriptor of the RX ring of a RX queue.
99 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
103 * Structure associated with each descriptor of the TX ring of a TX queue.
105 struct igb_tx_entry {
106 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
107 uint16_t next_id; /**< Index of next descriptor in ring. */
108 uint16_t last_id; /**< Index of last scattered descriptor. */
112 * Structure associated with each RX queue.
114 struct igb_rx_queue {
115 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
116 volatile union e1000_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
117 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
118 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
119 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
120 struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
121 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
122 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
123 uint16_t nb_rx_desc; /**< number of RX descriptors. */
124 uint16_t rx_tail; /**< current value of RDT register. */
125 uint16_t nb_rx_hold; /**< number of held free RX desc. */
126 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
127 uint16_t queue_id; /**< RX queue index. */
128 uint16_t reg_idx; /**< RX queue register index. */
129 uint8_t port_id; /**< Device port identifier. */
130 uint8_t pthresh; /**< Prefetch threshold register. */
131 uint8_t hthresh; /**< Host threshold register. */
132 uint8_t wthresh; /**< Write-back threshold register. */
133 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
134 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
138 * Hardware context number
140 enum igb_advctx_num {
141 IGB_CTX_0 = 0, /**< CTX0 */
142 IGB_CTX_1 = 1, /**< CTX1 */
143 IGB_CTX_NUM = 2, /**< CTX_NUM */
147 * Strucutre to check if new context need be built
149 struct igb_advctx_info {
150 uint16_t flags; /**< ol_flags related to context build. */
151 uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */
152 union rte_vlan_macip vlan_macip_lens; /**< vlan, mac & ip length. */
156 * Structure associated with each TX queue.
158 struct igb_tx_queue {
159 volatile union e1000_adv_tx_desc *tx_ring; /**< TX ring address */
160 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
161 struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
162 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
163 uint32_t txd_type; /**< Device-specific TXD type */
164 uint16_t nb_tx_desc; /**< number of TX descriptors. */
165 uint16_t tx_tail; /**< Current value of TDT register. */
167 /**< Index of first used TX descriptor. */
168 uint16_t queue_id; /**< TX queue index. */
169 uint16_t reg_idx; /**< TX queue register index. */
170 uint8_t port_id; /**< Device port identifier. */
171 uint8_t pthresh; /**< Prefetch threshold register. */
172 uint8_t hthresh; /**< Host threshold register. */
173 uint8_t wthresh; /**< Write-back threshold register. */
175 /**< Current used hardware descriptor. */
177 /**< Start context position for transmit queue. */
178 struct igb_advctx_info ctx_cache[IGB_CTX_NUM];
179 /**< Hardware context history.*/
183 #define RTE_PMD_USE_PREFETCH
186 #ifdef RTE_PMD_USE_PREFETCH
187 #define rte_igb_prefetch(p) rte_prefetch0(p)
189 #define rte_igb_prefetch(p) do {} while(0)
192 #ifdef RTE_PMD_PACKET_PREFETCH
193 #define rte_packet_prefetch(p) rte_prefetch1(p)
195 #define rte_packet_prefetch(p) do {} while(0)
199 * Macro for VMDq feature for 1 GbE NIC.
201 #define E1000_VMOLR_SIZE (8)
203 /*********************************************************************
207 **********************************************************************/
210 * Advanced context descriptor are almost same between igb/ixgbe
211 * This is a separate function, looking for optimization opportunity here
212 * Rework required to go with the pre-defined values.
216 igbe_set_xmit_ctx(struct igb_tx_queue* txq,
217 volatile struct e1000_adv_tx_context_desc *ctx_txd,
218 uint16_t ol_flags, uint32_t vlan_macip_lens)
220 uint32_t type_tucmd_mlhl;
221 uint32_t mss_l4len_idx;
222 uint32_t ctx_idx, ctx_curr;
225 ctx_curr = txq->ctx_curr;
226 ctx_idx = ctx_curr + txq->ctx_start;
231 if (ol_flags & PKT_TX_VLAN_PKT) {
232 cmp_mask |= TX_VLAN_CMP_MASK;
235 if (ol_flags & PKT_TX_IP_CKSUM) {
236 type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4;
237 cmp_mask |= TX_MAC_LEN_CMP_MASK;
240 /* Specify which HW CTX to upload. */
241 mss_l4len_idx = (ctx_idx << E1000_ADVTXD_IDX_SHIFT);
242 switch (ol_flags & PKT_TX_L4_MASK) {
243 case PKT_TX_UDP_CKSUM:
244 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP |
245 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
246 mss_l4len_idx |= sizeof(struct udp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
247 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
249 case PKT_TX_TCP_CKSUM:
250 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP |
251 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
252 mss_l4len_idx |= sizeof(struct tcp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
253 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
255 case PKT_TX_SCTP_CKSUM:
256 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP |
257 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
258 mss_l4len_idx |= sizeof(struct sctp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
259 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
262 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_RSV |
263 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
267 txq->ctx_cache[ctx_curr].flags = ol_flags;
268 txq->ctx_cache[ctx_curr].cmp_mask = cmp_mask;
269 txq->ctx_cache[ctx_curr].vlan_macip_lens.data =
270 vlan_macip_lens & cmp_mask;
272 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
273 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
274 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
275 ctx_txd->seqnum_seed = 0;
279 * Check which hardware context can be used. Use the existing match
280 * or create a new context descriptor.
282 static inline uint32_t
283 what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
284 uint32_t vlan_macip_lens)
286 /* If match with the current context */
287 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
288 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
289 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
290 return txq->ctx_curr;
293 /* If match with the second context */
295 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
296 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
297 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
298 return txq->ctx_curr;
301 /* Mismatch, use the previous context */
302 return (IGB_CTX_NUM);
305 static inline uint32_t
306 tx_desc_cksum_flags_to_olinfo(uint16_t ol_flags)
308 static const uint32_t l4_olinfo[2] = {0, E1000_ADVTXD_POPTS_TXSM};
309 static const uint32_t l3_olinfo[2] = {0, E1000_ADVTXD_POPTS_IXSM};
312 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
313 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
317 static inline uint32_t
318 tx_desc_vlan_flags_to_cmdtype(uint16_t ol_flags)
320 static uint32_t vlan_cmd[2] = {0, E1000_ADVTXD_DCMD_VLE};
321 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
325 eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
328 struct igb_tx_queue *txq;
329 struct igb_tx_entry *sw_ring;
330 struct igb_tx_entry *txe, *txn;
331 volatile union e1000_adv_tx_desc *txr;
332 volatile union e1000_adv_tx_desc *txd;
333 struct rte_mbuf *tx_pkt;
334 struct rte_mbuf *m_seg;
335 uint64_t buf_dma_addr;
336 uint32_t olinfo_status;
337 uint32_t cmd_type_len;
346 uint32_t new_ctx = 0;
348 uint32_t vlan_macip_lens;
351 sw_ring = txq->sw_ring;
353 tx_id = txq->tx_tail;
354 txe = &sw_ring[tx_id];
356 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
358 pkt_len = tx_pkt->pkt.pkt_len;
360 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
363 * The number of descriptors that must be allocated for a
364 * packet is the number of segments of that packet, plus 1
365 * Context Descriptor for the VLAN Tag Identifier, if any.
366 * Determine the last TX descriptor to allocate in the TX ring
367 * for the packet, starting from the current position (tx_id)
370 tx_last = (uint16_t) (tx_id + tx_pkt->pkt.nb_segs - 1);
372 ol_flags = tx_pkt->ol_flags;
373 vlan_macip_lens = tx_pkt->pkt.vlan_macip.data;
374 tx_ol_req = (uint16_t)(ol_flags & PKT_TX_OFFLOAD_MASK);
376 /* If a Context Descriptor need be built . */
378 ctx = what_advctx_update(txq, tx_ol_req,
380 /* Only allocate context descriptor if required*/
381 new_ctx = (ctx == IGB_CTX_NUM);
383 tx_last = (uint16_t) (tx_last + new_ctx);
385 if (tx_last >= txq->nb_tx_desc)
386 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
388 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
389 " tx_first=%u tx_last=%u\n",
390 (unsigned) txq->port_id,
391 (unsigned) txq->queue_id,
397 * Check if there are enough free descriptors in the TX ring
398 * to transmit the next packet.
399 * This operation is based on the two following rules:
401 * 1- Only check that the last needed TX descriptor can be
402 * allocated (by construction, if that descriptor is free,
403 * all intermediate ones are also free).
405 * For this purpose, the index of the last TX descriptor
406 * used for a packet (the "last descriptor" of a packet)
407 * is recorded in the TX entries (the last one included)
408 * that are associated with all TX descriptors allocated
411 * 2- Avoid to allocate the last free TX descriptor of the
412 * ring, in order to never set the TDT register with the
413 * same value stored in parallel by the NIC in the TDH
414 * register, which makes the TX engine of the NIC enter
415 * in a deadlock situation.
417 * By extension, avoid to allocate a free descriptor that
418 * belongs to the last set of free descriptors allocated
419 * to the same packet previously transmitted.
423 * The "last descriptor" of the previously sent packet, if any,
424 * which used the last descriptor to allocate.
426 tx_end = sw_ring[tx_last].last_id;
429 * The next descriptor following that "last descriptor" in the
432 tx_end = sw_ring[tx_end].next_id;
435 * The "last descriptor" associated with that next descriptor.
437 tx_end = sw_ring[tx_end].last_id;
440 * Check that this descriptor is free.
442 if (! (txr[tx_end].wb.status & E1000_TXD_STAT_DD)) {
449 * Set common flags of all TX Data Descriptors.
451 * The following bits must be set in all Data Descriptors:
452 * - E1000_ADVTXD_DTYP_DATA
453 * - E1000_ADVTXD_DCMD_DEXT
455 * The following bits must be set in the first Data Descriptor
456 * and are ignored in the other ones:
457 * - E1000_ADVTXD_DCMD_IFCS
458 * - E1000_ADVTXD_MAC_1588
459 * - E1000_ADVTXD_DCMD_VLE
461 * The following bits must only be set in the last Data
463 * - E1000_TXD_CMD_EOP
465 * The following bits can be set in any Data Descriptor, but
466 * are only set in the last Data Descriptor:
469 cmd_type_len = txq->txd_type |
470 E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
471 olinfo_status = (pkt_len << E1000_ADVTXD_PAYLEN_SHIFT);
472 #if defined(RTE_LIBRTE_IEEE1588)
473 if (ol_flags & PKT_TX_IEEE1588_TMST)
474 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
477 /* Setup TX Advanced context descriptor if required */
479 volatile struct e1000_adv_tx_context_desc *
482 ctx_txd = (volatile struct
483 e1000_adv_tx_context_desc *)
486 txn = &sw_ring[txe->next_id];
487 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
489 if (txe->mbuf != NULL) {
490 rte_pktmbuf_free_seg(txe->mbuf);
494 igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
497 txe->last_id = tx_last;
498 tx_id = txe->next_id;
502 /* Setup the TX Advanced Data Descriptor */
503 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
504 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
505 olinfo_status |= (ctx << E1000_ADVTXD_IDX_SHIFT);
510 txn = &sw_ring[txe->next_id];
513 if (txe->mbuf != NULL)
514 rte_pktmbuf_free_seg(txe->mbuf);
518 * Set up transmit descriptor.
520 slen = (uint16_t) m_seg->pkt.data_len;
521 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
522 txd->read.buffer_addr =
523 rte_cpu_to_le_64(buf_dma_addr);
524 txd->read.cmd_type_len =
525 rte_cpu_to_le_32(cmd_type_len | slen);
526 txd->read.olinfo_status =
527 rte_cpu_to_le_32(olinfo_status);
528 txe->last_id = tx_last;
529 tx_id = txe->next_id;
531 m_seg = m_seg->pkt.next;
532 } while (m_seg != NULL);
535 * The last packet data descriptor needs End Of Packet (EOP)
536 * and Report Status (RS).
538 txd->read.cmd_type_len |=
539 rte_cpu_to_le_32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS);
545 * Set the Transmit Descriptor Tail (TDT).
547 E1000_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
548 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
549 (unsigned) txq->port_id, (unsigned) txq->queue_id,
550 (unsigned) tx_id, (unsigned) nb_tx);
551 txq->tx_tail = tx_id;
556 /*********************************************************************
560 **********************************************************************/
561 static inline uint16_t
562 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
566 static uint16_t ip_pkt_types_map[16] = {
567 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
568 PKT_RX_IPV6_HDR, 0, 0, 0,
569 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
570 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
573 #if defined(RTE_LIBRTE_IEEE1588)
574 static uint32_t ip_pkt_etqf_map[8] = {
575 0, 0, 0, PKT_RX_IEEE1588_PTP,
579 pkt_flags = (uint16_t)((hl_tp_rs & E1000_RXDADV_PKTTYPE_ETQF) ?
580 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
581 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
583 pkt_flags = (uint16_t)((hl_tp_rs & E1000_RXDADV_PKTTYPE_ETQF) ? 0 :
584 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
586 return (uint16_t)(pkt_flags | (((hl_tp_rs & 0x0F) == 0) ?
587 0 : PKT_RX_RSS_HASH));
590 static inline uint16_t
591 rx_desc_status_to_pkt_flags(uint32_t rx_status)
595 /* Check if VLAN present */
596 pkt_flags = (uint16_t)((rx_status & E1000_RXD_STAT_VP) ?
597 PKT_RX_VLAN_PKT : 0);
599 #if defined(RTE_LIBRTE_IEEE1588)
600 if (rx_status & E1000_RXD_STAT_TMST)
601 pkt_flags = (uint16_t)(pkt_flags | PKT_RX_IEEE1588_TMST);
606 static inline uint16_t
607 rx_desc_error_to_pkt_flags(uint32_t rx_status)
610 * Bit 30: IPE, IPv4 checksum error
611 * Bit 29: L4I, L4I integrity error
614 static uint16_t error_to_pkt_flags_map[4] = {
615 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
616 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
618 return error_to_pkt_flags_map[(rx_status >>
619 E1000_RXD_ERR_CKSUM_BIT) & E1000_RXD_ERR_CKSUM_MSK];
623 eth_igb_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
626 struct igb_rx_queue *rxq;
627 volatile union e1000_adv_rx_desc *rx_ring;
628 volatile union e1000_adv_rx_desc *rxdp;
629 struct igb_rx_entry *sw_ring;
630 struct igb_rx_entry *rxe;
631 struct rte_mbuf *rxm;
632 struct rte_mbuf *nmb;
633 union e1000_adv_rx_desc rxd;
636 uint32_t hlen_type_rss;
646 rx_id = rxq->rx_tail;
647 rx_ring = rxq->rx_ring;
648 sw_ring = rxq->sw_ring;
649 while (nb_rx < nb_pkts) {
651 * The order of operations here is important as the DD status
652 * bit must not be read after any other descriptor fields.
653 * rx_ring and rxdp are pointing to volatile data so the order
654 * of accesses cannot be reordered by the compiler. If they were
655 * not volatile, they could be reordered which could lead to
656 * using invalid descriptor fields when read from rxd.
658 rxdp = &rx_ring[rx_id];
659 staterr = rxdp->wb.upper.status_error;
660 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
667 * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is
668 * likely to be invalid and to be dropped by the various
669 * validation checks performed by the network stack.
671 * Allocate a new mbuf to replenish the RX ring descriptor.
672 * If the allocation fails:
673 * - arrange for that RX descriptor to be the first one
674 * being parsed the next time the receive function is
675 * invoked [on the same queue].
677 * - Stop parsing the RX ring and return immediately.
679 * This policy do not drop the packet received in the RX
680 * descriptor for which the allocation of a new mbuf failed.
681 * Thus, it allows that packet to be later retrieved if
682 * mbuf have been freed in the mean time.
683 * As a side effect, holding RX descriptors instead of
684 * systematically giving them back to the NIC may lead to
685 * RX ring exhaustion situations.
686 * However, the NIC can gracefully prevent such situations
687 * to happen by sending specific "back-pressure" flow control
688 * frames to its peer(s).
690 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
691 "staterr=0x%x pkt_len=%u\n",
692 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
693 (unsigned) rx_id, (unsigned) staterr,
694 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
696 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
698 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
699 "queue_id=%u\n", (unsigned) rxq->port_id,
700 (unsigned) rxq->queue_id);
701 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
706 rxe = &sw_ring[rx_id];
708 if (rx_id == rxq->nb_rx_desc)
711 /* Prefetch next mbuf while processing current one. */
712 rte_igb_prefetch(sw_ring[rx_id].mbuf);
715 * When next RX descriptor is on a cache-line boundary,
716 * prefetch the next 4 RX descriptors and the next 8 pointers
719 if ((rx_id & 0x3) == 0) {
720 rte_igb_prefetch(&rx_ring[rx_id]);
721 rte_igb_prefetch(&sw_ring[rx_id]);
727 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
728 rxdp->read.hdr_addr = dma_addr;
729 rxdp->read.pkt_addr = dma_addr;
732 * Initialize the returned mbuf.
733 * 1) setup generic mbuf fields:
734 * - number of segments,
737 * - RX port identifier.
738 * 2) integrate hardware offload data, if any:
740 * - IP checksum flag,
741 * - VLAN TCI, if any,
744 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
746 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
747 rte_packet_prefetch(rxm->pkt.data);
748 rxm->pkt.nb_segs = 1;
749 rxm->pkt.next = NULL;
750 rxm->pkt.pkt_len = pkt_len;
751 rxm->pkt.data_len = pkt_len;
752 rxm->pkt.in_port = rxq->port_id;
754 rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
755 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
756 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
757 rxm->pkt.vlan_macip.f.vlan_tci =
758 rte_le_to_cpu_16(rxd.wb.upper.vlan);
760 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
761 pkt_flags = (uint16_t)(pkt_flags |
762 rx_desc_status_to_pkt_flags(staterr));
763 pkt_flags = (uint16_t)(pkt_flags |
764 rx_desc_error_to_pkt_flags(staterr));
765 rxm->ol_flags = pkt_flags;
768 * Store the mbuf address into the next entry of the array
769 * of returned packets.
771 rx_pkts[nb_rx++] = rxm;
773 rxq->rx_tail = rx_id;
776 * If the number of free RX descriptors is greater than the RX free
777 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
779 * Update the RDT with the value of the last processed RX descriptor
780 * minus 1, to guarantee that the RDT register is never equal to the
781 * RDH register, which creates a "full" ring situtation from the
782 * hardware point of view...
784 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
785 if (nb_hold > rxq->rx_free_thresh) {
786 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
787 "nb_hold=%u nb_rx=%u\n",
788 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
789 (unsigned) rx_id, (unsigned) nb_hold,
791 rx_id = (uint16_t) ((rx_id == 0) ?
792 (rxq->nb_rx_desc - 1) : (rx_id - 1));
793 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
796 rxq->nb_rx_hold = nb_hold;
801 eth_igb_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
804 struct igb_rx_queue *rxq;
805 volatile union e1000_adv_rx_desc *rx_ring;
806 volatile union e1000_adv_rx_desc *rxdp;
807 struct igb_rx_entry *sw_ring;
808 struct igb_rx_entry *rxe;
809 struct rte_mbuf *first_seg;
810 struct rte_mbuf *last_seg;
811 struct rte_mbuf *rxm;
812 struct rte_mbuf *nmb;
813 union e1000_adv_rx_desc rxd;
814 uint64_t dma; /* Physical address of mbuf data buffer */
816 uint32_t hlen_type_rss;
826 rx_id = rxq->rx_tail;
827 rx_ring = rxq->rx_ring;
828 sw_ring = rxq->sw_ring;
831 * Retrieve RX context of current packet, if any.
833 first_seg = rxq->pkt_first_seg;
834 last_seg = rxq->pkt_last_seg;
836 while (nb_rx < nb_pkts) {
839 * The order of operations here is important as the DD status
840 * bit must not be read after any other descriptor fields.
841 * rx_ring and rxdp are pointing to volatile data so the order
842 * of accesses cannot be reordered by the compiler. If they were
843 * not volatile, they could be reordered which could lead to
844 * using invalid descriptor fields when read from rxd.
846 rxdp = &rx_ring[rx_id];
847 staterr = rxdp->wb.upper.status_error;
848 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
855 * Allocate a new mbuf to replenish the RX ring descriptor.
856 * If the allocation fails:
857 * - arrange for that RX descriptor to be the first one
858 * being parsed the next time the receive function is
859 * invoked [on the same queue].
861 * - Stop parsing the RX ring and return immediately.
863 * This policy does not drop the packet received in the RX
864 * descriptor for which the allocation of a new mbuf failed.
865 * Thus, it allows that packet to be later retrieved if
866 * mbuf have been freed in the mean time.
867 * As a side effect, holding RX descriptors instead of
868 * systematically giving them back to the NIC may lead to
869 * RX ring exhaustion situations.
870 * However, the NIC can gracefully prevent such situations
871 * to happen by sending specific "back-pressure" flow control
872 * frames to its peer(s).
874 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
875 "staterr=0x%x data_len=%u\n",
876 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
877 (unsigned) rx_id, (unsigned) staterr,
878 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
880 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
882 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
883 "queue_id=%u\n", (unsigned) rxq->port_id,
884 (unsigned) rxq->queue_id);
885 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
890 rxe = &sw_ring[rx_id];
892 if (rx_id == rxq->nb_rx_desc)
895 /* Prefetch next mbuf while processing current one. */
896 rte_igb_prefetch(sw_ring[rx_id].mbuf);
899 * When next RX descriptor is on a cache-line boundary,
900 * prefetch the next 4 RX descriptors and the next 8 pointers
903 if ((rx_id & 0x3) == 0) {
904 rte_igb_prefetch(&rx_ring[rx_id]);
905 rte_igb_prefetch(&sw_ring[rx_id]);
909 * Update RX descriptor with the physical address of the new
910 * data buffer of the new allocated mbuf.
914 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
915 rxdp->read.pkt_addr = dma;
916 rxdp->read.hdr_addr = dma;
919 * Set data length & data buffer address of mbuf.
921 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
922 rxm->pkt.data_len = data_len;
923 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
926 * If this is the first buffer of the received packet,
927 * set the pointer to the first mbuf of the packet and
928 * initialize its context.
929 * Otherwise, update the total length and the number of segments
930 * of the current scattered packet, and update the pointer to
931 * the last mbuf of the current packet.
933 if (first_seg == NULL) {
935 first_seg->pkt.pkt_len = data_len;
936 first_seg->pkt.nb_segs = 1;
938 first_seg->pkt.pkt_len += data_len;
939 first_seg->pkt.nb_segs++;
940 last_seg->pkt.next = rxm;
944 * If this is not the last buffer of the received packet,
945 * update the pointer to the last mbuf of the current scattered
946 * packet and continue to parse the RX ring.
948 if (! (staterr & E1000_RXD_STAT_EOP)) {
954 * This is the last buffer of the received packet.
955 * If the CRC is not stripped by the hardware:
956 * - Subtract the CRC length from the total packet length.
957 * - If the last buffer only contains the whole CRC or a part
958 * of it, free the mbuf associated to the last buffer.
959 * If part of the CRC is also contained in the previous
960 * mbuf, subtract the length of that CRC part from the
961 * data length of the previous mbuf.
963 rxm->pkt.next = NULL;
964 if (unlikely(rxq->crc_len > 0)) {
965 first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
966 if (data_len <= ETHER_CRC_LEN) {
967 rte_pktmbuf_free_seg(rxm);
968 first_seg->pkt.nb_segs--;
969 last_seg->pkt.data_len = (uint16_t)
970 (last_seg->pkt.data_len -
971 (ETHER_CRC_LEN - data_len));
972 last_seg->pkt.next = NULL;
975 (uint16_t) (data_len - ETHER_CRC_LEN);
979 * Initialize the first mbuf of the returned packet:
980 * - RX port identifier,
981 * - hardware offload data, if any:
983 * - IP checksum flag,
984 * - VLAN TCI, if any,
987 first_seg->pkt.in_port = rxq->port_id;
988 first_seg->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
991 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
992 * set in the pkt_flags field.
994 first_seg->pkt.vlan_macip.f.vlan_tci =
995 rte_le_to_cpu_16(rxd.wb.upper.vlan);
996 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
997 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
998 pkt_flags = (uint16_t)(pkt_flags |
999 rx_desc_status_to_pkt_flags(staterr));
1000 pkt_flags = (uint16_t)(pkt_flags |
1001 rx_desc_error_to_pkt_flags(staterr));
1002 first_seg->ol_flags = pkt_flags;
1004 /* Prefetch data of first segment, if configured to do so. */
1005 rte_packet_prefetch(first_seg->pkt.data);
1008 * Store the mbuf address into the next entry of the array
1009 * of returned packets.
1011 rx_pkts[nb_rx++] = first_seg;
1014 * Setup receipt context for a new packet.
1020 * Record index of the next RX descriptor to probe.
1022 rxq->rx_tail = rx_id;
1025 * Save receive context.
1027 rxq->pkt_first_seg = first_seg;
1028 rxq->pkt_last_seg = last_seg;
1031 * If the number of free RX descriptors is greater than the RX free
1032 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1034 * Update the RDT with the value of the last processed RX descriptor
1035 * minus 1, to guarantee that the RDT register is never equal to the
1036 * RDH register, which creates a "full" ring situtation from the
1037 * hardware point of view...
1039 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1040 if (nb_hold > rxq->rx_free_thresh) {
1041 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1042 "nb_hold=%u nb_rx=%u\n",
1043 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1044 (unsigned) rx_id, (unsigned) nb_hold,
1046 rx_id = (uint16_t) ((rx_id == 0) ?
1047 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1048 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1051 rxq->nb_rx_hold = nb_hold;
1056 * Rings setup and release.
1058 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1059 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
1060 * This will also optimize cache line size effect.
1061 * H/W supports up to cache line size 128.
1063 #define IGB_ALIGN 128
1066 * Maximum number of Ring Descriptors.
1068 * Since RDLEN/TDLEN should be multiple of 128bytes, the number of ring
1069 * desscriptors should meet the following condition:
1070 * (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0
1072 #define IGB_MIN_RING_DESC 32
1073 #define IGB_MAX_RING_DESC 4096
1075 static const struct rte_memzone *
1076 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1077 uint16_t queue_id, uint32_t ring_size, int socket_id)
1079 char z_name[RTE_MEMZONE_NAMESIZE];
1080 const struct rte_memzone *mz;
1082 rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1083 dev->driver->pci_drv.name, ring_name,
1084 dev->data->port_id, queue_id);
1085 mz = rte_memzone_lookup(z_name);
1089 return rte_memzone_reserve_aligned(z_name, ring_size,
1090 socket_id, 0, IGB_ALIGN);
1094 igb_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1098 if (txq->sw_ring != NULL) {
1099 for (i = 0; i < txq->nb_tx_desc; i++) {
1100 if (txq->sw_ring[i].mbuf != NULL) {
1101 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1102 txq->sw_ring[i].mbuf = NULL;
1109 igb_tx_queue_release(struct igb_tx_queue *txq)
1112 igb_tx_queue_release_mbufs(txq);
1113 rte_free(txq->sw_ring);
1119 eth_igb_tx_queue_release(void *txq)
1121 igb_tx_queue_release(txq);
1125 igb_reset_tx_queue_stat(struct igb_tx_queue *txq)
1130 memset((void*)&txq->ctx_cache, 0,
1131 IGB_CTX_NUM * sizeof(struct igb_advctx_info));
1135 igb_reset_tx_queue(struct igb_tx_queue *txq, struct rte_eth_dev *dev)
1137 static const union e1000_adv_tx_desc zeroed_desc = { .read = {
1139 struct igb_tx_entry *txe = txq->sw_ring;
1141 struct e1000_hw *hw;
1143 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1144 /* Zero out HW ring memory */
1145 for (i = 0; i < txq->nb_tx_desc; i++) {
1146 txq->tx_ring[i] = zeroed_desc;
1149 /* Initialize ring entries */
1150 prev = (uint16_t)(txq->nb_tx_desc - 1);
1151 for (i = 0; i < txq->nb_tx_desc; i++) {
1152 volatile union e1000_adv_tx_desc *txd = &(txq->tx_ring[i]);
1154 txd->wb.status = E1000_TXD_STAT_DD;
1157 txe[prev].next_id = i;
1161 txq->txd_type = E1000_ADVTXD_DTYP_DATA;
1162 /* 82575 specific, each tx queue will use 2 hw contexts */
1163 if (hw->mac.type == e1000_82575)
1164 txq->ctx_start = txq->queue_id * IGB_CTX_NUM;
1166 igb_reset_tx_queue_stat(txq);
1170 eth_igb_tx_queue_setup(struct rte_eth_dev *dev,
1173 unsigned int socket_id,
1174 const struct rte_eth_txconf *tx_conf)
1176 const struct rte_memzone *tz;
1177 struct igb_tx_queue *txq;
1178 struct e1000_hw *hw;
1181 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1184 * Validate number of transmit descriptors.
1185 * It must not exceed hardware maximum, and must be multiple
1188 if (((nb_desc * sizeof(union e1000_adv_tx_desc)) % IGB_ALIGN) != 0 ||
1189 (nb_desc > IGB_MAX_RING_DESC) || (nb_desc < IGB_MIN_RING_DESC)) {
1194 * The tx_free_thresh and tx_rs_thresh values are not used in the 1G
1197 if (tx_conf->tx_free_thresh != 0)
1198 RTE_LOG(WARNING, PMD,
1199 "The tx_free_thresh parameter is not "
1200 "used for the 1G driver.\n");
1201 if (tx_conf->tx_rs_thresh != 0)
1202 RTE_LOG(WARNING, PMD,
1203 "The tx_rs_thresh parameter is not "
1204 "used for the 1G driver.\n");
1205 if (tx_conf->tx_thresh.wthresh == 0)
1206 RTE_LOG(WARNING, PMD,
1207 "To improve 1G driver performance, consider setting "
1208 "the TX WTHRESH value to 4, 8, or 16.\n");
1210 /* Free memory prior to re-allocation if needed */
1211 if (dev->data->tx_queues[queue_idx] != NULL)
1212 igb_tx_queue_release(dev->data->tx_queues[queue_idx]);
1214 /* First allocate the tx queue data structure */
1215 txq = rte_zmalloc("ethdev TX queue", sizeof(struct igb_tx_queue),
1221 * Allocate TX ring hardware descriptors. A memzone large enough to
1222 * handle the maximum ring size is allocated in order to allow for
1223 * resizing in later calls to the queue setup function.
1225 size = sizeof(union e1000_adv_tx_desc) * IGB_MAX_RING_DESC;
1226 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1229 igb_tx_queue_release(txq);
1233 txq->nb_tx_desc = nb_desc;
1234 txq->pthresh = tx_conf->tx_thresh.pthresh;
1235 txq->hthresh = tx_conf->tx_thresh.hthresh;
1236 txq->wthresh = tx_conf->tx_thresh.wthresh;
1237 txq->queue_id = queue_idx;
1238 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1239 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1240 txq->port_id = dev->data->port_id;
1242 txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(txq->reg_idx));
1243 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1244 txq->tx_ring = (union e1000_adv_tx_desc *) tz->addr;
1246 /* Allocate software ring */
1247 txq->sw_ring = rte_zmalloc("txq->sw_ring",
1248 sizeof(struct igb_tx_entry) * nb_desc,
1250 if (txq->sw_ring == NULL) {
1251 igb_tx_queue_release(txq);
1254 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1255 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1257 igb_reset_tx_queue(txq, dev);
1258 dev->tx_pkt_burst = eth_igb_xmit_pkts;
1259 dev->data->tx_queues[queue_idx] = txq;
1265 igb_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1269 if (rxq->sw_ring != NULL) {
1270 for (i = 0; i < rxq->nb_rx_desc; i++) {
1271 if (rxq->sw_ring[i].mbuf != NULL) {
1272 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1273 rxq->sw_ring[i].mbuf = NULL;
1280 igb_rx_queue_release(struct igb_rx_queue *rxq)
1283 igb_rx_queue_release_mbufs(rxq);
1284 rte_free(rxq->sw_ring);
1290 eth_igb_rx_queue_release(void *rxq)
1292 igb_rx_queue_release(rxq);
1296 igb_reset_rx_queue(struct igb_rx_queue *rxq)
1298 static const union e1000_adv_rx_desc zeroed_desc = { .read = {
1302 /* Zero out HW ring memory */
1303 for (i = 0; i < rxq->nb_rx_desc; i++) {
1304 rxq->rx_ring[i] = zeroed_desc;
1308 rxq->pkt_first_seg = NULL;
1309 rxq->pkt_last_seg = NULL;
1313 eth_igb_rx_queue_setup(struct rte_eth_dev *dev,
1316 unsigned int socket_id,
1317 const struct rte_eth_rxconf *rx_conf,
1318 struct rte_mempool *mp)
1320 const struct rte_memzone *rz;
1321 struct igb_rx_queue *rxq;
1322 struct e1000_hw *hw;
1325 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1328 * Validate number of receive descriptors.
1329 * It must not exceed hardware maximum, and must be multiple
1332 if (((nb_desc * sizeof(union e1000_adv_rx_desc)) % IGB_ALIGN) != 0 ||
1333 (nb_desc > IGB_MAX_RING_DESC) || (nb_desc < IGB_MIN_RING_DESC)) {
1337 /* Free memory prior to re-allocation if needed */
1338 if (dev->data->rx_queues[queue_idx] != NULL) {
1339 igb_rx_queue_release(dev->data->rx_queues[queue_idx]);
1340 dev->data->rx_queues[queue_idx] = NULL;
1343 /* First allocate the RX queue data structure. */
1344 rxq = rte_zmalloc("ethdev RX queue", sizeof(struct igb_rx_queue),
1349 rxq->nb_rx_desc = nb_desc;
1350 rxq->pthresh = rx_conf->rx_thresh.pthresh;
1351 rxq->hthresh = rx_conf->rx_thresh.hthresh;
1352 rxq->wthresh = rx_conf->rx_thresh.wthresh;
1353 rxq->drop_en = rx_conf->rx_drop_en;
1354 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1355 rxq->queue_id = queue_idx;
1356 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1357 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1358 rxq->port_id = dev->data->port_id;
1359 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
1363 * Allocate RX ring hardware descriptors. A memzone large enough to
1364 * handle the maximum ring size is allocated in order to allow for
1365 * resizing in later calls to the queue setup function.
1367 size = sizeof(union e1000_adv_rx_desc) * IGB_MAX_RING_DESC;
1368 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx, size, socket_id);
1370 igb_rx_queue_release(rxq);
1373 rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(rxq->reg_idx));
1374 rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(rxq->reg_idx));
1375 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
1376 rxq->rx_ring = (union e1000_adv_rx_desc *) rz->addr;
1378 /* Allocate software ring. */
1379 rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1380 sizeof(struct igb_rx_entry) * nb_desc,
1382 if (rxq->sw_ring == NULL) {
1383 igb_rx_queue_release(rxq);
1386 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1387 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1389 dev->data->rx_queues[queue_idx] = rxq;
1390 igb_reset_rx_queue(rxq);
1396 eth_igb_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1398 #define IGB_RXQ_SCAN_INTERVAL 4
1399 volatile union e1000_adv_rx_desc *rxdp;
1400 struct igb_rx_queue *rxq;
1403 if (rx_queue_id >= dev->data->nb_rx_queues) {
1404 PMD_RX_LOG(ERR, "Invalid RX queue id=%d\n", rx_queue_id);
1408 rxq = dev->data->rx_queues[rx_queue_id];
1409 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1411 while ((desc < rxq->nb_rx_desc) &&
1412 (rxdp->wb.upper.status_error & E1000_RXD_STAT_DD)) {
1413 desc += IGB_RXQ_SCAN_INTERVAL;
1414 rxdp += IGB_RXQ_SCAN_INTERVAL;
1415 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1416 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1417 desc - rxq->nb_rx_desc]);
1424 eth_igb_rx_descriptor_done(void *rx_queue, uint16_t offset)
1426 volatile union e1000_adv_rx_desc *rxdp;
1427 struct igb_rx_queue *rxq = rx_queue;
1430 if (unlikely(offset >= rxq->nb_rx_desc))
1432 desc = rxq->rx_tail + offset;
1433 if (desc >= rxq->nb_rx_desc)
1434 desc -= rxq->nb_rx_desc;
1436 rxdp = &rxq->rx_ring[desc];
1437 return !!(rxdp->wb.upper.status_error & E1000_RXD_STAT_DD);
1441 igb_dev_clear_queues(struct rte_eth_dev *dev)
1444 struct igb_tx_queue *txq;
1445 struct igb_rx_queue *rxq;
1447 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1448 txq = dev->data->tx_queues[i];
1450 igb_tx_queue_release_mbufs(txq);
1451 igb_reset_tx_queue(txq, dev);
1455 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1456 rxq = dev->data->rx_queues[i];
1458 igb_rx_queue_release_mbufs(rxq);
1459 igb_reset_rx_queue(rxq);
1465 * Receive Side Scaling (RSS).
1466 * See section 7.1.1.7 in the following document:
1467 * "Intel 82576 GbE Controller Datasheet" - Revision 2.45 October 2009
1470 * The source and destination IP addresses of the IP header and the source and
1471 * destination ports of TCP/UDP headers, if any, of received packets are hashed
1472 * against a configurable random key to compute a 32-bit RSS hash result.
1473 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
1474 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
1475 * RSS output index which is used as the RX queue index where to store the
1477 * The following output is supplied in the RX write-back descriptor:
1478 * - 32-bit result of the Microsoft RSS hash function,
1479 * - 4-bit RSS type field.
1483 * RSS random key supplied in section 7.1.1.7.3 of the Intel 82576 datasheet.
1484 * Used as the default key.
1486 static uint8_t rss_intel_key[40] = {
1487 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
1488 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
1489 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
1490 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
1491 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
1495 igb_rss_disable(struct rte_eth_dev *dev)
1497 struct e1000_hw *hw;
1500 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1501 mrqc = E1000_READ_REG(hw, E1000_MRQC);
1502 mrqc &= ~E1000_MRQC_ENABLE_MASK;
1503 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1507 igb_rss_configure(struct rte_eth_dev *dev)
1509 struct e1000_hw *hw;
1517 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1519 rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
1520 if (rss_hf == 0) /* Disable RSS. */ {
1521 igb_rss_disable(dev);
1524 hash_key = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
1525 if (hash_key == NULL)
1526 hash_key = rss_intel_key; /* Default hash key. */
1528 /* Fill in RSS hash key. */
1529 for (i = 0; i < 10; i++) {
1530 rss_key = hash_key[(i * 4)];
1531 rss_key |= hash_key[(i * 4) + 1] << 8;
1532 rss_key |= hash_key[(i * 4) + 2] << 16;
1533 rss_key |= hash_key[(i * 4) + 3] << 24;
1534 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key);
1537 /* Fill in redirection table. */
1538 shift = (hw->mac.type == e1000_82575) ? 6 : 0;
1539 for (i = 0; i < 128; i++) {
1546 q_idx = (uint8_t) ((dev->data->nb_rx_queues > 1) ?
1547 i % dev->data->nb_rx_queues : 0);
1548 reta.bytes[i & 3] = (uint8_t) (q_idx << shift);
1550 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta.dword);
1553 /* Set configured hashing functions in MRQC register. */
1554 mrqc = E1000_MRQC_ENABLE_RSS_4Q; /* RSS enabled. */
1555 if (rss_hf & ETH_RSS_IPV4)
1556 mrqc |= E1000_MRQC_RSS_FIELD_IPV4;
1557 if (rss_hf & ETH_RSS_IPV4_TCP)
1558 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_TCP;
1559 if (rss_hf & ETH_RSS_IPV6)
1560 mrqc |= E1000_MRQC_RSS_FIELD_IPV6;
1561 if (rss_hf & ETH_RSS_IPV6_EX)
1562 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_EX;
1563 if (rss_hf & ETH_RSS_IPV6_TCP)
1564 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP;
1565 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
1566 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
1567 if (rss_hf & ETH_RSS_IPV4_UDP)
1568 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
1569 if (rss_hf & ETH_RSS_IPV6_UDP)
1570 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
1571 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
1572 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP_EX;
1573 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1577 * Check if the mac type support VMDq or not.
1578 * Return 1 if it supports, otherwise, return 0.
1581 igb_is_vmdq_supported(const struct rte_eth_dev *dev)
1583 const struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585 switch (hw->mac.type) {
1606 PMD_INIT_LOG(ERR, "Cannot support VMDq feature\n");
1612 igb_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
1614 struct rte_eth_vmdq_rx_conf *cfg;
1615 struct e1000_hw *hw;
1616 uint32_t mrqc, vt_ctl, vmolr, rctl;
1619 PMD_INIT_LOG(DEBUG, ">>");
1620 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1621 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1623 /* Check if mac type can support VMDq, return value of 0 means NOT support */
1624 if (igb_is_vmdq_supported(dev) == 0)
1627 igb_rss_disable(dev);
1629 /* RCTL: eanble VLAN filter */
1630 rctl = E1000_READ_REG(hw, E1000_RCTL);
1631 rctl |= E1000_RCTL_VFE;
1632 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1634 /* MRQC: enable vmdq */
1635 mrqc = E1000_READ_REG(hw, E1000_MRQC);
1636 mrqc |= E1000_MRQC_ENABLE_VMDQ;
1637 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1639 /* VTCTL: pool selection according to VLAN tag */
1640 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
1641 if (cfg->enable_default_pool)
1642 vt_ctl |= (cfg->default_pool << E1000_VT_CTL_DEFAULT_POOL_SHIFT);
1643 vt_ctl |= E1000_VT_CTL_IGNORE_MAC;
1644 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
1647 * VMOLR: set STRVLAN as 1 if IGMAC in VTCTL is set as 1
1648 * Both 82576 and 82580 support it
1650 if (hw->mac.type != e1000_i350) {
1651 for (i = 0; i < E1000_VMOLR_SIZE; i++) {
1652 vmolr = E1000_READ_REG(hw, E1000_VMOLR(i));
1653 vmolr |= E1000_VMOLR_STRVLAN;
1654 E1000_WRITE_REG(hw, E1000_VMOLR(i), vmolr);
1658 /* VFTA - enable all vlan filters */
1659 for (i = 0; i < IGB_VFTA_SIZE; i++)
1660 E1000_WRITE_REG(hw, (E1000_VFTA+(i*4)), UINT32_MAX);
1662 /* VFRE: 8 pools enabling for rx, both 82576 and i350 support it */
1663 if (hw->mac.type != e1000_82580)
1664 E1000_WRITE_REG(hw, E1000_VFRE, E1000_MBVFICR_VFREQ_MASK);
1667 * RAH/RAL - allow pools to read specific mac addresses
1668 * In this case, all pools should be able to read from mac addr 0
1670 E1000_WRITE_REG(hw, E1000_RAH(0), (E1000_RAH_AV | UINT16_MAX));
1671 E1000_WRITE_REG(hw, E1000_RAL(0), UINT32_MAX);
1673 /* VLVF: set up filters for vlan tags as configured */
1674 for (i = 0; i < cfg->nb_pool_maps; i++) {
1675 /* set vlan id in VF register and set the valid bit */
1676 E1000_WRITE_REG(hw, E1000_VLVF(i), (E1000_VLVF_VLANID_ENABLE | \
1677 (cfg->pool_map[i].vlan_id & ETH_VLAN_ID_MAX) | \
1678 ((cfg->pool_map[i].pools << E1000_VLVF_POOLSEL_SHIFT ) & \
1679 E1000_VLVF_POOLSEL_MASK)));
1682 E1000_WRITE_FLUSH(hw);
1688 /*********************************************************************
1690 * Enable receive unit.
1692 **********************************************************************/
1695 igb_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
1697 struct igb_rx_entry *rxe = rxq->sw_ring;
1701 /* Initialize software ring entries. */
1702 for (i = 0; i < rxq->nb_rx_desc; i++) {
1703 volatile union e1000_adv_rx_desc *rxd;
1704 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
1707 PMD_INIT_LOG(ERR, "RX mbuf alloc failed "
1708 "queue_id=%hu\n", rxq->queue_id);
1709 igb_rx_queue_release(rxq);
1713 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
1714 rxd = &rxq->rx_ring[i];
1715 rxd->read.hdr_addr = dma_addr;
1716 rxd->read.pkt_addr = dma_addr;
1723 #define E1000_MRQC_DEF_Q_SHIFT (3)
1725 igb_dev_mq_rx_configure(struct rte_eth_dev *dev)
1727 struct e1000_hw *hw =
1728 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1731 if (RTE_ETH_DEV_SRIOV(dev).active == ETH_8_POOLS) {
1733 * SRIOV active scheme
1734 * FIXME if support RSS together with VMDq & SRIOV
1736 mrqc = E1000_MRQC_ENABLE_VMDQ;
1737 /* 011b Def_Q ignore, according to VT_CTL.DEF_PL */
1738 mrqc |= 0x3 << E1000_MRQC_DEF_Q_SHIFT;
1739 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1740 } else if(RTE_ETH_DEV_SRIOV(dev).active == 0) {
1742 * SRIOV inactive scheme
1744 if (dev->data->nb_rx_queues > 1)
1745 switch (dev->data->dev_conf.rxmode.mq_mode) {
1746 case ETH_MQ_RX_NONE:
1747 /* if mq_mode not assign, we use rss mode.*/
1749 igb_rss_configure(dev);
1751 case ETH_MQ_RX_VMDQ_ONLY:
1752 /*Configure general VMDQ only RX parameters*/
1753 igb_vmdq_rx_hw_configure(dev);
1756 igb_rss_disable(dev);
1760 igb_rss_disable(dev);
1767 eth_igb_rx_init(struct rte_eth_dev *dev)
1769 struct e1000_hw *hw;
1770 struct igb_rx_queue *rxq;
1771 struct rte_pktmbuf_pool_private *mbp_priv;
1776 uint16_t rctl_bsize;
1780 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1784 * Make sure receives are disabled while setting
1785 * up the descriptor ring.
1787 rctl = E1000_READ_REG(hw, E1000_RCTL);
1788 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
1791 * Configure support of jumbo frames, if any.
1793 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
1794 rctl |= E1000_RCTL_LPE;
1797 * Set maximum packet length by default, and might be updated
1798 * together with enabling/disabling dual VLAN.
1800 E1000_WRITE_REG(hw, E1000_RLPML,
1801 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1804 rctl &= ~E1000_RCTL_LPE;
1806 /* Configure and enable each RX queue. */
1808 dev->rx_pkt_burst = eth_igb_recv_pkts;
1809 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1813 rxq = dev->data->rx_queues[i];
1815 /* Allocate buffers for descriptor rings and set up queue */
1816 ret = igb_alloc_rx_queue_mbufs(rxq);
1821 * Reset crc_len in case it was changed after queue setup by a
1825 (uint8_t)(dev->data->dev_conf.rxmode.hw_strip_crc ?
1828 bus_addr = rxq->rx_ring_phys_addr;
1829 E1000_WRITE_REG(hw, E1000_RDLEN(rxq->reg_idx),
1831 sizeof(union e1000_adv_rx_desc));
1832 E1000_WRITE_REG(hw, E1000_RDBAH(rxq->reg_idx),
1833 (uint32_t)(bus_addr >> 32));
1834 E1000_WRITE_REG(hw, E1000_RDBAL(rxq->reg_idx), (uint32_t)bus_addr);
1836 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1839 * Configure RX buffer size.
1841 mbp_priv = (struct rte_pktmbuf_pool_private *)
1842 ((char *)rxq->mb_pool + sizeof(struct rte_mempool));
1843 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
1844 RTE_PKTMBUF_HEADROOM);
1845 if (buf_size >= 1024) {
1847 * Configure the BSIZEPACKET field of the SRRCTL
1848 * register of the queue.
1849 * Value is in 1 KB resolution, from 1 KB to 127 KB.
1850 * If this field is equal to 0b, then RCTL.BSIZE
1851 * determines the RX packet buffer size.
1853 srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
1854 E1000_SRRCTL_BSIZEPKT_MASK);
1855 buf_size = (uint16_t) ((srrctl &
1856 E1000_SRRCTL_BSIZEPKT_MASK) <<
1857 E1000_SRRCTL_BSIZEPKT_SHIFT);
1859 /* It adds dual VLAN length for supporting dual VLAN */
1860 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
1861 2 * VLAN_TAG_SIZE) > buf_size){
1862 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
1863 dev->data->scattered_rx = 1;
1867 * Use BSIZE field of the device RCTL register.
1869 if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
1870 rctl_bsize = buf_size;
1871 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
1872 dev->data->scattered_rx = 1;
1875 /* Set if packets are dropped when no descriptors available */
1877 srrctl |= E1000_SRRCTL_DROP_EN;
1879 E1000_WRITE_REG(hw, E1000_SRRCTL(rxq->reg_idx), srrctl);
1881 /* Enable this RX queue. */
1882 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rxq->reg_idx));
1883 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1884 rxdctl &= 0xFFF00000;
1885 rxdctl |= (rxq->pthresh & 0x1F);
1886 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
1887 rxdctl |= ((rxq->wthresh & 0x1F) << 16);
1888 E1000_WRITE_REG(hw, E1000_RXDCTL(rxq->reg_idx), rxdctl);
1892 * Setup BSIZE field of RCTL register, if needed.
1893 * Buffer sizes >= 1024 are not [supposed to be] setup in the RCTL
1894 * register, since the code above configures the SRRCTL register of
1895 * the RX queue in such a case.
1896 * All configurable sizes are:
1897 * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);
1898 * 8192: rctl |= (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX);
1899 * 4096: rctl |= (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX);
1900 * 2048: rctl |= E1000_RCTL_SZ_2048;
1901 * 1024: rctl |= E1000_RCTL_SZ_1024;
1902 * 512: rctl |= E1000_RCTL_SZ_512;
1903 * 256: rctl |= E1000_RCTL_SZ_256;
1905 if (rctl_bsize > 0) {
1906 if (rctl_bsize >= 512) /* 512 <= buf_size < 1024 - use 512 */
1907 rctl |= E1000_RCTL_SZ_512;
1908 else /* 256 <= buf_size < 512 - use 256 */
1909 rctl |= E1000_RCTL_SZ_256;
1913 * Configure RSS if device configured with multiple RX queues.
1915 igb_dev_mq_rx_configure(dev);
1917 /* Update the rctl since igb_dev_mq_rx_configure may change its value */
1918 rctl |= E1000_READ_REG(hw, E1000_RCTL);
1921 * Setup the Checksum Register.
1922 * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
1924 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
1925 rxcsum |= E1000_RXCSUM_PCSD;
1927 /* Enable both L3/L4 rx checksum offload */
1928 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
1929 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
1931 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
1932 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
1934 /* Setup the Receive Control Register. */
1935 if (dev->data->dev_conf.rxmode.hw_strip_crc) {
1936 rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */
1938 /* set STRCRC bit in all queues */
1939 if (hw->mac.type == e1000_i350 ||
1940 hw->mac.type == e1000_i210 ||
1941 hw->mac.type == e1000_i211 ||
1942 hw->mac.type == e1000_i354) {
1943 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1944 rxq = dev->data->rx_queues[i];
1945 uint32_t dvmolr = E1000_READ_REG(hw,
1946 E1000_DVMOLR(rxq->reg_idx));
1947 dvmolr |= E1000_DVMOLR_STRCRC;
1948 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
1952 rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
1954 /* clear STRCRC bit in all queues */
1955 if (hw->mac.type == e1000_i350 ||
1956 hw->mac.type == e1000_i210 ||
1957 hw->mac.type == e1000_i211 ||
1958 hw->mac.type == e1000_i354) {
1959 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1960 rxq = dev->data->rx_queues[i];
1961 uint32_t dvmolr = E1000_READ_REG(hw,
1962 E1000_DVMOLR(rxq->reg_idx));
1963 dvmolr &= ~E1000_DVMOLR_STRCRC;
1964 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
1969 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1970 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
1971 E1000_RCTL_RDMTS_HALF |
1972 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1974 /* Make sure VLAN Filters are off. */
1975 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_VMDQ_ONLY)
1976 rctl &= ~E1000_RCTL_VFE;
1977 /* Don't store bad packets. */
1978 rctl &= ~E1000_RCTL_SBP;
1980 /* Enable Receives. */
1981 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1984 * Setup the HW Rx Head and Tail Descriptor Pointers.
1985 * This needs to be done after enable.
1987 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1988 rxq = dev->data->rx_queues[i];
1989 E1000_WRITE_REG(hw, E1000_RDH(rxq->reg_idx), 0);
1990 E1000_WRITE_REG(hw, E1000_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
1996 /*********************************************************************
1998 * Enable transmit unit.
2000 **********************************************************************/
2002 eth_igb_tx_init(struct rte_eth_dev *dev)
2004 struct e1000_hw *hw;
2005 struct igb_tx_queue *txq;
2010 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2012 /* Setup the Base and Length of the Tx Descriptor Rings. */
2013 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2015 txq = dev->data->tx_queues[i];
2016 bus_addr = txq->tx_ring_phys_addr;
2018 E1000_WRITE_REG(hw, E1000_TDLEN(txq->reg_idx),
2020 sizeof(union e1000_adv_tx_desc));
2021 E1000_WRITE_REG(hw, E1000_TDBAH(txq->reg_idx),
2022 (uint32_t)(bus_addr >> 32));
2023 E1000_WRITE_REG(hw, E1000_TDBAL(txq->reg_idx), (uint32_t)bus_addr);
2025 /* Setup the HW Tx Head and Tail descriptor pointers. */
2026 E1000_WRITE_REG(hw, E1000_TDT(txq->reg_idx), 0);
2027 E1000_WRITE_REG(hw, E1000_TDH(txq->reg_idx), 0);
2029 /* Setup Transmit threshold registers. */
2030 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(txq->reg_idx));
2031 txdctl |= txq->pthresh & 0x1F;
2032 txdctl |= ((txq->hthresh & 0x1F) << 8);
2033 txdctl |= ((txq->wthresh & 0x1F) << 16);
2034 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2035 E1000_WRITE_REG(hw, E1000_TXDCTL(txq->reg_idx), txdctl);
2038 /* Program the Transmit Control Register. */
2039 tctl = E1000_READ_REG(hw, E1000_TCTL);
2040 tctl &= ~E1000_TCTL_CT;
2041 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2042 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
2044 e1000_config_collision_dist(hw);
2046 /* This write will effectively turn on the transmit unit. */
2047 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2050 /*********************************************************************
2052 * Enable VF receive unit.
2054 **********************************************************************/
2056 eth_igbvf_rx_init(struct rte_eth_dev *dev)
2058 struct e1000_hw *hw;
2059 struct igb_rx_queue *rxq;
2060 struct rte_pktmbuf_pool_private *mbp_priv;
2063 uint16_t rctl_bsize;
2067 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2069 /* Configure and enable each RX queue. */
2071 dev->rx_pkt_burst = eth_igb_recv_pkts;
2072 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2076 rxq = dev->data->rx_queues[i];
2078 /* Allocate buffers for descriptor rings and set up queue */
2079 ret = igb_alloc_rx_queue_mbufs(rxq);
2083 bus_addr = rxq->rx_ring_phys_addr;
2084 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2086 sizeof(union e1000_adv_rx_desc));
2087 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2088 (uint32_t)(bus_addr >> 32));
2089 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
2091 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2094 * Configure RX buffer size.
2096 mbp_priv = (struct rte_pktmbuf_pool_private *)
2097 ((char *)rxq->mb_pool + sizeof(struct rte_mempool));
2098 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
2099 RTE_PKTMBUF_HEADROOM);
2100 if (buf_size >= 1024) {
2102 * Configure the BSIZEPACKET field of the SRRCTL
2103 * register of the queue.
2104 * Value is in 1 KB resolution, from 1 KB to 127 KB.
2105 * If this field is equal to 0b, then RCTL.BSIZE
2106 * determines the RX packet buffer size.
2108 srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
2109 E1000_SRRCTL_BSIZEPKT_MASK);
2110 buf_size = (uint16_t) ((srrctl &
2111 E1000_SRRCTL_BSIZEPKT_MASK) <<
2112 E1000_SRRCTL_BSIZEPKT_SHIFT);
2114 /* It adds dual VLAN length for supporting dual VLAN */
2115 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
2116 2 * VLAN_TAG_SIZE) > buf_size){
2117 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2118 dev->data->scattered_rx = 1;
2122 * Use BSIZE field of the device RCTL register.
2124 if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
2125 rctl_bsize = buf_size;
2126 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2127 dev->data->scattered_rx = 1;
2130 /* Set if packets are dropped when no descriptors available */
2132 srrctl |= E1000_SRRCTL_DROP_EN;
2134 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2136 /* Enable this RX queue. */
2137 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2138 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2139 rxdctl &= 0xFFF00000;
2140 rxdctl |= (rxq->pthresh & 0x1F);
2141 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
2142 if (hw->mac.type == e1000_82576) {
2144 * Workaround of 82576 VF Erratum
2145 * force set WTHRESH to 1
2146 * to avoid Write-Back not triggered sometimes
2149 PMD_INIT_LOG(DEBUG, "Force set RX WTHRESH to 1 !\n");
2152 rxdctl |= ((rxq->wthresh & 0x1F) << 16);
2153 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2157 * Setup the HW Rx Head and Tail Descriptor Pointers.
2158 * This needs to be done after enable.
2160 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2161 rxq = dev->data->rx_queues[i];
2162 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
2163 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
2169 /*********************************************************************
2171 * Enable VF transmit unit.
2173 **********************************************************************/
2175 eth_igbvf_tx_init(struct rte_eth_dev *dev)
2177 struct e1000_hw *hw;
2178 struct igb_tx_queue *txq;
2182 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2184 /* Setup the Base and Length of the Tx Descriptor Rings. */
2185 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2188 txq = dev->data->tx_queues[i];
2189 bus_addr = txq->tx_ring_phys_addr;
2190 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2192 sizeof(union e1000_adv_tx_desc));
2193 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2194 (uint32_t)(bus_addr >> 32));
2195 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
2197 /* Setup the HW Tx Head and Tail descriptor pointers. */
2198 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2199 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2201 /* Setup Transmit threshold registers. */
2202 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
2203 txdctl |= txq->pthresh & 0x1F;
2204 txdctl |= ((txq->hthresh & 0x1F) << 8);
2205 if (hw->mac.type == e1000_82576) {
2207 * Workaround of 82576 VF Erratum
2208 * force set WTHRESH to 1
2209 * to avoid Write-Back not triggered sometimes
2212 PMD_INIT_LOG(DEBUG, "Force set TX WTHRESH to 1 !\n");
2215 txdctl |= ((txq->wthresh & 0x1F) << 16);
2216 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2217 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);