lib/librte_pmd_e1000/igb_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35
  36 #include <endian.h>
  37 #include <stdio.h>
  38 #include <stdlib.h>
  39 #include <string.h>
  40 #include <errno.h>
  41 #include <stdint.h>
  42 #include <stdarg.h>
  43 #include <inttypes.h>
  44
  45 #include <rte_interrupts.h>
  46 #include <rte_byteorder.h>
  47 #include <rte_common.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_memory.h>
  52 #include <rte_memcpy.h>
  53 #include <rte_memzone.h>
  54 #include <rte_launch.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_per_lcore.h>
  58 #include <rte_lcore.h>
  59 #include <rte_atomic.h>
  60 #include <rte_branch_prediction.h>
  61 #include <rte_ring.h>
  62 #include <rte_mempool.h>
  63 #include <rte_malloc.h>
  64 #include <rte_mbuf.h>
  65 #include <rte_ether.h>
  66 #include <rte_ethdev.h>
  67 #include <rte_prefetch.h>
  68 #include <rte_udp.h>
  69 #include <rte_tcp.h>
  70 #include <rte_sctp.h>
  71 #include <rte_string_fns.h>
  72
  73 #include "e1000_logs.h"
  74 #include "e1000/e1000_api.h"
  75 #include "e1000_ethdev.h"
  76
  77 static inline struct rte_mbuf *
  78 rte_rxmbuf_alloc(struct rte_mempool *mp)
  79 {
  80         struct rte_mbuf *m;
  81
  82         m = __rte_mbuf_raw_alloc(mp);
  83         __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
  84         return (m);
  85 }
  86
  87 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
  88         (uint64_t) ((mb)->buf_physaddr +                   \
  89                         (uint64_t) ((char *)((mb)->pkt.data) -     \
  90                                 (char *)(mb)->buf_addr))
  91
  92 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
  93         (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
  94
  95 /**
  96  * Structure associated with each descriptor of the RX ring of a RX queue.
  97  */
  98 struct igb_rx_entry {
  99         struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
 100 };
 101
 102 /**
 103  * Structure associated with each descriptor of the TX ring of a TX queue.
 104  */
 105 struct igb_tx_entry {
 106         struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
 107         uint16_t next_id; /**< Index of next descriptor in ring. */
 108         uint16_t last_id; /**< Index of last scattered descriptor. */
 109 };
 110
 111 /**
 112  * Structure associated with each RX queue.
 113  */
 114 struct igb_rx_queue {
 115         struct rte_mempool  *mb_pool;   /**< mbuf pool to populate RX ring. */
 116         volatile union e1000_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
 117         uint64_t            rx_ring_phys_addr; /**< RX ring DMA address. */
 118         volatile uint32_t   *rdt_reg_addr; /**< RDT register address. */
 119         volatile uint32_t   *rdh_reg_addr; /**< RDH register address. */
 120         struct igb_rx_entry *sw_ring;   /**< address of RX software ring. */
 121         struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
 122         struct rte_mbuf *pkt_last_seg;  /**< Last segment of current packet. */
 123         uint16_t            nb_rx_desc; /**< number of RX descriptors. */
 124         uint16_t            rx_tail;    /**< current value of RDT register. */
 125         uint16_t            nb_rx_hold; /**< number of held free RX desc. */
 126         uint16_t            rx_free_thresh; /**< max free RX desc to hold. */
 127         uint16_t            queue_id;   /**< RX queue index. */
 128         uint16_t            reg_idx;    /**< RX queue register index. */
 129         uint8_t             port_id;    /**< Device port identifier. */
 130         uint8_t             pthresh;    /**< Prefetch threshold register. */
 131         uint8_t             hthresh;    /**< Host threshold register. */
 132         uint8_t             wthresh;    /**< Write-back threshold register. */
 133         uint8_t             crc_len;    /**< 0 if CRC stripped, 4 otherwise. */
 134         uint8_t             drop_en;  /**< If not 0, set SRRCTL.Drop_En. */
 135 };
 136
 137 /**
 138  * Hardware context number
 139  */
 140 enum igb_advctx_num {
 141         IGB_CTX_0    = 0, /**< CTX0    */
 142         IGB_CTX_1    = 1, /**< CTX1    */
 143         IGB_CTX_NUM  = 2, /**< CTX_NUM */
 144 };
 145
 146 /**
 147  * Strucutre to check if new context need be built
 148  */
 149 struct igb_advctx_info {
 150         uint16_t flags;           /**< ol_flags related to context build. */
 151         uint32_t cmp_mask;        /**< compare mask for vlan_macip_lens */
 152         union rte_vlan_macip vlan_macip_lens; /**< vlan, mac & ip length. */
 153 };
 154
 155 /**
 156  * Structure associated with each TX queue.
 157  */
 158 struct igb_tx_queue {
 159         volatile union e1000_adv_tx_desc *tx_ring; /**< TX ring address */
 160         uint64_t               tx_ring_phys_addr; /**< TX ring DMA address. */
 161         struct igb_tx_entry    *sw_ring; /**< virtual address of SW ring. */
 162         volatile uint32_t      *tdt_reg_addr; /**< Address of TDT register. */
 163         uint32_t               txd_type;      /**< Device-specific TXD type */
 164         uint16_t               nb_tx_desc;    /**< number of TX descriptors. */
 165         uint16_t               tx_tail; /**< Current value of TDT register. */
 166         uint16_t               tx_head;
 167         /**< Index of first used TX descriptor. */
 168         uint16_t               queue_id; /**< TX queue index. */
 169         uint16_t               reg_idx;  /**< TX queue register index. */
 170         uint8_t                port_id;  /**< Device port identifier. */
 171         uint8_t                pthresh;  /**< Prefetch threshold register. */
 172         uint8_t                hthresh;  /**< Host threshold register. */
 173         uint8_t                wthresh;  /**< Write-back threshold register. */
 174         uint32_t               ctx_curr;
 175         /**< Current used hardware descriptor. */
 176         uint32_t               ctx_start;
 177         /**< Start context position for transmit queue. */
 178         struct igb_advctx_info ctx_cache[IGB_CTX_NUM];
 179         /**< Hardware context history.*/
 180 };
 181
 182 #if 1
 183 #define RTE_PMD_USE_PREFETCH
 184 #endif
 185
 186 #ifdef RTE_PMD_USE_PREFETCH
 187 #define rte_igb_prefetch(p)     rte_prefetch0(p)
 188 #else
 189 #define rte_igb_prefetch(p)     do {} while(0)
 190 #endif
 191
 192 #ifdef RTE_PMD_PACKET_PREFETCH
 193 #define rte_packet_prefetch(p) rte_prefetch1(p)
 194 #else
 195 #define rte_packet_prefetch(p)  do {} while(0)
 196 #endif
 197
 198 /*
 199  * Macro for VMDq feature for 1 GbE NIC.
 200  */
 201 #define E1000_VMOLR_SIZE                        (8)
 202
 203 /*********************************************************************
 204  *
 205  *  TX function
 206  *
 207  **********************************************************************/
 208
 209 /*
 210  * Advanced context descriptor are almost same between igb/ixgbe
 211  * This is a separate function, looking for optimization opportunity here
 212  * Rework required to go with the pre-defined values.
 213  */
 214
 215 static inline void
 216 igbe_set_xmit_ctx(struct igb_tx_queue* txq,
 217                 volatile struct e1000_adv_tx_context_desc *ctx_txd,
 218                 uint16_t ol_flags, uint32_t vlan_macip_lens)
 219 {
 220         uint32_t type_tucmd_mlhl;
 221         uint32_t mss_l4len_idx;
 222         uint32_t ctx_idx, ctx_curr;
 223         uint32_t cmp_mask;
 224
 225         ctx_curr = txq->ctx_curr;
 226         ctx_idx = ctx_curr + txq->ctx_start;
 227
 228         cmp_mask = 0;
 229         type_tucmd_mlhl = 0;
 230
 231         if (ol_flags & PKT_TX_VLAN_PKT) {
 232                 cmp_mask |= TX_VLAN_CMP_MASK;
 233         }
 234
 235         if (ol_flags & PKT_TX_IP_CKSUM) {
 236                 type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4;
 237                 cmp_mask |= TX_MAC_LEN_CMP_MASK;
 238         }
 239
 240         /* Specify which HW CTX to upload. */
 241         mss_l4len_idx = (ctx_idx << E1000_ADVTXD_IDX_SHIFT);
 242         switch (ol_flags & PKT_TX_L4_MASK) {
 243         case PKT_TX_UDP_CKSUM:
 244                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP |
 245                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 246                 mss_l4len_idx |= sizeof(struct udp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
 247                 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
 248                 break;
 249         case PKT_TX_TCP_CKSUM:
 250                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP |
 251                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 252                 mss_l4len_idx |= sizeof(struct tcp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
 253                 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
 254                 break;
 255         case PKT_TX_SCTP_CKSUM:
 256                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP |
 257                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 258                 mss_l4len_idx |= sizeof(struct sctp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
 259                 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
 260                 break;
 261         default:
 262                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_RSV |
 263                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 264                 break;
 265         }
 266
 267         txq->ctx_cache[ctx_curr].flags           = ol_flags;
 268         txq->ctx_cache[ctx_curr].cmp_mask        = cmp_mask;
 269         txq->ctx_cache[ctx_curr].vlan_macip_lens.data =
 270                 vlan_macip_lens & cmp_mask;
 271
 272         ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
 273         ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
 274         ctx_txd->mss_l4len_idx   = rte_cpu_to_le_32(mss_l4len_idx);
 275         ctx_txd->seqnum_seed     = 0;
 276 }
 277
 278 /*
 279  * Check which hardware context can be used. Use the existing match
 280  * or create a new context descriptor.
 281  */
 282 static inline uint32_t
 283 what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
 284                 uint32_t vlan_macip_lens)
 285 {
 286         /* If match with the current context */
 287         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 288                 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
 289                 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
 290                         return txq->ctx_curr;
 291         }
 292
 293         /* If match with the second context */
 294         txq->ctx_curr ^= 1;
 295         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 296                 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
 297                 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
 298                         return txq->ctx_curr;
 299         }
 300
 301         /* Mismatch, use the previous context */
 302         return (IGB_CTX_NUM);
 303 }
 304
 305 static inline uint32_t
 306 tx_desc_cksum_flags_to_olinfo(uint16_t ol_flags)
 307 {
 308         static const uint32_t l4_olinfo[2] = {0, E1000_ADVTXD_POPTS_TXSM};
 309         static const uint32_t l3_olinfo[2] = {0, E1000_ADVTXD_POPTS_IXSM};
 310         uint32_t tmp;
 311
 312         tmp  = l4_olinfo[(ol_flags & PKT_TX_L4_MASK)  != PKT_TX_L4_NO_CKSUM];
 313         tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
 314         return tmp;
 315 }
 316
 317 static inline uint32_t
 318 tx_desc_vlan_flags_to_cmdtype(uint16_t ol_flags)
 319 {
 320         static uint32_t vlan_cmd[2] = {0, E1000_ADVTXD_DCMD_VLE};
 321         return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
 322 }
 323
 324 uint16_t
 325 eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 326                uint16_t nb_pkts)
 327 {
 328         struct igb_tx_queue *txq;
 329         struct igb_tx_entry *sw_ring;
 330         struct igb_tx_entry *txe, *txn;
 331         volatile union e1000_adv_tx_desc *txr;
 332         volatile union e1000_adv_tx_desc *txd;
 333         struct rte_mbuf     *tx_pkt;
 334         struct rte_mbuf     *m_seg;
 335         uint64_t buf_dma_addr;
 336         uint32_t olinfo_status;
 337         uint32_t cmd_type_len;
 338         uint32_t pkt_len;
 339         uint16_t slen;
 340         uint16_t ol_flags;
 341         uint16_t tx_end;
 342         uint16_t tx_id;
 343         uint16_t tx_last;
 344         uint16_t nb_tx;
 345         uint16_t tx_ol_req;
 346         uint32_t new_ctx = 0;
 347         uint32_t ctx = 0;
 348         uint32_t vlan_macip_lens;
 349
 350         txq = tx_queue;
 351         sw_ring = txq->sw_ring;
 352         txr     = txq->tx_ring;
 353         tx_id   = txq->tx_tail;
 354         txe = &sw_ring[tx_id];
 355
 356         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
 357                 tx_pkt = *tx_pkts++;
 358                 pkt_len = tx_pkt->pkt.pkt_len;
 359
 360                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
 361
 362                 /*
 363                  * The number of descriptors that must be allocated for a
 364                  * packet is the number of segments of that packet, plus 1
 365                  * Context Descriptor for the VLAN Tag Identifier, if any.
 366                  * Determine the last TX descriptor to allocate in the TX ring
 367                  * for the packet, starting from the current position (tx_id)
 368                  * in the ring.
 369                  */
 370                 tx_last = (uint16_t) (tx_id + tx_pkt->pkt.nb_segs - 1);
 371
 372                 ol_flags = tx_pkt->ol_flags;
 373                 vlan_macip_lens = tx_pkt->pkt.vlan_macip.data;
 374                 tx_ol_req = (uint16_t)(ol_flags & PKT_TX_OFFLOAD_MASK);
 375
 376                 /* If a Context Descriptor need be built . */
 377                 if (tx_ol_req) {
 378                         ctx = what_advctx_update(txq, tx_ol_req,
 379                                 vlan_macip_lens);
 380                         /* Only allocate context descriptor if required*/
 381                         new_ctx = (ctx == IGB_CTX_NUM);
 382                         ctx = txq->ctx_curr;
 383                         tx_last = (uint16_t) (tx_last + new_ctx);
 384                 }
 385                 if (tx_last >= txq->nb_tx_desc)
 386                         tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
 387
 388                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
 389                            " tx_first=%u tx_last=%u\n",
 390                            (unsigned) txq->port_id,
 391                            (unsigned) txq->queue_id,
 392                            (unsigned) pkt_len,
 393                            (unsigned) tx_id,
 394                            (unsigned) tx_last);
 395
 396                 /*
 397                  * Check if there are enough free descriptors in the TX ring
 398                  * to transmit the next packet.
 399                  * This operation is based on the two following rules:
 400                  *
 401                  *   1- Only check that the last needed TX descriptor can be
 402                  *      allocated (by construction, if that descriptor is free,
 403                  *      all intermediate ones are also free).
 404                  *
 405                  *      For this purpose, the index of the last TX descriptor
 406                  *      used for a packet (the "last descriptor" of a packet)
 407                  *      is recorded in the TX entries (the last one included)
 408                  *      that are associated with all TX descriptors allocated
 409                  *      for that packet.
 410                  *
 411                  *   2- Avoid to allocate the last free TX descriptor of the
 412                  *      ring, in order to never set the TDT register with the
 413                  *      same value stored in parallel by the NIC in the TDH
 414                  *      register, which makes the TX engine of the NIC enter
 415                  *      in a deadlock situation.
 416                  *
 417                  *      By extension, avoid to allocate a free descriptor that
 418                  *      belongs to the last set of free descriptors allocated
 419                  *      to the same packet previously transmitted.
 420                  */
 421
 422                 /*
 423                  * The "last descriptor" of the previously sent packet, if any,
 424                  * which used the last descriptor to allocate.
 425                  */
 426                 tx_end = sw_ring[tx_last].last_id;
 427
 428                 /*
 429                  * The next descriptor following that "last descriptor" in the
 430                  * ring.
 431                  */
 432                 tx_end = sw_ring[tx_end].next_id;
 433
 434                 /*
 435                  * The "last descriptor" associated with that next descriptor.
 436                  */
 437                 tx_end = sw_ring[tx_end].last_id;
 438
 439                 /*
 440                  * Check that this descriptor is free.
 441                  */
 442                 if (! (txr[tx_end].wb.status & E1000_TXD_STAT_DD)) {
 443                         if (nb_tx == 0)
 444                                 return (0);
 445                         goto end_of_tx;
 446                 }
 447
 448                 /*
 449                  * Set common flags of all TX Data Descriptors.
 450                  *
 451                  * The following bits must be set in all Data Descriptors:
 452                  *   - E1000_ADVTXD_DTYP_DATA
 453                  *   - E1000_ADVTXD_DCMD_DEXT
 454                  *
 455                  * The following bits must be set in the first Data Descriptor
 456                  * and are ignored in the other ones:
 457                  *   - E1000_ADVTXD_DCMD_IFCS
 458                  *   - E1000_ADVTXD_MAC_1588
 459                  *   - E1000_ADVTXD_DCMD_VLE
 460                  *
 461                  * The following bits must only be set in the last Data
 462                  * Descriptor:
 463                  *   - E1000_TXD_CMD_EOP
 464                  *
 465                  * The following bits can be set in any Data Descriptor, but
 466                  * are only set in the last Data Descriptor:
 467                  *   - E1000_TXD_CMD_RS
 468                  */
 469                 cmd_type_len = txq->txd_type |
 470                         E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
 471                 olinfo_status = (pkt_len << E1000_ADVTXD_PAYLEN_SHIFT);
 472 #if defined(RTE_LIBRTE_IEEE1588)
 473                 if (ol_flags & PKT_TX_IEEE1588_TMST)
 474                         cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
 475 #endif
 476                 if (tx_ol_req) {
 477                         /* Setup TX Advanced context descriptor if required */
 478                         if (new_ctx) {
 479                                 volatile struct e1000_adv_tx_context_desc *
 480                                     ctx_txd;
 481
 482                                 ctx_txd = (volatile struct
 483                                     e1000_adv_tx_context_desc *)
 484                                     &txr[tx_id];
 485
 486                                 txn = &sw_ring[txe->next_id];
 487                                 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
 488
 489                                 if (txe->mbuf != NULL) {
 490                                         rte_pktmbuf_free_seg(txe->mbuf);
 491                                         txe->mbuf = NULL;
 492                                 }
 493
 494                                 igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
 495                                     vlan_macip_lens);
 496
 497                                 txe->last_id = tx_last;
 498                                 tx_id = txe->next_id;
 499                                 txe = txn;
 500                         }
 501
 502                         /* Setup the TX Advanced Data Descriptor */
 503                         cmd_type_len  |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
 504                         olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
 505                         olinfo_status |= (ctx << E1000_ADVTXD_IDX_SHIFT);
 506                 }
 507
 508                 m_seg = tx_pkt;
 509                 do {
 510                         txn = &sw_ring[txe->next_id];
 511                         txd = &txr[tx_id];
 512
 513                         if (txe->mbuf != NULL)
 514                                 rte_pktmbuf_free_seg(txe->mbuf);
 515                         txe->mbuf = m_seg;
 516
 517                         /*
 518                          * Set up transmit descriptor.
 519                          */
 520                         slen = (uint16_t) m_seg->pkt.data_len;
 521                         buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
 522                         txd->read.buffer_addr =
 523                                 rte_cpu_to_le_64(buf_dma_addr);
 524                         txd->read.cmd_type_len =
 525                                 rte_cpu_to_le_32(cmd_type_len | slen);
 526                         txd->read.olinfo_status =
 527                                 rte_cpu_to_le_32(olinfo_status);
 528                         txe->last_id = tx_last;
 529                         tx_id = txe->next_id;
 530                         txe = txn;
 531                         m_seg = m_seg->pkt.next;
 532                 } while (m_seg != NULL);
 533
 534                 /*
 535                  * The last packet data descriptor needs End Of Packet (EOP)
 536                  * and Report Status (RS).
 537                  */
 538                 txd->read.cmd_type_len |=
 539                         rte_cpu_to_le_32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS);
 540         }
 541  end_of_tx:
 542         rte_wmb();
 543
 544         /*
 545          * Set the Transmit Descriptor Tail (TDT).
 546          */
 547         E1000_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
 548         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
 549                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
 550                    (unsigned) tx_id, (unsigned) nb_tx);
 551         txq->tx_tail = tx_id;
 552
 553         return (nb_tx);
 554 }
 555
 556 /*********************************************************************
 557  *
 558  *  RX functions
 559  *
 560  **********************************************************************/
 561 static inline uint16_t
 562 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
 563 {
 564         uint16_t pkt_flags;
 565
 566         static uint16_t ip_pkt_types_map[16] = {
 567                 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
 568                 PKT_RX_IPV6_HDR, 0, 0, 0,
 569                 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
 570                 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
 571         };
 572
 573 #if defined(RTE_LIBRTE_IEEE1588)
 574         static uint32_t ip_pkt_etqf_map[8] = {
 575                 0, 0, 0, PKT_RX_IEEE1588_PTP,
 576                 0, 0, 0, 0,
 577         };
 578
 579         pkt_flags = (uint16_t)((hl_tp_rs & E1000_RXDADV_PKTTYPE_ETQF) ?
 580                                 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
 581                                 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
 582 #else
 583         pkt_flags = (uint16_t)((hl_tp_rs & E1000_RXDADV_PKTTYPE_ETQF) ? 0 :
 584                                 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
 585 #endif
 586         return (uint16_t)(pkt_flags | (((hl_tp_rs & 0x0F) == 0) ?
 587                                                 0 : PKT_RX_RSS_HASH));
 588 }
 589
 590 static inline uint16_t
 591 rx_desc_status_to_pkt_flags(uint32_t rx_status)
 592 {
 593         uint16_t pkt_flags;
 594
 595         /* Check if VLAN present */
 596         pkt_flags = (uint16_t)((rx_status & E1000_RXD_STAT_VP) ?
 597                                                 PKT_RX_VLAN_PKT : 0);
 598
 599 #if defined(RTE_LIBRTE_IEEE1588)
 600         if (rx_status & E1000_RXD_STAT_TMST)
 601                 pkt_flags = (uint16_t)(pkt_flags | PKT_RX_IEEE1588_TMST);
 602 #endif
 603         return pkt_flags;
 604 }
 605
 606 static inline uint16_t
 607 rx_desc_error_to_pkt_flags(uint32_t rx_status)
 608 {
 609         /*
 610          * Bit 30: IPE, IPv4 checksum error
 611          * Bit 29: L4I, L4I integrity error
 612          */
 613
 614         static uint16_t error_to_pkt_flags_map[4] = {
 615                 0,  PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
 616                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
 617         };
 618         return error_to_pkt_flags_map[(rx_status >>
 619                 E1000_RXD_ERR_CKSUM_BIT) & E1000_RXD_ERR_CKSUM_MSK];
 620 }
 621
 622 uint16_t
 623 eth_igb_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 624                uint16_t nb_pkts)
 625 {
 626         struct igb_rx_queue *rxq;
 627         volatile union e1000_adv_rx_desc *rx_ring;
 628         volatile union e1000_adv_rx_desc *rxdp;
 629         struct igb_rx_entry *sw_ring;
 630         struct igb_rx_entry *rxe;
 631         struct rte_mbuf *rxm;
 632         struct rte_mbuf *nmb;
 633         union e1000_adv_rx_desc rxd;
 634         uint64_t dma_addr;
 635         uint32_t staterr;
 636         uint32_t hlen_type_rss;
 637         uint16_t pkt_len;
 638         uint16_t rx_id;
 639         uint16_t nb_rx;
 640         uint16_t nb_hold;
 641         uint16_t pkt_flags;
 642
 643         nb_rx = 0;
 644         nb_hold = 0;
 645         rxq = rx_queue;
 646         rx_id = rxq->rx_tail;
 647         rx_ring = rxq->rx_ring;
 648         sw_ring = rxq->sw_ring;
 649         while (nb_rx < nb_pkts) {
 650                 /*
 651                  * The order of operations here is important as the DD status
 652                  * bit must not be read after any other descriptor fields.
 653                  * rx_ring and rxdp are pointing to volatile data so the order
 654                  * of accesses cannot be reordered by the compiler. If they were
 655                  * not volatile, they could be reordered which could lead to
 656                  * using invalid descriptor fields when read from rxd.
 657                  */
 658                 rxdp = &rx_ring[rx_id];
 659                 staterr = rxdp->wb.upper.status_error;
 660                 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
 661                         break;
 662                 rxd = *rxdp;
 663
 664                 /*
 665                  * End of packet.
 666                  *
 667                  * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is
 668                  * likely to be invalid and to be dropped by the various
 669                  * validation checks performed by the network stack.
 670                  *
 671                  * Allocate a new mbuf to replenish the RX ring descriptor.
 672                  * If the allocation fails:
 673                  *    - arrange for that RX descriptor to be the first one
 674                  *      being parsed the next time the receive function is
 675                  *      invoked [on the same queue].
 676                  *
 677                  *    - Stop parsing the RX ring and return immediately.
 678                  *
 679                  * This policy do not drop the packet received in the RX
 680                  * descriptor for which the allocation of a new mbuf failed.
 681                  * Thus, it allows that packet to be later retrieved if
 682                  * mbuf have been freed in the mean time.
 683                  * As a side effect, holding RX descriptors instead of
 684                  * systematically giving them back to the NIC may lead to
 685                  * RX ring exhaustion situations.
 686                  * However, the NIC can gracefully prevent such situations
 687                  * to happen by sending specific "back-pressure" flow control
 688                  * frames to its peer(s).
 689                  */
 690                 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
 691                            "staterr=0x%x pkt_len=%u\n",
 692                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
 693                            (unsigned) rx_id, (unsigned) staterr,
 694                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
 695
 696                 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
 697                 if (nmb == NULL) {
 698                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 699                                    "queue_id=%u\n", (unsigned) rxq->port_id,
 700                                    (unsigned) rxq->queue_id);
 701                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
 702                         break;
 703                 }
 704
 705                 nb_hold++;
 706                 rxe = &sw_ring[rx_id];
 707                 rx_id++;
 708                 if (rx_id == rxq->nb_rx_desc)
 709                         rx_id = 0;
 710
 711                 /* Prefetch next mbuf while processing current one. */
 712                 rte_igb_prefetch(sw_ring[rx_id].mbuf);
 713
 714                 /*
 715                  * When next RX descriptor is on a cache-line boundary,
 716                  * prefetch the next 4 RX descriptors and the next 8 pointers
 717                  * to mbufs.
 718                  */
 719                 if ((rx_id & 0x3) == 0) {
 720                         rte_igb_prefetch(&rx_ring[rx_id]);
 721                         rte_igb_prefetch(&sw_ring[rx_id]);
 722                 }
 723
 724                 rxm = rxe->mbuf;
 725                 rxe->mbuf = nmb;
 726                 dma_addr =
 727                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 728                 rxdp->read.hdr_addr = dma_addr;
 729                 rxdp->read.pkt_addr = dma_addr;
 730
 731                 /*
 732                  * Initialize the returned mbuf.
 733                  * 1) setup generic mbuf fields:
 734                  *    - number of segments,
 735                  *    - next segment,
 736                  *    - packet length,
 737                  *    - RX port identifier.
 738                  * 2) integrate hardware offload data, if any:
 739                  *    - RSS flag & hash,
 740                  *    - IP checksum flag,
 741                  *    - VLAN TCI, if any,
 742                  *    - error flags.
 743                  */
 744                 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
 745                                       rxq->crc_len);
 746                 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
 747                 rte_packet_prefetch(rxm->pkt.data);
 748                 rxm->pkt.nb_segs = 1;
 749                 rxm->pkt.next = NULL;
 750                 rxm->pkt.pkt_len = pkt_len;
 751                 rxm->pkt.data_len = pkt_len;
 752                 rxm->pkt.in_port = rxq->port_id;
 753
 754                 rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
 755                 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
 756                 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
 757                 rxm->pkt.vlan_macip.f.vlan_tci =
 758                         rte_le_to_cpu_16(rxd.wb.upper.vlan);
 759
 760                 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
 761                 pkt_flags = (uint16_t)(pkt_flags |
 762                                 rx_desc_status_to_pkt_flags(staterr));
 763                 pkt_flags = (uint16_t)(pkt_flags |
 764                                 rx_desc_error_to_pkt_flags(staterr));
 765                 rxm->ol_flags = pkt_flags;
 766
 767                 /*
 768                  * Store the mbuf address into the next entry of the array
 769                  * of returned packets.
 770                  */
 771                 rx_pkts[nb_rx++] = rxm;
 772         }
 773         rxq->rx_tail = rx_id;
 774
 775         /*
 776          * If the number of free RX descriptors is greater than the RX free
 777          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 778          * register.
 779          * Update the RDT with the value of the last processed RX descriptor
 780          * minus 1, to guarantee that the RDT register is never equal to the
 781          * RDH register, which creates a "full" ring situtation from the
 782          * hardware point of view...
 783          */
 784         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
 785         if (nb_hold > rxq->rx_free_thresh) {
 786                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
 787                            "nb_hold=%u nb_rx=%u\n",
 788                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
 789                            (unsigned) rx_id, (unsigned) nb_hold,
 790                            (unsigned) nb_rx);
 791                 rx_id = (uint16_t) ((rx_id == 0) ?
 792                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
 793                 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
 794                 nb_hold = 0;
 795         }
 796         rxq->nb_rx_hold = nb_hold;
 797         return (nb_rx);
 798 }
 799
 800 uint16_t
 801 eth_igb_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 802                          uint16_t nb_pkts)
 803 {
 804         struct igb_rx_queue *rxq;
 805         volatile union e1000_adv_rx_desc *rx_ring;
 806         volatile union e1000_adv_rx_desc *rxdp;
 807         struct igb_rx_entry *sw_ring;
 808         struct igb_rx_entry *rxe;
 809         struct rte_mbuf *first_seg;
 810         struct rte_mbuf *last_seg;
 811         struct rte_mbuf *rxm;
 812         struct rte_mbuf *nmb;
 813         union e1000_adv_rx_desc rxd;
 814         uint64_t dma; /* Physical address of mbuf data buffer */
 815         uint32_t staterr;
 816         uint32_t hlen_type_rss;
 817         uint16_t rx_id;
 818         uint16_t nb_rx;
 819         uint16_t nb_hold;
 820         uint16_t data_len;
 821         uint16_t pkt_flags;
 822
 823         nb_rx = 0;
 824         nb_hold = 0;
 825         rxq = rx_queue;
 826         rx_id = rxq->rx_tail;
 827         rx_ring = rxq->rx_ring;
 828         sw_ring = rxq->sw_ring;
 829
 830         /*
 831          * Retrieve RX context of current packet, if any.
 832          */
 833         first_seg = rxq->pkt_first_seg;
 834         last_seg = rxq->pkt_last_seg;
 835
 836         while (nb_rx < nb_pkts) {
 837         next_desc:
 838                 /*
 839                  * The order of operations here is important as the DD status
 840                  * bit must not be read after any other descriptor fields.
 841                  * rx_ring and rxdp are pointing to volatile data so the order
 842                  * of accesses cannot be reordered by the compiler. If they were
 843                  * not volatile, they could be reordered which could lead to
 844                  * using invalid descriptor fields when read from rxd.
 845                  */
 846                 rxdp = &rx_ring[rx_id];
 847                 staterr = rxdp->wb.upper.status_error;
 848                 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
 849                         break;
 850                 rxd = *rxdp;
 851
 852                 /*
 853                  * Descriptor done.
 854                  *
 855                  * Allocate a new mbuf to replenish the RX ring descriptor.
 856                  * If the allocation fails:
 857                  *    - arrange for that RX descriptor to be the first one
 858                  *      being parsed the next time the receive function is
 859                  *      invoked [on the same queue].
 860                  *
 861                  *    - Stop parsing the RX ring and return immediately.
 862                  *
 863                  * This policy does not drop the packet received in the RX
 864                  * descriptor for which the allocation of a new mbuf failed.
 865                  * Thus, it allows that packet to be later retrieved if
 866                  * mbuf have been freed in the mean time.
 867                  * As a side effect, holding RX descriptors instead of
 868                  * systematically giving them back to the NIC may lead to
 869                  * RX ring exhaustion situations.
 870                  * However, the NIC can gracefully prevent such situations
 871                  * to happen by sending specific "back-pressure" flow control
 872                  * frames to its peer(s).
 873                  */
 874                 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
 875                            "staterr=0x%x data_len=%u\n",
 876                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
 877                            (unsigned) rx_id, (unsigned) staterr,
 878                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
 879
 880                 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
 881                 if (nmb == NULL) {
 882                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 883                                    "queue_id=%u\n", (unsigned) rxq->port_id,
 884                                    (unsigned) rxq->queue_id);
 885                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
 886                         break;
 887                 }
 888
 889                 nb_hold++;
 890                 rxe = &sw_ring[rx_id];
 891                 rx_id++;
 892                 if (rx_id == rxq->nb_rx_desc)
 893                         rx_id = 0;
 894
 895                 /* Prefetch next mbuf while processing current one. */
 896                 rte_igb_prefetch(sw_ring[rx_id].mbuf);
 897
 898                 /*
 899                  * When next RX descriptor is on a cache-line boundary,
 900                  * prefetch the next 4 RX descriptors and the next 8 pointers
 901                  * to mbufs.
 902                  */
 903                 if ((rx_id & 0x3) == 0) {
 904                         rte_igb_prefetch(&rx_ring[rx_id]);
 905                         rte_igb_prefetch(&sw_ring[rx_id]);
 906                 }
 907
 908                 /*
 909                  * Update RX descriptor with the physical address of the new
 910                  * data buffer of the new allocated mbuf.
 911                  */
 912                 rxm = rxe->mbuf;
 913                 rxe->mbuf = nmb;
 914                 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 915                 rxdp->read.pkt_addr = dma;
 916                 rxdp->read.hdr_addr = dma;
 917
 918                 /*
 919                  * Set data length & data buffer address of mbuf.
 920                  */
 921                 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
 922                 rxm->pkt.data_len = data_len;
 923                 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
 924
 925                 /*
 926                  * If this is the first buffer of the received packet,
 927                  * set the pointer to the first mbuf of the packet and
 928                  * initialize its context.
 929                  * Otherwise, update the total length and the number of segments
 930                  * of the current scattered packet, and update the pointer to
 931                  * the last mbuf of the current packet.
 932                  */
 933                 if (first_seg == NULL) {
 934                         first_seg = rxm;
 935                         first_seg->pkt.pkt_len = data_len;
 936                         first_seg->pkt.nb_segs = 1;
 937                 } else {
 938                         first_seg->pkt.pkt_len += data_len;
 939                         first_seg->pkt.nb_segs++;
 940                         last_seg->pkt.next = rxm;
 941                 }
 942
 943                 /*
 944                  * If this is not the last buffer of the received packet,
 945                  * update the pointer to the last mbuf of the current scattered
 946                  * packet and continue to parse the RX ring.
 947                  */
 948                 if (! (staterr & E1000_RXD_STAT_EOP)) {
 949                         last_seg = rxm;
 950                         goto next_desc;
 951                 }
 952
 953                 /*
 954                  * This is the last buffer of the received packet.
 955                  * If the CRC is not stripped by the hardware:
 956                  *   - Subtract the CRC length from the total packet length.
 957                  *   - If the last buffer only contains the whole CRC or a part
 958                  *     of it, free the mbuf associated to the last buffer.
 959                  *     If part of the CRC is also contained in the previous
 960                  *     mbuf, subtract the length of that CRC part from the
 961                  *     data length of the previous mbuf.
 962                  */
 963                 rxm->pkt.next = NULL;
 964                 if (unlikely(rxq->crc_len > 0)) {
 965                         first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
 966                         if (data_len <= ETHER_CRC_LEN) {
 967                                 rte_pktmbuf_free_seg(rxm);
 968                                 first_seg->pkt.nb_segs--;
 969                                 last_seg->pkt.data_len = (uint16_t)
 970                                         (last_seg->pkt.data_len -
 971                                          (ETHER_CRC_LEN - data_len));
 972                                 last_seg->pkt.next = NULL;
 973                         } else
 974                                 rxm->pkt.data_len =
 975                                         (uint16_t) (data_len - ETHER_CRC_LEN);
 976                 }
 977
 978                 /*
 979                  * Initialize the first mbuf of the returned packet:
 980                  *    - RX port identifier,
 981                  *    - hardware offload data, if any:
 982                  *      - RSS flag & hash,
 983                  *      - IP checksum flag,
 984                  *      - VLAN TCI, if any,
 985                  *      - error flags.
 986                  */
 987                 first_seg->pkt.in_port = rxq->port_id;
 988                 first_seg->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
 989
 990                 /*
 991                  * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
 992                  * set in the pkt_flags field.
 993                  */
 994                 first_seg->pkt.vlan_macip.f.vlan_tci =
 995                         rte_le_to_cpu_16(rxd.wb.upper.vlan);
 996                 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
 997                 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
 998                 pkt_flags = (uint16_t)(pkt_flags |
 999                                 rx_desc_status_to_pkt_flags(staterr));
1000                 pkt_flags = (uint16_t)(pkt_flags |
1001                                 rx_desc_error_to_pkt_flags(staterr));
1002                 first_seg->ol_flags = pkt_flags;
1003
1004                 /* Prefetch data of first segment, if configured to do so. */
1005                 rte_packet_prefetch(first_seg->pkt.data);
1006
1007                 /*
1008                  * Store the mbuf address into the next entry of the array
1009                  * of returned packets.
1010                  */
1011                 rx_pkts[nb_rx++] = first_seg;
1012
1013                 /*
1014                  * Setup receipt context for a new packet.
1015                  */
1016                 first_seg = NULL;
1017         }
1018
1019         /*
1020          * Record index of the next RX descriptor to probe.
1021          */
1022         rxq->rx_tail = rx_id;
1023
1024         /*
1025          * Save receive context.
1026          */
1027         rxq->pkt_first_seg = first_seg;
1028         rxq->pkt_last_seg = last_seg;
1029
1030         /*
1031          * If the number of free RX descriptors is greater than the RX free
1032          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1033          * register.
1034          * Update the RDT with the value of the last processed RX descriptor
1035          * minus 1, to guarantee that the RDT register is never equal to the
1036          * RDH register, which creates a "full" ring situtation from the
1037          * hardware point of view...
1038          */
1039         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1040         if (nb_hold > rxq->rx_free_thresh) {
1041                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1042                            "nb_hold=%u nb_rx=%u\n",
1043                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1044                            (unsigned) rx_id, (unsigned) nb_hold,
1045                            (unsigned) nb_rx);
1046                 rx_id = (uint16_t) ((rx_id == 0) ?
1047                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
1048                 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1049                 nb_hold = 0;
1050         }
1051         rxq->nb_rx_hold = nb_hold;
1052         return (nb_rx);
1053 }
1054
1055 /*
1056  * Rings setup and release.
1057  *
1058  * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1059  * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
1060  * This will also optimize cache line size effect.
1061  * H/W supports up to cache line size 128.
1062  */
1063 #define IGB_ALIGN 128
1064
1065 /*
1066  * Maximum number of Ring Descriptors.
1067  *
1068  * Since RDLEN/TDLEN should be multiple of 128bytes, the number of ring
1069  * desscriptors should meet the following condition:
1070  *      (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0
1071  */
1072 #define IGB_MIN_RING_DESC 32
1073 #define IGB_MAX_RING_DESC 4096
1074
1075 static const struct rte_memzone *
1076 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1077                       uint16_t queue_id, uint32_t ring_size, int socket_id)
1078 {
1079         char z_name[RTE_MEMZONE_NAMESIZE];
1080         const struct rte_memzone *mz;
1081
1082         rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1083                         dev->driver->pci_drv.name, ring_name,
1084                                 dev->data->port_id, queue_id);
1085         mz = rte_memzone_lookup(z_name);
1086         if (mz)
1087                 return mz;
1088
1089 #ifdef RTE_LIBRTE_XEN_DOM0
1090         return rte_memzone_reserve_bounded(z_name, ring_size,
1091                         socket_id, 0, IGB_ALIGN, RTE_PGSIZE_2M);
1092 #else
1093         return rte_memzone_reserve_aligned(z_name, ring_size,
1094                         socket_id, 0, IGB_ALIGN);
1095 #endif
1096 }
1097
1098 static void
1099 igb_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1100 {
1101         unsigned i;
1102
1103         if (txq->sw_ring != NULL) {
1104                 for (i = 0; i < txq->nb_tx_desc; i++) {
1105                         if (txq->sw_ring[i].mbuf != NULL) {
1106                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1107                                 txq->sw_ring[i].mbuf = NULL;
1108                         }
1109                 }
1110         }
1111 }
1112
1113 static void
1114 igb_tx_queue_release(struct igb_tx_queue *txq)
1115 {
1116         if (txq != NULL) {
1117                 igb_tx_queue_release_mbufs(txq);
1118                 rte_free(txq->sw_ring);
1119                 rte_free(txq);
1120         }
1121 }
1122
1123 void
1124 eth_igb_tx_queue_release(void *txq)
1125 {
1126         igb_tx_queue_release(txq);
1127 }
1128
1129 static void
1130 igb_reset_tx_queue_stat(struct igb_tx_queue *txq)
1131 {
1132         txq->tx_head = 0;
1133         txq->tx_tail = 0;
1134         txq->ctx_curr = 0;
1135         memset((void*)&txq->ctx_cache, 0,
1136                 IGB_CTX_NUM * sizeof(struct igb_advctx_info));
1137 }
1138
1139 static void
1140 igb_reset_tx_queue(struct igb_tx_queue *txq, struct rte_eth_dev *dev)
1141 {
1142         static const union e1000_adv_tx_desc zeroed_desc = { .read = {
1143                         .buffer_addr = 0}};
1144         struct igb_tx_entry *txe = txq->sw_ring;
1145         uint16_t i, prev;
1146         struct e1000_hw *hw;
1147
1148         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1149         /* Zero out HW ring memory */
1150         for (i = 0; i < txq->nb_tx_desc; i++) {
1151                 txq->tx_ring[i] = zeroed_desc;
1152         }
1153
1154         /* Initialize ring entries */
1155         prev = (uint16_t)(txq->nb_tx_desc - 1);
1156         for (i = 0; i < txq->nb_tx_desc; i++) {
1157                 volatile union e1000_adv_tx_desc *txd = &(txq->tx_ring[i]);
1158
1159                 txd->wb.status = E1000_TXD_STAT_DD;
1160                 txe[i].mbuf = NULL;
1161                 txe[i].last_id = i;
1162                 txe[prev].next_id = i;
1163                 prev = i;
1164         }
1165
1166         txq->txd_type = E1000_ADVTXD_DTYP_DATA;
1167         /* 82575 specific, each tx queue will use 2 hw contexts */
1168         if (hw->mac.type == e1000_82575)
1169                 txq->ctx_start = txq->queue_id * IGB_CTX_NUM;
1170
1171         igb_reset_tx_queue_stat(txq);
1172 }
1173
1174 int
1175 eth_igb_tx_queue_setup(struct rte_eth_dev *dev,
1176                          uint16_t queue_idx,
1177                          uint16_t nb_desc,
1178                          unsigned int socket_id,
1179                          const struct rte_eth_txconf *tx_conf)
1180 {
1181         const struct rte_memzone *tz;
1182         struct igb_tx_queue *txq;
1183         struct e1000_hw     *hw;
1184         uint32_t size;
1185
1186         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1187
1188         /*
1189          * Validate number of transmit descriptors.
1190          * It must not exceed hardware maximum, and must be multiple
1191          * of IGB_ALIGN.
1192          */
1193         if (((nb_desc * sizeof(union e1000_adv_tx_desc)) % IGB_ALIGN) != 0 ||
1194             (nb_desc > IGB_MAX_RING_DESC) || (nb_desc < IGB_MIN_RING_DESC)) {
1195                 return -EINVAL;
1196         }
1197
1198         /*
1199          * The tx_free_thresh and tx_rs_thresh values are not used in the 1G
1200          * driver.
1201          */
1202         if (tx_conf->tx_free_thresh != 0)
1203                 RTE_LOG(WARNING, PMD,
1204                         "The tx_free_thresh parameter is not "
1205                         "used for the 1G driver.\n");
1206         if (tx_conf->tx_rs_thresh != 0)
1207                 RTE_LOG(WARNING, PMD,
1208                         "The tx_rs_thresh parameter is not "
1209                         "used for the 1G driver.\n");
1210         if (tx_conf->tx_thresh.wthresh == 0)
1211                 RTE_LOG(WARNING, PMD,
1212                         "To improve 1G driver performance, consider setting "
1213                         "the TX WTHRESH value to 4, 8, or 16.\n");
1214
1215         /* Free memory prior to re-allocation if needed */
1216         if (dev->data->tx_queues[queue_idx] != NULL)
1217                 igb_tx_queue_release(dev->data->tx_queues[queue_idx]);
1218
1219         /* First allocate the tx queue data structure */
1220         txq = rte_zmalloc("ethdev TX queue", sizeof(struct igb_tx_queue),
1221                                                         CACHE_LINE_SIZE);
1222         if (txq == NULL)
1223                 return (-ENOMEM);
1224
1225         /*
1226          * Allocate TX ring hardware descriptors. A memzone large enough to
1227          * handle the maximum ring size is allocated in order to allow for
1228          * resizing in later calls to the queue setup function.
1229          */
1230         size = sizeof(union e1000_adv_tx_desc) * IGB_MAX_RING_DESC;
1231         tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1232                                         size, socket_id);
1233         if (tz == NULL) {
1234                 igb_tx_queue_release(txq);
1235                 return (-ENOMEM);
1236         }
1237
1238         txq->nb_tx_desc = nb_desc;
1239         txq->pthresh = tx_conf->tx_thresh.pthresh;
1240         txq->hthresh = tx_conf->tx_thresh.hthresh;
1241         txq->wthresh = tx_conf->tx_thresh.wthresh;
1242         txq->queue_id = queue_idx;
1243         txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1244                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1245         txq->port_id = dev->data->port_id;
1246
1247         txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(txq->reg_idx));
1248 #ifndef RTE_LIBRTE_XEN_DOM0
1249         txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1250 #else
1251         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1252 #endif
1253          txq->tx_ring = (union e1000_adv_tx_desc *) tz->addr;
1254         /* Allocate software ring */
1255         txq->sw_ring = rte_zmalloc("txq->sw_ring",
1256                                    sizeof(struct igb_tx_entry) * nb_desc,
1257                                    CACHE_LINE_SIZE);
1258         if (txq->sw_ring == NULL) {
1259                 igb_tx_queue_release(txq);
1260                 return (-ENOMEM);
1261         }
1262         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1263                      txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1264
1265         igb_reset_tx_queue(txq, dev);
1266         dev->tx_pkt_burst = eth_igb_xmit_pkts;
1267         dev->data->tx_queues[queue_idx] = txq;
1268
1269         return (0);
1270 }
1271
1272 static void
1273 igb_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1274 {
1275         unsigned i;
1276
1277         if (rxq->sw_ring != NULL) {
1278                 for (i = 0; i < rxq->nb_rx_desc; i++) {
1279                         if (rxq->sw_ring[i].mbuf != NULL) {
1280                                 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1281                                 rxq->sw_ring[i].mbuf = NULL;
1282                         }
1283                 }
1284         }
1285 }
1286
1287 static void
1288 igb_rx_queue_release(struct igb_rx_queue *rxq)
1289 {
1290         if (rxq != NULL) {
1291                 igb_rx_queue_release_mbufs(rxq);
1292                 rte_free(rxq->sw_ring);
1293                 rte_free(rxq);
1294         }
1295 }
1296
1297 void
1298 eth_igb_rx_queue_release(void *rxq)
1299 {
1300         igb_rx_queue_release(rxq);
1301 }
1302
1303 static void
1304 igb_reset_rx_queue(struct igb_rx_queue *rxq)
1305 {
1306         static const union e1000_adv_rx_desc zeroed_desc = { .read = {
1307                         .pkt_addr = 0}};
1308         unsigned i;
1309
1310         /* Zero out HW ring memory */
1311         for (i = 0; i < rxq->nb_rx_desc; i++) {
1312                 rxq->rx_ring[i] = zeroed_desc;
1313         }
1314
1315         rxq->rx_tail = 0;
1316         rxq->pkt_first_seg = NULL;
1317         rxq->pkt_last_seg = NULL;
1318 }
1319
1320 int
1321 eth_igb_rx_queue_setup(struct rte_eth_dev *dev,
1322                          uint16_t queue_idx,
1323                          uint16_t nb_desc,
1324                          unsigned int socket_id,
1325                          const struct rte_eth_rxconf *rx_conf,
1326                          struct rte_mempool *mp)
1327 {
1328         const struct rte_memzone *rz;
1329         struct igb_rx_queue *rxq;
1330         struct e1000_hw     *hw;
1331         unsigned int size;
1332
1333         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1334
1335         /*
1336          * Validate number of receive descriptors.
1337          * It must not exceed hardware maximum, and must be multiple
1338          * of IGB_ALIGN.
1339          */
1340         if (((nb_desc * sizeof(union e1000_adv_rx_desc)) % IGB_ALIGN) != 0 ||
1341             (nb_desc > IGB_MAX_RING_DESC) || (nb_desc < IGB_MIN_RING_DESC)) {
1342                 return (-EINVAL);
1343         }
1344
1345         /* Free memory prior to re-allocation if needed */
1346         if (dev->data->rx_queues[queue_idx] != NULL) {
1347                 igb_rx_queue_release(dev->data->rx_queues[queue_idx]);
1348                 dev->data->rx_queues[queue_idx] = NULL;
1349         }
1350
1351         /* First allocate the RX queue data structure. */
1352         rxq = rte_zmalloc("ethdev RX queue", sizeof(struct igb_rx_queue),
1353                           CACHE_LINE_SIZE);
1354         if (rxq == NULL)
1355                 return (-ENOMEM);
1356         rxq->mb_pool = mp;
1357         rxq->nb_rx_desc = nb_desc;
1358         rxq->pthresh = rx_conf->rx_thresh.pthresh;
1359         rxq->hthresh = rx_conf->rx_thresh.hthresh;
1360         rxq->wthresh = rx_conf->rx_thresh.wthresh;
1361         rxq->drop_en = rx_conf->rx_drop_en;
1362         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1363         rxq->queue_id = queue_idx;
1364         rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1365                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1366         rxq->port_id = dev->data->port_id;
1367         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
1368                                   ETHER_CRC_LEN);
1369
1370         /*
1371          *  Allocate RX ring hardware descriptors. A memzone large enough to
1372          *  handle the maximum ring size is allocated in order to allow for
1373          *  resizing in later calls to the queue setup function.
1374          */
1375         size = sizeof(union e1000_adv_rx_desc) * IGB_MAX_RING_DESC;
1376         rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx, size, socket_id);
1377         if (rz == NULL) {
1378                 igb_rx_queue_release(rxq);
1379                 return (-ENOMEM);
1380         }
1381         rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(rxq->reg_idx));
1382         rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(rxq->reg_idx));
1383 #ifndef RTE_LIBRTE_XEN_DOM0
1384         rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
1385 #else
1386         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1387 #endif
1388         rxq->rx_ring = (union e1000_adv_rx_desc *) rz->addr;
1389
1390         /* Allocate software ring. */
1391         rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1392                                    sizeof(struct igb_rx_entry) * nb_desc,
1393                                    CACHE_LINE_SIZE);
1394         if (rxq->sw_ring == NULL) {
1395                 igb_rx_queue_release(rxq);
1396                 return (-ENOMEM);
1397         }
1398         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1399                      rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1400
1401         dev->data->rx_queues[queue_idx] = rxq;
1402         igb_reset_rx_queue(rxq);
1403
1404         return 0;
1405 }
1406
1407 uint32_t
1408 eth_igb_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1409 {
1410 #define IGB_RXQ_SCAN_INTERVAL 4
1411         volatile union e1000_adv_rx_desc *rxdp;
1412         struct igb_rx_queue *rxq;
1413         uint32_t desc = 0;
1414
1415         if (rx_queue_id >= dev->data->nb_rx_queues) {
1416                 PMD_RX_LOG(ERR, "Invalid RX queue id=%d\n", rx_queue_id);
1417                 return 0;
1418         }
1419
1420         rxq = dev->data->rx_queues[rx_queue_id];
1421         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1422
1423         while ((desc < rxq->nb_rx_desc) &&
1424                 (rxdp->wb.upper.status_error & E1000_RXD_STAT_DD)) {
1425                 desc += IGB_RXQ_SCAN_INTERVAL;
1426                 rxdp += IGB_RXQ_SCAN_INTERVAL;
1427                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1428                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1429                                 desc - rxq->nb_rx_desc]);
1430         }
1431
1432         return 0;
1433 }
1434
1435 int
1436 eth_igb_rx_descriptor_done(void *rx_queue, uint16_t offset)
1437 {
1438         volatile union e1000_adv_rx_desc *rxdp;
1439         struct igb_rx_queue *rxq = rx_queue;
1440         uint32_t desc;
1441
1442         if (unlikely(offset >= rxq->nb_rx_desc))
1443                 return 0;
1444         desc = rxq->rx_tail + offset;
1445         if (desc >= rxq->nb_rx_desc)
1446                 desc -= rxq->nb_rx_desc;
1447
1448         rxdp = &rxq->rx_ring[desc];
1449         return !!(rxdp->wb.upper.status_error & E1000_RXD_STAT_DD);
1450 }
1451
1452 void
1453 igb_dev_clear_queues(struct rte_eth_dev *dev)
1454 {
1455         uint16_t i;
1456         struct igb_tx_queue *txq;
1457         struct igb_rx_queue *rxq;
1458
1459         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1460                 txq = dev->data->tx_queues[i];
1461                 if (txq != NULL) {
1462                         igb_tx_queue_release_mbufs(txq);
1463                         igb_reset_tx_queue(txq, dev);
1464                 }
1465         }
1466
1467         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1468                 rxq = dev->data->rx_queues[i];
1469                 if (rxq != NULL) {
1470                         igb_rx_queue_release_mbufs(rxq);
1471                         igb_reset_rx_queue(rxq);
1472                 }
1473         }
1474 }
1475
1476 /**
1477  * Receive Side Scaling (RSS).
1478  * See section 7.1.1.7 in the following document:
1479  *     "Intel 82576 GbE Controller Datasheet" - Revision 2.45 October 2009
1480  *
1481  * Principles:
1482  * The source and destination IP addresses of the IP header and the source and
1483  * destination ports of TCP/UDP headers, if any, of received packets are hashed
1484  * against a configurable random key to compute a 32-bit RSS hash result.
1485  * The seven (7) LSBs of the 32-bit hash result are used as an index into a
1486  * 128-entry redirection table (RETA).  Each entry of the RETA provides a 3-bit
1487  * RSS output index which is used as the RX queue index where to store the
1488  * received packets.
1489  * The following output is supplied in the RX write-back descriptor:
1490  *     - 32-bit result of the Microsoft RSS hash function,
1491  *     - 4-bit RSS type field.
1492  */
1493
1494 /*
1495  * RSS random key supplied in section 7.1.1.7.3 of the Intel 82576 datasheet.
1496  * Used as the default key.
1497  */
1498 static uint8_t rss_intel_key[40] = {
1499         0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
1500         0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
1501         0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
1502         0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
1503         0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
1504 };
1505
1506 static void
1507 igb_rss_disable(struct rte_eth_dev *dev)
1508 {
1509         struct e1000_hw *hw;
1510         uint32_t mrqc;
1511
1512         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1513         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1514         mrqc &= ~E1000_MRQC_ENABLE_MASK;
1515         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1516 }
1517
1518 static void
1519 igb_rss_configure(struct rte_eth_dev *dev)
1520 {
1521         struct e1000_hw *hw;
1522         uint8_t *hash_key;
1523         uint32_t rss_key;
1524         uint32_t mrqc;
1525         uint32_t shift;
1526         uint16_t rss_hf;
1527         uint16_t i;
1528
1529         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1530
1531         rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
1532         if (rss_hf == 0) /* Disable RSS. */ {
1533                 igb_rss_disable(dev);
1534                 return;
1535         }
1536         hash_key = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
1537         if (hash_key == NULL)
1538                 hash_key = rss_intel_key; /* Default hash key. */
1539
1540         /* Fill in RSS hash key. */
1541         for (i = 0; i < 10; i++) {
1542                 rss_key  = hash_key[(i * 4)];
1543                 rss_key |= hash_key[(i * 4) + 1] << 8;
1544                 rss_key |= hash_key[(i * 4) + 2] << 16;
1545                 rss_key |= hash_key[(i * 4) + 3] << 24;
1546                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key);
1547         }
1548
1549         /* Fill in redirection table. */
1550         shift = (hw->mac.type == e1000_82575) ? 6 : 0;
1551         for (i = 0; i < 128; i++) {
1552                 union e1000_reta {
1553                         uint32_t dword;
1554                         uint8_t  bytes[4];
1555                 } reta;
1556                 uint8_t q_idx;
1557
1558                 q_idx = (uint8_t) ((dev->data->nb_rx_queues > 1) ?
1559                                    i % dev->data->nb_rx_queues : 0);
1560                 reta.bytes[i & 3] = (uint8_t) (q_idx << shift);
1561                 if ((i & 3) == 3)
1562                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta.dword);
1563         }
1564
1565         /* Set configured hashing functions in MRQC register. */
1566         mrqc = E1000_MRQC_ENABLE_RSS_4Q; /* RSS enabled. */
1567         if (rss_hf & ETH_RSS_IPV4)
1568                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4;
1569         if (rss_hf & ETH_RSS_IPV4_TCP)
1570                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_TCP;
1571         if (rss_hf & ETH_RSS_IPV6)
1572                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6;
1573         if (rss_hf & ETH_RSS_IPV6_EX)
1574                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_EX;
1575         if (rss_hf & ETH_RSS_IPV6_TCP)
1576                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP;
1577         if (rss_hf & ETH_RSS_IPV6_TCP_EX)
1578                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
1579         if (rss_hf & ETH_RSS_IPV4_UDP)
1580                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
1581         if (rss_hf & ETH_RSS_IPV6_UDP)
1582                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
1583         if (rss_hf & ETH_RSS_IPV6_UDP_EX)
1584                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP_EX;
1585         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1586 }
1587
1588 /*
1589  * Check if the mac type support VMDq or not.
1590  * Return 1 if it supports, otherwise, return 0.
1591  */
1592 static int
1593 igb_is_vmdq_supported(const struct rte_eth_dev *dev)
1594 {
1595         const struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596
1597         switch (hw->mac.type) {
1598         case e1000_82576:
1599         case e1000_82580:
1600         case e1000_i350:
1601                 return 1;
1602         case e1000_82540:
1603         case e1000_82541:
1604         case e1000_82542:
1605         case e1000_82543:
1606         case e1000_82544:
1607         case e1000_82545:
1608         case e1000_82546:
1609         case e1000_82547:
1610         case e1000_82571:
1611         case e1000_82572:
1612         case e1000_82573:
1613         case e1000_82574:
1614         case e1000_82583:
1615         case e1000_i210:
1616         case e1000_i211:
1617         default:
1618                 PMD_INIT_LOG(ERR, "Cannot support VMDq feature\n");
1619                 return 0;
1620         }
1621 }
1622
1623 static int
1624 igb_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
1625 {
1626         struct rte_eth_vmdq_rx_conf *cfg;
1627         struct e1000_hw *hw;
1628         uint32_t mrqc, vt_ctl, vmolr, rctl;
1629         int i;
1630
1631         PMD_INIT_LOG(DEBUG, ">>");
1632         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1634
1635         /* Check if mac type can support VMDq, return value of 0 means NOT support */
1636         if (igb_is_vmdq_supported(dev) == 0)
1637                 return -1;
1638
1639         igb_rss_disable(dev);
1640
1641         /* RCTL: eanble VLAN filter */
1642         rctl = E1000_READ_REG(hw, E1000_RCTL);
1643         rctl |= E1000_RCTL_VFE;
1644         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1645
1646         /* MRQC: enable vmdq */
1647         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1648         mrqc |= E1000_MRQC_ENABLE_VMDQ;
1649         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1650
1651         /* VTCTL:  pool selection according to VLAN tag */
1652         vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
1653         if (cfg->enable_default_pool)
1654                 vt_ctl |= (cfg->default_pool << E1000_VT_CTL_DEFAULT_POOL_SHIFT);
1655         vt_ctl |= E1000_VT_CTL_IGNORE_MAC;
1656         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
1657
1658         /*
1659          * VMOLR: set STRVLAN as 1 if IGMAC in VTCTL is set as 1
1660          * Both 82576 and 82580 support it
1661          */
1662         if (hw->mac.type != e1000_i350) {
1663                 for (i = 0; i < E1000_VMOLR_SIZE; i++) {
1664                         vmolr = E1000_READ_REG(hw, E1000_VMOLR(i));
1665                         vmolr |= E1000_VMOLR_STRVLAN;
1666                         E1000_WRITE_REG(hw, E1000_VMOLR(i), vmolr);
1667                 }
1668         }
1669
1670         /* VFTA - enable all vlan filters */
1671         for (i = 0; i < IGB_VFTA_SIZE; i++)
1672                 E1000_WRITE_REG(hw, (E1000_VFTA+(i*4)), UINT32_MAX);
1673
1674         /* VFRE: 8 pools enabling for rx, both 82576 and i350 support it */
1675         if (hw->mac.type != e1000_82580)
1676                 E1000_WRITE_REG(hw, E1000_VFRE, E1000_MBVFICR_VFREQ_MASK);
1677
1678         /*
1679          * RAH/RAL - allow pools to read specific mac addresses
1680          * In this case, all pools should be able to read from mac addr 0
1681          */
1682         E1000_WRITE_REG(hw, E1000_RAH(0), (E1000_RAH_AV | UINT16_MAX));
1683         E1000_WRITE_REG(hw, E1000_RAL(0), UINT32_MAX);
1684
1685         /* VLVF: set up filters for vlan tags as configured */
1686         for (i = 0; i < cfg->nb_pool_maps; i++) {
1687                 /* set vlan id in VF register and set the valid bit */
1688                 E1000_WRITE_REG(hw, E1000_VLVF(i), (E1000_VLVF_VLANID_ENABLE | \
1689                         (cfg->pool_map[i].vlan_id & ETH_VLAN_ID_MAX) | \
1690                         ((cfg->pool_map[i].pools << E1000_VLVF_POOLSEL_SHIFT ) & \
1691                         E1000_VLVF_POOLSEL_MASK)));
1692         }
1693
1694         E1000_WRITE_FLUSH(hw);
1695
1696         return 0;
1697 }
1698
1699
1700 /*********************************************************************
1701  *
1702  *  Enable receive unit.
1703  *
1704  **********************************************************************/
1705
1706 static int
1707 igb_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
1708 {
1709         struct igb_rx_entry *rxe = rxq->sw_ring;
1710         uint64_t dma_addr;
1711         unsigned i;
1712
1713         /* Initialize software ring entries. */
1714         for (i = 0; i < rxq->nb_rx_desc; i++) {
1715                 volatile union e1000_adv_rx_desc *rxd;
1716                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
1717
1718                 if (mbuf == NULL) {
1719                         PMD_INIT_LOG(ERR, "RX mbuf alloc failed "
1720                                 "queue_id=%hu\n", rxq->queue_id);
1721                         igb_rx_queue_release(rxq);
1722                         return (-ENOMEM);
1723                 }
1724                 dma_addr =
1725                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
1726                 rxd = &rxq->rx_ring[i];
1727                 rxd->read.hdr_addr = dma_addr;
1728                 rxd->read.pkt_addr = dma_addr;
1729                 rxe[i].mbuf = mbuf;
1730         }
1731
1732         return 0;
1733 }
1734
1735 #define E1000_MRQC_DEF_Q_SHIFT               (3)
1736 static int
1737 igb_dev_mq_rx_configure(struct rte_eth_dev *dev)
1738 {
1739         struct e1000_hw *hw =
1740                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1741         uint32_t mrqc;
1742
1743         if (RTE_ETH_DEV_SRIOV(dev).active == ETH_8_POOLS) {
1744                 /*
1745                 * SRIOV active scheme
1746                 * FIXME if support RSS together with VMDq & SRIOV
1747                 */
1748                 mrqc = E1000_MRQC_ENABLE_VMDQ;
1749                 /* 011b Def_Q ignore, according to VT_CTL.DEF_PL */
1750                 mrqc |= 0x3 << E1000_MRQC_DEF_Q_SHIFT;
1751                 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1752         } else if(RTE_ETH_DEV_SRIOV(dev).active == 0) {
1753                 /*
1754                 * SRIOV inactive scheme
1755                 */
1756                 if (dev->data->nb_rx_queues > 1)
1757                         switch (dev->data->dev_conf.rxmode.mq_mode) {
1758                         case ETH_MQ_RX_NONE:
1759                                 /* if mq_mode not assign, we use rss mode.*/
1760                         case ETH_MQ_RX_RSS:
1761                                 igb_rss_configure(dev);
1762                                 break;
1763                         case ETH_MQ_RX_VMDQ_ONLY:
1764                                 /*Configure general VMDQ only RX parameters*/
1765                                 igb_vmdq_rx_hw_configure(dev);
1766                                 break;
1767                         default:
1768                                 igb_rss_disable(dev);
1769                                 break;
1770                         }
1771                 else
1772                         igb_rss_disable(dev);
1773         }
1774
1775         return 0;
1776 }
1777
1778 int
1779 eth_igb_rx_init(struct rte_eth_dev *dev)
1780 {
1781         struct e1000_hw     *hw;
1782         struct igb_rx_queue *rxq;
1783         struct rte_pktmbuf_pool_private *mbp_priv;
1784         uint32_t rctl;
1785         uint32_t rxcsum;
1786         uint32_t srrctl;
1787         uint16_t buf_size;
1788         uint16_t rctl_bsize;
1789         uint16_t i;
1790         int ret;
1791
1792         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1793         srrctl = 0;
1794
1795         /*
1796          * Make sure receives are disabled while setting
1797          * up the descriptor ring.
1798          */
1799         rctl = E1000_READ_REG(hw, E1000_RCTL);
1800         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
1801
1802         /*
1803          * Configure support of jumbo frames, if any.
1804          */
1805         if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
1806                 rctl |= E1000_RCTL_LPE;
1807
1808                 /*
1809                  * Set maximum packet length by default, and might be updated
1810                  * together with enabling/disabling dual VLAN.
1811                  */
1812                 E1000_WRITE_REG(hw, E1000_RLPML,
1813                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1814                                                 VLAN_TAG_SIZE);
1815         } else
1816                 rctl &= ~E1000_RCTL_LPE;
1817
1818         /* Configure and enable each RX queue. */
1819         rctl_bsize = 0;
1820         dev->rx_pkt_burst = eth_igb_recv_pkts;
1821         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1822                 uint64_t bus_addr;
1823                 uint32_t rxdctl;
1824
1825                 rxq = dev->data->rx_queues[i];
1826
1827                 /* Allocate buffers for descriptor rings and set up queue */
1828                 ret = igb_alloc_rx_queue_mbufs(rxq);
1829                 if (ret)
1830                         return ret;
1831
1832                 /*
1833                  * Reset crc_len in case it was changed after queue setup by a
1834                  *  call to configure
1835                  */
1836                 rxq->crc_len =
1837                         (uint8_t)(dev->data->dev_conf.rxmode.hw_strip_crc ?
1838                                                         0 : ETHER_CRC_LEN);
1839
1840                 bus_addr = rxq->rx_ring_phys_addr;
1841                 E1000_WRITE_REG(hw, E1000_RDLEN(rxq->reg_idx),
1842                                 rxq->nb_rx_desc *
1843                                 sizeof(union e1000_adv_rx_desc));
1844                 E1000_WRITE_REG(hw, E1000_RDBAH(rxq->reg_idx),
1845                                 (uint32_t)(bus_addr >> 32));
1846                 E1000_WRITE_REG(hw, E1000_RDBAL(rxq->reg_idx), (uint32_t)bus_addr);
1847
1848                 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1849
1850                 /*
1851                  * Configure RX buffer size.
1852                  */
1853                 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
1854                 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
1855                                        RTE_PKTMBUF_HEADROOM);
1856                 if (buf_size >= 1024) {
1857                         /*
1858                          * Configure the BSIZEPACKET field of the SRRCTL
1859                          * register of the queue.
1860                          * Value is in 1 KB resolution, from 1 KB to 127 KB.
1861                          * If this field is equal to 0b, then RCTL.BSIZE
1862                          * determines the RX packet buffer size.
1863                          */
1864                         srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
1865                                    E1000_SRRCTL_BSIZEPKT_MASK);
1866                         buf_size = (uint16_t) ((srrctl &
1867                                                 E1000_SRRCTL_BSIZEPKT_MASK) <<
1868                                                E1000_SRRCTL_BSIZEPKT_SHIFT);
1869
1870                         /* It adds dual VLAN length for supporting dual VLAN */
1871                         if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
1872                                                 2 * VLAN_TAG_SIZE) > buf_size){
1873                                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
1874                                 dev->data->scattered_rx = 1;
1875                         }
1876                 } else {
1877                         /*
1878                          * Use BSIZE field of the device RCTL register.
1879                          */
1880                         if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
1881                                 rctl_bsize = buf_size;
1882                         dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
1883                         dev->data->scattered_rx = 1;
1884                 }
1885
1886                 /* Set if packets are dropped when no descriptors available */
1887                 if (rxq->drop_en)
1888                         srrctl |= E1000_SRRCTL_DROP_EN;
1889
1890                 E1000_WRITE_REG(hw, E1000_SRRCTL(rxq->reg_idx), srrctl);
1891
1892                 /* Enable this RX queue. */
1893                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rxq->reg_idx));
1894                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1895                 rxdctl &= 0xFFF00000;
1896                 rxdctl |= (rxq->pthresh & 0x1F);
1897                 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
1898                 rxdctl |= ((rxq->wthresh & 0x1F) << 16);
1899                 E1000_WRITE_REG(hw, E1000_RXDCTL(rxq->reg_idx), rxdctl);
1900         }
1901
1902         /*
1903          * Setup BSIZE field of RCTL register, if needed.
1904          * Buffer sizes >= 1024 are not [supposed to be] setup in the RCTL
1905          * register, since the code above configures the SRRCTL register of
1906          * the RX queue in such a case.
1907          * All configurable sizes are:
1908          * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);
1909          *  8192: rctl |= (E1000_RCTL_SZ_8192  | E1000_RCTL_BSEX);
1910          *  4096: rctl |= (E1000_RCTL_SZ_4096  | E1000_RCTL_BSEX);
1911          *  2048: rctl |= E1000_RCTL_SZ_2048;
1912          *  1024: rctl |= E1000_RCTL_SZ_1024;
1913          *   512: rctl |= E1000_RCTL_SZ_512;
1914          *   256: rctl |= E1000_RCTL_SZ_256;
1915          */
1916         if (rctl_bsize > 0) {
1917                 if (rctl_bsize >= 512) /* 512 <= buf_size < 1024 - use 512 */
1918                         rctl |= E1000_RCTL_SZ_512;
1919                 else /* 256 <= buf_size < 512 - use 256 */
1920                         rctl |= E1000_RCTL_SZ_256;
1921         }
1922
1923         /*
1924          * Configure RSS if device configured with multiple RX queues.
1925          */
1926         igb_dev_mq_rx_configure(dev);
1927
1928         /* Update the rctl since igb_dev_mq_rx_configure may change its value */
1929         rctl |= E1000_READ_REG(hw, E1000_RCTL);
1930
1931         /*
1932          * Setup the Checksum Register.
1933          * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
1934          */
1935         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
1936         rxcsum |= E1000_RXCSUM_PCSD;
1937
1938         /* Enable both L3/L4 rx checksum offload */
1939         if (dev->data->dev_conf.rxmode.hw_ip_checksum)
1940                 rxcsum |= (E1000_RXCSUM_IPOFL  | E1000_RXCSUM_TUOFL);
1941         else
1942                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
1943         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
1944
1945         /* Setup the Receive Control Register. */
1946         if (dev->data->dev_conf.rxmode.hw_strip_crc) {
1947                 rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */
1948
1949                 /* set STRCRC bit in all queues */
1950                 if (hw->mac.type == e1000_i350 ||
1951                     hw->mac.type == e1000_i210 ||
1952                     hw->mac.type == e1000_i211 ||
1953                     hw->mac.type == e1000_i354) {
1954                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1955                                 rxq = dev->data->rx_queues[i];
1956                                 uint32_t dvmolr = E1000_READ_REG(hw,
1957                                         E1000_DVMOLR(rxq->reg_idx));
1958                                 dvmolr |= E1000_DVMOLR_STRCRC;
1959                                 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
1960                         }
1961                 }
1962         } else {
1963                 rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
1964
1965                 /* clear STRCRC bit in all queues */
1966                 if (hw->mac.type == e1000_i350 ||
1967                     hw->mac.type == e1000_i210 ||
1968                     hw->mac.type == e1000_i211 ||
1969                     hw->mac.type == e1000_i354) {
1970                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1971                                 rxq = dev->data->rx_queues[i];
1972                                 uint32_t dvmolr = E1000_READ_REG(hw,
1973                                         E1000_DVMOLR(rxq->reg_idx));
1974                                 dvmolr &= ~E1000_DVMOLR_STRCRC;
1975                                 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
1976                         }
1977                 }
1978         }
1979
1980         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1981         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
1982                 E1000_RCTL_RDMTS_HALF |
1983                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1984
1985         /* Make sure VLAN Filters are off. */
1986         if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_VMDQ_ONLY)
1987                 rctl &= ~E1000_RCTL_VFE;
1988         /* Don't store bad packets. */
1989         rctl &= ~E1000_RCTL_SBP;
1990
1991         /* Enable Receives. */
1992         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1993
1994         /*
1995          * Setup the HW Rx Head and Tail Descriptor Pointers.
1996          * This needs to be done after enable.
1997          */
1998         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1999                 rxq = dev->data->rx_queues[i];
2000                 E1000_WRITE_REG(hw, E1000_RDH(rxq->reg_idx), 0);
2001                 E1000_WRITE_REG(hw, E1000_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
2002         }
2003
2004         return 0;
2005 }
2006
2007 /*********************************************************************
2008  *
2009  *  Enable transmit unit.
2010  *
2011  **********************************************************************/
2012 void
2013 eth_igb_tx_init(struct rte_eth_dev *dev)
2014 {
2015         struct e1000_hw     *hw;
2016         struct igb_tx_queue *txq;
2017         uint32_t tctl;
2018         uint32_t txdctl;
2019         uint16_t i;
2020
2021         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022
2023         /* Setup the Base and Length of the Tx Descriptor Rings. */
2024         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2025                 uint64_t bus_addr;
2026                 txq = dev->data->tx_queues[i];
2027                 bus_addr = txq->tx_ring_phys_addr;
2028
2029                 E1000_WRITE_REG(hw, E1000_TDLEN(txq->reg_idx),
2030                                 txq->nb_tx_desc *
2031                                 sizeof(union e1000_adv_tx_desc));
2032                 E1000_WRITE_REG(hw, E1000_TDBAH(txq->reg_idx),
2033                                 (uint32_t)(bus_addr >> 32));
2034                 E1000_WRITE_REG(hw, E1000_TDBAL(txq->reg_idx), (uint32_t)bus_addr);
2035
2036                 /* Setup the HW Tx Head and Tail descriptor pointers. */
2037                 E1000_WRITE_REG(hw, E1000_TDT(txq->reg_idx), 0);
2038                 E1000_WRITE_REG(hw, E1000_TDH(txq->reg_idx), 0);
2039
2040                 /* Setup Transmit threshold registers. */
2041                 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(txq->reg_idx));
2042                 txdctl |= txq->pthresh & 0x1F;
2043                 txdctl |= ((txq->hthresh & 0x1F) << 8);
2044                 txdctl |= ((txq->wthresh & 0x1F) << 16);
2045                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2046                 E1000_WRITE_REG(hw, E1000_TXDCTL(txq->reg_idx), txdctl);
2047         }
2048
2049         /* Program the Transmit Control Register. */
2050         tctl = E1000_READ_REG(hw, E1000_TCTL);
2051         tctl &= ~E1000_TCTL_CT;
2052         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2053                  (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
2054
2055         e1000_config_collision_dist(hw);
2056
2057         /* This write will effectively turn on the transmit unit. */
2058         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2059 }
2060
2061 /*********************************************************************
2062  *
2063  *  Enable VF receive unit.
2064  *
2065  **********************************************************************/
2066 int
2067 eth_igbvf_rx_init(struct rte_eth_dev *dev)
2068 {
2069         struct e1000_hw     *hw;
2070         struct igb_rx_queue *rxq;
2071         struct rte_pktmbuf_pool_private *mbp_priv;
2072         uint32_t srrctl;
2073         uint16_t buf_size;
2074         uint16_t rctl_bsize;
2075         uint16_t i;
2076         int ret;
2077
2078         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079
2080         /* Configure and enable each RX queue. */
2081         rctl_bsize = 0;
2082         dev->rx_pkt_burst = eth_igb_recv_pkts;
2083         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2084                 uint64_t bus_addr;
2085                 uint32_t rxdctl;
2086
2087                 rxq = dev->data->rx_queues[i];
2088
2089                 /* Allocate buffers for descriptor rings and set up queue */
2090                 ret = igb_alloc_rx_queue_mbufs(rxq);
2091                 if (ret)
2092                         return ret;
2093
2094                 bus_addr = rxq->rx_ring_phys_addr;
2095                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2096                                 rxq->nb_rx_desc *
2097                                 sizeof(union e1000_adv_rx_desc));
2098                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2099                                 (uint32_t)(bus_addr >> 32));
2100                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
2101
2102                 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2103
2104                 /*
2105                  * Configure RX buffer size.
2106                  */
2107                 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
2108                 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
2109                                        RTE_PKTMBUF_HEADROOM);
2110                 if (buf_size >= 1024) {
2111                         /*
2112                          * Configure the BSIZEPACKET field of the SRRCTL
2113                          * register of the queue.
2114                          * Value is in 1 KB resolution, from 1 KB to 127 KB.
2115                          * If this field is equal to 0b, then RCTL.BSIZE
2116                          * determines the RX packet buffer size.
2117                          */
2118                         srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
2119                                    E1000_SRRCTL_BSIZEPKT_MASK);
2120                         buf_size = (uint16_t) ((srrctl &
2121                                                 E1000_SRRCTL_BSIZEPKT_MASK) <<
2122                                                E1000_SRRCTL_BSIZEPKT_SHIFT);
2123
2124                         /* It adds dual VLAN length for supporting dual VLAN */
2125                         if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
2126                                                 2 * VLAN_TAG_SIZE) > buf_size){
2127                                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2128                                 dev->data->scattered_rx = 1;
2129                         }
2130                 } else {
2131                         /*
2132                          * Use BSIZE field of the device RCTL register.
2133                          */
2134                         if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
2135                                 rctl_bsize = buf_size;
2136                         dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2137                         dev->data->scattered_rx = 1;
2138                 }
2139
2140                 /* Set if packets are dropped when no descriptors available */
2141                 if (rxq->drop_en)
2142                         srrctl |= E1000_SRRCTL_DROP_EN;
2143
2144                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2145
2146                 /* Enable this RX queue. */
2147                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2148                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2149                 rxdctl &= 0xFFF00000;
2150                 rxdctl |= (rxq->pthresh & 0x1F);
2151                 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
2152                 if (hw->mac.type == e1000_82576) {
2153                         /*
2154                          * Workaround of 82576 VF Erratum
2155                          * force set WTHRESH to 1
2156                          * to avoid Write-Back not triggered sometimes
2157                          */
2158                         rxdctl |= 0x10000;
2159                         PMD_INIT_LOG(DEBUG, "Force set RX WTHRESH to 1 !\n");
2160                 }
2161                 else
2162                         rxdctl |= ((rxq->wthresh & 0x1F) << 16);
2163                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2164         }
2165
2166         /*
2167          * Setup the HW Rx Head and Tail Descriptor Pointers.
2168          * This needs to be done after enable.
2169          */
2170         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2171                 rxq = dev->data->rx_queues[i];
2172                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
2173                 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
2174         }
2175
2176         return 0;
2177 }
2178
2179 /*********************************************************************
2180  *
2181  *  Enable VF transmit unit.
2182  *
2183  **********************************************************************/
2184 void
2185 eth_igbvf_tx_init(struct rte_eth_dev *dev)
2186 {
2187         struct e1000_hw     *hw;
2188         struct igb_tx_queue *txq;
2189         uint32_t txdctl;
2190         uint16_t i;
2191
2192         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193
2194         /* Setup the Base and Length of the Tx Descriptor Rings. */
2195         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2196                 uint64_t bus_addr;
2197
2198                 txq = dev->data->tx_queues[i];
2199                 bus_addr = txq->tx_ring_phys_addr;
2200                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2201                                 txq->nb_tx_desc *
2202                                 sizeof(union e1000_adv_tx_desc));
2203                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2204                                 (uint32_t)(bus_addr >> 32));
2205                 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
2206
2207                 /* Setup the HW Tx Head and Tail descriptor pointers. */
2208                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2209                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2210
2211                 /* Setup Transmit threshold registers. */
2212                 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
2213                 txdctl |= txq->pthresh & 0x1F;
2214                 txdctl |= ((txq->hthresh & 0x1F) << 8);
2215                 if (hw->mac.type == e1000_82576) {
2216                         /*
2217                          * Workaround of 82576 VF Erratum
2218                          * force set WTHRESH to 1
2219                          * to avoid Write-Back not triggered sometimes
2220                          */
2221                         txdctl |= 0x10000;
2222                         PMD_INIT_LOG(DEBUG, "Force set TX WTHRESH to 1 !\n");
2223                 }
2224                 else
2225                         txdctl |= ((txq->wthresh & 0x1F) << 16);
2226                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2227                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2228         }
2229
2230 }
2231