lib/librte_pmd_igb/e1000_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  *  version: DPDK.L.1.2.3-3
  34  */
  35
  36 #include <sys/queue.h>
  37 #include <stdio.h>
  38 #include <errno.h>
  39 #include <stdint.h>
  40 #include <stdarg.h>
  41
  42 #include <rte_common.h>
  43 #include <rte_interrupts.h>
  44 #include <rte_byteorder.h>
  45 #include <rte_log.h>
  46 #include <rte_debug.h>
  47 #include <rte_pci.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_memory.h>
  51 #include <rte_memzone.h>
  52 #include <rte_tailq.h>
  53 #include <rte_eal.h>
  54 #include <rte_atomic.h>
  55 #include <rte_malloc.h>
  56
  57 #include "e1000_logs.h"
  58 #include "igb/e1000_api.h"
  59 #include "igb/e1000_hw.h"
  60 #include "e1000_ethdev.h"
  61
  62 static int  eth_igb_configure(struct rte_eth_dev *dev, uint16_t nb_rx_q,
  63                 uint16_t nb_tx_q);
  64 static int  eth_igb_start(struct rte_eth_dev *dev);
  65 static void eth_igb_stop(struct rte_eth_dev *dev);
  66 static void eth_igb_close(struct rte_eth_dev *dev);
  67 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  68 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  69 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  70 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  71 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  72                                 int wait_to_complete);
  73 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  74                                 struct rte_eth_stats *rte_stats);
  75 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  76 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  77                                 struct rte_eth_dev_info *dev_info);
  78 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  79                                 struct rte_eth_fc_conf *fc_conf);
  80 static int eth_igb_interrupt_setup(struct rte_eth_dev *dev);
  81 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  82 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  83 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  84                                                         void *param);
  85 static int  igb_hardware_init(struct e1000_hw *hw);
  86 static void igb_hw_control_acquire(struct e1000_hw *hw);
  87 static void igb_hw_control_release(struct e1000_hw *hw);
  88 static void igb_init_manageability(struct e1000_hw *hw);
  89 static void igb_release_manageability(struct e1000_hw *hw);
  90 static void igb_vlan_hw_support_enable(struct rte_eth_dev *dev);
  91 static void igb_vlan_hw_support_disable(struct rte_eth_dev *dev);
  92 static void eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  93                                       uint16_t vlan_id,
  94                                       int on);
  95 static int eth_igb_led_on(struct rte_eth_dev *dev);
  96 static int eth_igb_led_off(struct rte_eth_dev *dev);
  97
  98 static void igb_intr_disable(struct e1000_hw *hw);
  99 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 100 static void eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 101                 uint32_t index, uint32_t pool);
 102 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 103
 104 #define IGB_FC_PAUSE_TIME 0x0680
 105 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 106 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 107
 108 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 109
 110 /*
 111  * The set of PCI devices this driver supports
 112  */
 113 static struct rte_pci_id pci_id_igb_map[] = {
 114
 115 #undef RTE_LIBRTE_IXGBE_PMD
 116 #define RTE_PCI_DEV_ID_DECL(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 117 #include "rte_pci_dev_ids.h"
 118
 119 {.device_id = 0},
 120 };
 121
 122 static struct eth_dev_ops eth_igb_ops = {
 123         .dev_configure        = eth_igb_configure,
 124         .dev_start            = eth_igb_start,
 125         .dev_stop             = eth_igb_stop,
 126         .dev_close            = eth_igb_close,
 127         .promiscuous_enable   = eth_igb_promiscuous_enable,
 128         .promiscuous_disable  = eth_igb_promiscuous_disable,
 129         .allmulticast_enable  = eth_igb_allmulticast_enable,
 130         .allmulticast_disable = eth_igb_allmulticast_disable,
 131         .link_update          = eth_igb_link_update,
 132         .stats_get            = eth_igb_stats_get,
 133         .stats_reset          = eth_igb_stats_reset,
 134         .dev_infos_get        = eth_igb_infos_get,
 135         .vlan_filter_set      = eth_igb_vlan_filter_set,
 136         .rx_queue_setup       = eth_igb_rx_queue_setup,
 137         .tx_queue_setup       = eth_igb_tx_queue_setup,
 138         .dev_led_on           = eth_igb_led_on,
 139         .dev_led_off          = eth_igb_led_off,
 140         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 141         .mac_addr_add         = eth_igb_rar_set,
 142         .mac_addr_remove      = eth_igb_rar_clear,
 143 };
 144
 145 /**
 146  * Atomically reads the link status information from global
 147  * structure rte_eth_dev.
 148  *
 149  * @param dev
 150  *   - Pointer to the structure rte_eth_dev to read from.
 151  *   - Pointer to the buffer to be saved with the link status.
 152  *
 153  * @return
 154  *   - On success, zero.
 155  *   - On failure, negative value.
 156  */
 157 static inline int
 158 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 159                                 struct rte_eth_link *link)
 160 {
 161         struct rte_eth_link *dst = link;
 162         struct rte_eth_link *src = &(dev->data->dev_link);
 163
 164         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 165                                         *(uint64_t *)src) == 0)
 166                 return -1;
 167
 168         return 0;
 169 }
 170
 171 /**
 172  * Atomically writes the link status information into global
 173  * structure rte_eth_dev.
 174  *
 175  * @param dev
 176  *   - Pointer to the structure rte_eth_dev to read from.
 177  *   - Pointer to the buffer to be saved with the link status.
 178  *
 179  * @return
 180  *   - On success, zero.
 181  *   - On failure, negative value.
 182  */
 183 static inline int
 184 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 185                                 struct rte_eth_link *link)
 186 {
 187         struct rte_eth_link *dst = &(dev->data->dev_link);
 188         struct rte_eth_link *src = link;
 189
 190         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 191                                         *(uint64_t *)src) == 0)
 192                 return -1;
 193
 194         return 0;
 195 }
 196
 197 static void
 198 igb_identify_hardware(struct rte_eth_dev *dev)
 199 {
 200         struct e1000_hw *hw =
 201                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 202
 203         hw->vendor_id = dev->pci_dev->id.vendor_id;
 204         hw->device_id = dev->pci_dev->id.device_id;
 205         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 206         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 207
 208         e1000_set_mac_type(hw);
 209
 210         /* need to check if it is a vf device below */
 211 }
 212
 213 static int
 214 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 215                    struct rte_eth_dev *eth_dev)
 216 {
 217         int error = 0;
 218         struct rte_pci_device *pci_dev;
 219         struct e1000_hw *hw =
 220                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 221         struct e1000_vfta * shadow_vfta =
 222                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 223
 224         pci_dev = eth_dev->pci_dev;
 225         eth_dev->dev_ops = &eth_igb_ops;
 226         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 227         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 228
 229         /* for secondary processes, we don't initialise any further as primary
 230          * has already done this work. Only check we don't need a different
 231          * RX function */
 232         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 233                 if (eth_dev->data->scattered_rx)
 234                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 235                 return 0;
 236         }
 237
 238         hw->hw_addr= (void *)pci_dev->mem_resource.addr;
 239
 240         igb_identify_hardware(eth_dev);
 241
 242         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 243                 error = -EIO;
 244                 goto err_late;
 245         }
 246
 247         e1000_get_bus_info(hw);
 248
 249         hw->mac.autoneg = 1;
 250         hw->phy.autoneg_wait_to_complete = 0;
 251         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 252
 253         /* Copper options */
 254         if (hw->phy.media_type == e1000_media_type_copper) {
 255                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 256                 hw->phy.disable_polarity_correction = 0;
 257                 hw->phy.ms_type = e1000_ms_hw_default;
 258         }
 259
 260         /*
 261          * Start from a known state, this is important in reading the nvm
 262          * and mac from that.
 263          */
 264         e1000_reset_hw(hw);
 265
 266         /* Make sure we have a good EEPROM before we read from it */
 267         if (e1000_validate_nvm_checksum(hw) < 0) {
 268                 /*
 269                  * Some PCI-E parts fail the first check due to
 270                  * the link being in sleep state, call it again,
 271                  * if it fails a second time its a real issue.
 272                  */
 273                 if (e1000_validate_nvm_checksum(hw) < 0) {
 274                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 275                         error = -EIO;
 276                         goto err_late;
 277                 }
 278         }
 279
 280         /* Read the permanent MAC address out of the EEPROM */
 281         if (e1000_read_mac_addr(hw) != 0) {
 282                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 283                 error = -EIO;
 284                 goto err_late;
 285         }
 286
 287         /* Allocate memory for storing MAC addresses */
 288         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 289                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 290         if (eth_dev->data->mac_addrs == NULL) {
 291                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 292                                                 "store MAC addresses",
 293                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 294                 error = -ENOMEM;
 295                 goto err_late;
 296         }
 297
 298         /* Copy the permanent MAC address */
 299         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 300
 301         /* initialize the vfta */
 302         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 303
 304         /* Now initialize the hardware */
 305         if (igb_hardware_init(hw) != 0) {
 306                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 307                 rte_free(eth_dev->data->mac_addrs);
 308                 eth_dev->data->mac_addrs = NULL;
 309                 error = -ENODEV;
 310                 goto err_late;
 311         }
 312         hw->mac.get_link_status = 1;
 313
 314         /* Indicate SOL/IDER usage */
 315         if (e1000_check_reset_block(hw) < 0) {
 316                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 317                                         "SOL/IDER session");
 318         }
 319
 320         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 321                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 322                      pci_dev->id.device_id);
 323
 324         rte_intr_callback_register(&(pci_dev->intr_handle),
 325                 eth_igb_interrupt_handler, (void *)eth_dev);
 326
 327         return 0;
 328
 329 err_late:
 330         igb_hw_control_release(hw);
 331
 332         return (error);
 333 }
 334
 335 static struct eth_driver rte_igb_pmd = {
 336         {
 337                 .name = "rte_igb_pmd",
 338                 .id_table = pci_id_igb_map,
 339                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 340         },
 341         .eth_dev_init = eth_igb_dev_init,
 342         .dev_private_size = sizeof(struct e1000_adapter),
 343 };
 344
 345 int
 346 rte_igb_pmd_init(void)
 347 {
 348         rte_eth_driver_register(&rte_igb_pmd);
 349         return 0;
 350 }
 351
 352 static int
 353 eth_igb_configure(struct rte_eth_dev *dev, uint16_t nb_rx_q, uint16_t nb_tx_q)
 354 {
 355         struct e1000_interrupt *intr =
 356                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 357         int diag;
 358
 359         PMD_INIT_LOG(DEBUG, ">>");
 360
 361         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 362
 363         /* Allocate the array of pointers to RX structures */
 364         diag = igb_dev_rx_queue_alloc(dev, nb_rx_q);
 365         if (diag != 0) {
 366                 PMD_INIT_LOG(ERR, "ethdev port_id=%u allocation of array of %u"
 367                                         " pointers to RX queues failed",
 368                                         dev->data->port_id, nb_rx_q);
 369                 return diag;
 370         }
 371
 372         /* Allocate the array of pointers to TX structures */
 373         diag = igb_dev_tx_queue_alloc(dev, nb_tx_q);
 374         if (diag != 0) {
 375                 PMD_INIT_LOG(ERR, "ethdev port_id=%u allocation of array of %u"
 376                                         " pointers to TX queues failed",
 377                                         dev->data->port_id, nb_tx_q);
 378
 379                 return diag;
 380         }
 381
 382         PMD_INIT_LOG(DEBUG, "<<");
 383
 384         return (0);
 385 }
 386
 387 static int
 388 eth_igb_start(struct rte_eth_dev *dev)
 389 {
 390         struct e1000_hw *hw =
 391                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 392         int ret, i;
 393
 394         PMD_INIT_LOG(DEBUG, ">>");
 395
 396         igb_intr_disable(hw);
 397
 398         /* Power up the phy. Needed to make the link go Up */
 399         e1000_power_up_phy(hw);
 400
 401         /*
 402          * Packet Buffer Allocation (PBA)
 403          * Writing PBA sets the receive portion of the buffer
 404          * the remainder is used for the transmit buffer.
 405          */
 406         if (hw->mac.type == e1000_82575) {
 407                 uint32_t pba;
 408
 409                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 410                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 411         }
 412
 413         /* Put the address into the Receive Address Array */
 414         e1000_rar_set(hw, hw->mac.addr, 0);
 415
 416         /* Initialize the hardware */
 417         if (igb_hardware_init(hw)) {
 418                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 419                 return (-1);
 420         }
 421
 422         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 423
 424         /* Configure for OS presence */
 425         igb_init_manageability(hw);
 426
 427         eth_igb_tx_init(dev);
 428
 429         /* This can fail when allocating mbufs for descriptor rings */
 430         ret = eth_igb_rx_init(dev);
 431         if (ret) {
 432                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 433                 return ret;
 434         }
 435
 436         e1000_clear_hw_cntrs_base_generic(hw);
 437
 438         /*
 439          * If VLAN filtering is enabled, set up VLAN tag offload and filtering
 440          * and restore the VFTA.
 441          */
 442         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
 443                 igb_vlan_hw_support_enable(dev);
 444         else
 445                 igb_vlan_hw_support_disable(dev);
 446
 447         /*
 448          * Configure the Interrupt Moderation register (EITR) with the maximum
 449          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 450          * spurious [DMA] memory updates of RX and TX ring descriptors.
 451          *
 452          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 453          * spurious memory updates per second should be expected.
 454          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 455          *
 456          * Because interrupts are not used at all, the MSI-X is not activated
 457          * and interrupt moderation is controlled by EITR[0].
 458          *
 459          * Note that having [almost] disabled memory updates of RX and TX ring
 460          * descriptors through the Interrupt Moderation mechanism, memory
 461          * updates of ring descriptors are now moderated by the configurable
 462          * value of Write-Back Threshold registers.
 463          */
 464         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 465                         (hw->mac.type == e1000_i350)) {
 466                 uint32_t ivar;
 467
 468                 /* Enable all RX & TX queues in the IVAR registers */
 469                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 470                 for (i = 0; i < 8; i++)
 471                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 472
 473                 /* Configure EITR with the maximum possible value (0xFFFF) */
 474                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 475         }
 476
 477         /* Don't reset the phy next time init gets called */
 478         hw->phy.reset_disable = 1;
 479
 480         /* Setup link speed and duplex */
 481         switch (dev->data->dev_conf.link_speed) {
 482         case ETH_LINK_SPEED_AUTONEG:
 483                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 484                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 485                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 486                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 487                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 488                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 489                 else
 490                         goto error_invalid_config;
 491                 break;
 492         case ETH_LINK_SPEED_10:
 493                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 494                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 495                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 496                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 497                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 498                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 499                 else
 500                         goto error_invalid_config;
 501                 break;
 502         case ETH_LINK_SPEED_100:
 503                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 504                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 505                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 506                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 507                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 508                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 509                 else
 510                         goto error_invalid_config;
 511                 break;
 512         case ETH_LINK_SPEED_1000:
 513                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 514                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 515                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 516                 else
 517                         goto error_invalid_config;
 518                 break;
 519         case ETH_LINK_SPEED_10000:
 520         default:
 521                 goto error_invalid_config;
 522         }
 523         e1000_setup_link(hw);
 524
 525         PMD_INIT_LOG(DEBUG, "<<");
 526
 527         /* check if lsc interrupt feature is enabled */
 528         if (dev->data->dev_conf.intr_conf.lsc != 0)
 529                 return eth_igb_interrupt_setup(dev);
 530
 531         return (0);
 532
 533 error_invalid_config:
 534         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 535                         dev->data->dev_conf.link_speed,
 536                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 537         return -1;
 538 }
 539
 540 /*********************************************************************
 541  *
 542  *  This routine disables all traffic on the adapter by issuing a
 543  *  global reset on the MAC.
 544  *
 545  **********************************************************************/
 546 static void
 547 eth_igb_stop(struct rte_eth_dev *dev)
 548 {
 549         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 550         struct rte_eth_link link;
 551
 552         igb_intr_disable(hw);
 553         e1000_reset_hw(hw);
 554         E1000_WRITE_REG(hw, E1000_WUC, 0);
 555
 556         /* Power down the phy. Needed to make the link go Down */
 557         e1000_power_down_phy(hw);
 558
 559         igb_dev_clear_queues(dev);
 560
 561         /* clear the recorded link status */
 562         memset(&link, 0, sizeof(link));
 563         rte_igb_dev_atomic_write_link_status(dev, &link);
 564 }
 565
 566 static void
 567 eth_igb_close(struct rte_eth_dev *dev)
 568 {
 569         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 570         struct rte_eth_link link;
 571
 572         eth_igb_stop(dev);
 573         e1000_phy_hw_reset(hw);
 574         igb_release_manageability(hw);
 575         igb_hw_control_release(hw);
 576
 577         igb_dev_clear_queues(dev);
 578
 579         memset(&link, 0, sizeof(link));
 580         rte_igb_dev_atomic_write_link_status(dev, &link);
 581 }
 582
 583 static int
 584 igb_get_rx_buffer_size(struct e1000_hw *hw)
 585 {
 586         uint32_t rx_buf_size;
 587         if (hw->mac.type == e1000_82576) {
 588                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 589         } else if (hw->mac.type == e1000_82580) {
 590                 /* PBS needs to be translated according to a lookup table */
 591                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 592                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 593                 rx_buf_size = (rx_buf_size << 10);
 594         } else {
 595                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 596         }
 597
 598         return rx_buf_size;
 599 }
 600
 601 /*********************************************************************
 602  *
 603  *  Initialize the hardware
 604  *
 605  **********************************************************************/
 606 static int
 607 igb_hardware_init(struct e1000_hw *hw)
 608 {
 609         uint32_t rx_buf_size;
 610         int diag;
 611
 612         /* Let the firmware know the OS is in control */
 613         igb_hw_control_acquire(hw);
 614
 615         /*
 616          * These parameters control the automatic generation (Tx) and
 617          * response (Rx) to Ethernet PAUSE frames.
 618          * - High water mark should allow for at least two standard size (1518)
 619          *   frames to be received after sending an XOFF.
 620          * - Low water mark works best when it is very near the high water mark.
 621          *   This allows the receiver to restart by sending XON when it has
 622          *   drained a bit. Here we use an arbitary value of 1500 which will
 623          *   restart after one full frame is pulled from the buffer. There
 624          *   could be several smaller frames in the buffer and if so they will
 625          *   not trigger the XON until their total number reduces the buffer
 626          *   by 1500.
 627          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 628          */
 629         rx_buf_size = igb_get_rx_buffer_size(hw);
 630
 631         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
 632         hw->fc.low_water = hw->fc.high_water - 1500;
 633         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
 634         hw->fc.send_xon = 1;
 635
 636         /* Set Flow control, use the tunable location if sane */
 637         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
 638                 hw->fc.requested_mode = igb_fc_setting;
 639         else
 640                 hw->fc.requested_mode = e1000_fc_none;
 641
 642         /* Issue a global reset */
 643         e1000_reset_hw(hw);
 644         E1000_WRITE_REG(hw, E1000_WUC, 0);
 645
 646         diag = e1000_init_hw(hw);
 647         if (diag < 0)
 648                 return (diag);
 649
 650         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 651         e1000_get_phy_info(hw);
 652         e1000_check_for_link(hw);
 653
 654         return (0);
 655 }
 656
 657 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
 658 static void
 659 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 660 {
 661         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 662         struct e1000_hw_stats *stats =
 663                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 664         int pause_frames;
 665
 666         if(hw->phy.media_type == e1000_media_type_copper ||
 667             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 668                 stats->symerrs +=
 669                     E1000_READ_REG(hw,E1000_SYMERRS);
 670                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 671         }
 672
 673         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 674         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 675         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 676         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 677
 678         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 679         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 680         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 681         stats->dc += E1000_READ_REG(hw, E1000_DC);
 682         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 683         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 684         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 685         /*
 686         ** For watchdog management we need to know if we have been
 687         ** paused during the last interval, so capture that here.
 688         */
 689         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 690         stats->xoffrxc += pause_frames;
 691         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 692         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 693         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 694         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 695         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 696         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 697         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 698         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 699         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 700         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 701         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 702         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 703
 704         /* For the 64-bit byte counters the low dword must be read first. */
 705         /* Both registers clear on the read of the high dword */
 706
 707         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 708         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 709         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 710         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 711
 712         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 713         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 714         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 715         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 716         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 717
 718         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 719         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 720
 721         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 722         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 723         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 724         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 725         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 726         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 727         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 728         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 729         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 730         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 731
 732         /* Interrupt Counts */
 733
 734         stats->iac += E1000_READ_REG(hw, E1000_IAC);
 735         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 736         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 737         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 738         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 739         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 740         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 741         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 742         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 743
 744         /* Host to Card Statistics */
 745
 746         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
 747         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
 748         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
 749         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
 750         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
 751         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
 752         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
 753         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
 754         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
 755         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
 756         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
 757         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
 758         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
 759         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
 760
 761         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 762         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 763         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 764         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 765         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 766         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 767
 768         if (rte_stats == NULL)
 769                 return;
 770
 771         /* Rx Errors */
 772         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 773             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 774
 775         /* Tx Errors */
 776         rte_stats->oerrors = stats->ecol + stats->latecol;
 777
 778         rte_stats->ipackets = stats->gprc;
 779         rte_stats->opackets = stats->gptc;
 780         rte_stats->ibytes   = stats->gorc;
 781         rte_stats->obytes   = stats->gotc;
 782 }
 783
 784 static void
 785 eth_igb_stats_reset(struct rte_eth_dev *dev)
 786 {
 787         struct e1000_hw_stats *hw_stats =
 788                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 789
 790         /* HW registers are cleared on read */
 791         eth_igb_stats_get(dev, NULL);
 792
 793         /* Reset software totals */
 794         memset(hw_stats, 0, sizeof(*hw_stats));
 795 }
 796
 797 static void
 798 eth_igb_infos_get(struct rte_eth_dev *dev,
 799                     struct rte_eth_dev_info *dev_info)
 800 {
 801         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 802
 803         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
 804         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
 805         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
 806
 807         switch (hw->mac.type) {
 808         case e1000_82575:
 809                 dev_info->max_rx_queues = 4;
 810                 dev_info->max_tx_queues = 4;
 811                 break;
 812
 813         case e1000_82576:
 814                 dev_info->max_rx_queues = 16;
 815                 dev_info->max_tx_queues = 16;
 816                 break;
 817
 818         case e1000_82580:
 819                 dev_info->max_rx_queues = 8;
 820                 dev_info->max_tx_queues = 8;
 821                 break;
 822
 823         case e1000_i350:
 824                 dev_info->max_rx_queues = 8;
 825                 dev_info->max_tx_queues = 8;
 826                 break;
 827
 828         default:
 829                 /* Should not happen */
 830                 dev_info->max_rx_queues = 0;
 831                 dev_info->max_tx_queues = 0;
 832         }
 833 }
 834
 835 /* return 0 means link status changed, -1 means not changed */
 836 static int
 837 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 838 {
 839         struct e1000_hw *hw =
 840                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 841         struct rte_eth_link link, old;
 842         int link_check, count;
 843
 844         link_check = 0;
 845         hw->mac.get_link_status = 1;
 846
 847         /* possible wait-to-complete in up to 9 seconds */
 848         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
 849                 /* Read the real link status */
 850                 switch (hw->phy.media_type) {
 851                 case e1000_media_type_copper:
 852                         /* Do the work to read phy */
 853                         e1000_check_for_link(hw);
 854                         link_check = !hw->mac.get_link_status;
 855                         break;
 856
 857                 case e1000_media_type_fiber:
 858                         e1000_check_for_link(hw);
 859                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
 860                                       E1000_STATUS_LU);
 861                         break;
 862
 863                 case e1000_media_type_internal_serdes:
 864                         e1000_check_for_link(hw);
 865                         link_check = hw->mac.serdes_has_link;
 866                         break;
 867
 868                 default:
 869                 case e1000_media_type_unknown:
 870                         break;
 871                 }
 872                 if (link_check || wait_to_complete == 0)
 873                         break;
 874                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
 875         }
 876         memset(&link, 0, sizeof(link));
 877         rte_igb_dev_atomic_read_link_status(dev, &link);
 878         old = link;
 879
 880         /* Now we check if a transition has happened */
 881         if (link_check) {
 882                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
 883                                           &link.link_duplex);
 884                 link.link_status = 1;
 885         } else if (!link_check) {
 886                 link.link_speed = 0;
 887                 link.link_duplex = 0;
 888                 link.link_status = 0;
 889         }
 890         rte_igb_dev_atomic_write_link_status(dev, &link);
 891
 892         /* not changed */
 893         if (old.link_status == link.link_status)
 894                 return -1;
 895
 896         /* changed */
 897         return 0;
 898 }
 899
 900 /*
 901  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
 902  * For ASF and Pass Through versions of f/w this means
 903  * that the driver is loaded.
 904  */
 905 static void
 906 igb_hw_control_acquire(struct e1000_hw *hw)
 907 {
 908         uint32_t ctrl_ext;
 909
 910         /* Let firmware know the driver has taken over */
 911         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 912         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 913 }
 914
 915 /*
 916  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
 917  * For ASF and Pass Through versions of f/w this means that the
 918  * driver is no longer loaded.
 919  */
 920 static void
 921 igb_hw_control_release(struct e1000_hw *hw)
 922 {
 923         uint32_t ctrl_ext;
 924
 925         /* Let firmware taken over control of h/w */
 926         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 927         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 928                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 929 }
 930
 931 /*
 932  * Bit of a misnomer, what this really means is
 933  * to enable OS management of the system... aka
 934  * to disable special hardware management features.
 935  */
 936 static void
 937 igb_init_manageability(struct e1000_hw *hw)
 938 {
 939         if (e1000_enable_mng_pass_thru(hw)) {
 940                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
 941                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
 942
 943                 /* disable hardware interception of ARP */
 944                 manc &= ~(E1000_MANC_ARP_EN);
 945
 946                 /* enable receiving management packets to the host */
 947                 manc |= E1000_MANC_EN_MNG2HOST;
 948                 manc2h |= 1 << 5;  /* Mng Port 623 */
 949                 manc2h |= 1 << 6;  /* Mng Port 664 */
 950                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
 951                 E1000_WRITE_REG(hw, E1000_MANC, manc);
 952         }
 953 }
 954
 955 static void
 956 igb_release_manageability(struct e1000_hw *hw)
 957 {
 958         if (e1000_enable_mng_pass_thru(hw)) {
 959                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
 960
 961                 manc |= E1000_MANC_ARP_EN;
 962                 manc &= ~E1000_MANC_EN_MNG2HOST;
 963
 964                 E1000_WRITE_REG(hw, E1000_MANC, manc);
 965         }
 966 }
 967
 968 static void
 969 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
 970 {
 971         struct e1000_hw *hw =
 972                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 973         uint32_t rctl;
 974
 975         rctl = E1000_READ_REG(hw, E1000_RCTL);
 976         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
 977         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 978 }
 979
 980 static void
 981 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
 982 {
 983         struct e1000_hw *hw =
 984                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 985         uint32_t rctl;
 986
 987         rctl = E1000_READ_REG(hw, E1000_RCTL);
 988         rctl &= (~E1000_RCTL_UPE);
 989         if (dev->data->all_multicast == 1)
 990                 rctl |= E1000_RCTL_MPE;
 991         else
 992                 rctl &= (~E1000_RCTL_MPE);
 993         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 994 }
 995
 996 static void
 997 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
 998 {
 999         struct e1000_hw *hw =
1000                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1001         uint32_t rctl;
1002
1003         rctl = E1000_READ_REG(hw, E1000_RCTL);
1004         rctl |= E1000_RCTL_MPE;
1005         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1006 }
1007
1008 static void
1009 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1010 {
1011         struct e1000_hw *hw =
1012                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1013         uint32_t rctl;
1014
1015         if (dev->data->promiscuous == 1)
1016                 return; /* must remain in all_multicast mode */
1017         rctl = E1000_READ_REG(hw, E1000_RCTL);
1018         rctl &= (~E1000_RCTL_MPE);
1019         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1020 }
1021
1022 static void
1023 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1024 {
1025         struct e1000_hw *hw =
1026                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027         struct e1000_vfta * shadow_vfta =
1028                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1029         uint32_t vfta;
1030         uint32_t vid_idx;
1031         uint32_t vid_bit;
1032
1033         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1034                               E1000_VFTA_ENTRY_MASK);
1035         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1036         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1037         if (on)
1038                 vfta |= vid_bit;
1039         else
1040                 vfta &= ~vid_bit;
1041         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1042
1043         /* update local VFTA copy */
1044         shadow_vfta->vfta[vid_idx] = vfta;
1045 }
1046
1047 static void
1048 igb_vlan_hw_support_enable(struct rte_eth_dev *dev)
1049 {
1050         struct e1000_hw *hw =
1051                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1052         struct e1000_vfta * shadow_vfta =
1053                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1054         uint32_t reg;
1055         int i;
1056
1057         /* VLAN Mode Enable */
1058         reg = E1000_READ_REG(hw, E1000_CTRL);
1059         reg |= E1000_CTRL_VME;
1060         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1061
1062         /* Filter Table Enable */
1063         reg = E1000_READ_REG(hw, E1000_RCTL);
1064         reg &= ~E1000_RCTL_CFIEN;
1065         reg |= E1000_RCTL_VFE;
1066         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1067
1068         /* Update maximum frame size */
1069         reg = E1000_READ_REG(hw, E1000_RLPML);
1070         reg += VLAN_TAG_SIZE;
1071         E1000_WRITE_REG(hw, E1000_RLPML, reg);
1072
1073         /* restore VFTA table */
1074         for (i = 0; i < E1000_VFTA_SIZE; i++)
1075                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1076 }
1077
1078 static void
1079 igb_vlan_hw_support_disable(struct rte_eth_dev *dev)
1080 {
1081         struct e1000_hw *hw =
1082                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1083         uint32_t reg;
1084
1085         /* VLAN Mode disable */
1086         reg = E1000_READ_REG(hw, E1000_CTRL);
1087         reg &= ~E1000_CTRL_VME;
1088         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1089 }
1090
1091 static void
1092 igb_intr_disable(struct e1000_hw *hw)
1093 {
1094         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1095         E1000_WRITE_FLUSH(hw);
1096 }
1097
1098 /**
1099  * It enables the interrupt mask and then enable the interrupt.
1100  *
1101  * @param dev
1102  *  Pointer to struct rte_eth_dev.
1103  *
1104  * @return
1105  *  - On success, zero.
1106  *  - On failure, a negative value.
1107  */
1108 static int
1109 eth_igb_interrupt_setup(struct rte_eth_dev *dev)
1110 {
1111         struct e1000_hw *hw =
1112                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1113
1114         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1115         E1000_WRITE_FLUSH(hw);
1116         rte_intr_enable(&(dev->pci_dev->intr_handle));
1117
1118         return 0;
1119 }
1120
1121 /*
1122  * It reads ICR and gets interrupt causes, check it and set a bit flag
1123  * to update link status.
1124  *
1125  * @param dev
1126  *  Pointer to struct rte_eth_dev.
1127  *
1128  * @return
1129  *  - On success, zero.
1130  *  - On failure, a negative value.
1131  */
1132 static int
1133 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1134 {
1135         uint32_t icr;
1136         struct e1000_hw *hw =
1137                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1138         struct e1000_interrupt *intr =
1139                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1140
1141         /* read-on-clear nic registers here */
1142         icr = E1000_READ_REG(hw, E1000_ICR);
1143         if (icr & E1000_ICR_LSC) {
1144                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1145         }
1146
1147         return 0;
1148 }
1149
1150 /*
1151  * It executes link_update after knowing an interrupt is prsent.
1152  *
1153  * @param dev
1154  *  Pointer to struct rte_eth_dev.
1155  *
1156  * @return
1157  *  - On success, zero.
1158  *  - On failure, a negative value.
1159  */
1160 static int
1161 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1162 {
1163         struct e1000_hw *hw =
1164                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1165         struct e1000_interrupt *intr =
1166                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1167         uint32_t tctl, rctl;
1168         struct rte_eth_link link;
1169         int ret;
1170
1171         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1172                 return -1;
1173
1174         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1175         rte_intr_enable(&(dev->pci_dev->intr_handle));
1176
1177         /* set get_link_status to check register later */
1178         hw->mac.get_link_status = 1;
1179         ret = eth_igb_link_update(dev, 0);
1180
1181         /* check if link has changed */
1182         if (ret < 0)
1183                 return 0;
1184
1185         memset(&link, 0, sizeof(link));
1186         rte_igb_dev_atomic_read_link_status(dev, &link);
1187         if (link.link_status) {
1188                 PMD_INIT_LOG(INFO,
1189                         " Port %d: Link Up - speed %u Mbps - %s\n",
1190                         dev->data->port_id, (unsigned)link.link_speed,
1191                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1192                                 "full-duplex" : "half-duplex");
1193         } else {
1194                 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1195                                         dev->data->port_id);
1196         }
1197         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1198                                 dev->pci_dev->addr.domain,
1199                                 dev->pci_dev->addr.bus,
1200                                 dev->pci_dev->addr.devid,
1201                                 dev->pci_dev->addr.function);
1202         tctl = E1000_READ_REG(hw, E1000_TCTL);
1203         rctl = E1000_READ_REG(hw, E1000_RCTL);
1204         if (link.link_status) {
1205                 /* enable Tx/Rx */
1206                 tctl |= E1000_TCTL_EN;
1207                 rctl |= E1000_RCTL_EN;
1208         } else {
1209                 /* disable Tx/Rx */
1210                 tctl &= ~E1000_TCTL_EN;
1211                 rctl &= ~E1000_RCTL_EN;
1212         }
1213         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1214         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1215         E1000_WRITE_FLUSH(hw);
1216
1217         return 0;
1218 }
1219
1220 /**
1221  * Interrupt handler which shall be registered at first.
1222  *
1223  * @param handle
1224  *  Pointer to interrupt handle.
1225  * @param param
1226  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1227  *
1228  * @return
1229  *  void
1230  */
1231 static void
1232 eth_igb_interrupt_handler(struct rte_intr_handle *handle, void *param)
1233 {
1234         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1235
1236         eth_igb_interrupt_get_status(dev);
1237         eth_igb_interrupt_action(dev);
1238         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1239 }
1240
1241 static int
1242 eth_igb_led_on(struct rte_eth_dev *dev)
1243 {
1244         struct e1000_hw *hw;
1245
1246         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1247         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1248 }
1249
1250 static int
1251 eth_igb_led_off(struct rte_eth_dev *dev)
1252 {
1253         struct e1000_hw *hw;
1254
1255         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1256         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1257 }
1258
1259 static int
1260 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1261 {
1262         struct e1000_hw *hw;
1263         int err;
1264         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1265                 e1000_fc_none,
1266                 e1000_fc_rx_pause,
1267                 e1000_fc_tx_pause,
1268                 e1000_fc_full
1269         };
1270         uint32_t rx_buf_size;
1271         uint32_t max_high_water;
1272
1273         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274         rx_buf_size = igb_get_rx_buffer_size(hw);
1275         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1276
1277         /* At least reserve one Ethernet frame for watermark */
1278         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1279         if ((fc_conf->high_water > max_high_water) ||
1280                 (fc_conf->high_water < fc_conf->low_water)) {
1281                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1282                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1283                 return (-EINVAL);
1284         }
1285
1286         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1287         hw->fc.pause_time     = fc_conf->pause_time;
1288         hw->fc.high_water     = fc_conf->high_water;
1289         hw->fc.low_water      = fc_conf->low_water;
1290         hw->fc.send_xon       = fc_conf->send_xon;
1291
1292         err = e1000_setup_link_generic(hw);
1293         if (err == E1000_SUCCESS) {
1294                 return 0;
1295         }
1296
1297         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1298         return (-EIO);
1299 }
1300
1301 static void
1302 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1303                 uint32_t index, __rte_unused uint32_t pool)
1304 {
1305         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1306
1307         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1308 }
1309
1310 static void
1311 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1312 {
1313         uint8_t addr[ETHER_ADDR_LEN];
1314         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1315
1316         memset(addr, 0, sizeof(addr));
1317
1318         e1000_rar_set(hw, addr, index);
1319 }