lib/librte_pmd_igb/igb/e1000_hw.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2011, Intel Corporation
   4   All rights reserved.
   5
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   7   modification, are permitted provided that the following conditions are met:
   8
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  10       this list of conditions and the following disclaimer.
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  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
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  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_HW_H_
  36 #define _E1000_HW_H_
  37
  38 #include "e1000_osdep.h"
  39 #include "e1000_regs.h"
  40 #include "e1000_defines.h"
  41
  42 struct e1000_hw;
  43
  44 #define E1000_DEV_ID_82576                    0x10C9
  45 #define E1000_DEV_ID_82576_FIBER              0x10E6
  46 #define E1000_DEV_ID_82576_SERDES             0x10E7
  47 #define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
  48 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2    0x1526
  49 #define E1000_DEV_ID_82576_NS                 0x150A
  50 #define E1000_DEV_ID_82576_NS_SERDES          0x1518
  51 #define E1000_DEV_ID_82576_SERDES_QUAD        0x150D
  52 #define E1000_DEV_ID_82576_VF                 0x10CA
  53 #define E1000_DEV_ID_I350_VF                  0x1520
  54 #define E1000_DEV_ID_82575EB_COPPER           0x10A7
  55 #define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
  56 #define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
  57 #define E1000_DEV_ID_82580_COPPER             0x150E
  58 #define E1000_DEV_ID_82580_FIBER              0x150F
  59 #define E1000_DEV_ID_82580_SERDES             0x1510
  60 #define E1000_DEV_ID_82580_SGMII              0x1511
  61 #define E1000_DEV_ID_82580_COPPER_DUAL        0x1516
  62 #define E1000_DEV_ID_82580_QUAD_FIBER         0x1527
  63 #define E1000_DEV_ID_I350_COPPER              0x1521
  64 #define E1000_DEV_ID_I350_FIBER               0x1522
  65 #define E1000_DEV_ID_I350_SERDES              0x1523
  66 #define E1000_DEV_ID_I350_SGMII               0x1524
  67 #define E1000_DEV_ID_I350_DA4                 0x1546
  68 #define E1000_DEV_ID_DH89XXCC_SGMII           0x0438
  69 #define E1000_DEV_ID_DH89XXCC_SERDES          0x043A
  70 #define E1000_DEV_ID_DH89XXCC_BACKPLANE       0x043C
  71 #define E1000_DEV_ID_DH89XXCC_SFP             0x0440
  72 #define E1000_REVISION_0 0
  73 #define E1000_REVISION_1 1
  74 #define E1000_REVISION_2 2
  75 #define E1000_REVISION_3 3
  76 #define E1000_REVISION_4 4
  77
  78 #define E1000_FUNC_0     0
  79 #define E1000_FUNC_1     1
  80 #define E1000_FUNC_2     2
  81 #define E1000_FUNC_3     3
  82
  83 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
  84 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
  85 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6
  86 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9
  87
  88 enum e1000_mac_type {
  89         e1000_undefined = 0,
  90         e1000_82575,
  91         e1000_82576,
  92         e1000_82580,
  93         e1000_i350,
  94         e1000_vfadapt,
  95         e1000_vfadapt_i350,
  96         e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
  97 };
  98
  99 enum e1000_media_type {
 100         e1000_media_type_unknown = 0,
 101         e1000_media_type_copper = 1,
 102         e1000_media_type_fiber = 2,
 103         e1000_media_type_internal_serdes = 3,
 104         e1000_num_media_types
 105 };
 106
 107 enum e1000_nvm_type {
 108         e1000_nvm_unknown = 0,
 109         e1000_nvm_none,
 110         e1000_nvm_eeprom_spi,
 111         e1000_nvm_eeprom_microwire,
 112         e1000_nvm_flash_hw,
 113         e1000_nvm_flash_sw
 114 };
 115
 116 enum e1000_nvm_override {
 117         e1000_nvm_override_none = 0,
 118         e1000_nvm_override_spi_small,
 119         e1000_nvm_override_spi_large,
 120         e1000_nvm_override_microwire_small,
 121         e1000_nvm_override_microwire_large
 122 };
 123
 124 enum e1000_phy_type {
 125         e1000_phy_unknown = 0,
 126         e1000_phy_none,
 127         e1000_phy_m88,
 128         e1000_phy_igp,
 129         e1000_phy_igp_2,
 130         e1000_phy_gg82563,
 131         e1000_phy_igp_3,
 132         e1000_phy_ife,
 133         e1000_phy_82580,
 134         e1000_phy_vf,
 135 };
 136
 137 enum e1000_bus_type {
 138         e1000_bus_type_unknown = 0,
 139         e1000_bus_type_pci,
 140         e1000_bus_type_pcix,
 141         e1000_bus_type_pci_express,
 142         e1000_bus_type_reserved
 143 };
 144
 145 enum e1000_bus_speed {
 146         e1000_bus_speed_unknown = 0,
 147         e1000_bus_speed_33,
 148         e1000_bus_speed_66,
 149         e1000_bus_speed_100,
 150         e1000_bus_speed_120,
 151         e1000_bus_speed_133,
 152         e1000_bus_speed_2500,
 153         e1000_bus_speed_5000,
 154         e1000_bus_speed_reserved
 155 };
 156
 157 enum e1000_bus_width {
 158         e1000_bus_width_unknown = 0,
 159         e1000_bus_width_pcie_x1,
 160         e1000_bus_width_pcie_x2,
 161         e1000_bus_width_pcie_x4 = 4,
 162         e1000_bus_width_pcie_x8 = 8,
 163         e1000_bus_width_32,
 164         e1000_bus_width_64,
 165         e1000_bus_width_reserved
 166 };
 167
 168 enum e1000_1000t_rx_status {
 169         e1000_1000t_rx_status_not_ok = 0,
 170         e1000_1000t_rx_status_ok,
 171         e1000_1000t_rx_status_undefined = 0xFF
 172 };
 173
 174 enum e1000_rev_polarity {
 175         e1000_rev_polarity_normal = 0,
 176         e1000_rev_polarity_reversed,
 177         e1000_rev_polarity_undefined = 0xFF
 178 };
 179
 180 enum e1000_fc_mode {
 181         e1000_fc_none = 0,
 182         e1000_fc_rx_pause,
 183         e1000_fc_tx_pause,
 184         e1000_fc_full,
 185         e1000_fc_default = 0xFF
 186 };
 187
 188 enum e1000_ms_type {
 189         e1000_ms_hw_default = 0,
 190         e1000_ms_force_master,
 191         e1000_ms_force_slave,
 192         e1000_ms_auto
 193 };
 194
 195 enum e1000_smart_speed {
 196         e1000_smart_speed_default = 0,
 197         e1000_smart_speed_on,
 198         e1000_smart_speed_off
 199 };
 200
 201 enum e1000_serdes_link_state {
 202         e1000_serdes_link_down = 0,
 203         e1000_serdes_link_autoneg_progress,
 204         e1000_serdes_link_autoneg_complete,
 205         e1000_serdes_link_forced_up
 206 };
 207
 208 #define __le16 u16
 209 #define __le32 u32
 210 #define __le64 u64
 211 /* Receive Descriptor */
 212 struct e1000_rx_desc {
 213         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 214         __le16 length;      /* Length of data DMAed into data buffer */
 215         __le16 csum;        /* Packet checksum */
 216         u8  status;         /* Descriptor status */
 217         u8  errors;         /* Descriptor Errors */
 218         __le16 special;
 219 };
 220
 221 /* Receive Descriptor - Extended */
 222 union e1000_rx_desc_extended {
 223         struct {
 224                 __le64 buffer_addr;
 225                 __le64 reserved;
 226         } read;
 227         struct {
 228                 struct {
 229                         __le32 mrq;           /* Multiple Rx Queues */
 230                         union {
 231                                 __le32 rss;         /* RSS Hash */
 232                                 struct {
 233                                         __le16 ip_id;  /* IP id */
 234                                         __le16 csum;   /* Packet Checksum */
 235                                 } csum_ip;
 236                         } hi_dword;
 237                 } lower;
 238                 struct {
 239                         __le32 status_error;  /* ext status/error */
 240                         __le16 length;
 241                         __le16 vlan;          /* VLAN tag */
 242                 } upper;
 243         } wb;  /* writeback */
 244 };
 245
 246 #define MAX_PS_BUFFERS 4
 247 /* Receive Descriptor - Packet Split */
 248 union e1000_rx_desc_packet_split {
 249         struct {
 250                 /* one buffer for protocol header(s), three data buffers */
 251                 __le64 buffer_addr[MAX_PS_BUFFERS];
 252         } read;
 253         struct {
 254                 struct {
 255                         __le32 mrq;           /* Multiple Rx Queues */
 256                         union {
 257                                 __le32 rss;           /* RSS Hash */
 258                                 struct {
 259                                         __le16 ip_id;    /* IP id */
 260                                         __le16 csum;     /* Packet Checksum */
 261                                 } csum_ip;
 262                         } hi_dword;
 263                 } lower;
 264                 struct {
 265                         __le32 status_error;  /* ext status/error */
 266                         __le16 length0;       /* length of buffer 0 */
 267                         __le16 vlan;          /* VLAN tag */
 268                 } middle;
 269                 struct {
 270                         __le16 header_status;
 271                         __le16 length[3];     /* length of buffers 1-3 */
 272                 } upper;
 273                 __le64 reserved;
 274         } wb; /* writeback */
 275 };
 276
 277 /* Transmit Descriptor */
 278 struct e1000_tx_desc {
 279         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 280         union {
 281                 __le32 data;
 282                 struct {
 283                         __le16 length;    /* Data buffer length */
 284                         u8 cso;           /* Checksum offset */
 285                         u8 cmd;           /* Descriptor control */
 286                 } flags;
 287         } lower;
 288         union {
 289                 __le32 data;
 290                 struct {
 291                         u8 status;        /* Descriptor status */
 292                         u8 css;           /* Checksum start */
 293                         __le16 special;
 294                 } fields;
 295         } upper;
 296 };
 297
 298 /* Offload Context Descriptor */
 299 struct e1000_context_desc {
 300         union {
 301                 __le32 ip_config;
 302                 struct {
 303                         u8 ipcss;         /* IP checksum start */
 304                         u8 ipcso;         /* IP checksum offset */
 305                         __le16 ipcse;     /* IP checksum end */
 306                 } ip_fields;
 307         } lower_setup;
 308         union {
 309                 __le32 tcp_config;
 310                 struct {
 311                         u8 tucss;         /* TCP checksum start */
 312                         u8 tucso;         /* TCP checksum offset */
 313                         __le16 tucse;     /* TCP checksum end */
 314                 } tcp_fields;
 315         } upper_setup;
 316         __le32 cmd_and_length;
 317         union {
 318                 __le32 data;
 319                 struct {
 320                         u8 status;        /* Descriptor status */
 321                         u8 hdr_len;       /* Header length */
 322                         __le16 mss;       /* Maximum segment size */
 323                 } fields;
 324         } tcp_seg_setup;
 325 };
 326
 327 /* Offload data descriptor */
 328 struct e1000_data_desc {
 329         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 330         union {
 331                 __le32 data;
 332                 struct {
 333                         __le16 length;    /* Data buffer length */
 334                         u8 typ_len_ext;
 335                         u8 cmd;
 336                 } flags;
 337         } lower;
 338         union {
 339                 __le32 data;
 340                 struct {
 341                         u8 status;        /* Descriptor status */
 342                         u8 popts;         /* Packet Options */
 343                         __le16 special;
 344                 } fields;
 345         } upper;
 346 };
 347
 348 /* Statistics counters collected by the MAC */
 349 struct e1000_hw_stats {
 350         u64 crcerrs;
 351         u64 algnerrc;
 352         u64 symerrs;
 353         u64 rxerrc;
 354         u64 mpc;
 355         u64 scc;
 356         u64 ecol;
 357         u64 mcc;
 358         u64 latecol;
 359         u64 colc;
 360         u64 dc;
 361         u64 tncrs;
 362         u64 sec;
 363         u64 cexterr;
 364         u64 rlec;
 365         u64 xonrxc;
 366         u64 xontxc;
 367         u64 xoffrxc;
 368         u64 xofftxc;
 369         u64 fcruc;
 370         u64 prc64;
 371         u64 prc127;
 372         u64 prc255;
 373         u64 prc511;
 374         u64 prc1023;
 375         u64 prc1522;
 376         u64 gprc;
 377         u64 bprc;
 378         u64 mprc;
 379         u64 gptc;
 380         u64 gorc;
 381         u64 gotc;
 382         u64 rnbc;
 383         u64 ruc;
 384         u64 rfc;
 385         u64 roc;
 386         u64 rjc;
 387         u64 mgprc;
 388         u64 mgpdc;
 389         u64 mgptc;
 390         u64 tor;
 391         u64 tot;
 392         u64 tpr;
 393         u64 tpt;
 394         u64 ptc64;
 395         u64 ptc127;
 396         u64 ptc255;
 397         u64 ptc511;
 398         u64 ptc1023;
 399         u64 ptc1522;
 400         u64 mptc;
 401         u64 bptc;
 402         u64 tsctc;
 403         u64 tsctfc;
 404         u64 iac;
 405         u64 icrxptc;
 406         u64 icrxatc;
 407         u64 ictxptc;
 408         u64 ictxatc;
 409         u64 ictxqec;
 410         u64 ictxqmtc;
 411         u64 icrxdmtc;
 412         u64 icrxoc;
 413         u64 cbtmpc;
 414         u64 htdpmc;
 415         u64 cbrdpc;
 416         u64 cbrmpc;
 417         u64 rpthc;
 418         u64 hgptc;
 419         u64 htcbdpc;
 420         u64 hgorc;
 421         u64 hgotc;
 422         u64 lenerrs;
 423         u64 scvpc;
 424         u64 hrmpc;
 425         u64 doosync;
 426 };
 427
 428 struct e1000_vf_stats {
 429         u64 base_gprc;
 430         u64 base_gptc;
 431         u64 base_gorc;
 432         u64 base_gotc;
 433         u64 base_mprc;
 434         u64 base_gotlbc;
 435         u64 base_gptlbc;
 436         u64 base_gorlbc;
 437         u64 base_gprlbc;
 438
 439         u32 last_gprc;
 440         u32 last_gptc;
 441         u32 last_gorc;
 442         u32 last_gotc;
 443         u32 last_mprc;
 444         u32 last_gotlbc;
 445         u32 last_gptlbc;
 446         u32 last_gorlbc;
 447         u32 last_gprlbc;
 448
 449         u64 gprc;
 450         u64 gptc;
 451         u64 gorc;
 452         u64 gotc;
 453         u64 mprc;
 454         u64 gotlbc;
 455         u64 gptlbc;
 456         u64 gorlbc;
 457         u64 gprlbc;
 458 };
 459
 460 struct e1000_phy_stats {
 461         u32 idle_errors;
 462         u32 receive_errors;
 463 };
 464
 465 struct e1000_host_mng_dhcp_cookie {
 466         u32 signature;
 467         u8  status;
 468         u8  reserved0;
 469         u16 vlan_id;
 470         u32 reserved1;
 471         u16 reserved2;
 472         u8  reserved3;
 473         u8  checksum;
 474 };
 475
 476 /* Host Interface "Rev 1" */
 477 struct e1000_host_command_header {
 478         u8 command_id;
 479         u8 command_length;
 480         u8 command_options;
 481         u8 checksum;
 482 };
 483
 484 #define E1000_HI_MAX_DATA_LENGTH     252
 485 struct e1000_host_command_info {
 486         struct e1000_host_command_header command_header;
 487         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 488 };
 489
 490 /* Host Interface "Rev 2" */
 491 struct e1000_host_mng_command_header {
 492         u8  command_id;
 493         u8  checksum;
 494         u16 reserved1;
 495         u16 reserved2;
 496         u16 command_length;
 497 };
 498
 499 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 500 struct e1000_host_mng_command_info {
 501         struct e1000_host_mng_command_header command_header;
 502         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 503 };
 504
 505 #include "e1000_mac.h"
 506 #include "e1000_phy.h"
 507 #include "e1000_nvm.h"
 508 #include "e1000_manage.h"
 509 #include "e1000_mbx.h"
 510
 511 struct e1000_mac_operations {
 512         /* Function pointers for the MAC. */
 513         s32  (*init_params)(struct e1000_hw *);
 514         s32  (*id_led_init)(struct e1000_hw *);
 515         s32  (*blink_led)(struct e1000_hw *);
 516         s32  (*check_for_link)(struct e1000_hw *);
 517         bool (*check_mng_mode)(struct e1000_hw *hw);
 518         s32  (*cleanup_led)(struct e1000_hw *);
 519         void (*clear_hw_cntrs)(struct e1000_hw *);
 520         void (*clear_vfta)(struct e1000_hw *);
 521         s32  (*get_bus_info)(struct e1000_hw *);
 522         void (*set_lan_id)(struct e1000_hw *);
 523         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 524         s32  (*led_on)(struct e1000_hw *);
 525         s32  (*led_off)(struct e1000_hw *);
 526         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 527         s32  (*reset_hw)(struct e1000_hw *);
 528         s32  (*init_hw)(struct e1000_hw *);
 529         void (*shutdown_serdes)(struct e1000_hw *);
 530         void (*power_up_serdes)(struct e1000_hw *);
 531         s32  (*setup_link)(struct e1000_hw *);
 532         s32  (*setup_physical_interface)(struct e1000_hw *);
 533         s32  (*setup_led)(struct e1000_hw *);
 534         void (*write_vfta)(struct e1000_hw *, u32, u32);
 535         void (*config_collision_dist)(struct e1000_hw *);
 536         void (*rar_set)(struct e1000_hw *, u8*, u32);
 537         s32  (*read_mac_addr)(struct e1000_hw *);
 538         s32  (*validate_mdi_setting)(struct e1000_hw *);
 539         s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
 540         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
 541                       struct e1000_host_mng_command_header*);
 542         s32  (*mng_enable_host_if)(struct e1000_hw *);
 543         s32  (*wait_autoneg)(struct e1000_hw *);
 544 };
 545
 546 struct e1000_phy_operations {
 547         s32  (*init_params)(struct e1000_hw *);
 548         s32  (*acquire)(struct e1000_hw *);
 549         s32  (*check_polarity)(struct e1000_hw *);
 550         s32  (*check_reset_block)(struct e1000_hw *);
 551         s32  (*commit)(struct e1000_hw *);
 552         s32  (*force_speed_duplex)(struct e1000_hw *);
 553         s32  (*get_cfg_done)(struct e1000_hw *hw);
 554         s32  (*get_cable_length)(struct e1000_hw *);
 555         s32  (*get_info)(struct e1000_hw *);
 556         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 557         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 558         void (*release)(struct e1000_hw *);
 559         s32  (*reset)(struct e1000_hw *);
 560         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 561         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 562         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 563         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 564         void (*power_up)(struct e1000_hw *);
 565         void (*power_down)(struct e1000_hw *);
 566 };
 567
 568 struct e1000_nvm_operations {
 569         s32  (*init_params)(struct e1000_hw *);
 570         s32  (*acquire)(struct e1000_hw *);
 571         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 572         void (*release)(struct e1000_hw *);
 573         void (*reload)(struct e1000_hw *);
 574         s32  (*update)(struct e1000_hw *);
 575         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 576         s32  (*validate)(struct e1000_hw *);
 577         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 578 };
 579
 580 struct e1000_mac_info {
 581         struct e1000_mac_operations ops;
 582         u8 addr[ETH_ADDR_LEN];
 583         u8 perm_addr[ETH_ADDR_LEN];
 584
 585         enum e1000_mac_type type;
 586
 587         u32 collision_delta;
 588         u32 ledctl_default;
 589         u32 ledctl_mode1;
 590         u32 ledctl_mode2;
 591         u32 mc_filter_type;
 592         u32 tx_packet_delta;
 593         u32 txcw;
 594
 595         u16 current_ifs_val;
 596         u16 ifs_max_val;
 597         u16 ifs_min_val;
 598         u16 ifs_ratio;
 599         u16 ifs_step_size;
 600         u16 mta_reg_count;
 601         u16 uta_reg_count;
 602
 603         /* Maximum size of the MTA register table in all supported adapters */
 604         #define MAX_MTA_REG 128
 605         u32 mta_shadow[MAX_MTA_REG];
 606         u16 rar_entry_count;
 607
 608         u8  forced_speed_duplex;
 609
 610         bool adaptive_ifs;
 611         bool has_fwsm;
 612         bool arc_subsystem_valid;
 613         bool asf_firmware_present;
 614         bool autoneg;
 615         bool autoneg_failed;
 616         bool get_link_status;
 617         bool in_ifs_mode;
 618         enum e1000_serdes_link_state serdes_link_state;
 619         bool serdes_has_link;
 620         bool tx_pkt_filtering;
 621 };
 622
 623 struct e1000_phy_info {
 624         struct e1000_phy_operations ops;
 625         enum e1000_phy_type type;
 626
 627         enum e1000_1000t_rx_status local_rx;
 628         enum e1000_1000t_rx_status remote_rx;
 629         enum e1000_ms_type ms_type;
 630         enum e1000_ms_type original_ms_type;
 631         enum e1000_rev_polarity cable_polarity;
 632         enum e1000_smart_speed smart_speed;
 633
 634         u32 addr;
 635         u32 id;
 636         u32 reset_delay_us; /* in usec */
 637         u32 revision;
 638
 639         enum e1000_media_type media_type;
 640
 641         u16 autoneg_advertised;
 642         u16 autoneg_mask;
 643         u16 cable_length;
 644         u16 max_cable_length;
 645         u16 min_cable_length;
 646
 647         u8 mdix;
 648
 649         bool disable_polarity_correction;
 650         bool is_mdix;
 651         bool polarity_correction;
 652         bool reset_disable;
 653         bool speed_downgraded;
 654         bool autoneg_wait_to_complete;
 655 };
 656
 657 struct e1000_nvm_info {
 658         struct e1000_nvm_operations ops;
 659         enum e1000_nvm_type type;
 660         enum e1000_nvm_override override;
 661
 662         u32 flash_bank_size;
 663         u32 flash_base_addr;
 664
 665         u16 word_size;
 666         u16 delay_usec;
 667         u16 address_bits;
 668         u16 opcode_bits;
 669         u16 page_size;
 670 };
 671
 672 struct e1000_bus_info {
 673         enum e1000_bus_type type;
 674         enum e1000_bus_speed speed;
 675         enum e1000_bus_width width;
 676
 677         u16 func;
 678         u16 pci_cmd_word;
 679 };
 680
 681 struct e1000_fc_info {
 682         u32 high_water;          /* Flow control high-water mark */
 683         u32 low_water;           /* Flow control low-water mark */
 684         u16 pause_time;          /* Flow control pause timer */
 685         u16 refresh_time;        /* Flow control refresh timer */
 686         bool send_xon;           /* Flow control send XON */
 687         bool strict_ieee;        /* Strict IEEE mode */
 688         enum e1000_fc_mode current_mode; /* FC mode in effect */
 689         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
 690 };
 691
 692 struct e1000_mbx_operations {
 693         s32 (*init_params)(struct e1000_hw *hw);
 694         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 695         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 696         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 697         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 698         s32 (*check_for_msg)(struct e1000_hw *, u16);
 699         s32 (*check_for_ack)(struct e1000_hw *, u16);
 700         s32 (*check_for_rst)(struct e1000_hw *, u16);
 701 };
 702
 703 struct e1000_mbx_stats {
 704         u32 msgs_tx;
 705         u32 msgs_rx;
 706
 707         u32 acks;
 708         u32 reqs;
 709         u32 rsts;
 710 };
 711
 712 struct e1000_mbx_info {
 713         struct e1000_mbx_operations ops;
 714         struct e1000_mbx_stats stats;
 715         u32 timeout;
 716         u32 usec_delay;
 717         u16 size;
 718 };
 719
 720 struct e1000_dev_spec_82575 {
 721         bool sgmii_active;
 722         bool global_device_reset;
 723         bool eee_disable;
 724 };
 725
 726 struct e1000_dev_spec_vf {
 727         u32 vf_number;
 728         u32 v2p_mailbox;
 729 };
 730
 731 struct e1000_hw {
 732         void *back;
 733
 734         u8 *hw_addr;
 735         u8 *flash_address;
 736         unsigned long io_base;
 737
 738         struct e1000_mac_info  mac;
 739         struct e1000_fc_info   fc;
 740         struct e1000_phy_info  phy;
 741         struct e1000_nvm_info  nvm;
 742         struct e1000_bus_info  bus;
 743         struct e1000_mbx_info mbx;
 744         struct e1000_host_mng_dhcp_cookie mng_cookie;
 745
 746         union {
 747                 struct e1000_dev_spec_82575 _82575;
 748                 struct e1000_dev_spec_vf vf;
 749         } dev_spec;
 750
 751         u16 device_id;
 752         u16 subsystem_vendor_id;
 753         u16 subsystem_device_id;
 754         u16 vendor_id;
 755
 756         u8  revision_id;
 757 };
 758
 759 #include "e1000_82575.h"
 760
 761 /* These functions must be implemented by drivers */
 762 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 763 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 764 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 765 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 766
 767 #endif