update Intel copyright years to 2014
[dpdk.git] / lib / librte_pmd_ixgbe / ixgbe_bypass_defines.h
1 /*-
2  *   BSD LICENSE
3  * 
4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5  *   All rights reserved.
6  * 
7  *   Redistribution and use in source and binary forms, with or without
8  *   modification, are permitted provided that the following conditions
9  *   are met:
10  * 
11  *     * Redistributions of source code must retain the above copyright
12  *       notice, this list of conditions and the following disclaimer.
13  *     * Redistributions in binary form must reproduce the above copyright
14  *       notice, this list of conditions and the following disclaimer in
15  *       the documentation and/or other materials provided with the
16  *       distribution.
17  *     * Neither the name of Intel Corporation nor the names of its
18  *       contributors may be used to endorse or promote products derived
19  *       from this software without specific prior written permission.
20  * 
21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33
34 #ifndef _IXGBE_BYPASS_DEFINES_H_
35 #define _IXGBE_BYPASS_DEFINES_H_
36
37 #ifdef RTE_NIC_BYPASS
38
39 #define msleep(x)             rte_delay_us(x*1000)
40 #define usleep_range(min, max) rte_delay_us(min)
41
42 #define BYPASS_PAGE_CTL0        0x00000000
43 #define BYPASS_PAGE_CTL1        0x40000000
44 #define BYPASS_PAGE_CTL2        0x80000000
45 #define BYPASS_PAGE_M           0xc0000000
46 #define BYPASS_WE               0x20000000
47
48 #define BYPASS_AUTO     0x0
49 #define BYPASS_NOP      0x0
50 #define BYPASS_NORM     0x1
51 #define BYPASS_BYPASS   0x2
52 #define BYPASS_ISOLATE  0x3
53
54 #define BYPASS_EVENT_MAIN_ON    0x1
55 #define BYPASS_EVENT_AUX_ON     0x2
56 #define BYPASS_EVENT_MAIN_OFF   0x3
57 #define BYPASS_EVENT_AUX_OFF    0x4
58 #define BYPASS_EVENT_WDT_TO     0x5
59 #define BYPASS_EVENT_USR        0x6
60
61 #define BYPASS_MODE_OFF_M       0x00000003
62 #define BYPASS_STATUS_OFF_M     0x0000000c
63 #define BYPASS_AUX_ON_M         0x00000030
64 #define BYPASS_MAIN_ON_M        0x000000c0
65 #define BYPASS_MAIN_OFF_M       0x00000300
66 #define BYPASS_AUX_OFF_M        0x00000c00
67 #define BYPASS_WDTIMEOUT_M      0x00003000
68 #define BYPASS_WDT_ENABLE_M     0x00004000
69 #define BYPASS_WDT_VALUE_M      0x00070000
70
71 #define BYPASS_MODE_OFF_SHIFT   0
72 #define BYPASS_STATUS_OFF_SHIFT 2
73 #define BYPASS_AUX_ON_SHIFT     4
74 #define BYPASS_MAIN_ON_SHIFT    6
75 #define BYPASS_MAIN_OFF_SHIFT   8
76 #define BYPASS_AUX_OFF_SHIFT    10
77 #define BYPASS_WDTIMEOUT_SHIFT  12
78 #define BYPASS_WDT_ENABLE_SHIFT 14
79 #define BYPASS_WDT_TIME_SHIFT   16
80
81 #define BYPASS_WDT_1    0x0
82 #define BYPASS_WDT_1_5  0x1
83 #define BYPASS_WDT_2    0x2
84 #define BYPASS_WDT_3    0x3
85 #define BYPASS_WDT_4    0x4
86 #define BYPASS_WDT_8    0x5
87 #define BYPASS_WDT_16   0x6
88 #define BYPASS_WDT_32   0x7
89 #define BYPASS_WDT_OFF  0xffff
90
91 #define BYPASS_WDT_MASK 0x7
92
93 #define BYPASS_CTL1_TIME_M      0x01ffffff
94 #define BYPASS_CTL1_VALID_M     0x02000000
95 #define BYPASS_CTL1_OFFTRST_M   0x04000000
96 #define BYPASS_CTL1_WDT_PET_M   0x08000000
97
98 #define BYPASS_CTL1_VALID       0x02000000
99 #define BYPASS_CTL1_OFFTRST     0x04000000
100 #define BYPASS_CTL1_WDT_PET     0x08000000
101
102 #define BYPASS_CTL2_DATA_M      0x000000ff
103 #define BYPASS_CTL2_OFFSET_M    0x0000ff00
104 #define BYPASS_CTL2_RW_M        0x00010000
105 #define BYPASS_CTL2_HEAD_M      0x0ff00000
106
107 #define BYPASS_CTL2_OFFSET_SHIFT        8
108 #define BYPASS_CTL2_HEAD_SHIFT          20
109
110 #define BYPASS_CTL2_RW          0x00010000
111
112 enum ixgbe_state_t {
113         __IXGBE_TESTING,
114         __IXGBE_RESETTING,
115         __IXGBE_DOWN,
116         __IXGBE_SERVICE_SCHED,
117         __IXGBE_IN_SFP_INIT,
118         __IXGBE_IN_BYPASS_LOW,
119         __IXGBE_IN_BYPASS_HIGH,
120         __IXGBE_IN_BYPASS_LOG,
121 };
122
123 #define BYPASS_MAX_LOGS         43
124 #define BYPASS_LOG_SIZE         5
125 #define BYPASS_LOG_LINE_SIZE    37
126
127 #define BYPASS_EEPROM_VER_ADD   0x02
128
129 #define BYPASS_LOG_TIME_M       0x01ffffff
130 #define BYPASS_LOG_TIME_VALID_M 0x02000000
131 #define BYPASS_LOG_HEAD_M       0x04000000
132 #define BYPASS_LOG_CLEAR_M      0x08000000
133 #define BYPASS_LOG_EVENT_M      0xf0000000
134 #define BYPASS_LOG_ACTION_M     0x03
135
136 #define BYPASS_LOG_EVENT_SHIFT  28
137 #define BYPASS_LOG_CLEAR_SHIFT  24 /* bit offset */
138 #define IXGBE_DEV_TO_ADPATER(dev) \
139         ((struct ixgbe_adapter*)(dev->data->dev_private))
140
141 /* extractions from ixgbe_phy.h */
142 #define IXGBE_I2C_EEPROM_DEV_ADDR2      0xA2
143
144 #define IXGBE_SFF_SFF_8472_SWAP         0x5C
145 #define IXGBE_SFF_SFF_8472_COMP         0x5E
146 #define IXGBE_SFF_SFF_8472_OSCB         0x6E
147 #define IXGBE_SFF_SFF_8472_ESCB         0x76
148
149 #define IXGBE_SFF_SOFT_RS_SELECT_MASK   0x8
150 #define IXGBE_SFF_SOFT_RS_SELECT_10G    0x8
151 #define IXGBE_SFF_SOFT_RS_SELECT_1G     0x0
152
153 /* extractions from ixgbe_type.h */
154 #define IXGBE_DEV_ID_82599_BYPASS       0x155D
155
156 #define IXGBE_BYPASS_FW_WRITE_FAILURE   -35
157
158 #endif /* RTE_NIC_BYPASS */
159
160 #endif /* _IXGBE_BYPASS_DEFINES_H_ */