lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "ixgbe/ixgbe_api.h"
  66 #include "ixgbe/ixgbe_vf.h"
  67 #include "ixgbe/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 /*
  96  *  Default values for RX/TX configuration
  97  */
  98 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  99 #define IXGBE_DEFAULT_RX_PTHRESH      8
 100 #define IXGBE_DEFAULT_RX_HTHRESH      8
 101 #define IXGBE_DEFAULT_RX_WTHRESH      0
 102
 103 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 104 #define IXGBE_DEFAULT_TX_PTHRESH      32
 105 #define IXGBE_DEFAULT_TX_HTHRESH      0
 106 #define IXGBE_DEFAULT_TX_WTHRESH      0
 107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 108
 109 /* Bit shift and mask */
 110 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 111 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 112 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 113 #define IXGBE_8_BIT_MASK   UINT8_MAX
 114
 115 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 116
 117 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 118
 119 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 120 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 121 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 122 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 123 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 124 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 125 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 126 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 127 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 128 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 129 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 130 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 131                                 int wait_to_complete);
 132 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 133                                 struct rte_eth_stats *stats);
 134 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 135 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 136                                              uint16_t queue_id,
 137                                              uint8_t stat_idx,
 138                                              uint8_t is_rx);
 139 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 140                                struct rte_eth_dev_info *dev_info);
 141 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 142                                  struct rte_eth_dev_info *dev_info);
 143 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 144
 145 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 146                 uint16_t vlan_id, int on);
 147 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 148 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 149                 uint16_t queue, bool on);
 150 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 151                 int on);
 152 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 153 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 154 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 155 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 156 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 157
 158 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 159 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 160 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 161                                struct rte_eth_fc_conf *fc_conf);
 162 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 163                                struct rte_eth_fc_conf *fc_conf);
 164 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 165                 struct rte_eth_pfc_conf *pfc_conf);
 166 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 167                         struct rte_eth_rss_reta_entry64 *reta_conf,
 168                         uint16_t reta_size);
 169 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 170                         struct rte_eth_rss_reta_entry64 *reta_conf,
 171                         uint16_t reta_size);
 172 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 173 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 174 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 177                 void *param);
 178 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 179 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 180                 uint32_t index, uint32_t pool);
 181 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 182 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 183
 184 /* For Virtual Function support */
 185 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 186 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 187 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 188 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 189 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 190 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 191 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 192                 struct rte_eth_stats *stats);
 193 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 194 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 195                 uint16_t vlan_id, int on);
 196 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 197                 uint16_t queue, int on);
 198 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 199 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 200
 201 /* For Eth VMDQ APIs support */
 202 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 203                 ether_addr* mac_addr,uint8_t on);
 204 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 205 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 206                 uint16_t rx_mask, uint8_t on);
 207 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 208 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 209 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 210                 uint64_t pool_mask,uint8_t vlan_on);
 211 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 212                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 213                 uint8_t rule_id, uint8_t on);
 214 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 215                 uint8_t rule_id);
 216
 217 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 218                 uint16_t queue_idx, uint16_t tx_rate);
 219 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 220                 uint16_t tx_rate, uint64_t q_msk);
 221
 222 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 223                                  struct ether_addr *mac_addr,
 224                                  uint32_t index, uint32_t pool);
 225 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 226 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 227                         struct rte_eth_syn_filter *filter,
 228                         bool add);
 229 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 230                         struct rte_eth_syn_filter *filter);
 231 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 232                         enum rte_filter_op filter_op,
 233                         void *arg);
 234 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 235                         struct ixgbe_5tuple_filter *filter);
 236 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 237                         struct ixgbe_5tuple_filter *filter);
 238 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 239                         struct rte_eth_ntuple_filter *filter,
 240                         bool add);
 241 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 242                                 enum rte_filter_op filter_op,
 243                                 void *arg);
 244 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 245                         struct rte_eth_ntuple_filter *filter);
 246 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 247                         struct rte_eth_ethertype_filter *filter,
 248                         bool add);
 249 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 250                                 enum rte_filter_op filter_op,
 251                                 void *arg);
 252 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 253                         struct rte_eth_ethertype_filter *filter);
 254 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 255                      enum rte_filter_type filter_type,
 256                      enum rte_filter_op filter_op,
 257                      void *arg);
 258 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 259
 260 /*
 261  * Define VF Stats MACRO for Non "cleared on read" register
 262  */
 263 #define UPDATE_VF_STAT(reg, last, cur)                          \
 264 {                                                               \
 265         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 266         cur += latest - last;                                   \
 267         last = latest;                                          \
 268 }
 269
 270 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 271 {                                                                \
 272         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 273         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 274         u64 latest = ((new_msb << 32) | new_lsb);                \
 275         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 276         last = latest;                                           \
 277 }
 278
 279 #define IXGBE_SET_HWSTRIP(h, q) do{\
 280                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 281                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 282                 (h)->bitmap[idx] |= 1 << bit;\
 283         }while(0)
 284
 285 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 286                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 287                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 288                 (h)->bitmap[idx] &= ~(1 << bit);\
 289         }while(0)
 290
 291 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 292                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 293                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 294                 (r) = (h)->bitmap[idx] >> bit & 1;\
 295         }while(0)
 296
 297 /*
 298  * The set of PCI devices this driver supports
 299  */
 300 static struct rte_pci_id pci_id_ixgbe_map[] = {
 301
 302 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 303 #include "rte_pci_dev_ids.h"
 304
 305 { .vendor_id = 0, /* sentinel */ },
 306 };
 307
 308
 309 /*
 310  * The set of PCI devices this driver supports (for 82599 VF)
 311  */
 312 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 313
 314 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 315 #include "rte_pci_dev_ids.h"
 316 { .vendor_id = 0, /* sentinel */ },
 317
 318 };
 319
 320 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 321         .dev_configure        = ixgbe_dev_configure,
 322         .dev_start            = ixgbe_dev_start,
 323         .dev_stop             = ixgbe_dev_stop,
 324         .dev_set_link_up    = ixgbe_dev_set_link_up,
 325         .dev_set_link_down  = ixgbe_dev_set_link_down,
 326         .dev_close            = ixgbe_dev_close,
 327         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 328         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 329         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 330         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 331         .link_update          = ixgbe_dev_link_update,
 332         .stats_get            = ixgbe_dev_stats_get,
 333         .stats_reset          = ixgbe_dev_stats_reset,
 334         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 335         .dev_infos_get        = ixgbe_dev_info_get,
 336         .mtu_set              = ixgbe_dev_mtu_set,
 337         .vlan_filter_set      = ixgbe_vlan_filter_set,
 338         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 339         .vlan_offload_set     = ixgbe_vlan_offload_set,
 340         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 341         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 342         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 343         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 344         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 345         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 346         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 347         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 348         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 349         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 350         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 351         .dev_led_on           = ixgbe_dev_led_on,
 352         .dev_led_off          = ixgbe_dev_led_off,
 353         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 354         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 355         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 356         .mac_addr_add         = ixgbe_add_rar,
 357         .mac_addr_remove      = ixgbe_remove_rar,
 358         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 359         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 360         .mirror_rule_set      = ixgbe_mirror_rule_set,
 361         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 362         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 363         .set_vf_rx            = ixgbe_set_pool_rx,
 364         .set_vf_tx            = ixgbe_set_pool_tx,
 365         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 366         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 367         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 368         .reta_update          = ixgbe_dev_rss_reta_update,
 369         .reta_query           = ixgbe_dev_rss_reta_query,
 370 #ifdef RTE_NIC_BYPASS
 371         .bypass_init          = ixgbe_bypass_init,
 372         .bypass_state_set     = ixgbe_bypass_state_store,
 373         .bypass_state_show    = ixgbe_bypass_state_show,
 374         .bypass_event_set     = ixgbe_bypass_event_store,
 375         .bypass_event_show    = ixgbe_bypass_event_show,
 376         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 377         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 378         .bypass_ver_show      = ixgbe_bypass_ver_show,
 379         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 380 #endif /* RTE_NIC_BYPASS */
 381         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 382         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 383         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 384 };
 385
 386 /*
 387  * dev_ops for virtual function, bare necessities for basic vf
 388  * operation have been implemented
 389  */
 390 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 391
 392         .dev_configure        = ixgbevf_dev_configure,
 393         .dev_start            = ixgbevf_dev_start,
 394         .dev_stop             = ixgbevf_dev_stop,
 395         .link_update          = ixgbe_dev_link_update,
 396         .stats_get            = ixgbevf_dev_stats_get,
 397         .stats_reset          = ixgbevf_dev_stats_reset,
 398         .dev_close            = ixgbevf_dev_close,
 399         .dev_infos_get        = ixgbevf_dev_info_get,
 400         .mtu_set              = ixgbevf_dev_set_mtu,
 401         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 402         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 403         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 404         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 405         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 406         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 407         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 408         .mac_addr_add         = ixgbevf_add_mac_addr,
 409         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 410 };
 411
 412 /**
 413  * Atomically reads the link status information from global
 414  * structure rte_eth_dev.
 415  *
 416  * @param dev
 417  *   - Pointer to the structure rte_eth_dev to read from.
 418  *   - Pointer to the buffer to be saved with the link status.
 419  *
 420  * @return
 421  *   - On success, zero.
 422  *   - On failure, negative value.
 423  */
 424 static inline int
 425 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 426                                 struct rte_eth_link *link)
 427 {
 428         struct rte_eth_link *dst = link;
 429         struct rte_eth_link *src = &(dev->data->dev_link);
 430
 431         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 432                                         *(uint64_t *)src) == 0)
 433                 return -1;
 434
 435         return 0;
 436 }
 437
 438 /**
 439  * Atomically writes the link status information into global
 440  * structure rte_eth_dev.
 441  *
 442  * @param dev
 443  *   - Pointer to the structure rte_eth_dev to read from.
 444  *   - Pointer to the buffer to be saved with the link status.
 445  *
 446  * @return
 447  *   - On success, zero.
 448  *   - On failure, negative value.
 449  */
 450 static inline int
 451 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 452                                 struct rte_eth_link *link)
 453 {
 454         struct rte_eth_link *dst = &(dev->data->dev_link);
 455         struct rte_eth_link *src = link;
 456
 457         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 458                                         *(uint64_t *)src) == 0)
 459                 return -1;
 460
 461         return 0;
 462 }
 463
 464 /*
 465  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 466  */
 467 static inline int
 468 ixgbe_is_sfp(struct ixgbe_hw *hw)
 469 {
 470         switch (hw->phy.type) {
 471         case ixgbe_phy_sfp_avago:
 472         case ixgbe_phy_sfp_ftl:
 473         case ixgbe_phy_sfp_intel:
 474         case ixgbe_phy_sfp_unknown:
 475         case ixgbe_phy_sfp_passive_tyco:
 476         case ixgbe_phy_sfp_passive_unknown:
 477                 return 1;
 478         default:
 479                 return 0;
 480         }
 481 }
 482
 483 static inline int32_t
 484 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 485 {
 486         uint32_t ctrl_ext;
 487         int32_t status;
 488
 489         status = ixgbe_reset_hw(hw);
 490
 491         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 492         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 493         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 494         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 495         IXGBE_WRITE_FLUSH(hw);
 496
 497         return status;
 498 }
 499
 500 static inline void
 501 ixgbe_enable_intr(struct rte_eth_dev *dev)
 502 {
 503         struct ixgbe_interrupt *intr =
 504                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 505         struct ixgbe_hw *hw =
 506                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 507
 508         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 509         IXGBE_WRITE_FLUSH(hw);
 510 }
 511
 512 /*
 513  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 514  */
 515 static void
 516 ixgbe_disable_intr(struct ixgbe_hw *hw)
 517 {
 518         PMD_INIT_FUNC_TRACE();
 519
 520         if (hw->mac.type == ixgbe_mac_82598EB) {
 521                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 522         } else {
 523                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 524                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 525                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 526         }
 527         IXGBE_WRITE_FLUSH(hw);
 528 }
 529
 530 /*
 531  * This function resets queue statistics mapping registers.
 532  * From Niantic datasheet, Initialization of Statistics section:
 533  * "...if software requires the queue counters, the RQSMR and TQSM registers
 534  * must be re-programmed following a device reset.
 535  */
 536 static void
 537 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 538 {
 539         uint32_t i;
 540
 541         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 542                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 543                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 544         }
 545 }
 546
 547
 548 static int
 549 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 550                                   uint16_t queue_id,
 551                                   uint8_t stat_idx,
 552                                   uint8_t is_rx)
 553 {
 554 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 555 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 556 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 557
 558         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 559         struct ixgbe_stat_mapping_registers *stat_mappings =
 560                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 561         uint32_t qsmr_mask = 0;
 562         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 563         uint32_t q_map;
 564         uint8_t n, offset;
 565
 566         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 567                 (hw->mac.type != ixgbe_mac_X540) &&
 568                 (hw->mac.type != ixgbe_mac_X550) &&
 569                 (hw->mac.type != ixgbe_mac_X550EM_x))
 570                 return -ENOSYS;
 571
 572         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 573                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 574                      queue_id, stat_idx);
 575
 576         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 577         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 578                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 579                 return -EIO;
 580         }
 581         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 582
 583         /* Now clear any previous stat_idx set */
 584         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 585         if (!is_rx)
 586                 stat_mappings->tqsm[n] &= ~clearing_mask;
 587         else
 588                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 589
 590         q_map = (uint32_t)stat_idx;
 591         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 592         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 593         if (!is_rx)
 594                 stat_mappings->tqsm[n] |= qsmr_mask;
 595         else
 596                 stat_mappings->rqsmr[n] |= qsmr_mask;
 597
 598         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 599                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 600                      queue_id, stat_idx);
 601         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 602                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 603
 604         /* Now write the mapping in the appropriate register */
 605         if (is_rx) {
 606                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 607                              stat_mappings->rqsmr[n], n);
 608                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 609         }
 610         else {
 611                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 612                              stat_mappings->tqsm[n], n);
 613                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 614         }
 615         return 0;
 616 }
 617
 618 static void
 619 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 620 {
 621         struct ixgbe_stat_mapping_registers *stat_mappings =
 622                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 623         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 624         int i;
 625
 626         /* write whatever was in stat mapping table to the NIC */
 627         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 628                 /* rx */
 629                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 630
 631                 /* tx */
 632                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 633         }
 634 }
 635
 636 static void
 637 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 638 {
 639         uint8_t i;
 640         struct ixgbe_dcb_tc_config *tc;
 641         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 642
 643         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 644         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 645         for (i = 0; i < dcb_max_tc; i++) {
 646                 tc = &dcb_config->tc_config[i];
 647                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 648                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 649                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 650                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 651                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 652                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 653                 tc->pfc = ixgbe_dcb_pfc_disabled;
 654         }
 655
 656         /* Initialize default user to priority mapping, UPx->TC0 */
 657         tc = &dcb_config->tc_config[0];
 658         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 659         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 660         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 661                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 662                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 663         }
 664         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 665         dcb_config->pfc_mode_enable = false;
 666         dcb_config->vt_mode = true;
 667         dcb_config->round_robin_enable = false;
 668         /* support all DCB capabilities in 82599 */
 669         dcb_config->support.capabilities = 0xFF;
 670
 671         /*we only support 4 Tcs for X540, X550 */
 672         if (hw->mac.type == ixgbe_mac_X540 ||
 673                 hw->mac.type == ixgbe_mac_X550 ||
 674                 hw->mac.type == ixgbe_mac_X550EM_x) {
 675                 dcb_config->num_tcs.pg_tcs = 4;
 676                 dcb_config->num_tcs.pfc_tcs = 4;
 677         }
 678 }
 679
 680 /*
 681  * Ensure that all locks are released before first NVM or PHY access
 682  */
 683 static void
 684 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 685 {
 686         uint16_t mask;
 687
 688         /*
 689          * Phy lock should not fail in this early stage. If this is the case,
 690          * it is due to an improper exit of the application.
 691          * So force the release of the faulty lock. Release of common lock
 692          * is done automatically by swfw_sync function.
 693          */
 694         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 695         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 696                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 697         }
 698         ixgbe_release_swfw_semaphore(hw, mask);
 699
 700         /*
 701          * These ones are more tricky since they are common to all ports; but
 702          * swfw_sync retries last long enough (1s) to be almost sure that if
 703          * lock can not be taken it is due to an improper lock of the
 704          * semaphore.
 705          */
 706         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 707         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 708                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 709         }
 710         ixgbe_release_swfw_semaphore(hw, mask);
 711 }
 712
 713 /*
 714  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 715  * It returns 0 on success.
 716  */
 717 static int
 718 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 719 {
 720         struct rte_pci_device *pci_dev;
 721         struct ixgbe_hw *hw =
 722                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 723         struct ixgbe_vfta * shadow_vfta =
 724                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 725         struct ixgbe_hwstrip *hwstrip =
 726                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 727         struct ixgbe_dcb_config *dcb_config =
 728                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 729         struct ixgbe_filter_info *filter_info =
 730                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 731         uint32_t ctrl_ext;
 732         uint16_t csum;
 733         int diag, i;
 734
 735         PMD_INIT_FUNC_TRACE();
 736
 737         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 738         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 739         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 740
 741         /*
 742          * For secondary processes, we don't initialise any further as primary
 743          * has already done this work. Only check we don't need a different
 744          * RX and TX function.
 745          */
 746         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 747                 struct igb_tx_queue *txq;
 748                 /* TX queue function in primary, set by last queue initialized
 749                  * Tx queue may not initialized by primary process */
 750                 if (eth_dev->data->tx_queues) {
 751                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 752                         set_tx_function(eth_dev, txq);
 753                 } else {
 754                         /* Use default TX function if we get here */
 755                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 756                                            "Using default TX function.");
 757                 }
 758
 759                 if (eth_dev->data->scattered_rx)
 760                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 761                 return 0;
 762         }
 763         pci_dev = eth_dev->pci_dev;
 764
 765         /* Vendor and Device ID need to be set before init of shared code */
 766         hw->device_id = pci_dev->id.device_id;
 767         hw->vendor_id = pci_dev->id.vendor_id;
 768         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 769         hw->allow_unsupported_sfp = 1;
 770
 771         /* Initialize the shared code (base driver) */
 772 #ifdef RTE_NIC_BYPASS
 773         diag = ixgbe_bypass_init_shared_code(hw);
 774 #else
 775         diag = ixgbe_init_shared_code(hw);
 776 #endif /* RTE_NIC_BYPASS */
 777
 778         if (diag != IXGBE_SUCCESS) {
 779                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 780                 return -EIO;
 781         }
 782
 783         /* pick up the PCI bus settings for reporting later */
 784         ixgbe_get_bus_info(hw);
 785
 786         /* Unlock any pending hardware semaphore */
 787         ixgbe_swfw_lock_reset(hw);
 788
 789         /* Initialize DCB configuration*/
 790         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 791         ixgbe_dcb_init(hw,dcb_config);
 792         /* Get Hardware Flow Control setting */
 793         hw->fc.requested_mode = ixgbe_fc_full;
 794         hw->fc.current_mode = ixgbe_fc_full;
 795         hw->fc.pause_time = IXGBE_FC_PAUSE;
 796         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 797                 hw->fc.low_water[i] = IXGBE_FC_LO;
 798                 hw->fc.high_water[i] = IXGBE_FC_HI;
 799         }
 800         hw->fc.send_xon = 1;
 801
 802         /* Make sure we have a good EEPROM before we read from it */
 803         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 804         if (diag != IXGBE_SUCCESS) {
 805                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 806                 return -EIO;
 807         }
 808
 809 #ifdef RTE_NIC_BYPASS
 810         diag = ixgbe_bypass_init_hw(hw);
 811 #else
 812         diag = ixgbe_init_hw(hw);
 813 #endif /* RTE_NIC_BYPASS */
 814
 815         /*
 816          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 817          * is called too soon after the kernel driver unbinding/binding occurs.
 818          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 819          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 820          * also called. See ixgbe_identify_phy_82599(). The reason for the
 821          * failure is not known, and only occuts when virtualisation features
 822          * are disabled in the bios. A delay of 100ms  was found to be enough by
 823          * trial-and-error, and is doubled to be safe.
 824          */
 825         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 826                 rte_delay_ms(200);
 827                 diag = ixgbe_init_hw(hw);
 828         }
 829
 830         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 831                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 832                     "LOM.  Please be aware there may be issues associated "
 833                     "with your hardware.");
 834                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 835                     "please contact your Intel or hardware representative "
 836                     "who provided you with this hardware.");
 837         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 838                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 839         if (diag) {
 840                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 841                 return -EIO;
 842         }
 843
 844         /* disable interrupt */
 845         ixgbe_disable_intr(hw);
 846
 847         /* reset mappings for queue statistics hw counters*/
 848         ixgbe_reset_qstat_mappings(hw);
 849
 850         /* Allocate memory for storing MAC addresses */
 851         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 852                         hw->mac.num_rar_entries, 0);
 853         if (eth_dev->data->mac_addrs == NULL) {
 854                 PMD_INIT_LOG(ERR,
 855                         "Failed to allocate %u bytes needed to store "
 856                         "MAC addresses",
 857                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 858                 return -ENOMEM;
 859         }
 860         /* Copy the permanent MAC address */
 861         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 862                         &eth_dev->data->mac_addrs[0]);
 863
 864         /* Allocate memory for storing hash filter MAC addresses */
 865         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 866                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 867         if (eth_dev->data->hash_mac_addrs == NULL) {
 868                 PMD_INIT_LOG(ERR,
 869                         "Failed to allocate %d bytes needed to store MAC addresses",
 870                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 871                 return -ENOMEM;
 872         }
 873
 874         /* initialize the vfta */
 875         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 876
 877         /* initialize the hw strip bitmap*/
 878         memset(hwstrip, 0, sizeof(*hwstrip));
 879
 880         /* initialize PF if max_vfs not zero */
 881         ixgbe_pf_host_init(eth_dev);
 882
 883         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 884         /* let hardware know driver is loaded */
 885         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 886         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 887         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 888         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 889         IXGBE_WRITE_FLUSH(hw);
 890
 891         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 892                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 893                              (int) hw->mac.type, (int) hw->phy.type,
 894                              (int) hw->phy.sfp_type);
 895         else
 896                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 897                              (int) hw->mac.type, (int) hw->phy.type);
 898
 899         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 900                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 901                         pci_dev->id.device_id);
 902
 903         rte_intr_callback_register(&(pci_dev->intr_handle),
 904                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 905
 906         /* enable uio intr after callback register */
 907         rte_intr_enable(&(pci_dev->intr_handle));
 908
 909         /* enable support intr */
 910         ixgbe_enable_intr(eth_dev);
 911
 912         /* initialize 5tuple filter list */
 913         TAILQ_INIT(&filter_info->fivetuple_list);
 914         memset(filter_info->fivetuple_mask, 0,
 915                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
 916
 917         return 0;
 918 }
 919
 920
 921 /*
 922  * Negotiate mailbox API version with the PF.
 923  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 924  * Then we try to negotiate starting with the most recent one.
 925  * If all negotiation attempts fail, then we will proceed with
 926  * the default one (ixgbe_mbox_api_10).
 927  */
 928 static void
 929 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 930 {
 931         int32_t i;
 932
 933         /* start with highest supported, proceed down */
 934         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 935                 ixgbe_mbox_api_11,
 936                 ixgbe_mbox_api_10,
 937         };
 938
 939         for (i = 0;
 940                         i != RTE_DIM(sup_ver) &&
 941                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 942                         i++)
 943                 ;
 944 }
 945
 946 static void
 947 generate_random_mac_addr(struct ether_addr *mac_addr)
 948 {
 949         uint64_t random;
 950
 951         /* Set Organizationally Unique Identifier (OUI) prefix. */
 952         mac_addr->addr_bytes[0] = 0x00;
 953         mac_addr->addr_bytes[1] = 0x09;
 954         mac_addr->addr_bytes[2] = 0xC0;
 955         /* Force indication of locally assigned MAC address. */
 956         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 957         /* Generate the last 3 bytes of the MAC address with a random number. */
 958         random = rte_rand();
 959         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 960 }
 961
 962 /*
 963  * Virtual Function device init
 964  */
 965 static int
 966 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
 967 {
 968         int diag;
 969         uint32_t tc, tcs;
 970         struct rte_pci_device *pci_dev;
 971         struct ixgbe_hw *hw =
 972                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 973         struct ixgbe_vfta * shadow_vfta =
 974                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 975         struct ixgbe_hwstrip *hwstrip =
 976                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 977         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 978
 979         PMD_INIT_FUNC_TRACE();
 980
 981         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 982         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 983         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 984
 985         /* for secondary processes, we don't initialise any further as primary
 986          * has already done this work. Only check we don't need a different
 987          * RX function */
 988         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 989                 if (eth_dev->data->scattered_rx)
 990                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 991                 return 0;
 992         }
 993
 994         pci_dev = eth_dev->pci_dev;
 995
 996         hw->device_id = pci_dev->id.device_id;
 997         hw->vendor_id = pci_dev->id.vendor_id;
 998         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 999
1000         /* initialize the vfta */
1001         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1002
1003         /* initialize the hw strip bitmap*/
1004         memset(hwstrip, 0, sizeof(*hwstrip));
1005
1006         /* Initialize the shared code (base driver) */
1007         diag = ixgbe_init_shared_code(hw);
1008         if (diag != IXGBE_SUCCESS) {
1009                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1010                 return -EIO;
1011         }
1012
1013         /* init_mailbox_params */
1014         hw->mbx.ops.init_params(hw);
1015
1016         /* Disable the interrupts for VF */
1017         ixgbevf_intr_disable(hw);
1018
1019         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1020         diag = hw->mac.ops.reset_hw(hw);
1021
1022         /*
1023          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1024          * the underlying PF driver has not assigned a MAC address to the VF.
1025          * In this case, assign a random MAC address.
1026          */
1027         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1028                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1029                 return (diag);
1030         }
1031
1032         /* negotiate mailbox API version to use with the PF. */
1033         ixgbevf_negotiate_api(hw);
1034
1035         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1036         ixgbevf_get_queues(hw, &tcs, &tc);
1037
1038         /* Allocate memory for storing MAC addresses */
1039         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1040                         hw->mac.num_rar_entries, 0);
1041         if (eth_dev->data->mac_addrs == NULL) {
1042                 PMD_INIT_LOG(ERR,
1043                         "Failed to allocate %u bytes needed to store "
1044                         "MAC addresses",
1045                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1046                 return -ENOMEM;
1047         }
1048
1049         /* Generate a random MAC address, if none was assigned by PF. */
1050         if (is_zero_ether_addr(perm_addr)) {
1051                 generate_random_mac_addr(perm_addr);
1052                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1053                 if (diag) {
1054                         rte_free(eth_dev->data->mac_addrs);
1055                         eth_dev->data->mac_addrs = NULL;
1056                         return diag;
1057                 }
1058                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1059                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1060                              "%02x:%02x:%02x:%02x:%02x:%02x",
1061                              perm_addr->addr_bytes[0],
1062                              perm_addr->addr_bytes[1],
1063                              perm_addr->addr_bytes[2],
1064                              perm_addr->addr_bytes[3],
1065                              perm_addr->addr_bytes[4],
1066                              perm_addr->addr_bytes[5]);
1067         }
1068
1069         /* Copy the permanent MAC address */
1070         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1071
1072         /* reset the hardware with the new settings */
1073         diag = hw->mac.ops.start_hw(hw);
1074         switch (diag) {
1075                 case  0:
1076                         break;
1077
1078                 default:
1079                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1080                         return (-EIO);
1081         }
1082
1083         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1084                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1085                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1086
1087         return 0;
1088 }
1089
1090 static struct eth_driver rte_ixgbe_pmd = {
1091         {
1092                 .name = "rte_ixgbe_pmd",
1093                 .id_table = pci_id_ixgbe_map,
1094                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1095         },
1096         .eth_dev_init = eth_ixgbe_dev_init,
1097         .dev_private_size = sizeof(struct ixgbe_adapter),
1098 };
1099
1100 /*
1101  * virtual function driver struct
1102  */
1103 static struct eth_driver rte_ixgbevf_pmd = {
1104         {
1105                 .name = "rte_ixgbevf_pmd",
1106                 .id_table = pci_id_ixgbevf_map,
1107                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1108         },
1109         .eth_dev_init = eth_ixgbevf_dev_init,
1110         .dev_private_size = sizeof(struct ixgbe_adapter),
1111 };
1112
1113 /*
1114  * Driver initialization routine.
1115  * Invoked once at EAL init time.
1116  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1117  */
1118 static int
1119 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1120 {
1121         PMD_INIT_FUNC_TRACE();
1122
1123         rte_eth_driver_register(&rte_ixgbe_pmd);
1124         return 0;
1125 }
1126
1127 /*
1128  * VF Driver initialization routine.
1129  * Invoked one at EAL init time.
1130  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1131  */
1132 static int
1133 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1134 {
1135         PMD_INIT_FUNC_TRACE();
1136
1137         rte_eth_driver_register(&rte_ixgbevf_pmd);
1138         return (0);
1139 }
1140
1141 static int
1142 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1143 {
1144         struct ixgbe_hw *hw =
1145                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1146         struct ixgbe_vfta * shadow_vfta =
1147                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1148         uint32_t vfta;
1149         uint32_t vid_idx;
1150         uint32_t vid_bit;
1151
1152         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1153         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1154         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1155         if (on)
1156                 vfta |= vid_bit;
1157         else
1158                 vfta &= ~vid_bit;
1159         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1160
1161         /* update local VFTA copy */
1162         shadow_vfta->vfta[vid_idx] = vfta;
1163
1164         return 0;
1165 }
1166
1167 static void
1168 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1169 {
1170         if (on)
1171                 ixgbe_vlan_hw_strip_enable(dev, queue);
1172         else
1173                 ixgbe_vlan_hw_strip_disable(dev, queue);
1174 }
1175
1176 static void
1177 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1178 {
1179         struct ixgbe_hw *hw =
1180                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1181
1182         /* Only the high 16-bits is valid */
1183         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1184 }
1185
1186 void
1187 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1188 {
1189         struct ixgbe_hw *hw =
1190                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1191         uint32_t vlnctrl;
1192
1193         PMD_INIT_FUNC_TRACE();
1194
1195         /* Filter Table Disable */
1196         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1197         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1198
1199         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1200 }
1201
1202 void
1203 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1204 {
1205         struct ixgbe_hw *hw =
1206                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1207         struct ixgbe_vfta * shadow_vfta =
1208                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1209         uint32_t vlnctrl;
1210         uint16_t i;
1211
1212         PMD_INIT_FUNC_TRACE();
1213
1214         /* Filter Table Enable */
1215         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1216         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1217         vlnctrl |= IXGBE_VLNCTRL_VFE;
1218
1219         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1220
1221         /* write whatever is in local vfta copy */
1222         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1223                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1224 }
1225
1226 static void
1227 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1228 {
1229         struct ixgbe_hwstrip *hwstrip =
1230                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1231
1232         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1233                 return;
1234
1235         if (on)
1236                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1237         else
1238                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1239 }
1240
1241 static void
1242 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1243 {
1244         struct ixgbe_hw *hw =
1245                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1246         uint32_t ctrl;
1247
1248         PMD_INIT_FUNC_TRACE();
1249
1250         if (hw->mac.type == ixgbe_mac_82598EB) {
1251                 /* No queue level support */
1252                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1253                 return;
1254         }
1255         else {
1256                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1257                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1258                 ctrl &= ~IXGBE_RXDCTL_VME;
1259                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1260         }
1261         /* record those setting for HW strip per queue */
1262         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1263 }
1264
1265 static void
1266 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1267 {
1268         struct ixgbe_hw *hw =
1269                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1270         uint32_t ctrl;
1271
1272         PMD_INIT_FUNC_TRACE();
1273
1274         if (hw->mac.type == ixgbe_mac_82598EB) {
1275                 /* No queue level supported */
1276                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1277                 return;
1278         }
1279         else {
1280                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1281                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1282                 ctrl |= IXGBE_RXDCTL_VME;
1283                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1284         }
1285         /* record those setting for HW strip per queue */
1286         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1287 }
1288
1289 void
1290 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1291 {
1292         struct ixgbe_hw *hw =
1293                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1294         uint32_t ctrl;
1295         uint16_t i;
1296
1297         PMD_INIT_FUNC_TRACE();
1298
1299         if (hw->mac.type == ixgbe_mac_82598EB) {
1300                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1301                 ctrl &= ~IXGBE_VLNCTRL_VME;
1302                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1303         }
1304         else {
1305                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1306                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1307                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1308                         ctrl &= ~IXGBE_RXDCTL_VME;
1309                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1310
1311                         /* record those setting for HW strip per queue */
1312                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1313                 }
1314         }
1315 }
1316
1317 void
1318 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1319 {
1320         struct ixgbe_hw *hw =
1321                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1322         uint32_t ctrl;
1323         uint16_t i;
1324
1325         PMD_INIT_FUNC_TRACE();
1326
1327         if (hw->mac.type == ixgbe_mac_82598EB) {
1328                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1329                 ctrl |= IXGBE_VLNCTRL_VME;
1330                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1331         }
1332         else {
1333                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1334                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1335                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1336                         ctrl |= IXGBE_RXDCTL_VME;
1337                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1338
1339                         /* record those setting for HW strip per queue */
1340                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1341                 }
1342         }
1343 }
1344
1345 static void
1346 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1347 {
1348         struct ixgbe_hw *hw =
1349                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1350         uint32_t ctrl;
1351
1352         PMD_INIT_FUNC_TRACE();
1353
1354         /* DMATXCTRL: Geric Double VLAN Disable */
1355         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1356         ctrl &= ~IXGBE_DMATXCTL_GDV;
1357         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1358
1359         /* CTRL_EXT: Global Double VLAN Disable */
1360         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1361         ctrl &= ~IXGBE_EXTENDED_VLAN;
1362         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1363
1364 }
1365
1366 static void
1367 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1368 {
1369         struct ixgbe_hw *hw =
1370                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1371         uint32_t ctrl;
1372
1373         PMD_INIT_FUNC_TRACE();
1374
1375         /* DMATXCTRL: Geric Double VLAN Enable */
1376         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1377         ctrl |= IXGBE_DMATXCTL_GDV;
1378         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1379
1380         /* CTRL_EXT: Global Double VLAN Enable */
1381         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1382         ctrl |= IXGBE_EXTENDED_VLAN;
1383         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1384
1385         /*
1386          * VET EXT field in the EXVET register = 0x8100 by default
1387          * So no need to change. Same to VT field of DMATXCTL register
1388          */
1389 }
1390
1391 static void
1392 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1393 {
1394         if(mask & ETH_VLAN_STRIP_MASK){
1395                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1396                         ixgbe_vlan_hw_strip_enable_all(dev);
1397                 else
1398                         ixgbe_vlan_hw_strip_disable_all(dev);
1399         }
1400
1401         if(mask & ETH_VLAN_FILTER_MASK){
1402                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1403                         ixgbe_vlan_hw_filter_enable(dev);
1404                 else
1405                         ixgbe_vlan_hw_filter_disable(dev);
1406         }
1407
1408         if(mask & ETH_VLAN_EXTEND_MASK){
1409                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1410                         ixgbe_vlan_hw_extend_enable(dev);
1411                 else
1412                         ixgbe_vlan_hw_extend_disable(dev);
1413         }
1414 }
1415
1416 static void
1417 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1418 {
1419         struct ixgbe_hw *hw =
1420                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1421         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1422         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1423         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1424         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1425 }
1426
1427 static int
1428 ixgbe_dev_configure(struct rte_eth_dev *dev)
1429 {
1430         struct ixgbe_interrupt *intr =
1431                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1432
1433         PMD_INIT_FUNC_TRACE();
1434
1435         /* set flag to update link status after init */
1436         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1437
1438         return 0;
1439 }
1440
1441 /*
1442  * Configure device link speed and setup link.
1443  * It returns 0 on success.
1444  */
1445 static int
1446 ixgbe_dev_start(struct rte_eth_dev *dev)
1447 {
1448         struct ixgbe_hw *hw =
1449                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1450         struct ixgbe_vf_info *vfinfo =
1451                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1452         int err, link_up = 0, negotiate = 0;
1453         uint32_t speed = 0;
1454         int mask = 0;
1455         int status;
1456         uint16_t vf, idx;
1457
1458         PMD_INIT_FUNC_TRACE();
1459
1460         /* IXGBE devices don't support half duplex */
1461         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1462                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1463                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1464                              dev->data->dev_conf.link_duplex,
1465                              dev->data->port_id);
1466                 return -EINVAL;
1467         }
1468
1469         /* stop adapter */
1470         hw->adapter_stopped = FALSE;
1471         ixgbe_stop_adapter(hw);
1472
1473         /* reinitialize adapter
1474          * this calls reset and start */
1475         status = ixgbe_pf_reset_hw(hw);
1476         if (status != 0)
1477                 return -1;
1478         hw->mac.ops.start_hw(hw);
1479         hw->mac.get_link_status = true;
1480
1481         /* configure PF module if SRIOV enabled */
1482         ixgbe_pf_host_configure(dev);
1483
1484         /* initialize transmission unit */
1485         ixgbe_dev_tx_init(dev);
1486
1487         /* This can fail when allocating mbufs for descriptor rings */
1488         err = ixgbe_dev_rx_init(dev);
1489         if (err) {
1490                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1491                 goto error;
1492         }
1493
1494         err = ixgbe_dev_rxtx_start(dev);
1495         if (err < 0) {
1496                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1497                 goto error;
1498         }
1499
1500         /* Skip link setup if loopback mode is enabled for 82599. */
1501         if (hw->mac.type == ixgbe_mac_82599EB &&
1502                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1503                 goto skip_link_setup;
1504
1505         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1506                 err = hw->mac.ops.setup_sfp(hw);
1507                 if (err)
1508                         goto error;
1509         }
1510
1511         /* Turn on the laser */
1512         ixgbe_enable_tx_laser(hw);
1513
1514         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1515         if (err)
1516                 goto error;
1517         dev->data->dev_link.link_status = link_up;
1518
1519         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1520         if (err)
1521                 goto error;
1522
1523         switch(dev->data->dev_conf.link_speed) {
1524         case ETH_LINK_SPEED_AUTONEG:
1525                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1526                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1527                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1528                 break;
1529         case ETH_LINK_SPEED_100:
1530                 /*
1531                  * Invalid for 82598 but error will be detected by
1532                  * ixgbe_setup_link()
1533                  */
1534                 speed = IXGBE_LINK_SPEED_100_FULL;
1535                 break;
1536         case ETH_LINK_SPEED_1000:
1537                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1538                 break;
1539         case ETH_LINK_SPEED_10000:
1540                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1541                 break;
1542         default:
1543                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1544                              dev->data->dev_conf.link_speed,
1545                              dev->data->port_id);
1546                 goto error;
1547         }
1548
1549         err = ixgbe_setup_link(hw, speed, link_up);
1550         if (err)
1551                 goto error;
1552
1553 skip_link_setup:
1554
1555         /* check if lsc interrupt is enabled */
1556         if (dev->data->dev_conf.intr_conf.lsc != 0)
1557                 ixgbe_dev_lsc_interrupt_setup(dev);
1558
1559         /* resume enabled intr since hw reset */
1560         ixgbe_enable_intr(dev);
1561
1562         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1563                 ETH_VLAN_EXTEND_MASK;
1564         ixgbe_vlan_offload_set(dev, mask);
1565
1566         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1567                 /* Enable vlan filtering for VMDq */
1568                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1569         }
1570
1571         /* Configure DCB hw */
1572         ixgbe_configure_dcb(dev);
1573
1574         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1575                 err = ixgbe_fdir_configure(dev);
1576                 if (err)
1577                         goto error;
1578         }
1579
1580         /* Restore vf rate limit */
1581         if (vfinfo != NULL) {
1582                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1583                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1584                                 if (vfinfo[vf].tx_rate[idx] != 0)
1585                                         ixgbe_set_vf_rate_limit(dev, vf,
1586                                                 vfinfo[vf].tx_rate[idx],
1587                                                 1 << idx);
1588         }
1589
1590         ixgbe_restore_statistics_mapping(dev);
1591
1592         return (0);
1593
1594 error:
1595         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1596         ixgbe_dev_clear_queues(dev);
1597         return -EIO;
1598 }
1599
1600 /*
1601  * Stop device: disable rx and tx functions to allow for reconfiguring.
1602  */
1603 static void
1604 ixgbe_dev_stop(struct rte_eth_dev *dev)
1605 {
1606         struct rte_eth_link link;
1607         struct ixgbe_hw *hw =
1608                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1609         struct ixgbe_vf_info *vfinfo =
1610                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1611         struct ixgbe_filter_info *filter_info =
1612                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1613         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1614         int vf;
1615
1616         PMD_INIT_FUNC_TRACE();
1617
1618         /* disable interrupts */
1619         ixgbe_disable_intr(hw);
1620
1621         /* reset the NIC */
1622         ixgbe_pf_reset_hw(hw);
1623         hw->adapter_stopped = FALSE;
1624
1625         /* stop adapter */
1626         ixgbe_stop_adapter(hw);
1627
1628         for (vf = 0; vfinfo != NULL &&
1629                      vf < dev->pci_dev->max_vfs; vf++)
1630                 vfinfo[vf].clear_to_send = false;
1631
1632         /* Turn off the laser */
1633         ixgbe_disable_tx_laser(hw);
1634
1635         ixgbe_dev_clear_queues(dev);
1636
1637         /* Clear stored conf */
1638         dev->data->scattered_rx = 0;
1639
1640         /* Clear recorded link status */
1641         memset(&link, 0, sizeof(link));
1642         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1643
1644         /* Remove all ntuple filters of the device */
1645         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1646              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1647                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1648                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1649                              p_5tuple, entries);
1650                 rte_free(p_5tuple);
1651         }
1652         memset(filter_info->fivetuple_mask, 0,
1653                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1654
1655 }
1656
1657 /*
1658  * Set device link up: enable tx laser.
1659  */
1660 static int
1661 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1662 {
1663         struct ixgbe_hw *hw =
1664                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665         if (hw->mac.type == ixgbe_mac_82599EB) {
1666 #ifdef RTE_NIC_BYPASS
1667                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1668                         /* Not suported in bypass mode */
1669                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1670                                      "by device id 0x%x", hw->device_id);
1671                         return -ENOTSUP;
1672                 }
1673 #endif
1674                 /* Turn on the laser */
1675                 ixgbe_enable_tx_laser(hw);
1676                 return 0;
1677         }
1678
1679         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1680                      hw->device_id);
1681         return -ENOTSUP;
1682 }
1683
1684 /*
1685  * Set device link down: disable tx laser.
1686  */
1687 static int
1688 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1689 {
1690         struct ixgbe_hw *hw =
1691                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1692         if (hw->mac.type == ixgbe_mac_82599EB) {
1693 #ifdef RTE_NIC_BYPASS
1694                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1695                         /* Not suported in bypass mode */
1696                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1697                                      "by device id 0x%x", hw->device_id);
1698                         return -ENOTSUP;
1699                 }
1700 #endif
1701                 /* Turn off the laser */
1702                 ixgbe_disable_tx_laser(hw);
1703                 return 0;
1704         }
1705
1706         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1707                      hw->device_id);
1708         return -ENOTSUP;
1709 }
1710
1711 /*
1712  * Reest and stop device.
1713  */
1714 static void
1715 ixgbe_dev_close(struct rte_eth_dev *dev)
1716 {
1717         struct ixgbe_hw *hw =
1718                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719
1720         PMD_INIT_FUNC_TRACE();
1721
1722         ixgbe_pf_reset_hw(hw);
1723
1724         ixgbe_dev_stop(dev);
1725         hw->adapter_stopped = 1;
1726
1727         ixgbe_disable_pcie_master(hw);
1728
1729         /* reprogram the RAR[0] in case user changed it. */
1730         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1731 }
1732
1733 /*
1734  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1735  */
1736 static void
1737 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1738 {
1739         struct ixgbe_hw *hw =
1740                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1741         struct ixgbe_hw_stats *hw_stats =
1742                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1743         uint32_t bprc, lxon, lxoff, total;
1744         uint64_t total_missed_rx, total_qbrc, total_qprc;
1745         unsigned i;
1746
1747         total_missed_rx = 0;
1748         total_qbrc = 0;
1749         total_qprc = 0;
1750
1751         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1752         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1753         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1754         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1755
1756         for (i = 0; i < 8; i++) {
1757                 uint32_t mp;
1758                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1759                 /* global total per queue */
1760                 hw_stats->mpc[i] += mp;
1761                 /* Running comprehensive total for stats display */
1762                 total_missed_rx += hw_stats->mpc[i];
1763                 if (hw->mac.type == ixgbe_mac_82598EB)
1764                         hw_stats->rnbc[i] +=
1765                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1766                 hw_stats->pxontxc[i] +=
1767                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1768                 hw_stats->pxonrxc[i] +=
1769                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1770                 hw_stats->pxofftxc[i] +=
1771                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1772                 hw_stats->pxoffrxc[i] +=
1773                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1774                 hw_stats->pxon2offc[i] +=
1775                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1776         }
1777         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1778                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1779                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1780                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1781                 hw_stats->qbrc[i] +=
1782                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1783                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1784                 hw_stats->qbtc[i] +=
1785                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1786                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1787
1788                 total_qprc += hw_stats->qprc[i];
1789                 total_qbrc += hw_stats->qbrc[i];
1790         }
1791         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1792         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1793         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1794
1795         /* Note that gprc counts missed packets */
1796         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1797
1798         if (hw->mac.type != ixgbe_mac_82598EB) {
1799                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1800                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1801                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1802                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1803                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1804                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1805                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1806                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1807         } else {
1808                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1809                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1810                 /* 82598 only has a counter in the high register */
1811                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1812                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1813                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1814         }
1815
1816         /*
1817          * Workaround: mprc hardware is incorrectly counting
1818          * broadcasts, so for now we subtract those.
1819          */
1820         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1821         hw_stats->bprc += bprc;
1822         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1823         if (hw->mac.type == ixgbe_mac_82598EB)
1824                 hw_stats->mprc -= bprc;
1825
1826         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1827         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1828         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1829         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1830         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1831         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1832
1833         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1834         hw_stats->lxontxc += lxon;
1835         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1836         hw_stats->lxofftxc += lxoff;
1837         total = lxon + lxoff;
1838
1839         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1840         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1841         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1842         hw_stats->gptc -= total;
1843         hw_stats->mptc -= total;
1844         hw_stats->ptc64 -= total;
1845         hw_stats->gotc -= total * ETHER_MIN_LEN;
1846
1847         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1848         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1849         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1850         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1851         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1852         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1853         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1854         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1855         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1856         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1857         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1858         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1859         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1860         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1861         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1862         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1863         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1864         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1865         /* Only read FCOE on 82599 */
1866         if (hw->mac.type != ixgbe_mac_82598EB) {
1867                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1868                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1869                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1870                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1871                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1872         }
1873
1874         if (stats == NULL)
1875                 return;
1876
1877         /* Fill out the rte_eth_stats statistics structure */
1878         stats->ipackets = total_qprc;
1879         stats->ibytes = total_qbrc;
1880         stats->opackets = hw_stats->gptc;
1881         stats->obytes = hw_stats->gotc;
1882         stats->imcasts = hw_stats->mprc;
1883
1884         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1885                 stats->q_ipackets[i] = hw_stats->qprc[i];
1886                 stats->q_opackets[i] = hw_stats->qptc[i];
1887                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1888                 stats->q_obytes[i] = hw_stats->qbtc[i];
1889                 stats->q_errors[i] = hw_stats->qprdc[i];
1890         }
1891
1892         /* Rx Errors */
1893         stats->ibadcrc  = hw_stats->crcerrs;
1894         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1895         stats->imissed  = total_missed_rx;
1896         stats->ierrors  = stats->ibadcrc +
1897                           stats->ibadlen +
1898                           stats->imissed +
1899                           hw_stats->illerrc + hw_stats->errbc;
1900
1901         /* Tx Errors */
1902         stats->oerrors  = 0;
1903
1904         /* XON/XOFF pause frames */
1905         stats->tx_pause_xon  = hw_stats->lxontxc;
1906         stats->rx_pause_xon  = hw_stats->lxonrxc;
1907         stats->tx_pause_xoff = hw_stats->lxofftxc;
1908         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1909
1910         /* Flow Director Stats registers */
1911         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1912         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1913         stats->fdirmatch = hw_stats->fdirmatch;
1914         stats->fdirmiss = hw_stats->fdirmiss;
1915 }
1916
1917 static void
1918 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1919 {
1920         struct ixgbe_hw_stats *stats =
1921                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1922
1923         /* HW registers are cleared on read */
1924         ixgbe_dev_stats_get(dev, NULL);
1925
1926         /* Reset software totals */
1927         memset(stats, 0, sizeof(*stats));
1928 }
1929
1930 static void
1931 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1932 {
1933         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1934         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1935                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1936
1937         /* Good Rx packet, include VF loopback */
1938         UPDATE_VF_STAT(IXGBE_VFGPRC,
1939             hw_stats->last_vfgprc, hw_stats->vfgprc);
1940
1941         /* Good Rx octets, include VF loopback */
1942         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1943             hw_stats->last_vfgorc, hw_stats->vfgorc);
1944
1945         /* Good Tx packet, include VF loopback */
1946         UPDATE_VF_STAT(IXGBE_VFGPTC,
1947             hw_stats->last_vfgptc, hw_stats->vfgptc);
1948
1949         /* Good Tx octets, include VF loopback */
1950         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1951             hw_stats->last_vfgotc, hw_stats->vfgotc);
1952
1953         /* Rx Multicst Packet */
1954         UPDATE_VF_STAT(IXGBE_VFMPRC,
1955             hw_stats->last_vfmprc, hw_stats->vfmprc);
1956
1957         if (stats == NULL)
1958                 return;
1959
1960         stats->ipackets = hw_stats->vfgprc;
1961         stats->ibytes = hw_stats->vfgorc;
1962         stats->opackets = hw_stats->vfgptc;
1963         stats->obytes = hw_stats->vfgotc;
1964         stats->imcasts = hw_stats->vfmprc;
1965 }
1966
1967 static void
1968 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1969 {
1970         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1971                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1972
1973         /* Sync HW register to the last stats */
1974         ixgbevf_dev_stats_get(dev, NULL);
1975
1976         /* reset HW current stats*/
1977         hw_stats->vfgprc = 0;
1978         hw_stats->vfgorc = 0;
1979         hw_stats->vfgptc = 0;
1980         hw_stats->vfgotc = 0;
1981         hw_stats->vfmprc = 0;
1982
1983 }
1984
1985 static void
1986 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1987 {
1988         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1989
1990         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1991         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1992         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1993         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1994         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1995         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1996         dev_info->max_vfs = dev->pci_dev->max_vfs;
1997         if (hw->mac.type == ixgbe_mac_82598EB)
1998                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1999         else
2000                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2001         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2002         dev_info->rx_offload_capa =
2003                 DEV_RX_OFFLOAD_VLAN_STRIP |
2004                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2005                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2006                 DEV_RX_OFFLOAD_TCP_CKSUM;
2007         dev_info->tx_offload_capa =
2008                 DEV_TX_OFFLOAD_VLAN_INSERT |
2009                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2010                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2011                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2012                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2013                 DEV_TX_OFFLOAD_TCP_TSO;
2014
2015         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2016                 .rx_thresh = {
2017                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2018                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2019                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2020                 },
2021                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2022                 .rx_drop_en = 0,
2023         };
2024
2025         dev_info->default_txconf = (struct rte_eth_txconf) {
2026                 .tx_thresh = {
2027                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2028                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2029                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2030                 },
2031                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2032                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2033                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2034                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2035         };
2036         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2037         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2038 }
2039
2040 static void
2041 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2042                      struct rte_eth_dev_info *dev_info)
2043 {
2044         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045
2046         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2047         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2048         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2049         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2050         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2051         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2052         dev_info->max_vfs = dev->pci_dev->max_vfs;
2053         if (hw->mac.type == ixgbe_mac_82598EB)
2054                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2055         else
2056                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2057         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2058                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2059                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2060                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2061         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2062                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2063                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2064                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2065                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2066
2067         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2068                 .rx_thresh = {
2069                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2070                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2071                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2072                 },
2073                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2074                 .rx_drop_en = 0,
2075         };
2076
2077         dev_info->default_txconf = (struct rte_eth_txconf) {
2078                 .tx_thresh = {
2079                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2080                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2081                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2082                 },
2083                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2084                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2085                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2086                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2087         };
2088 }
2089
2090 /* return 0 means link status changed, -1 means not changed */
2091 static int
2092 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2093 {
2094         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095         struct rte_eth_link link, old;
2096         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2097         int link_up;
2098         int diag;
2099
2100         link.link_status = 0;
2101         link.link_speed = 0;
2102         link.link_duplex = 0;
2103         memset(&old, 0, sizeof(old));
2104         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2105
2106         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2107         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2108                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2109         else
2110                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2111         if (diag != 0) {
2112                 link.link_speed = ETH_LINK_SPEED_100;
2113                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2114                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2115                 if (link.link_status == old.link_status)
2116                         return -1;
2117                 return 0;
2118         }
2119
2120         if (link_speed == IXGBE_LINK_SPEED_UNKNOWN &&
2121             !hw->mac.get_link_status) {
2122                 memcpy(&link, &old, sizeof(link));
2123                 return -1;
2124         }
2125
2126         if (link_up == 0) {
2127                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2128                 if (link.link_status == old.link_status)
2129                         return -1;
2130                 return 0;
2131         }
2132         link.link_status = 1;
2133         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2134
2135         switch (link_speed) {
2136         default:
2137         case IXGBE_LINK_SPEED_UNKNOWN:
2138                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2139                 link.link_speed = ETH_LINK_SPEED_100;
2140                 break;
2141
2142         case IXGBE_LINK_SPEED_100_FULL:
2143                 link.link_speed = ETH_LINK_SPEED_100;
2144                 break;
2145
2146         case IXGBE_LINK_SPEED_1GB_FULL:
2147                 link.link_speed = ETH_LINK_SPEED_1000;
2148                 break;
2149
2150         case IXGBE_LINK_SPEED_10GB_FULL:
2151                 link.link_speed = ETH_LINK_SPEED_10000;
2152                 break;
2153         }
2154         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2155
2156         if (link.link_status == old.link_status)
2157                 return -1;
2158
2159         return 0;
2160 }
2161
2162 static void
2163 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2164 {
2165         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2166         uint32_t fctrl;
2167
2168         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2169         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2170         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2171 }
2172
2173 static void
2174 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2175 {
2176         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177         uint32_t fctrl;
2178
2179         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2180         fctrl &= (~IXGBE_FCTRL_UPE);
2181         if (dev->data->all_multicast == 1)
2182                 fctrl |= IXGBE_FCTRL_MPE;
2183         else
2184                 fctrl &= (~IXGBE_FCTRL_MPE);
2185         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2186 }
2187
2188 static void
2189 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2190 {
2191         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192         uint32_t fctrl;
2193
2194         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2195         fctrl |= IXGBE_FCTRL_MPE;
2196         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2197 }
2198
2199 static void
2200 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2201 {
2202         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2203         uint32_t fctrl;
2204
2205         if (dev->data->promiscuous == 1)
2206                 return; /* must remain in all_multicast mode */
2207
2208         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2209         fctrl &= (~IXGBE_FCTRL_MPE);
2210         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2211 }
2212
2213 /**
2214  * It clears the interrupt causes and enables the interrupt.
2215  * It will be called once only during nic initialized.
2216  *
2217  * @param dev
2218  *  Pointer to struct rte_eth_dev.
2219  *
2220  * @return
2221  *  - On success, zero.
2222  *  - On failure, a negative value.
2223  */
2224 static int
2225 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2226 {
2227         struct ixgbe_interrupt *intr =
2228                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2229
2230         ixgbe_dev_link_status_print(dev);
2231         intr->mask |= IXGBE_EICR_LSC;
2232
2233         return 0;
2234 }
2235
2236 /*
2237  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2238  *
2239  * @param dev
2240  *  Pointer to struct rte_eth_dev.
2241  *
2242  * @return
2243  *  - On success, zero.
2244  *  - On failure, a negative value.
2245  */
2246 static int
2247 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2248 {
2249         uint32_t eicr;
2250         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2251         struct ixgbe_interrupt *intr =
2252                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2253
2254         /* clear all cause mask */
2255         ixgbe_disable_intr(hw);
2256
2257         /* read-on-clear nic registers here */
2258         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2259         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2260
2261         intr->flags = 0;
2262         if (eicr & IXGBE_EICR_LSC) {
2263                 /* set flag for async link update */
2264                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2265         }
2266
2267         if (eicr & IXGBE_EICR_MAILBOX)
2268                 intr->flags |= IXGBE_FLAG_MAILBOX;
2269
2270         return 0;
2271 }
2272
2273 /**
2274  * It gets and then prints the link status.
2275  *
2276  * @param dev
2277  *  Pointer to struct rte_eth_dev.
2278  *
2279  * @return
2280  *  - On success, zero.
2281  *  - On failure, a negative value.
2282  */
2283 static void
2284 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2285 {
2286         struct rte_eth_link link;
2287
2288         memset(&link, 0, sizeof(link));
2289         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2290         if (link.link_status) {
2291                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2292                                         (int)(dev->data->port_id),
2293                                         (unsigned)link.link_speed,
2294                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2295                                         "full-duplex" : "half-duplex");
2296         } else {
2297                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2298                                 (int)(dev->data->port_id));
2299         }
2300         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2301                                 dev->pci_dev->addr.domain,
2302                                 dev->pci_dev->addr.bus,
2303                                 dev->pci_dev->addr.devid,
2304                                 dev->pci_dev->addr.function);
2305 }
2306
2307 /*
2308  * It executes link_update after knowing an interrupt occurred.
2309  *
2310  * @param dev
2311  *  Pointer to struct rte_eth_dev.
2312  *
2313  * @return
2314  *  - On success, zero.
2315  *  - On failure, a negative value.
2316  */
2317 static int
2318 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2319 {
2320         struct ixgbe_interrupt *intr =
2321                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2322         int64_t timeout;
2323         struct rte_eth_link link;
2324         int intr_enable_delay = false;
2325
2326         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2327
2328         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2329                 ixgbe_pf_mbx_process(dev);
2330                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2331         }
2332
2333         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2334                 /* get the link status before link update, for predicting later */
2335                 memset(&link, 0, sizeof(link));
2336                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2337
2338                 ixgbe_dev_link_update(dev, 0);
2339
2340                 /* likely to up */
2341                 if (!link.link_status)
2342                         /* handle it 1 sec later, wait it being stable */
2343                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2344                 /* likely to down */
2345                 else
2346                         /* handle it 4 sec later, wait it being stable */
2347                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2348
2349                 ixgbe_dev_link_status_print(dev);
2350
2351                 intr_enable_delay = true;
2352         }
2353
2354         if (intr_enable_delay) {
2355                 if (rte_eal_alarm_set(timeout * 1000,
2356                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2357                         PMD_DRV_LOG(ERR, "Error setting alarm");
2358         } else {
2359                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2360                 ixgbe_enable_intr(dev);
2361                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2362         }
2363
2364
2365         return 0;
2366 }
2367
2368 /**
2369  * Interrupt handler which shall be registered for alarm callback for delayed
2370  * handling specific interrupt to wait for the stable nic state. As the
2371  * NIC interrupt state is not stable for ixgbe after link is just down,
2372  * it needs to wait 4 seconds to get the stable status.
2373  *
2374  * @param handle
2375  *  Pointer to interrupt handle.
2376  * @param param
2377  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2378  *
2379  * @return
2380  *  void
2381  */
2382 static void
2383 ixgbe_dev_interrupt_delayed_handler(void *param)
2384 {
2385         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2386         struct ixgbe_interrupt *intr =
2387                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2388         struct ixgbe_hw *hw =
2389                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2390         uint32_t eicr;
2391
2392         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2393         if (eicr & IXGBE_EICR_MAILBOX)
2394                 ixgbe_pf_mbx_process(dev);
2395
2396         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2397                 ixgbe_dev_link_update(dev, 0);
2398                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2399                 ixgbe_dev_link_status_print(dev);
2400                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2401         }
2402
2403         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2404         ixgbe_enable_intr(dev);
2405         rte_intr_enable(&(dev->pci_dev->intr_handle));
2406 }
2407
2408 /**
2409  * Interrupt handler triggered by NIC  for handling
2410  * specific interrupt.
2411  *
2412  * @param handle
2413  *  Pointer to interrupt handle.
2414  * @param param
2415  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2416  *
2417  * @return
2418  *  void
2419  */
2420 static void
2421 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2422                                                         void *param)
2423 {
2424         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2425         ixgbe_dev_interrupt_get_status(dev);
2426         ixgbe_dev_interrupt_action(dev);
2427 }
2428
2429 static int
2430 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2431 {
2432         struct ixgbe_hw *hw;
2433
2434         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2436 }
2437
2438 static int
2439 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2440 {
2441         struct ixgbe_hw *hw;
2442
2443         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2444         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2445 }
2446
2447 static int
2448 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2449 {
2450         struct ixgbe_hw *hw;
2451         uint32_t mflcn_reg;
2452         uint32_t fccfg_reg;
2453         int rx_pause;
2454         int tx_pause;
2455
2456         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457
2458         fc_conf->pause_time = hw->fc.pause_time;
2459         fc_conf->high_water = hw->fc.high_water[0];
2460         fc_conf->low_water = hw->fc.low_water[0];
2461         fc_conf->send_xon = hw->fc.send_xon;
2462         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2463
2464         /*
2465          * Return rx_pause status according to actual setting of
2466          * MFLCN register.
2467          */
2468         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2469         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2470                 rx_pause = 1;
2471         else
2472                 rx_pause = 0;
2473
2474         /*
2475          * Return tx_pause status according to actual setting of
2476          * FCCFG register.
2477          */
2478         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2479         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2480                 tx_pause = 1;
2481         else
2482                 tx_pause = 0;
2483
2484         if (rx_pause && tx_pause)
2485                 fc_conf->mode = RTE_FC_FULL;
2486         else if (rx_pause)
2487                 fc_conf->mode = RTE_FC_RX_PAUSE;
2488         else if (tx_pause)
2489                 fc_conf->mode = RTE_FC_TX_PAUSE;
2490         else
2491                 fc_conf->mode = RTE_FC_NONE;
2492
2493         return 0;
2494 }
2495
2496 static int
2497 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2498 {
2499         struct ixgbe_hw *hw;
2500         int err;
2501         uint32_t rx_buf_size;
2502         uint32_t max_high_water;
2503         uint32_t mflcn;
2504         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2505                 ixgbe_fc_none,
2506                 ixgbe_fc_rx_pause,
2507                 ixgbe_fc_tx_pause,
2508                 ixgbe_fc_full
2509         };
2510
2511         PMD_INIT_FUNC_TRACE();
2512
2513         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2514         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2515                 return -ENOTSUP;
2516         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2517         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2518
2519         /*
2520          * At least reserve one Ethernet frame for watermark
2521          * high_water/low_water in kilo bytes for ixgbe
2522          */
2523         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2524         if ((fc_conf->high_water > max_high_water) ||
2525                 (fc_conf->high_water < fc_conf->low_water)) {
2526                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2527                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2528                 return (-EINVAL);
2529         }
2530
2531         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2532         hw->fc.pause_time     = fc_conf->pause_time;
2533         hw->fc.high_water[0]  = fc_conf->high_water;
2534         hw->fc.low_water[0]   = fc_conf->low_water;
2535         hw->fc.send_xon       = fc_conf->send_xon;
2536
2537         err = ixgbe_fc_enable(hw);
2538
2539         /* Not negotiated is not an error case */
2540         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2541
2542                 /* check if we want to forward MAC frames - driver doesn't have native
2543                  * capability to do that, so we'll write the registers ourselves */
2544
2545                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2546
2547                 /* set or clear MFLCN.PMCF bit depending on configuration */
2548                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2549                         mflcn |= IXGBE_MFLCN_PMCF;
2550                 else
2551                         mflcn &= ~IXGBE_MFLCN_PMCF;
2552
2553                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2554                 IXGBE_WRITE_FLUSH(hw);
2555
2556                 return 0;
2557         }
2558
2559         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2560         return -EIO;
2561 }
2562
2563 /**
2564  *  ixgbe_pfc_enable_generic - Enable flow control
2565  *  @hw: pointer to hardware structure
2566  *  @tc_num: traffic class number
2567  *  Enable flow control according to the current settings.
2568  */
2569 static int
2570 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2571 {
2572         int ret_val = 0;
2573         uint32_t mflcn_reg, fccfg_reg;
2574         uint32_t reg;
2575         uint32_t fcrtl, fcrth;
2576         uint8_t i;
2577         uint8_t nb_rx_en;
2578
2579         /* Validate the water mark configuration */
2580         if (!hw->fc.pause_time) {
2581                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2582                 goto out;
2583         }
2584
2585         /* Low water mark of zero causes XOFF floods */
2586         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2587                  /* High/Low water can not be 0 */
2588                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2589                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2590                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2591                         goto out;
2592                 }
2593
2594                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2595                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2596                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2597                         goto out;
2598                 }
2599         }
2600         /* Negotiate the fc mode to use */
2601         ixgbe_fc_autoneg(hw);
2602
2603         /* Disable any previous flow control settings */
2604         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2605         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2606
2607         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2608         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2609
2610         switch (hw->fc.current_mode) {
2611         case ixgbe_fc_none:
2612                 /*
2613                  * If the count of enabled RX Priority Flow control >1,
2614                  * and the TX pause can not be disabled
2615                  */
2616                 nb_rx_en = 0;
2617                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2618                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2619                         if (reg & IXGBE_FCRTH_FCEN)
2620                                 nb_rx_en++;
2621                 }
2622                 if (nb_rx_en > 1)
2623                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2624                 break;
2625         case ixgbe_fc_rx_pause:
2626                 /*
2627                  * Rx Flow control is enabled and Tx Flow control is
2628                  * disabled by software override. Since there really
2629                  * isn't a way to advertise that we are capable of RX
2630                  * Pause ONLY, we will advertise that we support both
2631                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2632                  * disable the adapter's ability to send PAUSE frames.
2633                  */
2634                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2635                 /*
2636                  * If the count of enabled RX Priority Flow control >1,
2637                  * and the TX pause can not be disabled
2638                  */
2639                 nb_rx_en = 0;
2640                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2641                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2642                         if (reg & IXGBE_FCRTH_FCEN)
2643                                 nb_rx_en++;
2644                 }
2645                 if (nb_rx_en > 1)
2646                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2647                 break;
2648         case ixgbe_fc_tx_pause:
2649                 /*
2650                  * Tx Flow control is enabled, and Rx Flow control is
2651                  * disabled by software override.
2652                  */
2653                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2654                 break;
2655         case ixgbe_fc_full:
2656                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2657                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2658                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2659                 break;
2660         default:
2661                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2662                 ret_val = IXGBE_ERR_CONFIG;
2663                 goto out;
2664                 break;
2665         }
2666
2667         /* Set 802.3x based flow control settings. */
2668         mflcn_reg |= IXGBE_MFLCN_DPF;
2669         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2670         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2671
2672         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2673         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2674                 hw->fc.high_water[tc_num]) {
2675                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2676                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2677                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2678         } else {
2679                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2680                 /*
2681                  * In order to prevent Tx hangs when the internal Tx
2682                  * switch is enabled we must set the high water mark
2683                  * to the maximum FCRTH value.  This allows the Tx
2684                  * switch to function even under heavy Rx workloads.
2685                  */
2686                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2687         }
2688         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2689
2690         /* Configure pause time (2 TCs per register) */
2691         reg = hw->fc.pause_time * 0x00010001;
2692         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2693                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2694
2695         /* Configure flow control refresh threshold value */
2696         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2697
2698 out:
2699         return ret_val;
2700 }
2701
2702 static int
2703 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2704 {
2705         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2706         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2707
2708         if(hw->mac.type != ixgbe_mac_82598EB) {
2709                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2710         }
2711         return ret_val;
2712 }
2713
2714 static int
2715 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2716 {
2717         int err;
2718         uint32_t rx_buf_size;
2719         uint32_t max_high_water;
2720         uint8_t tc_num;
2721         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2722         struct ixgbe_hw *hw =
2723                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2724         struct ixgbe_dcb_config *dcb_config =
2725                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2726
2727         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2728                 ixgbe_fc_none,
2729                 ixgbe_fc_rx_pause,
2730                 ixgbe_fc_tx_pause,
2731                 ixgbe_fc_full
2732         };
2733
2734         PMD_INIT_FUNC_TRACE();
2735
2736         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2737         tc_num = map[pfc_conf->priority];
2738         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2739         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2740         /*
2741          * At least reserve one Ethernet frame for watermark
2742          * high_water/low_water in kilo bytes for ixgbe
2743          */
2744         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2745         if ((pfc_conf->fc.high_water > max_high_water) ||
2746             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2747                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2748                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2749                 return (-EINVAL);
2750         }
2751
2752         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2753         hw->fc.pause_time = pfc_conf->fc.pause_time;
2754         hw->fc.send_xon = pfc_conf->fc.send_xon;
2755         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2756         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2757
2758         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2759
2760         /* Not negotiated is not an error case */
2761         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2762                 return 0;
2763
2764         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2765         return -EIO;
2766 }
2767
2768 static int
2769 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2770                           struct rte_eth_rss_reta_entry64 *reta_conf,
2771                           uint16_t reta_size)
2772 {
2773         uint8_t i, j, mask;
2774         uint32_t reta, r;
2775         uint16_t idx, shift;
2776         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2777
2778         PMD_INIT_FUNC_TRACE();
2779         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2780                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2781                         "(%d) doesn't match the number hardware can supported "
2782                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2783                 return -EINVAL;
2784         }
2785
2786         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2787                 idx = i / RTE_RETA_GROUP_SIZE;
2788                 shift = i % RTE_RETA_GROUP_SIZE;
2789                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2790                                                 IXGBE_4_BIT_MASK);
2791                 if (!mask)
2792                         continue;
2793                 if (mask == IXGBE_4_BIT_MASK)
2794                         r = 0;
2795                 else
2796                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2797                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2798                         if (mask & (0x1 << j))
2799                                 reta |= reta_conf[idx].reta[shift + j] <<
2800                                                         (CHAR_BIT * j);
2801                         else
2802                                 reta |= r & (IXGBE_8_BIT_MASK <<
2803                                                 (CHAR_BIT * j));
2804                 }
2805                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2806         }
2807
2808         return 0;
2809 }
2810
2811 static int
2812 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2813                          struct rte_eth_rss_reta_entry64 *reta_conf,
2814                          uint16_t reta_size)
2815 {
2816         uint8_t i, j, mask;
2817         uint32_t reta;
2818         uint16_t idx, shift;
2819         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820
2821         PMD_INIT_FUNC_TRACE();
2822         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2823                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2824                         "(%d) doesn't match the number hardware can supported "
2825                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2826                 return -EINVAL;
2827         }
2828
2829         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2830                 idx = i / RTE_RETA_GROUP_SIZE;
2831                 shift = i % RTE_RETA_GROUP_SIZE;
2832                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2833                                                 IXGBE_4_BIT_MASK);
2834                 if (!mask)
2835                         continue;
2836
2837                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2838                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2839                         if (mask & (0x1 << j))
2840                                 reta_conf[idx].reta[shift + j] =
2841                                         ((reta >> (CHAR_BIT * j)) &
2842                                                 IXGBE_8_BIT_MASK);
2843                 }
2844         }
2845
2846         return 0;
2847 }
2848
2849 static void
2850 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2851                                 uint32_t index, uint32_t pool)
2852 {
2853         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2854         uint32_t enable_addr = 1;
2855
2856         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2857 }
2858
2859 static void
2860 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2861 {
2862         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2863
2864         ixgbe_clear_rar(hw, index);
2865 }
2866
2867 static int
2868 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2869 {
2870         uint32_t hlreg0;
2871         uint32_t maxfrs;
2872         struct ixgbe_hw *hw;
2873         struct rte_eth_dev_info dev_info;
2874         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2875
2876         ixgbe_dev_info_get(dev, &dev_info);
2877
2878         /* check that mtu is within the allowed range */
2879         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2880                 return -EINVAL;
2881
2882         /* refuse mtu that requires the support of scattered packets when this
2883          * feature has not been enabled before. */
2884         if (!dev->data->scattered_rx &&
2885             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2886              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2887                 return -EINVAL;
2888
2889         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2891
2892         /* switch to jumbo mode if needed */
2893         if (frame_size > ETHER_MAX_LEN) {
2894                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2895                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2896         } else {
2897                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2898                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2899         }
2900         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2901
2902         /* update max frame size */
2903         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2904
2905         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2906         maxfrs &= 0x0000FFFF;
2907         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2908         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2909
2910         return 0;
2911 }
2912
2913 /*
2914  * Virtual Function operations
2915  */
2916 static void
2917 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2918 {
2919         PMD_INIT_FUNC_TRACE();
2920
2921         /* Clear interrupt mask to stop from interrupts being generated */
2922         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2923
2924         IXGBE_WRITE_FLUSH(hw);
2925 }
2926
2927 static int
2928 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2929 {
2930         struct rte_eth_conf* conf = &dev->data->dev_conf;
2931
2932         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2933                      dev->data->port_id);
2934
2935         /*
2936          * VF has no ability to enable/disable HW CRC
2937          * Keep the persistent behavior the same as Host PF
2938          */
2939 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2940         if (!conf->rxmode.hw_strip_crc) {
2941                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2942                 conf->rxmode.hw_strip_crc = 1;
2943         }
2944 #else
2945         if (conf->rxmode.hw_strip_crc) {
2946                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2947                 conf->rxmode.hw_strip_crc = 0;
2948         }
2949 #endif
2950
2951         return 0;
2952 }
2953
2954 static int
2955 ixgbevf_dev_start(struct rte_eth_dev *dev)
2956 {
2957         struct ixgbe_hw *hw =
2958                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2959         int err, mask = 0;
2960
2961         PMD_INIT_FUNC_TRACE();
2962
2963         hw->mac.ops.reset_hw(hw);
2964         hw->mac.get_link_status = true;
2965
2966         /* negotiate mailbox API version to use with the PF. */
2967         ixgbevf_negotiate_api(hw);
2968
2969         ixgbevf_dev_tx_init(dev);
2970
2971         /* This can fail when allocating mbufs for descriptor rings */
2972         err = ixgbevf_dev_rx_init(dev);
2973         if (err) {
2974                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2975                 ixgbe_dev_clear_queues(dev);
2976                 return err;
2977         }
2978
2979         /* Set vfta */
2980         ixgbevf_set_vfta_all(dev,1);
2981
2982         /* Set HW strip */
2983         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2984                 ETH_VLAN_EXTEND_MASK;
2985         ixgbevf_vlan_offload_set(dev, mask);
2986
2987         ixgbevf_dev_rxtx_start(dev);
2988
2989         return 0;
2990 }
2991
2992 static void
2993 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2994 {
2995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2996
2997         PMD_INIT_FUNC_TRACE();
2998
2999         hw->adapter_stopped = TRUE;
3000         ixgbe_stop_adapter(hw);
3001
3002         /*
3003           * Clear what we set, but we still keep shadow_vfta to
3004           * restore after device starts
3005           */
3006         ixgbevf_set_vfta_all(dev,0);
3007
3008         /* Clear stored conf */
3009         dev->data->scattered_rx = 0;
3010
3011         ixgbe_dev_clear_queues(dev);
3012 }
3013
3014 static void
3015 ixgbevf_dev_close(struct rte_eth_dev *dev)
3016 {
3017         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3018
3019         PMD_INIT_FUNC_TRACE();
3020
3021         ixgbe_reset_hw(hw);
3022
3023         ixgbevf_dev_stop(dev);
3024
3025         /* reprogram the RAR[0] in case user changed it. */
3026         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3027 }
3028
3029 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3030 {
3031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3032         struct ixgbe_vfta * shadow_vfta =
3033                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3034         int i = 0, j = 0, vfta = 0, mask = 1;
3035
3036         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3037                 vfta = shadow_vfta->vfta[i];
3038                 if(vfta){
3039                         mask = 1;
3040                         for (j = 0; j < 32; j++){
3041                                 if(vfta & mask)
3042                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3043                                 mask<<=1;
3044                         }
3045                 }
3046         }
3047
3048 }
3049
3050 static int
3051 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3052 {
3053         struct ixgbe_hw *hw =
3054                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3055         struct ixgbe_vfta * shadow_vfta =
3056                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3057         uint32_t vid_idx = 0;
3058         uint32_t vid_bit = 0;
3059         int ret = 0;
3060
3061         PMD_INIT_FUNC_TRACE();
3062
3063         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3064         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3065         if(ret){
3066                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3067                 return ret;
3068         }
3069         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3070         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3071
3072         /* Save what we set and retore it after device reset */
3073         if (on)
3074                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3075         else
3076                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3077
3078         return 0;
3079 }
3080
3081 static void
3082 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3083 {
3084         struct ixgbe_hw *hw =
3085                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3086         uint32_t ctrl;
3087
3088         PMD_INIT_FUNC_TRACE();
3089
3090         if(queue >= hw->mac.max_rx_queues)
3091                 return;
3092
3093         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3094         if(on)
3095                 ctrl |= IXGBE_RXDCTL_VME;
3096         else
3097                 ctrl &= ~IXGBE_RXDCTL_VME;
3098         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3099
3100         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3101 }
3102
3103 static void
3104 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3105 {
3106         struct ixgbe_hw *hw =
3107                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3108         uint16_t i;
3109         int on = 0;
3110
3111         /* VF function only support hw strip feature, others are not support */
3112         if(mask & ETH_VLAN_STRIP_MASK){
3113                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3114
3115                 for(i=0; i < hw->mac.max_rx_queues; i++)
3116                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3117         }
3118 }
3119
3120 static int
3121 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3122 {
3123         uint32_t reg_val;
3124
3125         /* we only need to do this if VMDq is enabled */
3126         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3127         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3128                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3129                 return (-1);
3130         }
3131
3132         return 0;
3133 }
3134
3135 static uint32_t
3136 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3137 {
3138         uint32_t vector = 0;
3139         switch (hw->mac.mc_filter_type) {
3140         case 0:   /* use bits [47:36] of the address */
3141                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3142                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3143                 break;
3144         case 1:   /* use bits [46:35] of the address */
3145                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3146                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3147                 break;
3148         case 2:   /* use bits [45:34] of the address */
3149                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3150                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3151                 break;
3152         case 3:   /* use bits [43:32] of the address */
3153                 vector = ((uc_addr->addr_bytes[4]) |
3154                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3155                 break;
3156         default:  /* Invalid mc_filter_type */
3157                 break;
3158         }
3159
3160         /* vector can only be 12-bits or boundary will be exceeded */
3161         vector &= 0xFFF;
3162         return vector;
3163 }
3164
3165 static int
3166 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3167                                uint8_t on)
3168 {
3169         uint32_t vector;
3170         uint32_t uta_idx;
3171         uint32_t reg_val;
3172         uint32_t uta_shift;
3173         uint32_t rc;
3174         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3175         const uint32_t ixgbe_uta_bit_shift = 5;
3176         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3177         const uint32_t bit1 = 0x1;
3178
3179         struct ixgbe_hw *hw =
3180                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3181         struct ixgbe_uta_info *uta_info =
3182                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3183
3184         /* The UTA table only exists on 82599 hardware and newer */
3185         if (hw->mac.type < ixgbe_mac_82599EB)
3186                 return (-ENOTSUP);
3187
3188         vector = ixgbe_uta_vector(hw,mac_addr);
3189         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3190         uta_shift = vector & ixgbe_uta_bit_mask;
3191
3192         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3193         if(rc == on)
3194                 return 0;
3195
3196         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3197         if (on) {
3198                 uta_info->uta_in_use++;
3199                 reg_val |= (bit1 << uta_shift);
3200                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3201         } else {
3202                 uta_info->uta_in_use--;
3203                 reg_val &= ~(bit1 << uta_shift);
3204                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3205         }
3206
3207         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3208
3209         if (uta_info->uta_in_use > 0)
3210                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3211                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3212         else
3213                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3214
3215         return 0;
3216 }
3217
3218 static int
3219 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3220 {
3221         int i;
3222         struct ixgbe_hw *hw =
3223                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3224         struct ixgbe_uta_info *uta_info =
3225                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3226
3227         /* The UTA table only exists on 82599 hardware and newer */
3228         if (hw->mac.type < ixgbe_mac_82599EB)
3229                 return (-ENOTSUP);
3230
3231         if(on) {
3232                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3233                         uta_info->uta_shadow[i] = ~0;
3234                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3235                 }
3236         } else {
3237                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3238                         uta_info->uta_shadow[i] = 0;
3239                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3240                 }
3241         }
3242         return 0;
3243
3244 }
3245
3246 uint32_t
3247 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3248 {
3249         uint32_t new_val = orig_val;
3250
3251         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3252                 new_val |= IXGBE_VMOLR_AUPE;
3253         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3254                 new_val |= IXGBE_VMOLR_ROMPE;
3255         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3256                 new_val |= IXGBE_VMOLR_ROPE;
3257         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3258                 new_val |= IXGBE_VMOLR_BAM;
3259         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3260                 new_val |= IXGBE_VMOLR_MPE;
3261
3262         return new_val;
3263 }
3264
3265 static int
3266 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3267                                uint16_t rx_mask, uint8_t on)
3268 {
3269         int val = 0;
3270
3271         struct ixgbe_hw *hw =
3272                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3273         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3274
3275         if (hw->mac.type == ixgbe_mac_82598EB) {
3276                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3277                              " on 82599 hardware and newer");
3278                 return (-ENOTSUP);
3279         }
3280         if (ixgbe_vmdq_mode_check(hw) < 0)
3281                 return (-ENOTSUP);
3282
3283         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3284
3285         if (on)
3286                 vmolr |= val;
3287         else
3288                 vmolr &= ~val;
3289
3290         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3291
3292         return 0;
3293 }
3294
3295 static int
3296 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3297 {
3298         uint32_t reg,addr;
3299         uint32_t val;
3300         const uint8_t bit1 = 0x1;
3301
3302         struct ixgbe_hw *hw =
3303                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3304
3305         if (ixgbe_vmdq_mode_check(hw) < 0)
3306                 return (-ENOTSUP);
3307
3308         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3309         reg = IXGBE_READ_REG(hw, addr);
3310         val = bit1 << pool;
3311
3312         if (on)
3313                 reg |= val;
3314         else
3315                 reg &= ~val;
3316
3317         IXGBE_WRITE_REG(hw, addr,reg);
3318
3319         return 0;
3320 }
3321
3322 static int
3323 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3324 {
3325         uint32_t reg,addr;
3326         uint32_t val;
3327         const uint8_t bit1 = 0x1;
3328
3329         struct ixgbe_hw *hw =
3330                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3331
3332         if (ixgbe_vmdq_mode_check(hw) < 0)
3333                 return (-ENOTSUP);
3334
3335         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3336         reg = IXGBE_READ_REG(hw, addr);
3337         val = bit1 << pool;
3338
3339         if (on)
3340                 reg |= val;
3341         else
3342                 reg &= ~val;
3343
3344         IXGBE_WRITE_REG(hw, addr,reg);
3345
3346         return 0;
3347 }
3348
3349 static int
3350 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3351                         uint64_t pool_mask, uint8_t vlan_on)
3352 {
3353         int ret = 0;
3354         uint16_t pool_idx;
3355         struct ixgbe_hw *hw =
3356                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3357
3358         if (ixgbe_vmdq_mode_check(hw) < 0)
3359                 return (-ENOTSUP);
3360         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3361                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3362                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3363                         if (ret < 0)
3364                                 return ret;
3365         }
3366
3367         return ret;
3368 }
3369
3370 static int
3371 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3372                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3373                         uint8_t rule_id, uint8_t on)
3374 {
3375         uint32_t mr_ctl,vlvf;
3376         uint32_t mp_lsb = 0;
3377         uint32_t mv_msb = 0;
3378         uint32_t mv_lsb = 0;
3379         uint32_t mp_msb = 0;
3380         uint8_t i = 0;
3381         int reg_index = 0;
3382         uint64_t vlan_mask = 0;
3383
3384         const uint8_t pool_mask_offset = 32;
3385         const uint8_t vlan_mask_offset = 32;
3386         const uint8_t dst_pool_offset = 8;
3387         const uint8_t rule_mr_offset  = 4;
3388         const uint8_t mirror_rule_mask= 0x0F;
3389
3390         struct ixgbe_mirror_info *mr_info =
3391                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3392         struct ixgbe_hw *hw =
3393                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3394
3395         if (ixgbe_vmdq_mode_check(hw) < 0)
3396                 return (-ENOTSUP);
3397
3398         /* Check if vlan mask is valid */
3399         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3400                 if (mirror_conf->vlan.vlan_mask == 0)
3401                         return (-EINVAL);
3402         }
3403
3404         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3405         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3406                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3407                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3408                                 /* search vlan id related pool vlan filter index */
3409                                 reg_index = ixgbe_find_vlvf_slot(hw,
3410                                                 mirror_conf->vlan.vlan_id[i]);
3411                                 if(reg_index < 0)
3412                                         return (-EINVAL);
3413                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3414                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3415                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3416                                                 == mirror_conf->vlan.vlan_id[i]))
3417                                         vlan_mask |= (1ULL << reg_index);
3418                                 else
3419                                         return (-EINVAL);
3420                         }
3421                 }
3422
3423                 if (on) {
3424                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3425                         mv_msb = vlan_mask >> vlan_mask_offset;
3426
3427                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3428                                                 mirror_conf->vlan.vlan_mask;
3429                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3430                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3431                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3432                                                 mirror_conf->vlan.vlan_id[i];
3433                         }
3434                 } else {
3435                         mv_lsb = 0;
3436                         mv_msb = 0;
3437                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3438                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3439                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3440                 }
3441         }
3442
3443         /*
3444          * if enable pool mirror, write related pool mask register,if disable
3445          * pool mirror, clear PFMRVM register
3446          */
3447         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3448                 if (on) {
3449                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3450                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3451                         mr_info->mr_conf[rule_id].pool_mask =
3452                                         mirror_conf->pool_mask;
3453
3454                 } else {
3455                         mp_lsb = 0;
3456                         mp_msb = 0;
3457                         mr_info->mr_conf[rule_id].pool_mask = 0;
3458                 }
3459         }
3460
3461         /* read  mirror control register and recalculate it */
3462         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3463
3464         if (on) {
3465                 mr_ctl |= mirror_conf->rule_type_mask;
3466                 mr_ctl &= mirror_rule_mask;
3467                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3468         } else
3469                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3470
3471         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3472         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3473
3474         /* write mirrror control  register */
3475         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3476
3477         /* write pool mirrror control  register */
3478         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3479                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3480                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3481                                 mp_msb);
3482         }
3483         /* write VLAN mirrror control  register */
3484         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3485                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3486                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3487                                 mv_msb);
3488         }
3489
3490         return 0;
3491 }
3492
3493 static int
3494 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3495 {
3496         int mr_ctl = 0;
3497         uint32_t lsb_val = 0;
3498         uint32_t msb_val = 0;
3499         const uint8_t rule_mr_offset = 4;
3500
3501         struct ixgbe_hw *hw =
3502                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3503         struct ixgbe_mirror_info *mr_info =
3504                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3505
3506         if (ixgbe_vmdq_mode_check(hw) < 0)
3507                 return (-ENOTSUP);
3508
3509         memset(&mr_info->mr_conf[rule_id], 0,
3510                 sizeof(struct rte_eth_vmdq_mirror_conf));
3511
3512         /* clear PFVMCTL register */
3513         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3514
3515         /* clear pool mask register */
3516         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3517         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3518
3519         /* clear vlan mask register */
3520         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3521         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3522
3523         return 0;
3524 }
3525
3526 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3527         uint16_t queue_idx, uint16_t tx_rate)
3528 {
3529         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3530         uint32_t rf_dec, rf_int;
3531         uint32_t bcnrc_val;
3532         uint16_t link_speed = dev->data->dev_link.link_speed;
3533
3534         if (queue_idx >= hw->mac.max_tx_queues)
3535                 return -EINVAL;
3536
3537         if (tx_rate != 0) {
3538                 /* Calculate the rate factor values to set */
3539                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3540                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3541                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3542
3543                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3544                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3545                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3546                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3547         } else {
3548                 bcnrc_val = 0;
3549         }
3550
3551         /*
3552          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3553          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3554          * set as 0x4.
3555          */
3556         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3557                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3558                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3559                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3560                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3561         else
3562                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3563                         IXGBE_MMW_SIZE_DEFAULT);
3564
3565         /* Set RTTBCNRC of queue X */
3566         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3567         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3568         IXGBE_WRITE_FLUSH(hw);
3569
3570         return 0;
3571 }
3572
3573 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3574         uint16_t tx_rate, uint64_t q_msk)
3575 {
3576         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3577         struct ixgbe_vf_info *vfinfo =
3578                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3579         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3580         uint32_t queue_stride =
3581                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3582         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3583         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3584         uint16_t total_rate = 0;
3585
3586         if (queue_end >= hw->mac.max_tx_queues)
3587                 return -EINVAL;
3588
3589         if (vfinfo != NULL) {
3590                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3591                         if (vf_idx == vf)
3592                                 continue;
3593                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3594                                 idx++)
3595                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3596                 }
3597         } else
3598                 return -EINVAL;
3599
3600         /* Store tx_rate for this vf. */
3601         for (idx = 0; idx < nb_q_per_pool; idx++) {
3602                 if (((uint64_t)0x1 << idx) & q_msk) {
3603                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3604                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3605                         total_rate += tx_rate;
3606                 }
3607         }
3608
3609         if (total_rate > dev->data->dev_link.link_speed) {
3610                 /*
3611                  * Reset stored TX rate of the VF if it causes exceed
3612                  * link speed.
3613                  */
3614                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3615                 return -EINVAL;
3616         }
3617
3618         /* Set RTTBCNRC of each queue/pool for vf X  */
3619         for (; queue_idx <= queue_end; queue_idx++) {
3620                 if (0x1 & q_msk)
3621                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3622                 q_msk = q_msk >> 1;
3623         }
3624
3625         return 0;
3626 }
3627
3628 static void
3629 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3630                      __attribute__((unused)) uint32_t index,
3631                      __attribute__((unused)) uint32_t pool)
3632 {
3633         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3634         int diag;
3635
3636         /*
3637          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3638          * operation. Trap this case to avoid exhausting the [very limited]
3639          * set of PF resources used to store VF MAC addresses.
3640          */
3641         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3642                 return;
3643         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3644         if (diag == 0)
3645                 return;
3646         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3647 }
3648
3649 static void
3650 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3651 {
3652         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3653         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3654         struct ether_addr *mac_addr;
3655         uint32_t i;
3656         int diag;
3657
3658         /*
3659          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3660          * not support the deletion of a given MAC address.
3661          * Instead, it imposes to delete all MAC addresses, then to add again
3662          * all MAC addresses with the exception of the one to be deleted.
3663          */
3664         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3665
3666         /*
3667          * Add again all MAC addresses, with the exception of the deleted one
3668          * and of the permanent MAC address.
3669          */
3670         for (i = 0, mac_addr = dev->data->mac_addrs;
3671              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3672                 /* Skip the deleted MAC address */
3673                 if (i == index)
3674                         continue;
3675                 /* Skip NULL MAC addresses */
3676                 if (is_zero_ether_addr(mac_addr))
3677                         continue;
3678                 /* Skip the permanent MAC address */
3679                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3680                         continue;
3681                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3682                 if (diag != 0)
3683                         PMD_DRV_LOG(ERR,
3684                                     "Adding again MAC address "
3685                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3686                                     "diag=%d",
3687                                     mac_addr->addr_bytes[0],
3688                                     mac_addr->addr_bytes[1],
3689                                     mac_addr->addr_bytes[2],
3690                                     mac_addr->addr_bytes[3],
3691                                     mac_addr->addr_bytes[4],
3692                                     mac_addr->addr_bytes[5],
3693                                     diag);
3694         }
3695 }
3696
3697 #define MAC_TYPE_FILTER_SUP(type)    do {\
3698         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
3699                 (type) != ixgbe_mac_X550)\
3700                 return -ENOTSUP;\
3701 } while (0)
3702
3703 static int
3704 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
3705                         struct rte_eth_syn_filter *filter,
3706                         bool add)
3707 {
3708         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3709         uint32_t synqf;
3710
3711         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
3712                 return -EINVAL;
3713
3714         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3715
3716         if (add) {
3717                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3718                         return -EINVAL;
3719                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3720                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3721
3722                 if (filter->hig_pri)
3723                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
3724                 else
3725                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3726         } else {
3727                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
3728                         return -ENOENT;
3729                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3730         }
3731         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3732         IXGBE_WRITE_FLUSH(hw);
3733         return 0;
3734 }
3735
3736 static int
3737 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
3738                         struct rte_eth_syn_filter *filter)
3739 {
3740         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3741         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3742
3743         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3744                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3745                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3746                 return 0;
3747         }
3748         return -ENOENT;
3749 }
3750
3751 static int
3752 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
3753                         enum rte_filter_op filter_op,
3754                         void *arg)
3755 {
3756         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3757         int ret;
3758
3759         MAC_TYPE_FILTER_SUP(hw->mac.type);
3760
3761         if (filter_op == RTE_ETH_FILTER_NOP)
3762                 return 0;
3763
3764         if (arg == NULL) {
3765                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3766                             filter_op);
3767                 return -EINVAL;
3768         }
3769
3770         switch (filter_op) {
3771         case RTE_ETH_FILTER_ADD:
3772                 ret = ixgbe_syn_filter_set(dev,
3773                                 (struct rte_eth_syn_filter *)arg,
3774                                 TRUE);
3775                 break;
3776         case RTE_ETH_FILTER_DELETE:
3777                 ret = ixgbe_syn_filter_set(dev,
3778                                 (struct rte_eth_syn_filter *)arg,
3779                                 FALSE);
3780                 break;
3781         case RTE_ETH_FILTER_GET:
3782                 ret = ixgbe_syn_filter_get(dev,
3783                                 (struct rte_eth_syn_filter *)arg);
3784                 break;
3785         default:
3786                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3787                 ret = -EINVAL;
3788                 break;
3789         }
3790
3791         return ret;
3792 }
3793
3794
3795 static inline enum ixgbe_5tuple_protocol
3796 convert_protocol_type(uint8_t protocol_value)
3797 {
3798         if (protocol_value == IPPROTO_TCP)
3799                 return IXGBE_FILTER_PROTOCOL_TCP;
3800         else if (protocol_value == IPPROTO_UDP)
3801                 return IXGBE_FILTER_PROTOCOL_UDP;
3802         else if (protocol_value == IPPROTO_SCTP)
3803                 return IXGBE_FILTER_PROTOCOL_SCTP;
3804         else
3805                 return IXGBE_FILTER_PROTOCOL_NONE;
3806 }
3807
3808 /*
3809  * add a 5tuple filter
3810  *
3811  * @param
3812  * dev: Pointer to struct rte_eth_dev.
3813  * index: the index the filter allocates.
3814  * filter: ponter to the filter that will be added.
3815  * rx_queue: the queue id the filter assigned to.
3816  *
3817  * @return
3818  *    - On success, zero.
3819  *    - On failure, a negative value.
3820  */
3821 static int
3822 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3823                         struct ixgbe_5tuple_filter *filter)
3824 {
3825         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3826         struct ixgbe_filter_info *filter_info =
3827                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3828         int i, idx, shift;
3829         uint32_t ftqf, sdpqf;
3830         uint32_t l34timir = 0;
3831         uint8_t mask = 0xff;
3832
3833         /*
3834          * look for an unused 5tuple filter index,
3835          * and insert the filter to list.
3836          */
3837         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
3838                 idx = i / (sizeof(uint32_t) * NBBY);
3839                 shift = i % (sizeof(uint32_t) * NBBY);
3840                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3841                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3842                         filter->index = i;
3843                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3844                                           filter,
3845                                           entries);
3846                         break;
3847                 }
3848         }
3849         if (i >= IXGBE_MAX_FTQF_FILTERS) {
3850                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3851                 return -ENOSYS;
3852         }
3853
3854         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
3855                                 IXGBE_SDPQF_DSTPORT_SHIFT);
3856         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
3857
3858         ftqf = (uint32_t)(filter->filter_info.proto &
3859                 IXGBE_FTQF_PROTOCOL_MASK);
3860         ftqf |= (uint32_t)((filter->filter_info.priority &
3861                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
3862         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3863                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3864         if (filter->filter_info.dst_ip_mask == 0)
3865                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3866         if (filter->filter_info.src_port_mask == 0)
3867                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3868         if (filter->filter_info.dst_port_mask == 0)
3869                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3870         if (filter->filter_info.proto_mask == 0)
3871                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3872         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3873         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3874         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3875
3876         IXGBE_WRITE_REG(hw, IXGBE_DAQF(idx), filter->filter_info.dst_ip);
3877         IXGBE_WRITE_REG(hw, IXGBE_SAQF(idx), filter->filter_info.src_ip);
3878         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(idx), sdpqf);
3879         IXGBE_WRITE_REG(hw, IXGBE_FTQF(idx), ftqf);
3880
3881         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3882         l34timir |= (uint32_t)(filter->queue <<
3883                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
3884         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
3885         return 0;
3886 }
3887
3888 /*
3889  * remove a 5tuple filter
3890  *
3891  * @param
3892  * dev: Pointer to struct rte_eth_dev.
3893  * filter: the pointer of the filter will be removed.
3894  */
3895 static void
3896 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3897                         struct ixgbe_5tuple_filter *filter)
3898 {
3899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3900         struct ixgbe_filter_info *filter_info =
3901                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3902         uint16_t index = filter->index;
3903
3904         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3905                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3906         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3907         rte_free(filter);
3908
3909         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3910         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3911         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3912         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3913         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3914 }
3915
3916 static int
3917 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3918 {
3919         struct ixgbe_hw *hw;
3920         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3921
3922         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3923
3924         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3925                 return -EINVAL;
3926
3927         /* refuse mtu that requires the support of scattered packets when this
3928          * feature has not been enabled before. */
3929         if (!dev->data->scattered_rx &&
3930             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3931              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3932                 return -EINVAL;
3933
3934         /*
3935          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3936          * request of the version 2.0 of the mailbox API.
3937          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3938          * of the mailbox API.
3939          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3940          * prior to 3.11.33 which contains the following change:
3941          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3942          */
3943         ixgbevf_rlpml_set_vf(hw, max_frame);
3944
3945         /* update max frame size */
3946         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
3947         return 0;
3948 }
3949
3950 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3951         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
3952                 return -ENOTSUP;\
3953 } while (0)
3954
3955 static inline struct ixgbe_5tuple_filter *
3956 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
3957                         struct ixgbe_5tuple_filter_info *key)
3958 {
3959         struct ixgbe_5tuple_filter *it;
3960
3961         TAILQ_FOREACH(it, filter_list, entries) {
3962                 if (memcmp(key, &it->filter_info,
3963                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
3964                         return it;
3965                 }
3966         }
3967         return NULL;
3968 }
3969
3970 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
3971 static inline int
3972 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3973                         struct ixgbe_5tuple_filter_info *filter_info)
3974 {
3975         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3976                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3977                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3978                 return -EINVAL;
3979
3980         switch (filter->dst_ip_mask) {
3981         case UINT32_MAX:
3982                 filter_info->dst_ip_mask = 0;
3983                 filter_info->dst_ip = filter->dst_ip;
3984                 break;
3985         case 0:
3986                 filter_info->dst_ip_mask = 1;
3987                 break;
3988         default:
3989                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3990                 return -EINVAL;
3991         }
3992
3993         switch (filter->src_ip_mask) {
3994         case UINT32_MAX:
3995                 filter_info->src_ip_mask = 0;
3996                 filter_info->src_ip = filter->src_ip;
3997                 break;
3998         case 0:
3999                 filter_info->src_ip_mask = 1;
4000                 break;
4001         default:
4002                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4003                 return -EINVAL;
4004         }
4005
4006         switch (filter->dst_port_mask) {
4007         case UINT16_MAX:
4008                 filter_info->dst_port_mask = 0;
4009                 filter_info->dst_port = filter->dst_port;
4010                 break;
4011         case 0:
4012                 filter_info->dst_port_mask = 1;
4013                 break;
4014         default:
4015                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4016                 return -EINVAL;
4017         }
4018
4019         switch (filter->src_port_mask) {
4020         case UINT16_MAX:
4021                 filter_info->src_port_mask = 0;
4022                 filter_info->src_port = filter->src_port;
4023                 break;
4024         case 0:
4025                 filter_info->src_port_mask = 1;
4026                 break;
4027         default:
4028                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4029                 return -EINVAL;
4030         }
4031
4032         switch (filter->proto_mask) {
4033         case UINT8_MAX:
4034                 filter_info->proto_mask = 0;
4035                 filter_info->proto =
4036                         convert_protocol_type(filter->proto);
4037                 break;
4038         case 0:
4039                 filter_info->proto_mask = 1;
4040                 break;
4041         default:
4042                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4043                 return -EINVAL;
4044         }
4045
4046         filter_info->priority = (uint8_t)filter->priority;
4047         return 0;
4048 }
4049
4050 /*
4051  * add or delete a ntuple filter
4052  *
4053  * @param
4054  * dev: Pointer to struct rte_eth_dev.
4055  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4056  * add: if true, add filter, if false, remove filter
4057  *
4058  * @return
4059  *    - On success, zero.
4060  *    - On failure, a negative value.
4061  */
4062 static int
4063 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4064                         struct rte_eth_ntuple_filter *ntuple_filter,
4065                         bool add)
4066 {
4067         struct ixgbe_filter_info *filter_info =
4068                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4069         struct ixgbe_5tuple_filter_info filter_5tuple;
4070         struct ixgbe_5tuple_filter *filter;
4071         int ret;
4072
4073         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4074                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4075                 return -EINVAL;
4076         }
4077
4078         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4079         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4080         if (ret < 0)
4081                 return ret;
4082
4083         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4084                                          &filter_5tuple);
4085         if (filter != NULL && add) {
4086                 PMD_DRV_LOG(ERR, "filter exists.");
4087                 return -EEXIST;
4088         }
4089         if (filter == NULL && !add) {
4090                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4091                 return -ENOENT;
4092         }
4093
4094         if (add) {
4095                 filter = rte_zmalloc("ixgbe_5tuple_filter",
4096                                 sizeof(struct ixgbe_5tuple_filter), 0);
4097                 if (filter == NULL)
4098                         return -ENOMEM;
4099                 (void)rte_memcpy(&filter->filter_info,
4100                                  &filter_5tuple,
4101                                  sizeof(struct ixgbe_5tuple_filter_info));
4102                 filter->queue = ntuple_filter->queue;
4103                 ret = ixgbe_add_5tuple_filter(dev, filter);
4104                 if (ret < 0) {
4105                         rte_free(filter);
4106                         return ret;
4107                 }
4108         } else
4109                 ixgbe_remove_5tuple_filter(dev, filter);
4110
4111         return 0;
4112 }
4113
4114 /*
4115  * get a ntuple filter
4116  *
4117  * @param
4118  * dev: Pointer to struct rte_eth_dev.
4119  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4120  *
4121  * @return
4122  *    - On success, zero.
4123  *    - On failure, a negative value.
4124  */
4125 static int
4126 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4127                         struct rte_eth_ntuple_filter *ntuple_filter)
4128 {
4129         struct ixgbe_filter_info *filter_info =
4130                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4131         struct ixgbe_5tuple_filter_info filter_5tuple;
4132         struct ixgbe_5tuple_filter *filter;
4133         int ret;
4134
4135         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4136                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4137                 return -EINVAL;
4138         }
4139
4140         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4141         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4142         if (ret < 0)
4143                 return ret;
4144
4145         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4146                                          &filter_5tuple);
4147         if (filter == NULL) {
4148                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4149                 return -ENOENT;
4150         }
4151         ntuple_filter->queue = filter->queue;
4152         return 0;
4153 }
4154
4155 /*
4156  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4157  * @dev: pointer to rte_eth_dev structure
4158  * @filter_op:operation will be taken.
4159  * @arg: a pointer to specific structure corresponding to the filter_op
4160  *
4161  * @return
4162  *    - On success, zero.
4163  *    - On failure, a negative value.
4164  */
4165 static int
4166 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4167                                 enum rte_filter_op filter_op,
4168                                 void *arg)
4169 {
4170         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4171         int ret;
4172
4173         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4174
4175         if (filter_op == RTE_ETH_FILTER_NOP)
4176                 return 0;
4177
4178         if (arg == NULL) {
4179                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4180                             filter_op);
4181                 return -EINVAL;
4182         }
4183
4184         switch (filter_op) {
4185         case RTE_ETH_FILTER_ADD:
4186                 ret = ixgbe_add_del_ntuple_filter(dev,
4187                         (struct rte_eth_ntuple_filter *)arg,
4188                         TRUE);
4189                 break;
4190         case RTE_ETH_FILTER_DELETE:
4191                 ret = ixgbe_add_del_ntuple_filter(dev,
4192                         (struct rte_eth_ntuple_filter *)arg,
4193                         FALSE);
4194                 break;
4195         case RTE_ETH_FILTER_GET:
4196                 ret = ixgbe_get_ntuple_filter(dev,
4197                         (struct rte_eth_ntuple_filter *)arg);
4198                 break;
4199         default:
4200                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4201                 ret = -EINVAL;
4202                 break;
4203         }
4204         return ret;
4205 }
4206
4207 static inline int
4208 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4209                         uint16_t ethertype)
4210 {
4211         int i;
4212
4213         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4214                 if (filter_info->ethertype_filters[i] == ethertype &&
4215                     (filter_info->ethertype_mask & (1 << i)))
4216                         return i;
4217         }
4218         return -1;
4219 }
4220
4221 static inline int
4222 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4223                         uint16_t ethertype)
4224 {
4225         int i;
4226
4227         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4228                 if (!(filter_info->ethertype_mask & (1 << i))) {
4229                         filter_info->ethertype_mask |= 1 << i;
4230                         filter_info->ethertype_filters[i] = ethertype;
4231                         return i;
4232                 }
4233         }
4234         return -1;
4235 }
4236
4237 static inline int
4238 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4239                         uint8_t idx)
4240 {
4241         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4242                 return -1;
4243         filter_info->ethertype_mask &= ~(1 << idx);
4244         filter_info->ethertype_filters[idx] = 0;
4245         return idx;
4246 }
4247
4248 static int
4249 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4250                         struct rte_eth_ethertype_filter *filter,
4251                         bool add)
4252 {
4253         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4254         struct ixgbe_filter_info *filter_info =
4255                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4256         uint32_t etqf = 0;
4257         uint32_t etqs = 0;
4258         int ret;
4259
4260         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4261                 return -EINVAL;
4262
4263         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4264                 filter->ether_type == ETHER_TYPE_IPv6) {
4265                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4266                         " ethertype filter.", filter->ether_type);
4267                 return -EINVAL;
4268         }
4269
4270         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4271                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4272                 return -EINVAL;
4273         }
4274         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4275                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4276                 return -EINVAL;
4277         }
4278
4279         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4280         if (ret >= 0 && add) {
4281                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4282                             filter->ether_type);
4283                 return -EEXIST;
4284         }
4285         if (ret < 0 && !add) {
4286                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4287                             filter->ether_type);
4288                 return -ENOENT;
4289         }
4290
4291         if (add) {
4292                 ret = ixgbe_ethertype_filter_insert(filter_info,
4293                         filter->ether_type);
4294                 if (ret < 0) {
4295                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4296                         return -ENOSYS;
4297                 }
4298                 etqf = IXGBE_ETQF_FILTER_EN;
4299                 etqf |= (uint32_t)filter->ether_type;
4300                 etqs |= (uint32_t)((filter->queue <<
4301                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4302                                     IXGBE_ETQS_RX_QUEUE);
4303                 etqs |= IXGBE_ETQS_QUEUE_EN;
4304         } else {
4305                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4306                 if (ret < 0)
4307                         return -ENOSYS;
4308         }
4309         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4310         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4311         IXGBE_WRITE_FLUSH(hw);
4312
4313         return 0;
4314 }
4315
4316 static int
4317 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4318                         struct rte_eth_ethertype_filter *filter)
4319 {
4320         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4321         struct ixgbe_filter_info *filter_info =
4322                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4323         uint32_t etqf, etqs;
4324         int ret;
4325
4326         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4327         if (ret < 0) {
4328                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4329                             filter->ether_type);
4330                 return -ENOENT;
4331         }
4332
4333         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4334         if (etqf & IXGBE_ETQF_FILTER_EN) {
4335                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4336                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4337                 filter->flags = 0;
4338                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4339                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4340                 return 0;
4341         }
4342         return -ENOENT;
4343 }
4344
4345 /*
4346  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4347  * @dev: pointer to rte_eth_dev structure
4348  * @filter_op:operation will be taken.
4349  * @arg: a pointer to specific structure corresponding to the filter_op
4350  */
4351 static int
4352 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4353                                 enum rte_filter_op filter_op,
4354                                 void *arg)
4355 {
4356         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4357         int ret;
4358
4359         MAC_TYPE_FILTER_SUP(hw->mac.type);
4360
4361         if (filter_op == RTE_ETH_FILTER_NOP)
4362                 return 0;
4363
4364         if (arg == NULL) {
4365                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4366                             filter_op);
4367                 return -EINVAL;
4368         }
4369
4370         switch (filter_op) {
4371         case RTE_ETH_FILTER_ADD:
4372                 ret = ixgbe_add_del_ethertype_filter(dev,
4373                         (struct rte_eth_ethertype_filter *)arg,
4374                         TRUE);
4375                 break;
4376         case RTE_ETH_FILTER_DELETE:
4377                 ret = ixgbe_add_del_ethertype_filter(dev,
4378                         (struct rte_eth_ethertype_filter *)arg,
4379                         FALSE);
4380                 break;
4381         case RTE_ETH_FILTER_GET:
4382                 ret = ixgbe_get_ethertype_filter(dev,
4383                         (struct rte_eth_ethertype_filter *)arg);
4384                 break;
4385         default:
4386                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4387                 ret = -EINVAL;
4388                 break;
4389         }
4390         return ret;
4391 }
4392
4393 static int
4394 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4395                      enum rte_filter_type filter_type,
4396                      enum rte_filter_op filter_op,
4397                      void *arg)
4398 {
4399         int ret = -EINVAL;
4400
4401         switch (filter_type) {
4402         case RTE_ETH_FILTER_NTUPLE:
4403                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4404                 break;
4405         case RTE_ETH_FILTER_ETHERTYPE:
4406                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4407                 break;
4408         case RTE_ETH_FILTER_SYN:
4409                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4410                 break;
4411         case RTE_ETH_FILTER_FDIR:
4412                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4413                 break;
4414         default:
4415                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4416                                                         filter_type);
4417                 break;
4418         }
4419
4420         return ret;
4421 }
4422
4423 static struct rte_driver rte_ixgbe_driver = {
4424         .type = PMD_PDEV,
4425         .init = rte_ixgbe_pmd_init,
4426 };
4427
4428 static struct rte_driver rte_ixgbevf_driver = {
4429         .type = PMD_PDEV,
4430         .init = rte_ixgbevf_pmd_init,
4431 };
4432
4433 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4434 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);