lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_tailq.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "ixgbe/ixgbe_api.h"
  66 #include "ixgbe/ixgbe_vf.h"
  67 #include "ixgbe/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70
  71 /*
  72  * High threshold controlling when to start sending XOFF frames. Must be at
  73  * least 8 bytes less than receive packet buffer size. This value is in units
  74  * of 1024 bytes.
  75  */
  76 #define IXGBE_FC_HI    0x80
  77
  78 /*
  79  * Low threshold controlling when to start sending XON frames. This value is
  80  * in units of 1024 bytes.
  81  */
  82 #define IXGBE_FC_LO    0x40
  83
  84 /* Timer value included in XOFF frames. */
  85 #define IXGBE_FC_PAUSE 0x680
  86
  87 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  88 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  89 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  90
  91 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  92 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  93
  94 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  95
  96 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  97
  98 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
  99                 struct rte_eth_dev *eth_dev);
 100 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 101 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 102 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 103 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 104 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 105 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 106 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 107 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 108 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 109 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 110 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 111                                 int wait_to_complete);
 112 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 113                                 struct rte_eth_stats *stats);
 114 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 115 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 116                                              uint16_t queue_id,
 117                                              uint8_t stat_idx,
 118                                              uint8_t is_rx);
 119 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 120                                 struct rte_eth_dev_info *dev_info);
 121 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 122                 uint16_t vlan_id, int on);
 123 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 124 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 125                 uint16_t queue, bool on);
 126 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 127                 int on);
 128 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 129 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 130 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 131 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 132 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 133
 134 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 135 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 136 static int  ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 137                 struct rte_eth_fc_conf *fc_conf);
 138 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 139                 struct rte_eth_pfc_conf *pfc_conf);
 140 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 141                 struct rte_eth_rss_reta *reta_conf);
 142 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 143                 struct rte_eth_rss_reta *reta_conf);
 144 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 145 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 148 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 149                 void *param);
 150 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 151 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 152                 uint32_t index, uint32_t pool);
 153 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 154 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 155
 156 /* For Virtual Function support */
 157 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 158                 struct rte_eth_dev *eth_dev);
 159 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 160 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 161 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 162 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 163 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 164 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 165                 struct rte_eth_stats *stats);
 166 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 167 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 168                 uint16_t vlan_id, int on);
 169 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 170                 uint16_t queue, int on);
 171 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 172 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 173
 174 /* For Eth VMDQ APIs support */
 175 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 176                 ether_addr* mac_addr,uint8_t on);
 177 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 178 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 179                 uint16_t rx_mask, uint8_t on);
 180 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 181 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 182 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 183                 uint64_t pool_mask,uint8_t vlan_on);
 184 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 185                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 186                 uint8_t rule_id, uint8_t on);
 187 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 188                 uint8_t rule_id);
 189
 190 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 191                 uint16_t queue_idx, uint16_t tx_rate);
 192 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 193                 uint16_t tx_rate, uint64_t q_msk);
 194
 195 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 196                                  struct ether_addr *mac_addr,
 197                                  uint32_t index, uint32_t pool);
 198 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 199
 200 /*
 201  * Define VF Stats MACRO for Non "cleared on read" register
 202  */
 203 #define UPDATE_VF_STAT(reg, last, cur)                          \
 204 {                                                               \
 205         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 206         cur += latest - last;                                   \
 207         last = latest;                                          \
 208 }
 209
 210 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 211 {                                                                \
 212         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 213         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 214         u64 latest = ((new_msb << 32) | new_lsb);                \
 215         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 216         last = latest;                                           \
 217 }
 218
 219 #define IXGBE_SET_HWSTRIP(h, q) do{\
 220                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 221                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 222                 (h)->bitmap[idx] |= 1 << bit;\
 223         }while(0)
 224
 225 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 226                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 227                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 228                 (h)->bitmap[idx] &= ~(1 << bit);\
 229         }while(0)
 230
 231 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 232                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 233                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 234                 (r) = (h)->bitmap[idx] >> bit & 1;\
 235         }while(0)
 236
 237 /*
 238  * The set of PCI devices this driver supports
 239  */
 240 static struct rte_pci_id pci_id_ixgbe_map[] = {
 241
 242 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 243 #include "rte_pci_dev_ids.h"
 244
 245 { .vendor_id = 0, /* sentinel */ },
 246 };
 247
 248
 249 /*
 250  * The set of PCI devices this driver supports (for 82599 VF)
 251  */
 252 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 253
 254 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 255 #include "rte_pci_dev_ids.h"
 256 { .vendor_id = 0, /* sentinel */ },
 257
 258 };
 259
 260 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 261         .dev_configure        = ixgbe_dev_configure,
 262         .dev_start            = ixgbe_dev_start,
 263         .dev_stop             = ixgbe_dev_stop,
 264         .dev_set_link_up    = ixgbe_dev_set_link_up,
 265         .dev_set_link_down  = ixgbe_dev_set_link_down,
 266         .dev_close            = ixgbe_dev_close,
 267         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 268         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 269         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 270         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 271         .link_update          = ixgbe_dev_link_update,
 272         .stats_get            = ixgbe_dev_stats_get,
 273         .stats_reset          = ixgbe_dev_stats_reset,
 274         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 275         .dev_infos_get        = ixgbe_dev_info_get,
 276         .vlan_filter_set      = ixgbe_vlan_filter_set,
 277         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 278         .vlan_offload_set     = ixgbe_vlan_offload_set,
 279         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 280         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 281         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 282         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 283         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 284         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 285         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 286         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 287         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 288         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 289         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 290         .dev_led_on           = ixgbe_dev_led_on,
 291         .dev_led_off          = ixgbe_dev_led_off,
 292         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 293         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 294         .mac_addr_add         = ixgbe_add_rar,
 295         .mac_addr_remove      = ixgbe_remove_rar,
 296         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 297         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 298         .mirror_rule_set      = ixgbe_mirror_rule_set,
 299         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 300         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 301         .set_vf_rx            = ixgbe_set_pool_rx,
 302         .set_vf_tx            = ixgbe_set_pool_tx,
 303         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 304         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 305         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 306         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 307         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 308         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 309         .fdir_infos_get               = ixgbe_fdir_info_get,
 310         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 311         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 312         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 313         .fdir_set_masks               = ixgbe_fdir_set_masks,
 314         .reta_update          = ixgbe_dev_rss_reta_update,
 315         .reta_query           = ixgbe_dev_rss_reta_query,
 316 #ifdef RTE_NIC_BYPASS
 317         .bypass_init          = ixgbe_bypass_init,
 318         .bypass_state_set     = ixgbe_bypass_state_store,
 319         .bypass_state_show    = ixgbe_bypass_state_show,
 320         .bypass_event_set     = ixgbe_bypass_event_store,
 321         .bypass_event_show    = ixgbe_bypass_event_show,
 322         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 323         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 324         .bypass_ver_show      = ixgbe_bypass_ver_show,
 325         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 326 #endif /* RTE_NIC_BYPASS */
 327         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 328         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 329 };
 330
 331 /*
 332  * dev_ops for virtual function, bare necessities for basic vf
 333  * operation have been implemented
 334  */
 335 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 336
 337         .dev_configure        = ixgbevf_dev_configure,
 338         .dev_start            = ixgbevf_dev_start,
 339         .dev_stop             = ixgbevf_dev_stop,
 340         .link_update          = ixgbe_dev_link_update,
 341         .stats_get            = ixgbevf_dev_stats_get,
 342         .stats_reset          = ixgbevf_dev_stats_reset,
 343         .dev_close            = ixgbevf_dev_close,
 344         .dev_infos_get        = ixgbe_dev_info_get,
 345         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 346         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 347         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 348         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 349         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 350         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 351         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 352         .mac_addr_add         = ixgbevf_add_mac_addr,
 353         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 354 };
 355
 356 /**
 357  * Atomically reads the link status information from global
 358  * structure rte_eth_dev.
 359  *
 360  * @param dev
 361  *   - Pointer to the structure rte_eth_dev to read from.
 362  *   - Pointer to the buffer to be saved with the link status.
 363  *
 364  * @return
 365  *   - On success, zero.
 366  *   - On failure, negative value.
 367  */
 368 static inline int
 369 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 370                                 struct rte_eth_link *link)
 371 {
 372         struct rte_eth_link *dst = link;
 373         struct rte_eth_link *src = &(dev->data->dev_link);
 374
 375         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 376                                         *(uint64_t *)src) == 0)
 377                 return -1;
 378
 379         return 0;
 380 }
 381
 382 /**
 383  * Atomically writes the link status information into global
 384  * structure rte_eth_dev.
 385  *
 386  * @param dev
 387  *   - Pointer to the structure rte_eth_dev to read from.
 388  *   - Pointer to the buffer to be saved with the link status.
 389  *
 390  * @return
 391  *   - On success, zero.
 392  *   - On failure, negative value.
 393  */
 394 static inline int
 395 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 396                                 struct rte_eth_link *link)
 397 {
 398         struct rte_eth_link *dst = &(dev->data->dev_link);
 399         struct rte_eth_link *src = link;
 400
 401         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 402                                         *(uint64_t *)src) == 0)
 403                 return -1;
 404
 405         return 0;
 406 }
 407
 408 /*
 409  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 410  */
 411 static inline int
 412 ixgbe_is_sfp(struct ixgbe_hw *hw)
 413 {
 414         switch (hw->phy.type) {
 415         case ixgbe_phy_sfp_avago:
 416         case ixgbe_phy_sfp_ftl:
 417         case ixgbe_phy_sfp_intel:
 418         case ixgbe_phy_sfp_unknown:
 419         case ixgbe_phy_sfp_passive_tyco:
 420         case ixgbe_phy_sfp_passive_unknown:
 421                 return 1;
 422         default:
 423                 return 0;
 424         }
 425 }
 426
 427 static inline int32_t
 428 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 429 {
 430         uint32_t ctrl_ext;
 431         int32_t status;
 432
 433         status = ixgbe_reset_hw(hw);
 434
 435         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 436         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 437         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 438         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 439         IXGBE_WRITE_FLUSH(hw);
 440
 441         return status;
 442 }
 443
 444 static inline void
 445 ixgbe_enable_intr(struct rte_eth_dev *dev)
 446 {
 447         struct ixgbe_interrupt *intr =
 448                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 449         struct ixgbe_hw *hw =
 450                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 451
 452         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 453         IXGBE_WRITE_FLUSH(hw);
 454 }
 455
 456 /*
 457  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 458  */
 459 static void
 460 ixgbe_disable_intr(struct ixgbe_hw *hw)
 461 {
 462         PMD_INIT_FUNC_TRACE();
 463
 464         if (hw->mac.type == ixgbe_mac_82598EB) {
 465                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 466         } else {
 467                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 468                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 469                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 470         }
 471         IXGBE_WRITE_FLUSH(hw);
 472 }
 473
 474 /*
 475  * This function resets queue statistics mapping registers.
 476  * From Niantic datasheet, Initialization of Statistics section:
 477  * "...if software requires the queue counters, the RQSMR and TQSM registers
 478  * must be re-programmed following a device reset.
 479  */
 480 static void
 481 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 482 {
 483         uint32_t i;
 484
 485         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 486                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 487                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 488         }
 489 }
 490
 491
 492 static int
 493 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 494                                   uint16_t queue_id,
 495                                   uint8_t stat_idx,
 496                                   uint8_t is_rx)
 497 {
 498 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 499 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 500 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 501
 502         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 503         struct ixgbe_stat_mapping_registers *stat_mappings =
 504                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 505         uint32_t qsmr_mask = 0;
 506         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 507         uint32_t q_map;
 508         uint8_t n, offset;
 509
 510         if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
 511                 return -ENOSYS;
 512
 513         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
 514                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
 515
 516         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 517         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 518                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
 519                 return -EIO;
 520         }
 521         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 522
 523         /* Now clear any previous stat_idx set */
 524         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 525         if (!is_rx)
 526                 stat_mappings->tqsm[n] &= ~clearing_mask;
 527         else
 528                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 529
 530         q_map = (uint32_t)stat_idx;
 531         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 532         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 533         if (!is_rx)
 534                 stat_mappings->tqsm[n] |= qsmr_mask;
 535         else
 536                 stat_mappings->rqsmr[n] |= qsmr_mask;
 537
 538         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
 539                      "%s[%d] = 0x%08x\n",
 540                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
 541                      is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 542
 543         /* Now write the mapping in the appropriate register */
 544         if (is_rx) {
 545                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
 546                              stat_mappings->rqsmr[n], n);
 547                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 548         }
 549         else {
 550                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
 551                              stat_mappings->tqsm[n], n);
 552                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 553         }
 554         return 0;
 555 }
 556
 557 static void
 558 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 559 {
 560         struct ixgbe_stat_mapping_registers *stat_mappings =
 561                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 562         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 563         int i;
 564
 565         /* write whatever was in stat mapping table to the NIC */
 566         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 567                 /* rx */
 568                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 569
 570                 /* tx */
 571                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 572         }
 573 }
 574
 575 static void
 576 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 577 {
 578         uint8_t i;
 579         struct ixgbe_dcb_tc_config *tc;
 580         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 581
 582         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 583         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 584         for (i = 0; i < dcb_max_tc; i++) {
 585                 tc = &dcb_config->tc_config[i];
 586                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 587                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 588                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 589                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 590                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 591                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 592                 tc->pfc = ixgbe_dcb_pfc_disabled;
 593         }
 594
 595         /* Initialize default user to priority mapping, UPx->TC0 */
 596         tc = &dcb_config->tc_config[0];
 597         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 598         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 599         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 600                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 601                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 602         }
 603         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 604         dcb_config->pfc_mode_enable = false;
 605         dcb_config->vt_mode = true;
 606         dcb_config->round_robin_enable = false;
 607         /* support all DCB capabilities in 82599 */
 608         dcb_config->support.capabilities = 0xFF;
 609
 610         /*we only support 4 Tcs for X540*/
 611         if (hw->mac.type == ixgbe_mac_X540) {
 612                 dcb_config->num_tcs.pg_tcs = 4;
 613                 dcb_config->num_tcs.pfc_tcs = 4;
 614         }
 615 }
 616
 617 /*
 618  * Ensure that all locks are released before first NVM or PHY access
 619  */
 620 static void
 621 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 622 {
 623         uint16_t mask;
 624
 625         /*
 626          * Phy lock should not fail in this early stage. If this is the case,
 627          * it is due to an improper exit of the application.
 628          * So force the release of the faulty lock. Release of common lock
 629          * is done automatically by swfw_sync function.
 630          */
 631         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 632         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 633                    DEBUGOUT1("SWFW phy%d lock released", hw->bus.func);
 634         }
 635         ixgbe_release_swfw_semaphore(hw, mask);
 636
 637         /*
 638          * These ones are more tricky since they are common to all ports; but
 639          * swfw_sync retries last long enough (1s) to be almost sure that if
 640          * lock can not be taken it is due to an improper lock of the
 641          * semaphore.
 642          */
 643         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 644         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 645                    DEBUGOUT("SWFW common locks released");
 646         }
 647         ixgbe_release_swfw_semaphore(hw, mask);
 648 }
 649
 650 /*
 651  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 652  * It returns 0 on success.
 653  */
 654 static int
 655 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 656                      struct rte_eth_dev *eth_dev)
 657 {
 658         struct rte_pci_device *pci_dev;
 659         struct ixgbe_hw *hw =
 660                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 661         struct ixgbe_vfta * shadow_vfta =
 662                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 663         struct ixgbe_hwstrip *hwstrip =
 664                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 665         struct ixgbe_dcb_config *dcb_config =
 666                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 667         uint32_t ctrl_ext;
 668         uint16_t csum;
 669         int diag, i;
 670
 671         PMD_INIT_FUNC_TRACE();
 672
 673         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 674         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 675         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 676
 677         /* for secondary processes, we don't initialise any further as primary
 678          * has already done this work. Only check we don't need a different
 679          * RX function */
 680         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 681                 if (eth_dev->data->scattered_rx)
 682                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 683                 return 0;
 684         }
 685         pci_dev = eth_dev->pci_dev;
 686
 687         /* Vendor and Device ID need to be set before init of shared code */
 688         hw->device_id = pci_dev->id.device_id;
 689         hw->vendor_id = pci_dev->id.vendor_id;
 690         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 691 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
 692         hw->allow_unsupported_sfp = 1;
 693 #endif
 694
 695         /* Initialize the shared code */
 696 #ifdef RTE_NIC_BYPASS
 697         diag = ixgbe_bypass_init_shared_code(hw);
 698 #else
 699         diag = ixgbe_init_shared_code(hw);
 700 #endif /* RTE_NIC_BYPASS */
 701
 702         if (diag != IXGBE_SUCCESS) {
 703                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 704                 return -EIO;
 705         }
 706
 707         /* pick up the PCI bus settings for reporting later */
 708         ixgbe_get_bus_info(hw);
 709
 710         /* Unlock any pending hardware semaphore */
 711         ixgbe_swfw_lock_reset(hw);
 712
 713         /* Initialize DCB configuration*/
 714         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 715         ixgbe_dcb_init(hw,dcb_config);
 716         /* Get Hardware Flow Control setting */
 717         hw->fc.requested_mode = ixgbe_fc_full;
 718         hw->fc.current_mode = ixgbe_fc_full;
 719         hw->fc.pause_time = IXGBE_FC_PAUSE;
 720         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 721                 hw->fc.low_water[i] = IXGBE_FC_LO;
 722                 hw->fc.high_water[i] = IXGBE_FC_HI;
 723         }
 724         hw->fc.send_xon = 1;
 725
 726         /* Make sure we have a good EEPROM before we read from it */
 727         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 728         if (diag != IXGBE_SUCCESS) {
 729                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 730                 return -EIO;
 731         }
 732
 733 #ifdef RTE_NIC_BYPASS
 734         diag = ixgbe_bypass_init_hw(hw);
 735 #else
 736         diag = ixgbe_init_hw(hw);
 737 #endif /* RTE_NIC_BYPASS */
 738
 739         /*
 740          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 741          * is called too soon after the kernel driver unbinding/binding occurs.
 742          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 743          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 744          * also called. See ixgbe_identify_phy_82599(). The reason for the
 745          * failure is not known, and only occuts when virtualisation features
 746          * are disabled in the bios. A delay of 100ms  was found to be enough by
 747          * trial-and-error, and is doubled to be safe.
 748          */
 749         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 750                 rte_delay_ms(200);
 751                 diag = ixgbe_init_hw(hw);
 752         }
 753
 754         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 755                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 756                     "LOM.  Please be aware there may be issues associated "
 757                     "with your hardware.\n If you are experiencing problems "
 758                     "please contact your Intel or hardware representative "
 759                     "who provided you with this hardware.\n");
 760         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 761                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
 762         if (diag) {
 763                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 764                 return -EIO;
 765         }
 766
 767         /* disable interrupt */
 768         ixgbe_disable_intr(hw);
 769
 770         /* reset mappings for queue statistics hw counters*/
 771         ixgbe_reset_qstat_mappings(hw);
 772
 773         /* Allocate memory for storing MAC addresses */
 774         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 775                         hw->mac.num_rar_entries, 0);
 776         if (eth_dev->data->mac_addrs == NULL) {
 777                 PMD_INIT_LOG(ERR,
 778                         "Failed to allocate %u bytes needed to store "
 779                         "MAC addresses",
 780                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 781                 return -ENOMEM;
 782         }
 783         /* Copy the permanent MAC address */
 784         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 785                         &eth_dev->data->mac_addrs[0]);
 786
 787         /* Allocate memory for storing hash filter MAC addresses */
 788         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 789                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 790         if (eth_dev->data->hash_mac_addrs == NULL) {
 791                 PMD_INIT_LOG(ERR,
 792                         "Failed to allocate %d bytes needed to store MAC addresses",
 793                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 794                 return -ENOMEM;
 795         }
 796
 797         /* initialize the vfta */
 798         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 799
 800         /* initialize the hw strip bitmap*/
 801         memset(hwstrip, 0, sizeof(*hwstrip));
 802
 803         /* initialize PF if max_vfs not zero */
 804         ixgbe_pf_host_init(eth_dev);
 805
 806         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 807         /* let hardware know driver is loaded */
 808         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 809         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 810         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 811         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 812         IXGBE_WRITE_FLUSH(hw);
 813
 814         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 815                 PMD_INIT_LOG(DEBUG,
 816                              "MAC: %d, PHY: %d, SFP+: %d<n",
 817                              (int) hw->mac.type, (int) hw->phy.type,
 818                              (int) hw->phy.sfp_type);
 819         else
 820                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
 821                              (int) hw->mac.type, (int) hw->phy.type);
 822
 823         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 824                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 825                         pci_dev->id.device_id);
 826
 827         rte_intr_callback_register(&(pci_dev->intr_handle),
 828                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 829
 830         /* enable uio intr after callback register */
 831         rte_intr_enable(&(pci_dev->intr_handle));
 832
 833         /* enable support intr */
 834         ixgbe_enable_intr(eth_dev);
 835
 836         return 0;
 837 }
 838
 839
 840 /*
 841  * Negotiate mailbox API version with the PF.
 842  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 843  * Then we try to negotiate starting with the most recent one.
 844  * If all negotiation attempts fail, then we will proceed with
 845  * the default one (ixgbe_mbox_api_10).
 846  */
 847 static void
 848 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 849 {
 850         int32_t i;
 851
 852         /* start with highest supported, proceed down */
 853         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 854                 ixgbe_mbox_api_11,
 855                 ixgbe_mbox_api_10,
 856         };
 857
 858         for (i = 0;
 859                         i != RTE_DIM(sup_ver) &&
 860                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 861                         i++)
 862                 ;
 863 }
 864
 865 static void
 866 generate_random_mac_addr(struct ether_addr *mac_addr)
 867 {
 868         uint64_t random;
 869
 870         /* Set Organizationally Unique Identifier (OUI) prefix. */
 871         mac_addr->addr_bytes[0] = 0x00;
 872         mac_addr->addr_bytes[1] = 0x09;
 873         mac_addr->addr_bytes[2] = 0xC0;
 874         /* Force indication of locally assigned MAC address. */
 875         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 876         /* Generate the last 3 bytes of the MAC address with a random number. */
 877         random = rte_rand();
 878         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 879 }
 880
 881 /*
 882  * Virtual Function device init
 883  */
 884 static int
 885 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 886                      struct rte_eth_dev *eth_dev)
 887 {
 888         int diag;
 889         uint32_t tc, tcs;
 890         struct rte_pci_device *pci_dev;
 891         struct ixgbe_hw *hw =
 892                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 893         struct ixgbe_vfta * shadow_vfta =
 894                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 895         struct ixgbe_hwstrip *hwstrip =
 896                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 897         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 898
 899         PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
 900
 901         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 902         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 903         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 904
 905         /* for secondary processes, we don't initialise any further as primary
 906          * has already done this work. Only check we don't need a different
 907          * RX function */
 908         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 909                 if (eth_dev->data->scattered_rx)
 910                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 911                 return 0;
 912         }
 913
 914         pci_dev = eth_dev->pci_dev;
 915
 916         hw->device_id = pci_dev->id.device_id;
 917         hw->vendor_id = pci_dev->id.vendor_id;
 918         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 919
 920         /* initialize the vfta */
 921         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 922
 923         /* initialize the hw strip bitmap*/
 924         memset(hwstrip, 0, sizeof(*hwstrip));
 925
 926         /* Initialize the shared code */
 927         diag = ixgbe_init_shared_code(hw);
 928         if (diag != IXGBE_SUCCESS) {
 929                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 930                 return -EIO;
 931         }
 932
 933         /* init_mailbox_params */
 934         hw->mbx.ops.init_params(hw);
 935
 936         /* Disable the interrupts for VF */
 937         ixgbevf_intr_disable(hw);
 938
 939         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
 940         diag = hw->mac.ops.reset_hw(hw);
 941
 942         /*
 943          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
 944          * the underlying PF driver has not assigned a MAC address to the VF.
 945          * In this case, assign a random MAC address.
 946          */
 947         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
 948                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 949                 return (diag);
 950         }
 951
 952         /* negotiate mailbox API version to use with the PF. */
 953         ixgbevf_negotiate_api(hw);
 954
 955         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
 956         ixgbevf_get_queues(hw, &tcs, &tc);
 957
 958         /* Allocate memory for storing MAC addresses */
 959         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
 960                         hw->mac.num_rar_entries, 0);
 961         if (eth_dev->data->mac_addrs == NULL) {
 962                 PMD_INIT_LOG(ERR,
 963                         "Failed to allocate %u bytes needed to store "
 964                         "MAC addresses",
 965                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 966                 return -ENOMEM;
 967         }
 968
 969         /* Generate a random MAC address, if none was assigned by PF. */
 970         if (is_zero_ether_addr(perm_addr)) {
 971                 generate_random_mac_addr(perm_addr);
 972                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
 973                 if (diag) {
 974                         rte_free(eth_dev->data->mac_addrs);
 975                         eth_dev->data->mac_addrs = NULL;
 976                         return diag;
 977                 }
 978                 RTE_LOG(INFO, PMD,
 979                         "\tVF MAC address not assigned by Host PF\n"
 980                         "\tAssign randomly generated MAC address "
 981                         "%02x:%02x:%02x:%02x:%02x:%02x\n",
 982                         perm_addr->addr_bytes[0],
 983                         perm_addr->addr_bytes[1],
 984                         perm_addr->addr_bytes[2],
 985                         perm_addr->addr_bytes[3],
 986                         perm_addr->addr_bytes[4],
 987                         perm_addr->addr_bytes[5]);
 988         }
 989
 990         /* Copy the permanent MAC address */
 991         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
 992
 993         /* reset the hardware with the new settings */
 994         diag = hw->mac.ops.start_hw(hw);
 995         switch (diag) {
 996                 case  0:
 997                         break;
 998
 999                 default:
1000                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1001                         return (-EIO);
1002         }
1003
1004         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
1005                          eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
1006                          "ixgbe_mac_82599_vf");
1007
1008         return 0;
1009 }
1010
1011 static struct eth_driver rte_ixgbe_pmd = {
1012         {
1013                 .name = "rte_ixgbe_pmd",
1014                 .id_table = pci_id_ixgbe_map,
1015                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1016         },
1017         .eth_dev_init = eth_ixgbe_dev_init,
1018         .dev_private_size = sizeof(struct ixgbe_adapter),
1019 };
1020
1021 /*
1022  * virtual function driver struct
1023  */
1024 static struct eth_driver rte_ixgbevf_pmd = {
1025         {
1026                 .name = "rte_ixgbevf_pmd",
1027                 .id_table = pci_id_ixgbevf_map,
1028                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1029         },
1030         .eth_dev_init = eth_ixgbevf_dev_init,
1031         .dev_private_size = sizeof(struct ixgbe_adapter),
1032 };
1033
1034 /*
1035  * Driver initialization routine.
1036  * Invoked once at EAL init time.
1037  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1038  */
1039 static int
1040 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1041 {
1042         PMD_INIT_FUNC_TRACE();
1043
1044         rte_eth_driver_register(&rte_ixgbe_pmd);
1045         return 0;
1046 }
1047
1048 /*
1049  * VF Driver initialization routine.
1050  * Invoked one at EAL init time.
1051  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1052  */
1053 static int
1054 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1055 {
1056         DEBUGFUNC("rte_ixgbevf_pmd_init");
1057
1058         rte_eth_driver_register(&rte_ixgbevf_pmd);
1059         return (0);
1060 }
1061
1062 static int
1063 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1064 {
1065         struct ixgbe_hw *hw =
1066                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1067         struct ixgbe_vfta * shadow_vfta =
1068                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1069         uint32_t vfta;
1070         uint32_t vid_idx;
1071         uint32_t vid_bit;
1072
1073         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1074         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1075         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1076         if (on)
1077                 vfta |= vid_bit;
1078         else
1079                 vfta &= ~vid_bit;
1080         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1081
1082         /* update local VFTA copy */
1083         shadow_vfta->vfta[vid_idx] = vfta;
1084
1085         return 0;
1086 }
1087
1088 static void
1089 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1090 {
1091         if (on)
1092                 ixgbe_vlan_hw_strip_enable(dev, queue);
1093         else
1094                 ixgbe_vlan_hw_strip_disable(dev, queue);
1095 }
1096
1097 static void
1098 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1099 {
1100         struct ixgbe_hw *hw =
1101                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1102
1103         /* Only the high 16-bits is valid */
1104         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1105 }
1106
1107 void
1108 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1109 {
1110         struct ixgbe_hw *hw =
1111                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1112         uint32_t vlnctrl;
1113
1114         PMD_INIT_FUNC_TRACE();
1115
1116         /* Filter Table Disable */
1117         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1118         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1119
1120         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1121 }
1122
1123 void
1124 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1125 {
1126         struct ixgbe_hw *hw =
1127                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1128         struct ixgbe_vfta * shadow_vfta =
1129                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1130         uint32_t vlnctrl;
1131         uint16_t i;
1132
1133         PMD_INIT_FUNC_TRACE();
1134
1135         /* Filter Table Enable */
1136         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1137         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1138         vlnctrl |= IXGBE_VLNCTRL_VFE;
1139
1140         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1141
1142         /* write whatever is in local vfta copy */
1143         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1144                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1145 }
1146
1147 static void
1148 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1149 {
1150         struct ixgbe_hwstrip *hwstrip =
1151                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1152
1153         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1154                 return;
1155
1156         if (on)
1157                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1158         else
1159                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1160 }
1161
1162 static void
1163 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1164 {
1165         struct ixgbe_hw *hw =
1166                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1167         uint32_t ctrl;
1168
1169         PMD_INIT_FUNC_TRACE();
1170
1171         if (hw->mac.type == ixgbe_mac_82598EB) {
1172                 /* No queue level support */
1173                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1174                 return;
1175         }
1176         else {
1177                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1178                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1179                 ctrl &= ~IXGBE_RXDCTL_VME;
1180                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1181         }
1182         /* record those setting for HW strip per queue */
1183         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1184 }
1185
1186 static void
1187 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1188 {
1189         struct ixgbe_hw *hw =
1190                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1191         uint32_t ctrl;
1192
1193         PMD_INIT_FUNC_TRACE();
1194
1195         if (hw->mac.type == ixgbe_mac_82598EB) {
1196                 /* No queue level supported */
1197                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1198                 return;
1199         }
1200         else {
1201                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1202                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1203                 ctrl |= IXGBE_RXDCTL_VME;
1204                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1205         }
1206         /* record those setting for HW strip per queue */
1207         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1208 }
1209
1210 void
1211 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1212 {
1213         struct ixgbe_hw *hw =
1214                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1215         uint32_t ctrl;
1216         uint16_t i;
1217
1218         PMD_INIT_FUNC_TRACE();
1219
1220         if (hw->mac.type == ixgbe_mac_82598EB) {
1221                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1222                 ctrl &= ~IXGBE_VLNCTRL_VME;
1223                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1224         }
1225         else {
1226                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1227                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1228                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1229                         ctrl &= ~IXGBE_RXDCTL_VME;
1230                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1231
1232                         /* record those setting for HW strip per queue */
1233                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1234                 }
1235         }
1236 }
1237
1238 void
1239 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1240 {
1241         struct ixgbe_hw *hw =
1242                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1243         uint32_t ctrl;
1244         uint16_t i;
1245
1246         PMD_INIT_FUNC_TRACE();
1247
1248         if (hw->mac.type == ixgbe_mac_82598EB) {
1249                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1250                 ctrl |= IXGBE_VLNCTRL_VME;
1251                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1252         }
1253         else {
1254                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1255                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1256                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1257                         ctrl |= IXGBE_RXDCTL_VME;
1258                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1259
1260                         /* record those setting for HW strip per queue */
1261                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1262                 }
1263         }
1264 }
1265
1266 static void
1267 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1268 {
1269         struct ixgbe_hw *hw =
1270                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1271         uint32_t ctrl;
1272
1273         PMD_INIT_FUNC_TRACE();
1274
1275         /* DMATXCTRL: Geric Double VLAN Disable */
1276         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1277         ctrl &= ~IXGBE_DMATXCTL_GDV;
1278         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1279
1280         /* CTRL_EXT: Global Double VLAN Disable */
1281         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1282         ctrl &= ~IXGBE_EXTENDED_VLAN;
1283         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1284
1285 }
1286
1287 static void
1288 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1289 {
1290         struct ixgbe_hw *hw =
1291                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1292         uint32_t ctrl;
1293
1294         PMD_INIT_FUNC_TRACE();
1295
1296         /* DMATXCTRL: Geric Double VLAN Enable */
1297         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1298         ctrl |= IXGBE_DMATXCTL_GDV;
1299         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1300
1301         /* CTRL_EXT: Global Double VLAN Enable */
1302         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1303         ctrl |= IXGBE_EXTENDED_VLAN;
1304         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1305
1306         /*
1307          * VET EXT field in the EXVET register = 0x8100 by default
1308          * So no need to change. Same to VT field of DMATXCTL register
1309          */
1310 }
1311
1312 static void
1313 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1314 {
1315         if(mask & ETH_VLAN_STRIP_MASK){
1316                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1317                         ixgbe_vlan_hw_strip_enable_all(dev);
1318                 else
1319                         ixgbe_vlan_hw_strip_disable_all(dev);
1320         }
1321
1322         if(mask & ETH_VLAN_FILTER_MASK){
1323                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1324                         ixgbe_vlan_hw_filter_enable(dev);
1325                 else
1326                         ixgbe_vlan_hw_filter_disable(dev);
1327         }
1328
1329         if(mask & ETH_VLAN_EXTEND_MASK){
1330                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1331                         ixgbe_vlan_hw_extend_enable(dev);
1332                 else
1333                         ixgbe_vlan_hw_extend_disable(dev);
1334         }
1335 }
1336
1337 static void
1338 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1339 {
1340         struct ixgbe_hw *hw =
1341                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1342         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1343         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1344         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1345         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1346 }
1347
1348 static int
1349 ixgbe_dev_configure(struct rte_eth_dev *dev)
1350 {
1351         struct ixgbe_interrupt *intr =
1352                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1353
1354         PMD_INIT_FUNC_TRACE();
1355
1356         /* set flag to update link status after init */
1357         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1358
1359         return 0;
1360 }
1361
1362 /*
1363  * Configure device link speed and setup link.
1364  * It returns 0 on success.
1365  */
1366 static int
1367 ixgbe_dev_start(struct rte_eth_dev *dev)
1368 {
1369         struct ixgbe_hw *hw =
1370                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1371         struct ixgbe_vf_info *vfinfo =
1372                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1373         int err, link_up = 0, negotiate = 0;
1374         uint32_t speed = 0;
1375         int mask = 0;
1376         int status;
1377         uint16_t vf, idx;
1378
1379         PMD_INIT_FUNC_TRACE();
1380
1381         /* IXGBE devices don't support half duplex */
1382         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1383                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1384                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1385                                 dev->data->dev_conf.link_duplex,
1386                                 dev->data->port_id);
1387                 return -EINVAL;
1388         }
1389
1390         /* stop adapter */
1391         hw->adapter_stopped = FALSE;
1392         ixgbe_stop_adapter(hw);
1393
1394         /* reinitialize adapter
1395          * this calls reset and start */
1396         status = ixgbe_pf_reset_hw(hw);
1397         if (status != 0)
1398                 return -1;
1399         hw->mac.ops.start_hw(hw);
1400
1401         /* configure PF module if SRIOV enabled */
1402         ixgbe_pf_host_configure(dev);
1403
1404         /* initialize transmission unit */
1405         ixgbe_dev_tx_init(dev);
1406
1407         /* This can fail when allocating mbufs for descriptor rings */
1408         err = ixgbe_dev_rx_init(dev);
1409         if (err) {
1410                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1411                 goto error;
1412         }
1413
1414         ixgbe_dev_rxtx_start(dev);
1415
1416         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1417                 err = hw->mac.ops.setup_sfp(hw);
1418                 if (err)
1419                         goto error;
1420         }
1421
1422         /* Turn on the laser */
1423         ixgbe_enable_tx_laser(hw);
1424
1425         /* Skip link setup if loopback mode is enabled for 82599. */
1426         if (hw->mac.type == ixgbe_mac_82599EB &&
1427                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1428                 goto skip_link_setup;
1429
1430         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1431         if (err)
1432                 goto error;
1433         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1434         if (err)
1435                 goto error;
1436
1437         switch(dev->data->dev_conf.link_speed) {
1438         case ETH_LINK_SPEED_AUTONEG:
1439                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1440                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1441                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1442                 break;
1443         case ETH_LINK_SPEED_100:
1444                 /*
1445                  * Invalid for 82598 but error will be detected by
1446                  * ixgbe_setup_link()
1447                  */
1448                 speed = IXGBE_LINK_SPEED_100_FULL;
1449                 break;
1450         case ETH_LINK_SPEED_1000:
1451                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1452                 break;
1453         case ETH_LINK_SPEED_10000:
1454                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1455                 break;
1456         default:
1457                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1458                                 dev->data->dev_conf.link_speed,
1459                                 dev->data->port_id);
1460                 goto error;
1461         }
1462
1463         err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1464         if (err)
1465                 goto error;
1466
1467 skip_link_setup:
1468
1469         /* check if lsc interrupt is enabled */
1470         if (dev->data->dev_conf.intr_conf.lsc != 0)
1471                 ixgbe_dev_lsc_interrupt_setup(dev);
1472
1473         /* resume enabled intr since hw reset */
1474         ixgbe_enable_intr(dev);
1475
1476         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1477                 ETH_VLAN_EXTEND_MASK;
1478         ixgbe_vlan_offload_set(dev, mask);
1479
1480         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1481                 /* Enable vlan filtering for VMDq */
1482                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1483         }
1484
1485         /* Configure DCB hw */
1486         ixgbe_configure_dcb(dev);
1487
1488         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1489                 err = ixgbe_fdir_configure(dev);
1490                 if (err)
1491                         goto error;
1492         }
1493
1494         /* Restore vf rate limit */
1495         if (vfinfo != NULL) {
1496                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1497                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1498                                 if (vfinfo[vf].tx_rate[idx] != 0)
1499                                         ixgbe_set_vf_rate_limit(dev, vf,
1500                                                 vfinfo[vf].tx_rate[idx],
1501                                                 1 << idx);
1502         }
1503
1504         ixgbe_restore_statistics_mapping(dev);
1505
1506         return (0);
1507
1508 error:
1509         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1510         ixgbe_dev_clear_queues(dev);
1511         return -EIO;
1512 }
1513
1514 /*
1515  * Stop device: disable rx and tx functions to allow for reconfiguring.
1516  */
1517 static void
1518 ixgbe_dev_stop(struct rte_eth_dev *dev)
1519 {
1520         struct rte_eth_link link;
1521         struct ixgbe_hw *hw =
1522                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1523         struct ixgbe_vf_info *vfinfo =
1524                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1525         int vf;
1526
1527         PMD_INIT_FUNC_TRACE();
1528
1529         /* disable interrupts */
1530         ixgbe_disable_intr(hw);
1531
1532         /* reset the NIC */
1533         ixgbe_pf_reset_hw(hw);
1534         hw->adapter_stopped = FALSE;
1535
1536         /* stop adapter */
1537         ixgbe_stop_adapter(hw);
1538
1539         for (vf = 0; vfinfo != NULL &&
1540                      vf < dev->pci_dev->max_vfs; vf++)
1541                 vfinfo[vf].clear_to_send = false;
1542
1543         /* Turn off the laser */
1544         ixgbe_disable_tx_laser(hw);
1545
1546         ixgbe_dev_clear_queues(dev);
1547
1548         /* Clear recorded link status */
1549         memset(&link, 0, sizeof(link));
1550         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1551 }
1552
1553 /*
1554  * Set device link up: enable tx laser.
1555  */
1556 static int
1557 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1558 {
1559         struct ixgbe_hw *hw =
1560                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1561         if (hw->mac.type == ixgbe_mac_82599EB) {
1562 #ifdef RTE_NIC_BYPASS
1563                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1564                         /* Not suported in bypass mode */
1565                         PMD_INIT_LOG(ERR,
1566                                 "\nSet link up is not supported "
1567                                 "by device id 0x%x\n",
1568                                 hw->device_id);
1569                         return -ENOTSUP;
1570                 }
1571 #endif
1572                 /* Turn on the laser */
1573                 ixgbe_enable_tx_laser(hw);
1574                 return 0;
1575         }
1576
1577         PMD_INIT_LOG(ERR, "\nSet link up is not supported by device id 0x%x\n",
1578                 hw->device_id);
1579         return -ENOTSUP;
1580 }
1581
1582 /*
1583  * Set device link down: disable tx laser.
1584  */
1585 static int
1586 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1587 {
1588         struct ixgbe_hw *hw =
1589                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1590         if (hw->mac.type == ixgbe_mac_82599EB) {
1591 #ifdef RTE_NIC_BYPASS
1592                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1593                         /* Not suported in bypass mode */
1594                         PMD_INIT_LOG(ERR,
1595                                 "\nSet link down is not supported "
1596                                 "by device id 0x%x\n",
1597                                  hw->device_id);
1598                         return -ENOTSUP;
1599                 }
1600 #endif
1601                 /* Turn off the laser */
1602                 ixgbe_disable_tx_laser(hw);
1603                 return 0;
1604         }
1605
1606         PMD_INIT_LOG(ERR,
1607                 "\nSet link down is not supported by device id 0x%x\n",
1608                  hw->device_id);
1609         return -ENOTSUP;
1610 }
1611
1612 /*
1613  * Reest and stop device.
1614  */
1615 static void
1616 ixgbe_dev_close(struct rte_eth_dev *dev)
1617 {
1618         struct ixgbe_hw *hw =
1619                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1620
1621         PMD_INIT_FUNC_TRACE();
1622
1623         ixgbe_pf_reset_hw(hw);
1624
1625         ixgbe_dev_stop(dev);
1626         hw->adapter_stopped = 1;
1627
1628         ixgbe_disable_pcie_master(hw);
1629
1630         /* reprogram the RAR[0] in case user changed it. */
1631         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1632 }
1633
1634 /*
1635  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1636  */
1637 static void
1638 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1639 {
1640         struct ixgbe_hw *hw =
1641                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1642         struct ixgbe_hw_stats *hw_stats =
1643                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1644         uint32_t bprc, lxon, lxoff, total;
1645         uint64_t total_missed_rx, total_qbrc, total_qprc;
1646         unsigned i;
1647
1648         total_missed_rx = 0;
1649         total_qbrc = 0;
1650         total_qprc = 0;
1651
1652         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1653         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1654         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1655         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1656
1657         for (i = 0; i < 8; i++) {
1658                 uint32_t mp;
1659                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1660                 /* global total per queue */
1661                 hw_stats->mpc[i] += mp;
1662                 /* Running comprehensive total for stats display */
1663                 total_missed_rx += hw_stats->mpc[i];
1664                 if (hw->mac.type == ixgbe_mac_82598EB)
1665                         hw_stats->rnbc[i] +=
1666                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1667                 hw_stats->pxontxc[i] +=
1668                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1669                 hw_stats->pxonrxc[i] +=
1670                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1671                 hw_stats->pxofftxc[i] +=
1672                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1673                 hw_stats->pxoffrxc[i] +=
1674                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1675                 hw_stats->pxon2offc[i] +=
1676                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1677         }
1678         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1679                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1680                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1681                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1682                 hw_stats->qbrc[i] +=
1683                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1684                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1685                 hw_stats->qbtc[i] +=
1686                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1687                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1688
1689                 total_qprc += hw_stats->qprc[i];
1690                 total_qbrc += hw_stats->qbrc[i];
1691         }
1692         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1693         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1694         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1695
1696         /* Note that gprc counts missed packets */
1697         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1698
1699         if (hw->mac.type != ixgbe_mac_82598EB) {
1700                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1701                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1702                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1703                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1704                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1705                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1706                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1707                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1708         } else {
1709                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1710                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1711                 /* 82598 only has a counter in the high register */
1712                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1713                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1714                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1715         }
1716
1717         /*
1718          * Workaround: mprc hardware is incorrectly counting
1719          * broadcasts, so for now we subtract those.
1720          */
1721         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1722         hw_stats->bprc += bprc;
1723         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1724         if (hw->mac.type == ixgbe_mac_82598EB)
1725                 hw_stats->mprc -= bprc;
1726
1727         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1728         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1729         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1730         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1731         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1732         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1733
1734         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1735         hw_stats->lxontxc += lxon;
1736         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1737         hw_stats->lxofftxc += lxoff;
1738         total = lxon + lxoff;
1739
1740         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1741         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1742         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1743         hw_stats->gptc -= total;
1744         hw_stats->mptc -= total;
1745         hw_stats->ptc64 -= total;
1746         hw_stats->gotc -= total * ETHER_MIN_LEN;
1747
1748         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1749         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1750         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1751         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1752         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1753         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1754         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1755         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1756         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1757         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1758         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1759         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1760         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1761         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1762         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1763         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1764         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1765         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1766         /* Only read FCOE on 82599 */
1767         if (hw->mac.type != ixgbe_mac_82598EB) {
1768                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1769                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1770                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1771                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1772                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1773         }
1774
1775         if (stats == NULL)
1776                 return;
1777
1778         /* Fill out the rte_eth_stats statistics structure */
1779         stats->ipackets = total_qprc;
1780         stats->ibytes = total_qbrc;
1781         stats->opackets = hw_stats->gptc;
1782         stats->obytes = hw_stats->gotc;
1783         stats->imcasts = hw_stats->mprc;
1784
1785         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1786                 stats->q_ipackets[i] = hw_stats->qprc[i];
1787                 stats->q_opackets[i] = hw_stats->qptc[i];
1788                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1789                 stats->q_obytes[i] = hw_stats->qbtc[i];
1790                 stats->q_errors[i] = hw_stats->qprdc[i];
1791         }
1792
1793         /* Rx Errors */
1794         stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1795                 hw_stats->rlec;
1796
1797         stats->oerrors  = 0;
1798
1799         /* XON/XOFF pause frames */
1800         stats->tx_pause_xon  = hw_stats->lxontxc;
1801         stats->rx_pause_xon  = hw_stats->lxonrxc;
1802         stats->tx_pause_xoff = hw_stats->lxofftxc;
1803         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1804
1805         /* Flow Director Stats registers */
1806         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1807         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1808         stats->fdirmatch = hw_stats->fdirmatch;
1809         stats->fdirmiss = hw_stats->fdirmiss;
1810 }
1811
1812 static void
1813 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1814 {
1815         struct ixgbe_hw_stats *stats =
1816                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1817
1818         /* HW registers are cleared on read */
1819         ixgbe_dev_stats_get(dev, NULL);
1820
1821         /* Reset software totals */
1822         memset(stats, 0, sizeof(*stats));
1823 }
1824
1825 static void
1826 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1827 {
1828         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1829         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1830                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1831
1832         /* Good Rx packet, include VF loopback */
1833         UPDATE_VF_STAT(IXGBE_VFGPRC,
1834             hw_stats->last_vfgprc, hw_stats->vfgprc);
1835
1836         /* Good Rx octets, include VF loopback */
1837         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1838             hw_stats->last_vfgorc, hw_stats->vfgorc);
1839
1840         /* Good Tx packet, include VF loopback */
1841         UPDATE_VF_STAT(IXGBE_VFGPTC,
1842             hw_stats->last_vfgptc, hw_stats->vfgptc);
1843
1844         /* Good Tx octets, include VF loopback */
1845         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1846             hw_stats->last_vfgotc, hw_stats->vfgotc);
1847
1848         /* Rx Multicst Packet */
1849         UPDATE_VF_STAT(IXGBE_VFMPRC,
1850             hw_stats->last_vfmprc, hw_stats->vfmprc);
1851
1852         if (stats == NULL)
1853                 return;
1854
1855         memset(stats, 0, sizeof(*stats));
1856         stats->ipackets = hw_stats->vfgprc;
1857         stats->ibytes = hw_stats->vfgorc;
1858         stats->opackets = hw_stats->vfgptc;
1859         stats->obytes = hw_stats->vfgotc;
1860         stats->imcasts = hw_stats->vfmprc;
1861 }
1862
1863 static void
1864 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1865 {
1866         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1867                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1868
1869         /* Sync HW register to the last stats */
1870         ixgbevf_dev_stats_get(dev, NULL);
1871
1872         /* reset HW current stats*/
1873         hw_stats->vfgprc = 0;
1874         hw_stats->vfgorc = 0;
1875         hw_stats->vfgptc = 0;
1876         hw_stats->vfgotc = 0;
1877         hw_stats->vfmprc = 0;
1878
1879 }
1880
1881 static void
1882 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1883 {
1884         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1885
1886         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1887         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1888         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1889         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1890         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1891         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1892         dev_info->max_vfs = dev->pci_dev->max_vfs;
1893         if (hw->mac.type == ixgbe_mac_82598EB)
1894                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1895         else
1896                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1897         dev_info->rx_offload_capa =
1898                 DEV_RX_OFFLOAD_VLAN_STRIP |
1899                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1900                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1901                 DEV_RX_OFFLOAD_TCP_CKSUM;
1902         dev_info->tx_offload_capa =
1903                 DEV_TX_OFFLOAD_VLAN_INSERT |
1904                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1905                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1906                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1907                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1908 }
1909
1910 /* return 0 means link status changed, -1 means not changed */
1911 static int
1912 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1913 {
1914         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1915         struct rte_eth_link link, old;
1916         ixgbe_link_speed link_speed;
1917         int link_up;
1918         int diag;
1919
1920         link.link_status = 0;
1921         link.link_speed = 0;
1922         link.link_duplex = 0;
1923         memset(&old, 0, sizeof(old));
1924         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1925
1926         /* check if it needs to wait to complete, if lsc interrupt is enabled */
1927         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1928                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1929         else
1930                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1931         if (diag != 0) {
1932                 link.link_speed = ETH_LINK_SPEED_100;
1933                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1934                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1935                 if (link.link_status == old.link_status)
1936                         return -1;
1937                 return 0;
1938         }
1939
1940         if (link_up == 0) {
1941                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1942                 if (link.link_status == old.link_status)
1943                         return -1;
1944                 return 0;
1945         }
1946         link.link_status = 1;
1947         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1948
1949         switch (link_speed) {
1950         default:
1951         case IXGBE_LINK_SPEED_UNKNOWN:
1952                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1953                 link.link_speed = ETH_LINK_SPEED_100;
1954                 break;
1955
1956         case IXGBE_LINK_SPEED_100_FULL:
1957                 link.link_speed = ETH_LINK_SPEED_100;
1958                 break;
1959
1960         case IXGBE_LINK_SPEED_1GB_FULL:
1961                 link.link_speed = ETH_LINK_SPEED_1000;
1962                 break;
1963
1964         case IXGBE_LINK_SPEED_10GB_FULL:
1965                 link.link_speed = ETH_LINK_SPEED_10000;
1966                 break;
1967         }
1968         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1969
1970         if (link.link_status == old.link_status)
1971                 return -1;
1972
1973         return 0;
1974 }
1975
1976 static void
1977 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1978 {
1979         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1980         uint32_t fctrl;
1981
1982         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1983         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1984         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1985 }
1986
1987 static void
1988 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1989 {
1990         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         uint32_t fctrl;
1992
1993         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1994         fctrl &= (~IXGBE_FCTRL_UPE);
1995         if (dev->data->all_multicast == 1)
1996                 fctrl |= IXGBE_FCTRL_MPE;
1997         else
1998                 fctrl &= (~IXGBE_FCTRL_MPE);
1999         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2000 }
2001
2002 static void
2003 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2004 {
2005         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006         uint32_t fctrl;
2007
2008         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2009         fctrl |= IXGBE_FCTRL_MPE;
2010         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2011 }
2012
2013 static void
2014 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2015 {
2016         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017         uint32_t fctrl;
2018
2019         if (dev->data->promiscuous == 1)
2020                 return; /* must remain in all_multicast mode */
2021
2022         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2023         fctrl &= (~IXGBE_FCTRL_MPE);
2024         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2025 }
2026
2027 /**
2028  * It clears the interrupt causes and enables the interrupt.
2029  * It will be called once only during nic initialized.
2030  *
2031  * @param dev
2032  *  Pointer to struct rte_eth_dev.
2033  *
2034  * @return
2035  *  - On success, zero.
2036  *  - On failure, a negative value.
2037  */
2038 static int
2039 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2040 {
2041         struct ixgbe_interrupt *intr =
2042                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2043
2044         ixgbe_dev_link_status_print(dev);
2045         intr->mask |= IXGBE_EICR_LSC;
2046
2047         return 0;
2048 }
2049
2050 /*
2051  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2052  *
2053  * @param dev
2054  *  Pointer to struct rte_eth_dev.
2055  *
2056  * @return
2057  *  - On success, zero.
2058  *  - On failure, a negative value.
2059  */
2060 static int
2061 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2062 {
2063         uint32_t eicr;
2064         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065         struct ixgbe_interrupt *intr =
2066                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2067
2068         /* clear all cause mask */
2069         ixgbe_disable_intr(hw);
2070
2071         /* read-on-clear nic registers here */
2072         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2073         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2074
2075         intr->flags = 0;
2076         if (eicr & IXGBE_EICR_LSC) {
2077                 /* set flag for async link update */
2078                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2079         }
2080
2081         if (eicr & IXGBE_EICR_MAILBOX)
2082                 intr->flags |= IXGBE_FLAG_MAILBOX;
2083
2084         return 0;
2085 }
2086
2087 /**
2088  * It gets and then prints the link status.
2089  *
2090  * @param dev
2091  *  Pointer to struct rte_eth_dev.
2092  *
2093  * @return
2094  *  - On success, zero.
2095  *  - On failure, a negative value.
2096  */
2097 static void
2098 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2099 {
2100         struct rte_eth_link link;
2101
2102         memset(&link, 0, sizeof(link));
2103         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2104         if (link.link_status) {
2105                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2106                                         (int)(dev->data->port_id),
2107                                         (unsigned)link.link_speed,
2108                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2109                                         "full-duplex" : "half-duplex");
2110         } else {
2111                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2112                                 (int)(dev->data->port_id));
2113         }
2114         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2115                                 dev->pci_dev->addr.domain,
2116                                 dev->pci_dev->addr.bus,
2117                                 dev->pci_dev->addr.devid,
2118                                 dev->pci_dev->addr.function);
2119 }
2120
2121 /*
2122  * It executes link_update after knowing an interrupt occurred.
2123  *
2124  * @param dev
2125  *  Pointer to struct rte_eth_dev.
2126  *
2127  * @return
2128  *  - On success, zero.
2129  *  - On failure, a negative value.
2130  */
2131 static int
2132 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2133 {
2134         struct ixgbe_interrupt *intr =
2135                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2136         int64_t timeout;
2137         struct rte_eth_link link;
2138         int intr_enable_delay = false;
2139
2140         PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
2141
2142         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2143                 ixgbe_pf_mbx_process(dev);
2144                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2145         }
2146
2147         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2148                 /* get the link status before link update, for predicting later */
2149                 memset(&link, 0, sizeof(link));
2150                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2151
2152                 ixgbe_dev_link_update(dev, 0);
2153
2154                 /* likely to up */
2155                 if (!link.link_status)
2156                         /* handle it 1 sec later, wait it being stable */
2157                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2158                 /* likely to down */
2159                 else
2160                         /* handle it 4 sec later, wait it being stable */
2161                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2162
2163                 ixgbe_dev_link_status_print(dev);
2164
2165                 intr_enable_delay = true;
2166         }
2167
2168         if (intr_enable_delay) {
2169                 if (rte_eal_alarm_set(timeout * 1000,
2170                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2171                         PMD_DRV_LOG(ERR, "Error setting alarm");
2172         } else {
2173                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2174                 ixgbe_enable_intr(dev);
2175                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2176         }
2177
2178
2179         return 0;
2180 }
2181
2182 /**
2183  * Interrupt handler which shall be registered for alarm callback for delayed
2184  * handling specific interrupt to wait for the stable nic state. As the
2185  * NIC interrupt state is not stable for ixgbe after link is just down,
2186  * it needs to wait 4 seconds to get the stable status.
2187  *
2188  * @param handle
2189  *  Pointer to interrupt handle.
2190  * @param param
2191  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2192  *
2193  * @return
2194  *  void
2195  */
2196 static void
2197 ixgbe_dev_interrupt_delayed_handler(void *param)
2198 {
2199         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2200         struct ixgbe_interrupt *intr =
2201                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2202         struct ixgbe_hw *hw =
2203                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2204         uint32_t eicr;
2205
2206         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2207         if (eicr & IXGBE_EICR_MAILBOX)
2208                 ixgbe_pf_mbx_process(dev);
2209
2210         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2211                 ixgbe_dev_link_update(dev, 0);
2212                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2213                 ixgbe_dev_link_status_print(dev);
2214                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2215         }
2216
2217         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
2218         ixgbe_enable_intr(dev);
2219         rte_intr_enable(&(dev->pci_dev->intr_handle));
2220 }
2221
2222 /**
2223  * Interrupt handler triggered by NIC  for handling
2224  * specific interrupt.
2225  *
2226  * @param handle
2227  *  Pointer to interrupt handle.
2228  * @param param
2229  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2230  *
2231  * @return
2232  *  void
2233  */
2234 static void
2235 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2236                                                         void *param)
2237 {
2238         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2239         ixgbe_dev_interrupt_get_status(dev);
2240         ixgbe_dev_interrupt_action(dev);
2241 }
2242
2243 static int
2244 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2245 {
2246         struct ixgbe_hw *hw;
2247
2248         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2249         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2250 }
2251
2252 static int
2253 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2254 {
2255         struct ixgbe_hw *hw;
2256
2257         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2258         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2259 }
2260
2261 static int
2262 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2263 {
2264         struct ixgbe_hw *hw;
2265         int err;
2266         uint32_t rx_buf_size;
2267         uint32_t max_high_water;
2268         uint32_t mflcn;
2269         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2270                 ixgbe_fc_none,
2271                 ixgbe_fc_rx_pause,
2272                 ixgbe_fc_tx_pause,
2273                 ixgbe_fc_full
2274         };
2275
2276         PMD_INIT_FUNC_TRACE();
2277
2278         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2279         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2280         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2281
2282         /*
2283          * At least reserve one Ethernet frame for watermark
2284          * high_water/low_water in kilo bytes for ixgbe
2285          */
2286         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2287         if ((fc_conf->high_water > max_high_water) ||
2288                 (fc_conf->high_water < fc_conf->low_water)) {
2289                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2290                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2291                 return (-EINVAL);
2292         }
2293
2294         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2295         hw->fc.pause_time     = fc_conf->pause_time;
2296         hw->fc.high_water[0]  = fc_conf->high_water;
2297         hw->fc.low_water[0]   = fc_conf->low_water;
2298         hw->fc.send_xon       = fc_conf->send_xon;
2299
2300         err = ixgbe_fc_enable(hw);
2301
2302         /* Not negotiated is not an error case */
2303         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2304
2305                 /* check if we want to forward MAC frames - driver doesn't have native
2306                  * capability to do that, so we'll write the registers ourselves */
2307
2308                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2309
2310                 /* set or clear MFLCN.PMCF bit depending on configuration */
2311                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2312                         mflcn |= IXGBE_MFLCN_PMCF;
2313                 else
2314                         mflcn &= ~IXGBE_MFLCN_PMCF;
2315
2316                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2317                 IXGBE_WRITE_FLUSH(hw);
2318
2319                 return 0;
2320         }
2321
2322         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2323         return -EIO;
2324 }
2325
2326 /**
2327  *  ixgbe_pfc_enable_generic - Enable flow control
2328  *  @hw: pointer to hardware structure
2329  *  @tc_num: traffic class number
2330  *  Enable flow control according to the current settings.
2331  */
2332 static int
2333 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2334 {
2335         int ret_val = 0;
2336         uint32_t mflcn_reg, fccfg_reg;
2337         uint32_t reg;
2338         uint32_t fcrtl, fcrth;
2339         uint8_t i;
2340         uint8_t nb_rx_en;
2341
2342         /* Validate the water mark configuration */
2343         if (!hw->fc.pause_time) {
2344                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2345                 goto out;
2346         }
2347
2348         /* Low water mark of zero causes XOFF floods */
2349         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2350                  /* High/Low water can not be 0 */
2351                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2352                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2353                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2354                         goto out;
2355                 }
2356
2357                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2358                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2359                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2360                         goto out;
2361                 }
2362         }
2363         /* Negotiate the fc mode to use */
2364         ixgbe_fc_autoneg(hw);
2365
2366         /* Disable any previous flow control settings */
2367         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2368         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2369
2370         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2371         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2372
2373         switch (hw->fc.current_mode) {
2374         case ixgbe_fc_none:
2375                 /*
2376                  * If the count of enabled RX Priority Flow control >1,
2377                  * and the TX pause can not be disabled
2378                  */
2379                 nb_rx_en = 0;
2380                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2381                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2382                         if (reg & IXGBE_FCRTH_FCEN)
2383                                 nb_rx_en++;
2384                 }
2385                 if (nb_rx_en > 1)
2386                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2387                 break;
2388         case ixgbe_fc_rx_pause:
2389                 /*
2390                  * Rx Flow control is enabled and Tx Flow control is
2391                  * disabled by software override. Since there really
2392                  * isn't a way to advertise that we are capable of RX
2393                  * Pause ONLY, we will advertise that we support both
2394                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2395                  * disable the adapter's ability to send PAUSE frames.
2396                  */
2397                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2398                 /*
2399                  * If the count of enabled RX Priority Flow control >1,
2400                  * and the TX pause can not be disabled
2401                  */
2402                 nb_rx_en = 0;
2403                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2404                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2405                         if (reg & IXGBE_FCRTH_FCEN)
2406                                 nb_rx_en++;
2407                 }
2408                 if (nb_rx_en > 1)
2409                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2410                 break;
2411         case ixgbe_fc_tx_pause:
2412                 /*
2413                  * Tx Flow control is enabled, and Rx Flow control is
2414                  * disabled by software override.
2415                  */
2416                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2417                 break;
2418         case ixgbe_fc_full:
2419                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2420                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2421                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2422                 break;
2423         default:
2424                 DEBUGOUT("Flow control param set incorrectly\n");
2425                 ret_val = IXGBE_ERR_CONFIG;
2426                 goto out;
2427                 break;
2428         }
2429
2430         /* Set 802.3x based flow control settings. */
2431         mflcn_reg |= IXGBE_MFLCN_DPF;
2432         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2433         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2434
2435         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2436         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2437                 hw->fc.high_water[tc_num]) {
2438                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2439                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2440                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2441         } else {
2442                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2443                 /*
2444                  * In order to prevent Tx hangs when the internal Tx
2445                  * switch is enabled we must set the high water mark
2446                  * to the maximum FCRTH value.  This allows the Tx
2447                  * switch to function even under heavy Rx workloads.
2448                  */
2449                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2450         }
2451         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2452
2453         /* Configure pause time (2 TCs per register) */
2454         reg = hw->fc.pause_time * 0x00010001;
2455         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2456                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2457
2458         /* Configure flow control refresh threshold value */
2459         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2460
2461 out:
2462         return ret_val;
2463 }
2464
2465 static int
2466 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2467 {
2468         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2470
2471         if(hw->mac.type != ixgbe_mac_82598EB) {
2472                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2473         }
2474         return ret_val;
2475 }
2476
2477 static int
2478 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2479 {
2480         int err;
2481         uint32_t rx_buf_size;
2482         uint32_t max_high_water;
2483         uint8_t tc_num;
2484         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2485         struct ixgbe_hw *hw =
2486                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487         struct ixgbe_dcb_config *dcb_config =
2488                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2489
2490         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2491                 ixgbe_fc_none,
2492                 ixgbe_fc_rx_pause,
2493                 ixgbe_fc_tx_pause,
2494                 ixgbe_fc_full
2495         };
2496
2497         PMD_INIT_FUNC_TRACE();
2498
2499         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2500         tc_num = map[pfc_conf->priority];
2501         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2502         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2503         /*
2504          * At least reserve one Ethernet frame for watermark
2505          * high_water/low_water in kilo bytes for ixgbe
2506          */
2507         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2508         if ((pfc_conf->fc.high_water > max_high_water) ||
2509                 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2510                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2511                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2512                 return (-EINVAL);
2513         }
2514
2515         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2516         hw->fc.pause_time = pfc_conf->fc.pause_time;
2517         hw->fc.send_xon = pfc_conf->fc.send_xon;
2518         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2519         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2520
2521         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2522
2523         /* Not negotiated is not an error case */
2524         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2525                 return 0;
2526
2527         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2528         return -EIO;
2529 }
2530
2531 static int
2532 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2533                                 struct rte_eth_rss_reta *reta_conf)
2534 {
2535         uint8_t i,j,mask;
2536         uint32_t reta;
2537         struct ixgbe_hw *hw =
2538                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539
2540         PMD_INIT_FUNC_TRACE();
2541         /*
2542         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2543         * 128-entries in 32 registers
2544          */
2545         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2546                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2547                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2548                 else
2549                         mask = (uint8_t)((reta_conf->mask_hi >>
2550                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2551                 if (mask != 0) {
2552                         reta = 0;
2553                         if (mask != 0xF)
2554                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2555
2556                         for (j = 0; j < 4; j++) {
2557                                 if (mask & (0x1 << j)) {
2558                                         if (mask != 0xF)
2559                                                 reta &= ~(0xFF << 8 * j);
2560                                         reta |= reta_conf->reta[i + j] << 8*j;
2561                                 }
2562                         }
2563                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2564                 }
2565         }
2566
2567         return 0;
2568 }
2569
2570 static int
2571 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2572                                 struct rte_eth_rss_reta *reta_conf)
2573 {
2574         uint8_t i,j,mask;
2575         uint32_t reta;
2576         struct ixgbe_hw *hw =
2577                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578
2579         PMD_INIT_FUNC_TRACE();
2580         /*
2581          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2582          * 128-entries in 32 registers
2583          */
2584         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2585                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2586                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2587                 else
2588                         mask = (uint8_t)((reta_conf->mask_hi >>
2589                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2590
2591                 if (mask != 0) {
2592                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2593                         for (j = 0; j < 4; j++) {
2594                                 if (mask & (0x1 << j))
2595                                         reta_conf->reta[i + j] =
2596                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2597                         }
2598                 }
2599         }
2600
2601         return 0;
2602 }
2603
2604 static void
2605 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2606                                 uint32_t index, uint32_t pool)
2607 {
2608         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2609         uint32_t enable_addr = 1;
2610
2611         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2612 }
2613
2614 static void
2615 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2616 {
2617         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2618
2619         ixgbe_clear_rar(hw, index);
2620 }
2621
2622 /*
2623  * Virtual Function operations
2624  */
2625 static void
2626 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2627 {
2628         PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2629
2630         /* Clear interrupt mask to stop from interrupts being generated */
2631         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2632
2633         IXGBE_WRITE_FLUSH(hw);
2634 }
2635
2636 static int
2637 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2638 {
2639         struct rte_eth_conf* conf = &dev->data->dev_conf;
2640
2641         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2642                 dev->data->port_id);
2643
2644         /*
2645          * VF has no ability to enable/disable HW CRC
2646          * Keep the persistent behavior the same as Host PF
2647          */
2648 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2649         if (!conf->rxmode.hw_strip_crc) {
2650                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2651                 conf->rxmode.hw_strip_crc = 1;
2652         }
2653 #else
2654         if (conf->rxmode.hw_strip_crc) {
2655                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2656                 conf->rxmode.hw_strip_crc = 0;
2657         }
2658 #endif
2659
2660         return 0;
2661 }
2662
2663 static int
2664 ixgbevf_dev_start(struct rte_eth_dev *dev)
2665 {
2666         struct ixgbe_hw *hw =
2667                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2668         int err, mask = 0;
2669
2670         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2671
2672         hw->mac.ops.reset_hw(hw);
2673
2674         /* negotiate mailbox API version to use with the PF. */
2675         ixgbevf_negotiate_api(hw);
2676
2677         ixgbevf_dev_tx_init(dev);
2678
2679         /* This can fail when allocating mbufs for descriptor rings */
2680         err = ixgbevf_dev_rx_init(dev);
2681         if (err) {
2682                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2683                 ixgbe_dev_clear_queues(dev);
2684                 return err;
2685         }
2686
2687         /* Set vfta */
2688         ixgbevf_set_vfta_all(dev,1);
2689
2690         /* Set HW strip */
2691         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2692                 ETH_VLAN_EXTEND_MASK;
2693         ixgbevf_vlan_offload_set(dev, mask);
2694
2695         ixgbevf_dev_rxtx_start(dev);
2696
2697         return 0;
2698 }
2699
2700 static void
2701 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2702 {
2703         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704
2705         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2706
2707         hw->adapter_stopped = TRUE;
2708         ixgbe_stop_adapter(hw);
2709
2710         /*
2711           * Clear what we set, but we still keep shadow_vfta to
2712           * restore after device starts
2713           */
2714         ixgbevf_set_vfta_all(dev,0);
2715
2716         ixgbe_dev_clear_queues(dev);
2717 }
2718
2719 static void
2720 ixgbevf_dev_close(struct rte_eth_dev *dev)
2721 {
2722         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2723
2724         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2725
2726         ixgbe_reset_hw(hw);
2727
2728         ixgbevf_dev_stop(dev);
2729
2730         /* reprogram the RAR[0] in case user changed it. */
2731         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2732 }
2733
2734 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2735 {
2736         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2737         struct ixgbe_vfta * shadow_vfta =
2738                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2739         int i = 0, j = 0, vfta = 0, mask = 1;
2740
2741         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2742                 vfta = shadow_vfta->vfta[i];
2743                 if(vfta){
2744                         mask = 1;
2745                         for (j = 0; j < 32; j++){
2746                                 if(vfta & mask)
2747                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2748                                 mask<<=1;
2749                         }
2750                 }
2751         }
2752
2753 }
2754
2755 static int
2756 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2757 {
2758         struct ixgbe_hw *hw =
2759                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2760         struct ixgbe_vfta * shadow_vfta =
2761                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2762         uint32_t vid_idx = 0;
2763         uint32_t vid_bit = 0;
2764         int ret = 0;
2765
2766         PMD_INIT_FUNC_TRACE();
2767
2768         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2769         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2770         if(ret){
2771                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2772                 return ret;
2773         }
2774         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2775         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2776
2777         /* Save what we set and retore it after device reset */
2778         if (on)
2779                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2780         else
2781                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2782
2783         return 0;
2784 }
2785
2786 static void
2787 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2788 {
2789         struct ixgbe_hw *hw =
2790                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2791         uint32_t ctrl;
2792
2793         PMD_INIT_FUNC_TRACE();
2794
2795         if(queue >= hw->mac.max_rx_queues)
2796                 return;
2797
2798         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2799         if(on)
2800                 ctrl |= IXGBE_RXDCTL_VME;
2801         else
2802                 ctrl &= ~IXGBE_RXDCTL_VME;
2803         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2804
2805         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2806 }
2807
2808 static void
2809 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2810 {
2811         struct ixgbe_hw *hw =
2812                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2813         uint16_t i;
2814         int on = 0;
2815
2816         /* VF function only support hw strip feature, others are not support */
2817         if(mask & ETH_VLAN_STRIP_MASK){
2818                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2819
2820                 for(i=0; i < hw->mac.max_rx_queues; i++)
2821                         ixgbevf_vlan_strip_queue_set(dev,i,on);
2822         }
2823 }
2824
2825 static int
2826 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2827 {
2828         uint32_t reg_val;
2829
2830         /* we only need to do this if VMDq is enabled */
2831         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2832         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2833                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2834                 return (-1);
2835         }
2836
2837         return 0;
2838 }
2839
2840 static uint32_t
2841 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2842 {
2843         uint32_t vector = 0;
2844         switch (hw->mac.mc_filter_type) {
2845         case 0:   /* use bits [47:36] of the address */
2846                 vector = ((uc_addr->addr_bytes[4] >> 4) |
2847                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2848                 break;
2849         case 1:   /* use bits [46:35] of the address */
2850                 vector = ((uc_addr->addr_bytes[4] >> 3) |
2851                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2852                 break;
2853         case 2:   /* use bits [45:34] of the address */
2854                 vector = ((uc_addr->addr_bytes[4] >> 2) |
2855                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2856                 break;
2857         case 3:   /* use bits [43:32] of the address */
2858                 vector = ((uc_addr->addr_bytes[4]) |
2859                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2860                 break;
2861         default:  /* Invalid mc_filter_type */
2862                 break;
2863         }
2864
2865         /* vector can only be 12-bits or boundary will be exceeded */
2866         vector &= 0xFFF;
2867         return vector;
2868 }
2869
2870 static int
2871 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
2872                                uint8_t on)
2873 {
2874         uint32_t vector;
2875         uint32_t uta_idx;
2876         uint32_t reg_val;
2877         uint32_t uta_shift;
2878         uint32_t rc;
2879         const uint32_t ixgbe_uta_idx_mask = 0x7F;
2880         const uint32_t ixgbe_uta_bit_shift = 5;
2881         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
2882         const uint32_t bit1 = 0x1;
2883
2884         struct ixgbe_hw *hw =
2885                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2886         struct ixgbe_uta_info *uta_info =
2887                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2888
2889         /* The UTA table only exists on 82599 hardware and newer */
2890         if (hw->mac.type < ixgbe_mac_82599EB)
2891                 return (-ENOTSUP);
2892
2893         vector = ixgbe_uta_vector(hw,mac_addr);
2894         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
2895         uta_shift = vector & ixgbe_uta_bit_mask;
2896
2897         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
2898         if(rc == on)
2899                 return 0;
2900
2901         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
2902         if (on) {
2903                 uta_info->uta_in_use++;
2904                 reg_val |= (bit1 << uta_shift);
2905                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
2906         } else {
2907                 uta_info->uta_in_use--;
2908                 reg_val &= ~(bit1 << uta_shift);
2909                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
2910         }
2911
2912         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
2913
2914         if (uta_info->uta_in_use > 0)
2915                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2916                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2917         else
2918                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
2919
2920         return 0;
2921 }
2922
2923 static int
2924 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
2925 {
2926         int i;
2927         struct ixgbe_hw *hw =
2928                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2929         struct ixgbe_uta_info *uta_info =
2930                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2931
2932         /* The UTA table only exists on 82599 hardware and newer */
2933         if (hw->mac.type < ixgbe_mac_82599EB)
2934                 return (-ENOTSUP);
2935
2936         if(on) {
2937                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2938                         uta_info->uta_shadow[i] = ~0;
2939                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2940                 }
2941         } else {
2942                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2943                         uta_info->uta_shadow[i] = 0;
2944                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2945                 }
2946         }
2947         return 0;
2948
2949 }
2950 static int
2951 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
2952                                uint16_t rx_mask, uint8_t on)
2953 {
2954         int val = 0;
2955
2956         struct ixgbe_hw *hw =
2957                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2958         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
2959
2960         if (hw->mac.type == ixgbe_mac_82598EB) {
2961                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
2962                         " on 82599 hardware and newer\n");
2963                 return (-ENOTSUP);
2964         }
2965         if (ixgbe_vmdq_mode_check(hw) < 0)
2966                 return (-ENOTSUP);
2967
2968         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
2969                 val |= IXGBE_VMOLR_AUPE;
2970         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
2971                 val |= IXGBE_VMOLR_ROMPE;
2972         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
2973                 val |= IXGBE_VMOLR_ROPE;
2974         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
2975                 val |= IXGBE_VMOLR_BAM;
2976         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
2977                 val |= IXGBE_VMOLR_MPE;
2978
2979         if (on)
2980                 vmolr |= val;
2981         else
2982                 vmolr &= ~val;
2983
2984         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
2985
2986         return 0;
2987 }
2988
2989 static int
2990 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2991 {
2992         uint32_t reg,addr;
2993         uint32_t val;
2994         const uint8_t bit1 = 0x1;
2995
2996         struct ixgbe_hw *hw =
2997                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2998
2999         if (ixgbe_vmdq_mode_check(hw) < 0)
3000                 return (-ENOTSUP);
3001
3002         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3003         reg = IXGBE_READ_REG(hw, addr);
3004         val = bit1 << pool;
3005
3006         if (on)
3007                 reg |= val;
3008         else
3009                 reg &= ~val;
3010
3011         IXGBE_WRITE_REG(hw, addr,reg);
3012
3013         return 0;
3014 }
3015
3016 static int
3017 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3018 {
3019         uint32_t reg,addr;
3020         uint32_t val;
3021         const uint8_t bit1 = 0x1;
3022
3023         struct ixgbe_hw *hw =
3024                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3025
3026         if (ixgbe_vmdq_mode_check(hw) < 0)
3027                 return (-ENOTSUP);
3028
3029         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3030         reg = IXGBE_READ_REG(hw, addr);
3031         val = bit1 << pool;
3032
3033         if (on)
3034                 reg |= val;
3035         else
3036                 reg &= ~val;
3037
3038         IXGBE_WRITE_REG(hw, addr,reg);
3039
3040         return 0;
3041 }
3042
3043 static int
3044 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3045                         uint64_t pool_mask, uint8_t vlan_on)
3046 {
3047         int ret = 0;
3048         uint16_t pool_idx;
3049         struct ixgbe_hw *hw =
3050                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3051
3052         if (ixgbe_vmdq_mode_check(hw) < 0)
3053                 return (-ENOTSUP);
3054         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3055                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3056                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3057                         if (ret < 0)
3058                                 return ret;
3059         }
3060
3061         return ret;
3062 }
3063
3064 static int
3065 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3066                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3067                         uint8_t rule_id, uint8_t on)
3068 {
3069         uint32_t mr_ctl,vlvf;
3070         uint32_t mp_lsb = 0;
3071         uint32_t mv_msb = 0;
3072         uint32_t mv_lsb = 0;
3073         uint32_t mp_msb = 0;
3074         uint8_t i = 0;
3075         int reg_index = 0;
3076         uint64_t vlan_mask = 0;
3077
3078         const uint8_t pool_mask_offset = 32;
3079         const uint8_t vlan_mask_offset = 32;
3080         const uint8_t dst_pool_offset = 8;
3081         const uint8_t rule_mr_offset  = 4;
3082         const uint8_t mirror_rule_mask= 0x0F;
3083
3084         struct ixgbe_mirror_info *mr_info =
3085                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3086         struct ixgbe_hw *hw =
3087                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3088
3089         if (ixgbe_vmdq_mode_check(hw) < 0)
3090                 return (-ENOTSUP);
3091
3092         /* Check if vlan mask is valid */
3093         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3094                 if (mirror_conf->vlan.vlan_mask == 0)
3095                         return (-EINVAL);
3096         }
3097
3098         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3099         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3100                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3101                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3102                                 /* search vlan id related pool vlan filter index */
3103                                 reg_index = ixgbe_find_vlvf_slot(hw,
3104                                                 mirror_conf->vlan.vlan_id[i]);
3105                                 if(reg_index < 0)
3106                                         return (-EINVAL);
3107                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3108                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3109                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3110                                                 == mirror_conf->vlan.vlan_id[i]))
3111                                         vlan_mask |= (1ULL << reg_index);
3112                                 else
3113                                         return (-EINVAL);
3114                         }
3115                 }
3116
3117                 if (on) {
3118                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3119                         mv_msb = vlan_mask >> vlan_mask_offset;
3120
3121                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3122                                                 mirror_conf->vlan.vlan_mask;
3123                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3124                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3125                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3126                                                 mirror_conf->vlan.vlan_id[i];
3127                         }
3128                 } else {
3129                         mv_lsb = 0;
3130                         mv_msb = 0;
3131                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3132                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3133                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3134                 }
3135         }
3136
3137         /*
3138          * if enable pool mirror, write related pool mask register,if disable
3139          * pool mirror, clear PFMRVM register
3140          */
3141         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3142                 if (on) {
3143                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3144                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3145                         mr_info->mr_conf[rule_id].pool_mask =
3146                                         mirror_conf->pool_mask;
3147
3148                 } else {
3149                         mp_lsb = 0;
3150                         mp_msb = 0;
3151                         mr_info->mr_conf[rule_id].pool_mask = 0;
3152                 }
3153         }
3154
3155         /* read  mirror control register and recalculate it */
3156         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3157
3158         if (on) {
3159                 mr_ctl |= mirror_conf->rule_type_mask;
3160                 mr_ctl &= mirror_rule_mask;
3161                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3162         } else
3163                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3164
3165         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3166         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3167
3168         /* write mirrror control  register */
3169         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3170
3171         /* write pool mirrror control  register */
3172         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3173                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3174                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3175                                 mp_msb);
3176         }
3177         /* write VLAN mirrror control  register */
3178         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3179                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3180                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3181                                 mv_msb);
3182         }
3183
3184         return 0;
3185 }
3186
3187 static int
3188 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3189 {
3190         int mr_ctl = 0;
3191         uint32_t lsb_val = 0;
3192         uint32_t msb_val = 0;
3193         const uint8_t rule_mr_offset = 4;
3194
3195         struct ixgbe_hw *hw =
3196                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3197         struct ixgbe_mirror_info *mr_info =
3198                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3199
3200         if (ixgbe_vmdq_mode_check(hw) < 0)
3201                 return (-ENOTSUP);
3202
3203         memset(&mr_info->mr_conf[rule_id], 0,
3204                 sizeof(struct rte_eth_vmdq_mirror_conf));
3205
3206         /* clear PFVMCTL register */
3207         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3208
3209         /* clear pool mask register */
3210         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3211         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3212
3213         /* clear vlan mask register */
3214         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3215         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3216
3217         return 0;
3218 }
3219
3220 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3221         uint16_t queue_idx, uint16_t tx_rate)
3222 {
3223         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3224         uint32_t rf_dec, rf_int;
3225         uint32_t bcnrc_val;
3226         uint16_t link_speed = dev->data->dev_link.link_speed;
3227
3228         if (queue_idx >= hw->mac.max_tx_queues)
3229                 return -EINVAL;
3230
3231         if (tx_rate != 0) {
3232                 /* Calculate the rate factor values to set */
3233                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3234                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3235                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3236
3237                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3238                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3239                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3240                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3241         } else {
3242                 bcnrc_val = 0;
3243         }
3244
3245         /*
3246          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3247          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3248          * set as 0x4.
3249          */
3250         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3251                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3252                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3253                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3254                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3255         else
3256                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3257                         IXGBE_MMW_SIZE_DEFAULT);
3258
3259         /* Set RTTBCNRC of queue X */
3260         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3261         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3262         IXGBE_WRITE_FLUSH(hw);
3263
3264         return 0;
3265 }
3266
3267 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3268         uint16_t tx_rate, uint64_t q_msk)
3269 {
3270         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3271         struct ixgbe_vf_info *vfinfo =
3272                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3273         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3274         uint32_t queue_stride =
3275                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3276         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3277         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3278         uint16_t total_rate = 0;
3279
3280         if (queue_end >= hw->mac.max_tx_queues)
3281                 return -EINVAL;
3282
3283         if (vfinfo != NULL) {
3284                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3285                         if (vf_idx == vf)
3286                                 continue;
3287                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3288                                 idx++)
3289                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3290                 }
3291         } else
3292                 return -EINVAL;
3293
3294         /* Store tx_rate for this vf. */
3295         for (idx = 0; idx < nb_q_per_pool; idx++) {
3296                 if (((uint64_t)0x1 << idx) & q_msk) {
3297                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3298                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3299                         total_rate += tx_rate;
3300                 }
3301         }
3302
3303         if (total_rate > dev->data->dev_link.link_speed) {
3304                 /*
3305                  * Reset stored TX rate of the VF if it causes exceed
3306                  * link speed.
3307                  */
3308                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3309                 return -EINVAL;
3310         }
3311
3312         /* Set RTTBCNRC of each queue/pool for vf X  */
3313         for (; queue_idx <= queue_end; queue_idx++) {
3314                 if (0x1 & q_msk)
3315                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3316                 q_msk = q_msk >> 1;
3317         }
3318
3319         return 0;
3320 }
3321
3322 static void
3323 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3324                      __attribute__((unused)) uint32_t index,
3325                      __attribute__((unused)) uint32_t pool)
3326 {
3327         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3328         int diag;
3329
3330         /*
3331          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3332          * operation. Trap this case to avoid exhausting the [very limited]
3333          * set of PF resources used to store VF MAC addresses.
3334          */
3335         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3336                 return;
3337         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3338         if (diag == 0)
3339                 return;
3340         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3341 }
3342
3343 static void
3344 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3345 {
3346         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3347         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3348         struct ether_addr *mac_addr;
3349         uint32_t i;
3350         int diag;
3351
3352         /*
3353          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3354          * not support the deletion of a given MAC address.
3355          * Instead, it imposes to delete all MAC addresses, then to add again
3356          * all MAC addresses with the exception of the one to be deleted.
3357          */
3358         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3359
3360         /*
3361          * Add again all MAC addresses, with the exception of the deleted one
3362          * and of the permanent MAC address.
3363          */
3364         for (i = 0, mac_addr = dev->data->mac_addrs;
3365              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3366                 /* Skip the deleted MAC address */
3367                 if (i == index)
3368                         continue;
3369                 /* Skip NULL MAC addresses */
3370                 if (is_zero_ether_addr(mac_addr))
3371                         continue;
3372                 /* Skip the permanent MAC address */
3373                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3374                         continue;
3375                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3376                 if (diag != 0)
3377                         PMD_DRV_LOG(ERR,
3378                                     "Adding again MAC address "
3379                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3380                                     "diag=%d",
3381                                     mac_addr->addr_bytes[0],
3382                                     mac_addr->addr_bytes[1],
3383                                     mac_addr->addr_bytes[2],
3384                                     mac_addr->addr_bytes[3],
3385                                     mac_addr->addr_bytes[4],
3386                                     mac_addr->addr_bytes[5],
3387                                     diag);
3388         }
3389 }
3390
3391 static struct rte_driver rte_ixgbe_driver = {
3392         .type = PMD_PDEV,
3393         .init = rte_ixgbe_pmd_init,
3394 };
3395
3396 static struct rte_driver rte_ixgbevf_driver = {
3397         .type = PMD_PDEV,
3398         .init = rte_ixgbevf_pmd_init,
3399 };
3400
3401 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
3402 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);