lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72
  73 /*
  74  * High threshold controlling when to start sending XOFF frames. Must be at
  75  * least 8 bytes less than receive packet buffer size. This value is in units
  76  * of 1024 bytes.
  77  */
  78 #define IXGBE_FC_HI    0x80
  79
  80 /*
  81  * Low threshold controlling when to start sending XON frames. This value is
  82  * in units of 1024 bytes.
  83  */
  84 #define IXGBE_FC_LO    0x40
  85
  86 /* Timer value included in XOFF frames. */
  87 #define IXGBE_FC_PAUSE 0x680
  88
  89 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  90 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  91 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  92
  93 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  94 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  95
  96 /*
  97  *  Default values for RX/TX configuration
  98  */
  99 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 100 #define IXGBE_DEFAULT_RX_PTHRESH      8
 101 #define IXGBE_DEFAULT_RX_HTHRESH      8
 102 #define IXGBE_DEFAULT_RX_WTHRESH      0
 103
 104 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 105 #define IXGBE_DEFAULT_TX_PTHRESH      32
 106 #define IXGBE_DEFAULT_TX_HTHRESH      0
 107 #define IXGBE_DEFAULT_TX_WTHRESH      0
 108 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 109
 110 /* Bit shift and mask */
 111 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 112 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 113 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 114 #define IXGBE_8_BIT_MASK   UINT8_MAX
 115
 116 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 117
 118 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 119
 120 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 121 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 122 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 123 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 124 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 125 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 126 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 127 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 128 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 129 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 130 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 131 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 132                                 int wait_to_complete);
 133 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 134                                 struct rte_eth_stats *stats);
 135 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 136 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 137                                              uint16_t queue_id,
 138                                              uint8_t stat_idx,
 139                                              uint8_t is_rx);
 140 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 141                                struct rte_eth_dev_info *dev_info);
 142 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 143                                  struct rte_eth_dev_info *dev_info);
 144 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 145
 146 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 147                 uint16_t vlan_id, int on);
 148 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 149 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 150                 uint16_t queue, bool on);
 151 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 152                 int on);
 153 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 154 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 155 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 156 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 157 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 158
 159 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 160 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 161 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 162                                struct rte_eth_fc_conf *fc_conf);
 163 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 164                                struct rte_eth_fc_conf *fc_conf);
 165 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 166                 struct rte_eth_pfc_conf *pfc_conf);
 167 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 168                         struct rte_eth_rss_reta_entry64 *reta_conf,
 169                         uint16_t reta_size);
 170 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 171                         struct rte_eth_rss_reta_entry64 *reta_conf,
 172                         uint16_t reta_size);
 173 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 174 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 178                 void *param);
 179 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 180 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 181                 uint32_t index, uint32_t pool);
 182 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 183 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 184
 185 /* For Virtual Function support */
 186 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 187 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 188 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 189 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 190 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 191 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 192 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 193                 struct rte_eth_stats *stats);
 194 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 195 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 196                 uint16_t vlan_id, int on);
 197 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, int on);
 199 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 200 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 201
 202 /* For Eth VMDQ APIs support */
 203 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 204                 ether_addr* mac_addr,uint8_t on);
 205 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 206 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 207                 uint16_t rx_mask, uint8_t on);
 208 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 209 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 210 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 211                 uint64_t pool_mask,uint8_t vlan_on);
 212 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 213                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 214                 uint8_t rule_id, uint8_t on);
 215 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 216                 uint8_t rule_id);
 217
 218 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 219                 uint16_t queue_idx, uint16_t tx_rate);
 220 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 221                 uint16_t tx_rate, uint64_t q_msk);
 222
 223 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 224                                  struct ether_addr *mac_addr,
 225                                  uint32_t index, uint32_t pool);
 226 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 227 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 228                         struct rte_eth_syn_filter *filter,
 229                         bool add);
 230 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 231                         struct rte_eth_syn_filter *filter);
 232 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 233                         enum rte_filter_op filter_op,
 234                         void *arg);
 235 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 236                         struct ixgbe_5tuple_filter *filter);
 237 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 238                         struct ixgbe_5tuple_filter *filter);
 239 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 240                         struct rte_eth_ntuple_filter *filter,
 241                         bool add);
 242 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 243                                 enum rte_filter_op filter_op,
 244                                 void *arg);
 245 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 246                         struct rte_eth_ntuple_filter *filter);
 247 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 248                         struct rte_eth_ethertype_filter *filter,
 249                         bool add);
 250 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 251                                 enum rte_filter_op filter_op,
 252                                 void *arg);
 253 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 254                         struct rte_eth_ethertype_filter *filter);
 255 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 256                      enum rte_filter_type filter_type,
 257                      enum rte_filter_op filter_op,
 258                      void *arg);
 259 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 260
 261 /*
 262  * Define VF Stats MACRO for Non "cleared on read" register
 263  */
 264 #define UPDATE_VF_STAT(reg, last, cur)                          \
 265 {                                                               \
 266         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 267         cur += latest - last;                                   \
 268         last = latest;                                          \
 269 }
 270
 271 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 272 {                                                                \
 273         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 274         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 275         u64 latest = ((new_msb << 32) | new_lsb);                \
 276         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 277         last = latest;                                           \
 278 }
 279
 280 #define IXGBE_SET_HWSTRIP(h, q) do{\
 281                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 282                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 283                 (h)->bitmap[idx] |= 1 << bit;\
 284         }while(0)
 285
 286 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 287                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 288                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 289                 (h)->bitmap[idx] &= ~(1 << bit);\
 290         }while(0)
 291
 292 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 293                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 294                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 295                 (r) = (h)->bitmap[idx] >> bit & 1;\
 296         }while(0)
 297
 298 /*
 299  * The set of PCI devices this driver supports
 300  */
 301 static struct rte_pci_id pci_id_ixgbe_map[] = {
 302
 303 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 304 #include "rte_pci_dev_ids.h"
 305
 306 { .vendor_id = 0, /* sentinel */ },
 307 };
 308
 309
 310 /*
 311  * The set of PCI devices this driver supports (for 82599 VF)
 312  */
 313 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 314
 315 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 316 #include "rte_pci_dev_ids.h"
 317 { .vendor_id = 0, /* sentinel */ },
 318
 319 };
 320
 321 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 322         .dev_configure        = ixgbe_dev_configure,
 323         .dev_start            = ixgbe_dev_start,
 324         .dev_stop             = ixgbe_dev_stop,
 325         .dev_set_link_up    = ixgbe_dev_set_link_up,
 326         .dev_set_link_down  = ixgbe_dev_set_link_down,
 327         .dev_close            = ixgbe_dev_close,
 328         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 329         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 330         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 331         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 332         .link_update          = ixgbe_dev_link_update,
 333         .stats_get            = ixgbe_dev_stats_get,
 334         .stats_reset          = ixgbe_dev_stats_reset,
 335         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 336         .dev_infos_get        = ixgbe_dev_info_get,
 337         .mtu_set              = ixgbe_dev_mtu_set,
 338         .vlan_filter_set      = ixgbe_vlan_filter_set,
 339         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 340         .vlan_offload_set     = ixgbe_vlan_offload_set,
 341         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 342         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 343         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 344         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 345         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 346         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 347         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 348         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 349         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 350         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 351         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 352         .dev_led_on           = ixgbe_dev_led_on,
 353         .dev_led_off          = ixgbe_dev_led_off,
 354         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 355         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 356         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 357         .mac_addr_add         = ixgbe_add_rar,
 358         .mac_addr_remove      = ixgbe_remove_rar,
 359         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 360         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 361         .mirror_rule_set      = ixgbe_mirror_rule_set,
 362         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 363         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 364         .set_vf_rx            = ixgbe_set_pool_rx,
 365         .set_vf_tx            = ixgbe_set_pool_tx,
 366         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 367         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 368         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 369         .reta_update          = ixgbe_dev_rss_reta_update,
 370         .reta_query           = ixgbe_dev_rss_reta_query,
 371 #ifdef RTE_NIC_BYPASS
 372         .bypass_init          = ixgbe_bypass_init,
 373         .bypass_state_set     = ixgbe_bypass_state_store,
 374         .bypass_state_show    = ixgbe_bypass_state_show,
 375         .bypass_event_set     = ixgbe_bypass_event_store,
 376         .bypass_event_show    = ixgbe_bypass_event_show,
 377         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 378         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 379         .bypass_ver_show      = ixgbe_bypass_ver_show,
 380         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 381 #endif /* RTE_NIC_BYPASS */
 382         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 383         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 384         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 385 };
 386
 387 /*
 388  * dev_ops for virtual function, bare necessities for basic vf
 389  * operation have been implemented
 390  */
 391 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 392
 393         .dev_configure        = ixgbevf_dev_configure,
 394         .dev_start            = ixgbevf_dev_start,
 395         .dev_stop             = ixgbevf_dev_stop,
 396         .link_update          = ixgbe_dev_link_update,
 397         .stats_get            = ixgbevf_dev_stats_get,
 398         .stats_reset          = ixgbevf_dev_stats_reset,
 399         .dev_close            = ixgbevf_dev_close,
 400         .dev_infos_get        = ixgbevf_dev_info_get,
 401         .mtu_set              = ixgbevf_dev_set_mtu,
 402         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 403         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 404         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 405         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 406         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 407         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 408         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 409         .mac_addr_add         = ixgbevf_add_mac_addr,
 410         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 411 };
 412
 413 /**
 414  * Atomically reads the link status information from global
 415  * structure rte_eth_dev.
 416  *
 417  * @param dev
 418  *   - Pointer to the structure rte_eth_dev to read from.
 419  *   - Pointer to the buffer to be saved with the link status.
 420  *
 421  * @return
 422  *   - On success, zero.
 423  *   - On failure, negative value.
 424  */
 425 static inline int
 426 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 427                                 struct rte_eth_link *link)
 428 {
 429         struct rte_eth_link *dst = link;
 430         struct rte_eth_link *src = &(dev->data->dev_link);
 431
 432         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 433                                         *(uint64_t *)src) == 0)
 434                 return -1;
 435
 436         return 0;
 437 }
 438
 439 /**
 440  * Atomically writes the link status information into global
 441  * structure rte_eth_dev.
 442  *
 443  * @param dev
 444  *   - Pointer to the structure rte_eth_dev to read from.
 445  *   - Pointer to the buffer to be saved with the link status.
 446  *
 447  * @return
 448  *   - On success, zero.
 449  *   - On failure, negative value.
 450  */
 451 static inline int
 452 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 453                                 struct rte_eth_link *link)
 454 {
 455         struct rte_eth_link *dst = &(dev->data->dev_link);
 456         struct rte_eth_link *src = link;
 457
 458         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 459                                         *(uint64_t *)src) == 0)
 460                 return -1;
 461
 462         return 0;
 463 }
 464
 465 /*
 466  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 467  */
 468 static inline int
 469 ixgbe_is_sfp(struct ixgbe_hw *hw)
 470 {
 471         switch (hw->phy.type) {
 472         case ixgbe_phy_sfp_avago:
 473         case ixgbe_phy_sfp_ftl:
 474         case ixgbe_phy_sfp_intel:
 475         case ixgbe_phy_sfp_unknown:
 476         case ixgbe_phy_sfp_passive_tyco:
 477         case ixgbe_phy_sfp_passive_unknown:
 478                 return 1;
 479         default:
 480                 return 0;
 481         }
 482 }
 483
 484 static inline int32_t
 485 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 486 {
 487         uint32_t ctrl_ext;
 488         int32_t status;
 489
 490         status = ixgbe_reset_hw(hw);
 491
 492         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 493         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 494         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 495         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 496         IXGBE_WRITE_FLUSH(hw);
 497
 498         return status;
 499 }
 500
 501 static inline void
 502 ixgbe_enable_intr(struct rte_eth_dev *dev)
 503 {
 504         struct ixgbe_interrupt *intr =
 505                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 506         struct ixgbe_hw *hw =
 507                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 508
 509         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 510         IXGBE_WRITE_FLUSH(hw);
 511 }
 512
 513 /*
 514  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 515  */
 516 static void
 517 ixgbe_disable_intr(struct ixgbe_hw *hw)
 518 {
 519         PMD_INIT_FUNC_TRACE();
 520
 521         if (hw->mac.type == ixgbe_mac_82598EB) {
 522                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 523         } else {
 524                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 525                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 526                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 527         }
 528         IXGBE_WRITE_FLUSH(hw);
 529 }
 530
 531 /*
 532  * This function resets queue statistics mapping registers.
 533  * From Niantic datasheet, Initialization of Statistics section:
 534  * "...if software requires the queue counters, the RQSMR and TQSM registers
 535  * must be re-programmed following a device reset.
 536  */
 537 static void
 538 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 539 {
 540         uint32_t i;
 541
 542         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 543                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 544                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 545         }
 546 }
 547
 548
 549 static int
 550 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 551                                   uint16_t queue_id,
 552                                   uint8_t stat_idx,
 553                                   uint8_t is_rx)
 554 {
 555 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 556 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 557 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 558
 559         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 560         struct ixgbe_stat_mapping_registers *stat_mappings =
 561                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 562         uint32_t qsmr_mask = 0;
 563         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 564         uint32_t q_map;
 565         uint8_t n, offset;
 566
 567         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 568                 (hw->mac.type != ixgbe_mac_X540) &&
 569                 (hw->mac.type != ixgbe_mac_X550) &&
 570                 (hw->mac.type != ixgbe_mac_X550EM_x))
 571                 return -ENOSYS;
 572
 573         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 574                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 575                      queue_id, stat_idx);
 576
 577         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 578         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 579                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 580                 return -EIO;
 581         }
 582         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 583
 584         /* Now clear any previous stat_idx set */
 585         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 586         if (!is_rx)
 587                 stat_mappings->tqsm[n] &= ~clearing_mask;
 588         else
 589                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 590
 591         q_map = (uint32_t)stat_idx;
 592         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 593         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 594         if (!is_rx)
 595                 stat_mappings->tqsm[n] |= qsmr_mask;
 596         else
 597                 stat_mappings->rqsmr[n] |= qsmr_mask;
 598
 599         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 600                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 601                      queue_id, stat_idx);
 602         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 603                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 604
 605         /* Now write the mapping in the appropriate register */
 606         if (is_rx) {
 607                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 608                              stat_mappings->rqsmr[n], n);
 609                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 610         }
 611         else {
 612                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 613                              stat_mappings->tqsm[n], n);
 614                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 615         }
 616         return 0;
 617 }
 618
 619 static void
 620 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 621 {
 622         struct ixgbe_stat_mapping_registers *stat_mappings =
 623                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 624         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 625         int i;
 626
 627         /* write whatever was in stat mapping table to the NIC */
 628         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 629                 /* rx */
 630                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 631
 632                 /* tx */
 633                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 634         }
 635 }
 636
 637 static void
 638 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 639 {
 640         uint8_t i;
 641         struct ixgbe_dcb_tc_config *tc;
 642         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 643
 644         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 645         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 646         for (i = 0; i < dcb_max_tc; i++) {
 647                 tc = &dcb_config->tc_config[i];
 648                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 649                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 650                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 651                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 652                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 653                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 654                 tc->pfc = ixgbe_dcb_pfc_disabled;
 655         }
 656
 657         /* Initialize default user to priority mapping, UPx->TC0 */
 658         tc = &dcb_config->tc_config[0];
 659         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 660         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 661         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 662                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 663                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 664         }
 665         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 666         dcb_config->pfc_mode_enable = false;
 667         dcb_config->vt_mode = true;
 668         dcb_config->round_robin_enable = false;
 669         /* support all DCB capabilities in 82599 */
 670         dcb_config->support.capabilities = 0xFF;
 671
 672         /*we only support 4 Tcs for X540, X550 */
 673         if (hw->mac.type == ixgbe_mac_X540 ||
 674                 hw->mac.type == ixgbe_mac_X550 ||
 675                 hw->mac.type == ixgbe_mac_X550EM_x) {
 676                 dcb_config->num_tcs.pg_tcs = 4;
 677                 dcb_config->num_tcs.pfc_tcs = 4;
 678         }
 679 }
 680
 681 /*
 682  * Ensure that all locks are released before first NVM or PHY access
 683  */
 684 static void
 685 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 686 {
 687         uint16_t mask;
 688
 689         /*
 690          * Phy lock should not fail in this early stage. If this is the case,
 691          * it is due to an improper exit of the application.
 692          * So force the release of the faulty lock. Release of common lock
 693          * is done automatically by swfw_sync function.
 694          */
 695         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 696         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 697                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 698         }
 699         ixgbe_release_swfw_semaphore(hw, mask);
 700
 701         /*
 702          * These ones are more tricky since they are common to all ports; but
 703          * swfw_sync retries last long enough (1s) to be almost sure that if
 704          * lock can not be taken it is due to an improper lock of the
 705          * semaphore.
 706          */
 707         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 708         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 709                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 710         }
 711         ixgbe_release_swfw_semaphore(hw, mask);
 712 }
 713
 714 /*
 715  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 716  * It returns 0 on success.
 717  */
 718 static int
 719 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 720 {
 721         struct rte_pci_device *pci_dev;
 722         struct ixgbe_hw *hw =
 723                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 724         struct ixgbe_vfta * shadow_vfta =
 725                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 726         struct ixgbe_hwstrip *hwstrip =
 727                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 728         struct ixgbe_dcb_config *dcb_config =
 729                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 730         struct ixgbe_filter_info *filter_info =
 731                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 732         uint32_t ctrl_ext;
 733         uint16_t csum;
 734         int diag, i;
 735
 736         PMD_INIT_FUNC_TRACE();
 737
 738         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 739         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 740         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 741
 742         /*
 743          * For secondary processes, we don't initialise any further as primary
 744          * has already done this work. Only check we don't need a different
 745          * RX and TX function.
 746          */
 747         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 748                 struct igb_tx_queue *txq;
 749                 /* TX queue function in primary, set by last queue initialized
 750                  * Tx queue may not initialized by primary process */
 751                 if (eth_dev->data->tx_queues) {
 752                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 753                         set_tx_function(eth_dev, txq);
 754                 } else {
 755                         /* Use default TX function if we get here */
 756                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 757                                            "Using default TX function.");
 758                 }
 759
 760                 if (eth_dev->data->scattered_rx)
 761                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 762                 return 0;
 763         }
 764         pci_dev = eth_dev->pci_dev;
 765
 766         /* Vendor and Device ID need to be set before init of shared code */
 767         hw->device_id = pci_dev->id.device_id;
 768         hw->vendor_id = pci_dev->id.vendor_id;
 769         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 770         hw->allow_unsupported_sfp = 1;
 771
 772         /* Initialize the shared code (base driver) */
 773 #ifdef RTE_NIC_BYPASS
 774         diag = ixgbe_bypass_init_shared_code(hw);
 775 #else
 776         diag = ixgbe_init_shared_code(hw);
 777 #endif /* RTE_NIC_BYPASS */
 778
 779         if (diag != IXGBE_SUCCESS) {
 780                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 781                 return -EIO;
 782         }
 783
 784         /* pick up the PCI bus settings for reporting later */
 785         ixgbe_get_bus_info(hw);
 786
 787         /* Unlock any pending hardware semaphore */
 788         ixgbe_swfw_lock_reset(hw);
 789
 790         /* Initialize DCB configuration*/
 791         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 792         ixgbe_dcb_init(hw,dcb_config);
 793         /* Get Hardware Flow Control setting */
 794         hw->fc.requested_mode = ixgbe_fc_full;
 795         hw->fc.current_mode = ixgbe_fc_full;
 796         hw->fc.pause_time = IXGBE_FC_PAUSE;
 797         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 798                 hw->fc.low_water[i] = IXGBE_FC_LO;
 799                 hw->fc.high_water[i] = IXGBE_FC_HI;
 800         }
 801         hw->fc.send_xon = 1;
 802
 803         /* Make sure we have a good EEPROM before we read from it */
 804         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 805         if (diag != IXGBE_SUCCESS) {
 806                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 807                 return -EIO;
 808         }
 809
 810 #ifdef RTE_NIC_BYPASS
 811         diag = ixgbe_bypass_init_hw(hw);
 812 #else
 813         diag = ixgbe_init_hw(hw);
 814 #endif /* RTE_NIC_BYPASS */
 815
 816         /*
 817          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 818          * is called too soon after the kernel driver unbinding/binding occurs.
 819          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 820          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 821          * also called. See ixgbe_identify_phy_82599(). The reason for the
 822          * failure is not known, and only occuts when virtualisation features
 823          * are disabled in the bios. A delay of 100ms  was found to be enough by
 824          * trial-and-error, and is doubled to be safe.
 825          */
 826         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 827                 rte_delay_ms(200);
 828                 diag = ixgbe_init_hw(hw);
 829         }
 830
 831         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 832                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 833                     "LOM.  Please be aware there may be issues associated "
 834                     "with your hardware.");
 835                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 836                     "please contact your Intel or hardware representative "
 837                     "who provided you with this hardware.");
 838         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 839                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 840         if (diag) {
 841                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 842                 return -EIO;
 843         }
 844
 845         /* disable interrupt */
 846         ixgbe_disable_intr(hw);
 847
 848         /* reset mappings for queue statistics hw counters*/
 849         ixgbe_reset_qstat_mappings(hw);
 850
 851         /* Allocate memory for storing MAC addresses */
 852         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 853                         hw->mac.num_rar_entries, 0);
 854         if (eth_dev->data->mac_addrs == NULL) {
 855                 PMD_INIT_LOG(ERR,
 856                         "Failed to allocate %u bytes needed to store "
 857                         "MAC addresses",
 858                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 859                 return -ENOMEM;
 860         }
 861         /* Copy the permanent MAC address */
 862         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 863                         &eth_dev->data->mac_addrs[0]);
 864
 865         /* Allocate memory for storing hash filter MAC addresses */
 866         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 867                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 868         if (eth_dev->data->hash_mac_addrs == NULL) {
 869                 PMD_INIT_LOG(ERR,
 870                         "Failed to allocate %d bytes needed to store MAC addresses",
 871                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 872                 return -ENOMEM;
 873         }
 874
 875         /* initialize the vfta */
 876         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 877
 878         /* initialize the hw strip bitmap*/
 879         memset(hwstrip, 0, sizeof(*hwstrip));
 880
 881         /* initialize PF if max_vfs not zero */
 882         ixgbe_pf_host_init(eth_dev);
 883
 884         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 885         /* let hardware know driver is loaded */
 886         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 887         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 888         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 889         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 890         IXGBE_WRITE_FLUSH(hw);
 891
 892         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 893                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 894                              (int) hw->mac.type, (int) hw->phy.type,
 895                              (int) hw->phy.sfp_type);
 896         else
 897                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 898                              (int) hw->mac.type, (int) hw->phy.type);
 899
 900         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 901                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 902                         pci_dev->id.device_id);
 903
 904         rte_intr_callback_register(&(pci_dev->intr_handle),
 905                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 906
 907         /* enable uio intr after callback register */
 908         rte_intr_enable(&(pci_dev->intr_handle));
 909
 910         /* enable support intr */
 911         ixgbe_enable_intr(eth_dev);
 912
 913         /* initialize 5tuple filter list */
 914         TAILQ_INIT(&filter_info->fivetuple_list);
 915         memset(filter_info->fivetuple_mask, 0,
 916                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
 917
 918         return 0;
 919 }
 920
 921
 922 /*
 923  * Negotiate mailbox API version with the PF.
 924  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 925  * Then we try to negotiate starting with the most recent one.
 926  * If all negotiation attempts fail, then we will proceed with
 927  * the default one (ixgbe_mbox_api_10).
 928  */
 929 static void
 930 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 931 {
 932         int32_t i;
 933
 934         /* start with highest supported, proceed down */
 935         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 936                 ixgbe_mbox_api_11,
 937                 ixgbe_mbox_api_10,
 938         };
 939
 940         for (i = 0;
 941                         i != RTE_DIM(sup_ver) &&
 942                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 943                         i++)
 944                 ;
 945 }
 946
 947 static void
 948 generate_random_mac_addr(struct ether_addr *mac_addr)
 949 {
 950         uint64_t random;
 951
 952         /* Set Organizationally Unique Identifier (OUI) prefix. */
 953         mac_addr->addr_bytes[0] = 0x00;
 954         mac_addr->addr_bytes[1] = 0x09;
 955         mac_addr->addr_bytes[2] = 0xC0;
 956         /* Force indication of locally assigned MAC address. */
 957         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 958         /* Generate the last 3 bytes of the MAC address with a random number. */
 959         random = rte_rand();
 960         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 961 }
 962
 963 /*
 964  * Virtual Function device init
 965  */
 966 static int
 967 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
 968 {
 969         int diag;
 970         uint32_t tc, tcs;
 971         struct rte_pci_device *pci_dev;
 972         struct ixgbe_hw *hw =
 973                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 974         struct ixgbe_vfta * shadow_vfta =
 975                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 976         struct ixgbe_hwstrip *hwstrip =
 977                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 978         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 979
 980         PMD_INIT_FUNC_TRACE();
 981
 982         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 983         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 984         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 985
 986         /* for secondary processes, we don't initialise any further as primary
 987          * has already done this work. Only check we don't need a different
 988          * RX function */
 989         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 990                 if (eth_dev->data->scattered_rx)
 991                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 992                 return 0;
 993         }
 994
 995         pci_dev = eth_dev->pci_dev;
 996
 997         hw->device_id = pci_dev->id.device_id;
 998         hw->vendor_id = pci_dev->id.vendor_id;
 999         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1000
1001         /* initialize the vfta */
1002         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1003
1004         /* initialize the hw strip bitmap*/
1005         memset(hwstrip, 0, sizeof(*hwstrip));
1006
1007         /* Initialize the shared code (base driver) */
1008         diag = ixgbe_init_shared_code(hw);
1009         if (diag != IXGBE_SUCCESS) {
1010                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1011                 return -EIO;
1012         }
1013
1014         /* init_mailbox_params */
1015         hw->mbx.ops.init_params(hw);
1016
1017         /* Disable the interrupts for VF */
1018         ixgbevf_intr_disable(hw);
1019
1020         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1021         diag = hw->mac.ops.reset_hw(hw);
1022
1023         /*
1024          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1025          * the underlying PF driver has not assigned a MAC address to the VF.
1026          * In this case, assign a random MAC address.
1027          */
1028         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1029                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1030                 return (diag);
1031         }
1032
1033         /* negotiate mailbox API version to use with the PF. */
1034         ixgbevf_negotiate_api(hw);
1035
1036         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1037         ixgbevf_get_queues(hw, &tcs, &tc);
1038
1039         /* Allocate memory for storing MAC addresses */
1040         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1041                         hw->mac.num_rar_entries, 0);
1042         if (eth_dev->data->mac_addrs == NULL) {
1043                 PMD_INIT_LOG(ERR,
1044                         "Failed to allocate %u bytes needed to store "
1045                         "MAC addresses",
1046                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1047                 return -ENOMEM;
1048         }
1049
1050         /* Generate a random MAC address, if none was assigned by PF. */
1051         if (is_zero_ether_addr(perm_addr)) {
1052                 generate_random_mac_addr(perm_addr);
1053                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1054                 if (diag) {
1055                         rte_free(eth_dev->data->mac_addrs);
1056                         eth_dev->data->mac_addrs = NULL;
1057                         return diag;
1058                 }
1059                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1060                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1061                              "%02x:%02x:%02x:%02x:%02x:%02x",
1062                              perm_addr->addr_bytes[0],
1063                              perm_addr->addr_bytes[1],
1064                              perm_addr->addr_bytes[2],
1065                              perm_addr->addr_bytes[3],
1066                              perm_addr->addr_bytes[4],
1067                              perm_addr->addr_bytes[5]);
1068         }
1069
1070         /* Copy the permanent MAC address */
1071         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1072
1073         /* reset the hardware with the new settings */
1074         diag = hw->mac.ops.start_hw(hw);
1075         switch (diag) {
1076                 case  0:
1077                         break;
1078
1079                 default:
1080                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1081                         return (-EIO);
1082         }
1083
1084         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1085                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1086                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1087
1088         return 0;
1089 }
1090
1091 static struct eth_driver rte_ixgbe_pmd = {
1092         {
1093                 .name = "rte_ixgbe_pmd",
1094                 .id_table = pci_id_ixgbe_map,
1095                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1096         },
1097         .eth_dev_init = eth_ixgbe_dev_init,
1098         .dev_private_size = sizeof(struct ixgbe_adapter),
1099 };
1100
1101 /*
1102  * virtual function driver struct
1103  */
1104 static struct eth_driver rte_ixgbevf_pmd = {
1105         {
1106                 .name = "rte_ixgbevf_pmd",
1107                 .id_table = pci_id_ixgbevf_map,
1108                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1109         },
1110         .eth_dev_init = eth_ixgbevf_dev_init,
1111         .dev_private_size = sizeof(struct ixgbe_adapter),
1112 };
1113
1114 /*
1115  * Driver initialization routine.
1116  * Invoked once at EAL init time.
1117  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1118  */
1119 static int
1120 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1121 {
1122         PMD_INIT_FUNC_TRACE();
1123
1124         rte_eth_driver_register(&rte_ixgbe_pmd);
1125         return 0;
1126 }
1127
1128 /*
1129  * VF Driver initialization routine.
1130  * Invoked one at EAL init time.
1131  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1132  */
1133 static int
1134 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1135 {
1136         PMD_INIT_FUNC_TRACE();
1137
1138         rte_eth_driver_register(&rte_ixgbevf_pmd);
1139         return (0);
1140 }
1141
1142 static int
1143 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1144 {
1145         struct ixgbe_hw *hw =
1146                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1147         struct ixgbe_vfta * shadow_vfta =
1148                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1149         uint32_t vfta;
1150         uint32_t vid_idx;
1151         uint32_t vid_bit;
1152
1153         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1154         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1155         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1156         if (on)
1157                 vfta |= vid_bit;
1158         else
1159                 vfta &= ~vid_bit;
1160         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1161
1162         /* update local VFTA copy */
1163         shadow_vfta->vfta[vid_idx] = vfta;
1164
1165         return 0;
1166 }
1167
1168 static void
1169 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1170 {
1171         if (on)
1172                 ixgbe_vlan_hw_strip_enable(dev, queue);
1173         else
1174                 ixgbe_vlan_hw_strip_disable(dev, queue);
1175 }
1176
1177 static void
1178 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1179 {
1180         struct ixgbe_hw *hw =
1181                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1182
1183         /* Only the high 16-bits is valid */
1184         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1185 }
1186
1187 void
1188 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1189 {
1190         struct ixgbe_hw *hw =
1191                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1192         uint32_t vlnctrl;
1193
1194         PMD_INIT_FUNC_TRACE();
1195
1196         /* Filter Table Disable */
1197         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1198         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1199
1200         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1201 }
1202
1203 void
1204 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1205 {
1206         struct ixgbe_hw *hw =
1207                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1208         struct ixgbe_vfta * shadow_vfta =
1209                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1210         uint32_t vlnctrl;
1211         uint16_t i;
1212
1213         PMD_INIT_FUNC_TRACE();
1214
1215         /* Filter Table Enable */
1216         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1217         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1218         vlnctrl |= IXGBE_VLNCTRL_VFE;
1219
1220         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1221
1222         /* write whatever is in local vfta copy */
1223         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1224                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1225 }
1226
1227 static void
1228 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1229 {
1230         struct ixgbe_hwstrip *hwstrip =
1231                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1232
1233         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1234                 return;
1235
1236         if (on)
1237                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1238         else
1239                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1240 }
1241
1242 static void
1243 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1244 {
1245         struct ixgbe_hw *hw =
1246                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1247         uint32_t ctrl;
1248
1249         PMD_INIT_FUNC_TRACE();
1250
1251         if (hw->mac.type == ixgbe_mac_82598EB) {
1252                 /* No queue level support */
1253                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1254                 return;
1255         }
1256         else {
1257                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1258                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1259                 ctrl &= ~IXGBE_RXDCTL_VME;
1260                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1261         }
1262         /* record those setting for HW strip per queue */
1263         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1264 }
1265
1266 static void
1267 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1268 {
1269         struct ixgbe_hw *hw =
1270                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1271         uint32_t ctrl;
1272
1273         PMD_INIT_FUNC_TRACE();
1274
1275         if (hw->mac.type == ixgbe_mac_82598EB) {
1276                 /* No queue level supported */
1277                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1278                 return;
1279         }
1280         else {
1281                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1282                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1283                 ctrl |= IXGBE_RXDCTL_VME;
1284                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1285         }
1286         /* record those setting for HW strip per queue */
1287         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1288 }
1289
1290 void
1291 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1292 {
1293         struct ixgbe_hw *hw =
1294                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1295         uint32_t ctrl;
1296         uint16_t i;
1297
1298         PMD_INIT_FUNC_TRACE();
1299
1300         if (hw->mac.type == ixgbe_mac_82598EB) {
1301                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1302                 ctrl &= ~IXGBE_VLNCTRL_VME;
1303                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1304         }
1305         else {
1306                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1307                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1308                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1309                         ctrl &= ~IXGBE_RXDCTL_VME;
1310                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1311
1312                         /* record those setting for HW strip per queue */
1313                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1314                 }
1315         }
1316 }
1317
1318 void
1319 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1320 {
1321         struct ixgbe_hw *hw =
1322                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1323         uint32_t ctrl;
1324         uint16_t i;
1325
1326         PMD_INIT_FUNC_TRACE();
1327
1328         if (hw->mac.type == ixgbe_mac_82598EB) {
1329                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1330                 ctrl |= IXGBE_VLNCTRL_VME;
1331                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1332         }
1333         else {
1334                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1335                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1336                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1337                         ctrl |= IXGBE_RXDCTL_VME;
1338                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1339
1340                         /* record those setting for HW strip per queue */
1341                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1342                 }
1343         }
1344 }
1345
1346 static void
1347 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1348 {
1349         struct ixgbe_hw *hw =
1350                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1351         uint32_t ctrl;
1352
1353         PMD_INIT_FUNC_TRACE();
1354
1355         /* DMATXCTRL: Geric Double VLAN Disable */
1356         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1357         ctrl &= ~IXGBE_DMATXCTL_GDV;
1358         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1359
1360         /* CTRL_EXT: Global Double VLAN Disable */
1361         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1362         ctrl &= ~IXGBE_EXTENDED_VLAN;
1363         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1364
1365 }
1366
1367 static void
1368 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1369 {
1370         struct ixgbe_hw *hw =
1371                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1372         uint32_t ctrl;
1373
1374         PMD_INIT_FUNC_TRACE();
1375
1376         /* DMATXCTRL: Geric Double VLAN Enable */
1377         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1378         ctrl |= IXGBE_DMATXCTL_GDV;
1379         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1380
1381         /* CTRL_EXT: Global Double VLAN Enable */
1382         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1383         ctrl |= IXGBE_EXTENDED_VLAN;
1384         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1385
1386         /*
1387          * VET EXT field in the EXVET register = 0x8100 by default
1388          * So no need to change. Same to VT field of DMATXCTL register
1389          */
1390 }
1391
1392 static void
1393 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1394 {
1395         if(mask & ETH_VLAN_STRIP_MASK){
1396                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1397                         ixgbe_vlan_hw_strip_enable_all(dev);
1398                 else
1399                         ixgbe_vlan_hw_strip_disable_all(dev);
1400         }
1401
1402         if(mask & ETH_VLAN_FILTER_MASK){
1403                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1404                         ixgbe_vlan_hw_filter_enable(dev);
1405                 else
1406                         ixgbe_vlan_hw_filter_disable(dev);
1407         }
1408
1409         if(mask & ETH_VLAN_EXTEND_MASK){
1410                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1411                         ixgbe_vlan_hw_extend_enable(dev);
1412                 else
1413                         ixgbe_vlan_hw_extend_disable(dev);
1414         }
1415 }
1416
1417 static void
1418 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1419 {
1420         struct ixgbe_hw *hw =
1421                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1422         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1423         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1424         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1425         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1426 }
1427
1428 static int
1429 ixgbe_dev_configure(struct rte_eth_dev *dev)
1430 {
1431         struct ixgbe_interrupt *intr =
1432                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1433
1434         PMD_INIT_FUNC_TRACE();
1435
1436         /* set flag to update link status after init */
1437         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1438
1439         return 0;
1440 }
1441
1442 /*
1443  * Configure device link speed and setup link.
1444  * It returns 0 on success.
1445  */
1446 static int
1447 ixgbe_dev_start(struct rte_eth_dev *dev)
1448 {
1449         struct ixgbe_hw *hw =
1450                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1451         struct ixgbe_vf_info *vfinfo =
1452                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1453         int err, link_up = 0, negotiate = 0;
1454         uint32_t speed = 0;
1455         int mask = 0;
1456         int status;
1457         uint16_t vf, idx;
1458
1459         PMD_INIT_FUNC_TRACE();
1460
1461         /* IXGBE devices don't support half duplex */
1462         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1463                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1464                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1465                              dev->data->dev_conf.link_duplex,
1466                              dev->data->port_id);
1467                 return -EINVAL;
1468         }
1469
1470         /* stop adapter */
1471         hw->adapter_stopped = FALSE;
1472         ixgbe_stop_adapter(hw);
1473
1474         /* reinitialize adapter
1475          * this calls reset and start */
1476         status = ixgbe_pf_reset_hw(hw);
1477         if (status != 0)
1478                 return -1;
1479         hw->mac.ops.start_hw(hw);
1480         hw->mac.get_link_status = true;
1481
1482         /* configure PF module if SRIOV enabled */
1483         ixgbe_pf_host_configure(dev);
1484
1485         /* initialize transmission unit */
1486         ixgbe_dev_tx_init(dev);
1487
1488         /* This can fail when allocating mbufs for descriptor rings */
1489         err = ixgbe_dev_rx_init(dev);
1490         if (err) {
1491                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1492                 goto error;
1493         }
1494
1495         err = ixgbe_dev_rxtx_start(dev);
1496         if (err < 0) {
1497                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1498                 goto error;
1499         }
1500
1501         /* Skip link setup if loopback mode is enabled for 82599. */
1502         if (hw->mac.type == ixgbe_mac_82599EB &&
1503                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1504                 goto skip_link_setup;
1505
1506         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1507                 err = hw->mac.ops.setup_sfp(hw);
1508                 if (err)
1509                         goto error;
1510         }
1511
1512         /* Turn on the laser */
1513         ixgbe_enable_tx_laser(hw);
1514
1515         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1516         if (err)
1517                 goto error;
1518         dev->data->dev_link.link_status = link_up;
1519
1520         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1521         if (err)
1522                 goto error;
1523
1524         switch(dev->data->dev_conf.link_speed) {
1525         case ETH_LINK_SPEED_AUTONEG:
1526                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1527                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1528                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1529                 break;
1530         case ETH_LINK_SPEED_100:
1531                 /*
1532                  * Invalid for 82598 but error will be detected by
1533                  * ixgbe_setup_link()
1534                  */
1535                 speed = IXGBE_LINK_SPEED_100_FULL;
1536                 break;
1537         case ETH_LINK_SPEED_1000:
1538                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1539                 break;
1540         case ETH_LINK_SPEED_10000:
1541                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1542                 break;
1543         default:
1544                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1545                              dev->data->dev_conf.link_speed,
1546                              dev->data->port_id);
1547                 goto error;
1548         }
1549
1550         err = ixgbe_setup_link(hw, speed, link_up);
1551         if (err)
1552                 goto error;
1553
1554 skip_link_setup:
1555
1556         /* check if lsc interrupt is enabled */
1557         if (dev->data->dev_conf.intr_conf.lsc != 0)
1558                 ixgbe_dev_lsc_interrupt_setup(dev);
1559
1560         /* resume enabled intr since hw reset */
1561         ixgbe_enable_intr(dev);
1562
1563         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1564                 ETH_VLAN_EXTEND_MASK;
1565         ixgbe_vlan_offload_set(dev, mask);
1566
1567         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1568                 /* Enable vlan filtering for VMDq */
1569                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1570         }
1571
1572         /* Configure DCB hw */
1573         ixgbe_configure_dcb(dev);
1574
1575         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1576                 err = ixgbe_fdir_configure(dev);
1577                 if (err)
1578                         goto error;
1579         }
1580
1581         /* Restore vf rate limit */
1582         if (vfinfo != NULL) {
1583                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1584                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1585                                 if (vfinfo[vf].tx_rate[idx] != 0)
1586                                         ixgbe_set_vf_rate_limit(dev, vf,
1587                                                 vfinfo[vf].tx_rate[idx],
1588                                                 1 << idx);
1589         }
1590
1591         ixgbe_restore_statistics_mapping(dev);
1592
1593         return (0);
1594
1595 error:
1596         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1597         ixgbe_dev_clear_queues(dev);
1598         return -EIO;
1599 }
1600
1601 /*
1602  * Stop device: disable rx and tx functions to allow for reconfiguring.
1603  */
1604 static void
1605 ixgbe_dev_stop(struct rte_eth_dev *dev)
1606 {
1607         struct rte_eth_link link;
1608         struct ixgbe_hw *hw =
1609                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1610         struct ixgbe_vf_info *vfinfo =
1611                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1612         struct ixgbe_filter_info *filter_info =
1613                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1614         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1615         int vf;
1616
1617         PMD_INIT_FUNC_TRACE();
1618
1619         /* disable interrupts */
1620         ixgbe_disable_intr(hw);
1621
1622         /* reset the NIC */
1623         ixgbe_pf_reset_hw(hw);
1624         hw->adapter_stopped = FALSE;
1625
1626         /* stop adapter */
1627         ixgbe_stop_adapter(hw);
1628
1629         for (vf = 0; vfinfo != NULL &&
1630                      vf < dev->pci_dev->max_vfs; vf++)
1631                 vfinfo[vf].clear_to_send = false;
1632
1633         /* Turn off the laser */
1634         ixgbe_disable_tx_laser(hw);
1635
1636         ixgbe_dev_clear_queues(dev);
1637
1638         /* Clear stored conf */
1639         dev->data->scattered_rx = 0;
1640
1641         /* Clear recorded link status */
1642         memset(&link, 0, sizeof(link));
1643         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1644
1645         /* Remove all ntuple filters of the device */
1646         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1647              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1648                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1649                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1650                              p_5tuple, entries);
1651                 rte_free(p_5tuple);
1652         }
1653         memset(filter_info->fivetuple_mask, 0,
1654                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1655
1656 }
1657
1658 /*
1659  * Set device link up: enable tx laser.
1660  */
1661 static int
1662 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1663 {
1664         struct ixgbe_hw *hw =
1665                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1666         if (hw->mac.type == ixgbe_mac_82599EB) {
1667 #ifdef RTE_NIC_BYPASS
1668                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1669                         /* Not suported in bypass mode */
1670                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1671                                      "by device id 0x%x", hw->device_id);
1672                         return -ENOTSUP;
1673                 }
1674 #endif
1675                 /* Turn on the laser */
1676                 ixgbe_enable_tx_laser(hw);
1677                 return 0;
1678         }
1679
1680         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1681                      hw->device_id);
1682         return -ENOTSUP;
1683 }
1684
1685 /*
1686  * Set device link down: disable tx laser.
1687  */
1688 static int
1689 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1690 {
1691         struct ixgbe_hw *hw =
1692                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1693         if (hw->mac.type == ixgbe_mac_82599EB) {
1694 #ifdef RTE_NIC_BYPASS
1695                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1696                         /* Not suported in bypass mode */
1697                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1698                                      "by device id 0x%x", hw->device_id);
1699                         return -ENOTSUP;
1700                 }
1701 #endif
1702                 /* Turn off the laser */
1703                 ixgbe_disable_tx_laser(hw);
1704                 return 0;
1705         }
1706
1707         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1708                      hw->device_id);
1709         return -ENOTSUP;
1710 }
1711
1712 /*
1713  * Reest and stop device.
1714  */
1715 static void
1716 ixgbe_dev_close(struct rte_eth_dev *dev)
1717 {
1718         struct ixgbe_hw *hw =
1719                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1720
1721         PMD_INIT_FUNC_TRACE();
1722
1723         ixgbe_pf_reset_hw(hw);
1724
1725         ixgbe_dev_stop(dev);
1726         hw->adapter_stopped = 1;
1727
1728         ixgbe_disable_pcie_master(hw);
1729
1730         /* reprogram the RAR[0] in case user changed it. */
1731         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1732 }
1733
1734 /*
1735  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1736  */
1737 static void
1738 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1739 {
1740         struct ixgbe_hw *hw =
1741                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1742         struct ixgbe_hw_stats *hw_stats =
1743                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1744         uint32_t bprc, lxon, lxoff, total;
1745         uint64_t total_missed_rx, total_qbrc, total_qprc;
1746         unsigned i;
1747
1748         total_missed_rx = 0;
1749         total_qbrc = 0;
1750         total_qprc = 0;
1751
1752         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1753         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1754         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1755         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1756
1757         for (i = 0; i < 8; i++) {
1758                 uint32_t mp;
1759                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1760                 /* global total per queue */
1761                 hw_stats->mpc[i] += mp;
1762                 /* Running comprehensive total for stats display */
1763                 total_missed_rx += hw_stats->mpc[i];
1764                 if (hw->mac.type == ixgbe_mac_82598EB)
1765                         hw_stats->rnbc[i] +=
1766                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1767                 hw_stats->pxontxc[i] +=
1768                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1769                 hw_stats->pxonrxc[i] +=
1770                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1771                 hw_stats->pxofftxc[i] +=
1772                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1773                 hw_stats->pxoffrxc[i] +=
1774                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1775                 hw_stats->pxon2offc[i] +=
1776                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1777         }
1778         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1779                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1780                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1781                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1782                 hw_stats->qbrc[i] +=
1783                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1784                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1785                 hw_stats->qbtc[i] +=
1786                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1787                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1788
1789                 total_qprc += hw_stats->qprc[i];
1790                 total_qbrc += hw_stats->qbrc[i];
1791         }
1792         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1793         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1794         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1795
1796         /* Note that gprc counts missed packets */
1797         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1798
1799         if (hw->mac.type != ixgbe_mac_82598EB) {
1800                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1801                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1802                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1803                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1804                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1805                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1806                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1807                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1808         } else {
1809                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1810                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1811                 /* 82598 only has a counter in the high register */
1812                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1813                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1814                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1815         }
1816
1817         /*
1818          * Workaround: mprc hardware is incorrectly counting
1819          * broadcasts, so for now we subtract those.
1820          */
1821         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1822         hw_stats->bprc += bprc;
1823         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1824         if (hw->mac.type == ixgbe_mac_82598EB)
1825                 hw_stats->mprc -= bprc;
1826
1827         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1828         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1829         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1830         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1831         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1832         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1833
1834         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1835         hw_stats->lxontxc += lxon;
1836         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1837         hw_stats->lxofftxc += lxoff;
1838         total = lxon + lxoff;
1839
1840         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1841         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1842         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1843         hw_stats->gptc -= total;
1844         hw_stats->mptc -= total;
1845         hw_stats->ptc64 -= total;
1846         hw_stats->gotc -= total * ETHER_MIN_LEN;
1847
1848         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1849         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1850         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1851         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1852         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1853         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1854         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1855         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1856         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1857         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1858         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1859         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1860         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1861         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1862         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1863         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1864         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1865         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1866         /* Only read FCOE on 82599 */
1867         if (hw->mac.type != ixgbe_mac_82598EB) {
1868                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1869                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1870                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1871                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1872                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1873         }
1874
1875         if (stats == NULL)
1876                 return;
1877
1878         /* Fill out the rte_eth_stats statistics structure */
1879         stats->ipackets = total_qprc;
1880         stats->ibytes = total_qbrc;
1881         stats->opackets = hw_stats->gptc;
1882         stats->obytes = hw_stats->gotc;
1883         stats->imcasts = hw_stats->mprc;
1884
1885         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1886                 stats->q_ipackets[i] = hw_stats->qprc[i];
1887                 stats->q_opackets[i] = hw_stats->qptc[i];
1888                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1889                 stats->q_obytes[i] = hw_stats->qbtc[i];
1890                 stats->q_errors[i] = hw_stats->qprdc[i];
1891         }
1892
1893         /* Rx Errors */
1894         stats->ibadcrc  = hw_stats->crcerrs;
1895         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1896         stats->imissed  = total_missed_rx;
1897         stats->ierrors  = stats->ibadcrc +
1898                           stats->ibadlen +
1899                           stats->imissed +
1900                           hw_stats->illerrc + hw_stats->errbc;
1901
1902         /* Tx Errors */
1903         stats->oerrors  = 0;
1904
1905         /* XON/XOFF pause frames */
1906         stats->tx_pause_xon  = hw_stats->lxontxc;
1907         stats->rx_pause_xon  = hw_stats->lxonrxc;
1908         stats->tx_pause_xoff = hw_stats->lxofftxc;
1909         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1910
1911         /* Flow Director Stats registers */
1912         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1913         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1914         stats->fdirmatch = hw_stats->fdirmatch;
1915         stats->fdirmiss = hw_stats->fdirmiss;
1916 }
1917
1918 static void
1919 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1920 {
1921         struct ixgbe_hw_stats *stats =
1922                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1923
1924         /* HW registers are cleared on read */
1925         ixgbe_dev_stats_get(dev, NULL);
1926
1927         /* Reset software totals */
1928         memset(stats, 0, sizeof(*stats));
1929 }
1930
1931 static void
1932 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1933 {
1934         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1936                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1937
1938         /* Good Rx packet, include VF loopback */
1939         UPDATE_VF_STAT(IXGBE_VFGPRC,
1940             hw_stats->last_vfgprc, hw_stats->vfgprc);
1941
1942         /* Good Rx octets, include VF loopback */
1943         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1944             hw_stats->last_vfgorc, hw_stats->vfgorc);
1945
1946         /* Good Tx packet, include VF loopback */
1947         UPDATE_VF_STAT(IXGBE_VFGPTC,
1948             hw_stats->last_vfgptc, hw_stats->vfgptc);
1949
1950         /* Good Tx octets, include VF loopback */
1951         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1952             hw_stats->last_vfgotc, hw_stats->vfgotc);
1953
1954         /* Rx Multicst Packet */
1955         UPDATE_VF_STAT(IXGBE_VFMPRC,
1956             hw_stats->last_vfmprc, hw_stats->vfmprc);
1957
1958         if (stats == NULL)
1959                 return;
1960
1961         stats->ipackets = hw_stats->vfgprc;
1962         stats->ibytes = hw_stats->vfgorc;
1963         stats->opackets = hw_stats->vfgptc;
1964         stats->obytes = hw_stats->vfgotc;
1965         stats->imcasts = hw_stats->vfmprc;
1966 }
1967
1968 static void
1969 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1970 {
1971         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1972                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1973
1974         /* Sync HW register to the last stats */
1975         ixgbevf_dev_stats_get(dev, NULL);
1976
1977         /* reset HW current stats*/
1978         hw_stats->vfgprc = 0;
1979         hw_stats->vfgorc = 0;
1980         hw_stats->vfgptc = 0;
1981         hw_stats->vfgotc = 0;
1982         hw_stats->vfmprc = 0;
1983
1984 }
1985
1986 static void
1987 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1988 {
1989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1990
1991         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1992         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1993         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1994         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1995         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1996         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1997         dev_info->max_vfs = dev->pci_dev->max_vfs;
1998         if (hw->mac.type == ixgbe_mac_82598EB)
1999                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2000         else
2001                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2002         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2003         dev_info->rx_offload_capa =
2004                 DEV_RX_OFFLOAD_VLAN_STRIP |
2005                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2006                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2007                 DEV_RX_OFFLOAD_TCP_CKSUM;
2008         dev_info->tx_offload_capa =
2009                 DEV_TX_OFFLOAD_VLAN_INSERT |
2010                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2011                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2012                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2013                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2014                 DEV_TX_OFFLOAD_TCP_TSO;
2015
2016         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2017                 .rx_thresh = {
2018                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2019                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2020                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2021                 },
2022                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2023                 .rx_drop_en = 0,
2024         };
2025
2026         dev_info->default_txconf = (struct rte_eth_txconf) {
2027                 .tx_thresh = {
2028                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2029                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2030                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2031                 },
2032                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2033                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2034                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2035                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2036         };
2037         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2038         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2039 }
2040
2041 static void
2042 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2043                      struct rte_eth_dev_info *dev_info)
2044 {
2045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2046
2047         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2048         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2049         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2050         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2051         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2052         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2053         dev_info->max_vfs = dev->pci_dev->max_vfs;
2054         if (hw->mac.type == ixgbe_mac_82598EB)
2055                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2056         else
2057                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2058         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2059                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2060                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2061                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2062         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2063                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2064                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2065                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2066                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2067
2068         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2069                 .rx_thresh = {
2070                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2071                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2072                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2073                 },
2074                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2075                 .rx_drop_en = 0,
2076         };
2077
2078         dev_info->default_txconf = (struct rte_eth_txconf) {
2079                 .tx_thresh = {
2080                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2081                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2082                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2083                 },
2084                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2085                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2086                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2087                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2088         };
2089 }
2090
2091 /* return 0 means link status changed, -1 means not changed */
2092 static int
2093 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2094 {
2095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2096         struct rte_eth_link link, old;
2097         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2098         int link_up;
2099         int diag;
2100
2101         link.link_status = 0;
2102         link.link_speed = 0;
2103         link.link_duplex = 0;
2104         memset(&old, 0, sizeof(old));
2105         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2106
2107         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2108         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2109                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2110         else
2111                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2112         if (diag != 0) {
2113                 link.link_speed = ETH_LINK_SPEED_100;
2114                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2115                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2116                 if (link.link_status == old.link_status)
2117                         return -1;
2118                 return 0;
2119         }
2120
2121         if (link_speed == IXGBE_LINK_SPEED_UNKNOWN &&
2122             !hw->mac.get_link_status) {
2123                 memcpy(&link, &old, sizeof(link));
2124                 return -1;
2125         }
2126
2127         if (link_up == 0) {
2128                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2129                 if (link.link_status == old.link_status)
2130                         return -1;
2131                 return 0;
2132         }
2133         link.link_status = 1;
2134         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2135
2136         switch (link_speed) {
2137         default:
2138         case IXGBE_LINK_SPEED_UNKNOWN:
2139                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2140                 link.link_speed = ETH_LINK_SPEED_100;
2141                 break;
2142
2143         case IXGBE_LINK_SPEED_100_FULL:
2144                 link.link_speed = ETH_LINK_SPEED_100;
2145                 break;
2146
2147         case IXGBE_LINK_SPEED_1GB_FULL:
2148                 link.link_speed = ETH_LINK_SPEED_1000;
2149                 break;
2150
2151         case IXGBE_LINK_SPEED_10GB_FULL:
2152                 link.link_speed = ETH_LINK_SPEED_10000;
2153                 break;
2154         }
2155         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2156
2157         if (link.link_status == old.link_status)
2158                 return -1;
2159
2160         return 0;
2161 }
2162
2163 static void
2164 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2165 {
2166         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167         uint32_t fctrl;
2168
2169         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2170         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2171         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2172 }
2173
2174 static void
2175 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2176 {
2177         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2178         uint32_t fctrl;
2179
2180         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2181         fctrl &= (~IXGBE_FCTRL_UPE);
2182         if (dev->data->all_multicast == 1)
2183                 fctrl |= IXGBE_FCTRL_MPE;
2184         else
2185                 fctrl &= (~IXGBE_FCTRL_MPE);
2186         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2187 }
2188
2189 static void
2190 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2191 {
2192         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193         uint32_t fctrl;
2194
2195         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2196         fctrl |= IXGBE_FCTRL_MPE;
2197         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2198 }
2199
2200 static void
2201 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2202 {
2203         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2204         uint32_t fctrl;
2205
2206         if (dev->data->promiscuous == 1)
2207                 return; /* must remain in all_multicast mode */
2208
2209         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2210         fctrl &= (~IXGBE_FCTRL_MPE);
2211         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2212 }
2213
2214 /**
2215  * It clears the interrupt causes and enables the interrupt.
2216  * It will be called once only during nic initialized.
2217  *
2218  * @param dev
2219  *  Pointer to struct rte_eth_dev.
2220  *
2221  * @return
2222  *  - On success, zero.
2223  *  - On failure, a negative value.
2224  */
2225 static int
2226 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2227 {
2228         struct ixgbe_interrupt *intr =
2229                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2230
2231         ixgbe_dev_link_status_print(dev);
2232         intr->mask |= IXGBE_EICR_LSC;
2233
2234         return 0;
2235 }
2236
2237 /*
2238  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2239  *
2240  * @param dev
2241  *  Pointer to struct rte_eth_dev.
2242  *
2243  * @return
2244  *  - On success, zero.
2245  *  - On failure, a negative value.
2246  */
2247 static int
2248 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2249 {
2250         uint32_t eicr;
2251         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2252         struct ixgbe_interrupt *intr =
2253                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2254
2255         /* clear all cause mask */
2256         ixgbe_disable_intr(hw);
2257
2258         /* read-on-clear nic registers here */
2259         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2260         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2261
2262         intr->flags = 0;
2263         if (eicr & IXGBE_EICR_LSC) {
2264                 /* set flag for async link update */
2265                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2266         }
2267
2268         if (eicr & IXGBE_EICR_MAILBOX)
2269                 intr->flags |= IXGBE_FLAG_MAILBOX;
2270
2271         return 0;
2272 }
2273
2274 /**
2275  * It gets and then prints the link status.
2276  *
2277  * @param dev
2278  *  Pointer to struct rte_eth_dev.
2279  *
2280  * @return
2281  *  - On success, zero.
2282  *  - On failure, a negative value.
2283  */
2284 static void
2285 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2286 {
2287         struct rte_eth_link link;
2288
2289         memset(&link, 0, sizeof(link));
2290         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2291         if (link.link_status) {
2292                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2293                                         (int)(dev->data->port_id),
2294                                         (unsigned)link.link_speed,
2295                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2296                                         "full-duplex" : "half-duplex");
2297         } else {
2298                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2299                                 (int)(dev->data->port_id));
2300         }
2301         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2302                                 dev->pci_dev->addr.domain,
2303                                 dev->pci_dev->addr.bus,
2304                                 dev->pci_dev->addr.devid,
2305                                 dev->pci_dev->addr.function);
2306 }
2307
2308 /*
2309  * It executes link_update after knowing an interrupt occurred.
2310  *
2311  * @param dev
2312  *  Pointer to struct rte_eth_dev.
2313  *
2314  * @return
2315  *  - On success, zero.
2316  *  - On failure, a negative value.
2317  */
2318 static int
2319 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2320 {
2321         struct ixgbe_interrupt *intr =
2322                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2323         int64_t timeout;
2324         struct rte_eth_link link;
2325         int intr_enable_delay = false;
2326
2327         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2328
2329         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2330                 ixgbe_pf_mbx_process(dev);
2331                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2332         }
2333
2334         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2335                 /* get the link status before link update, for predicting later */
2336                 memset(&link, 0, sizeof(link));
2337                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2338
2339                 ixgbe_dev_link_update(dev, 0);
2340
2341                 /* likely to up */
2342                 if (!link.link_status)
2343                         /* handle it 1 sec later, wait it being stable */
2344                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2345                 /* likely to down */
2346                 else
2347                         /* handle it 4 sec later, wait it being stable */
2348                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2349
2350                 ixgbe_dev_link_status_print(dev);
2351
2352                 intr_enable_delay = true;
2353         }
2354
2355         if (intr_enable_delay) {
2356                 if (rte_eal_alarm_set(timeout * 1000,
2357                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2358                         PMD_DRV_LOG(ERR, "Error setting alarm");
2359         } else {
2360                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2361                 ixgbe_enable_intr(dev);
2362                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2363         }
2364
2365
2366         return 0;
2367 }
2368
2369 /**
2370  * Interrupt handler which shall be registered for alarm callback for delayed
2371  * handling specific interrupt to wait for the stable nic state. As the
2372  * NIC interrupt state is not stable for ixgbe after link is just down,
2373  * it needs to wait 4 seconds to get the stable status.
2374  *
2375  * @param handle
2376  *  Pointer to interrupt handle.
2377  * @param param
2378  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2379  *
2380  * @return
2381  *  void
2382  */
2383 static void
2384 ixgbe_dev_interrupt_delayed_handler(void *param)
2385 {
2386         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2387         struct ixgbe_interrupt *intr =
2388                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2389         struct ixgbe_hw *hw =
2390                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2391         uint32_t eicr;
2392
2393         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2394         if (eicr & IXGBE_EICR_MAILBOX)
2395                 ixgbe_pf_mbx_process(dev);
2396
2397         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2398                 ixgbe_dev_link_update(dev, 0);
2399                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2400                 ixgbe_dev_link_status_print(dev);
2401                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2402         }
2403
2404         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2405         ixgbe_enable_intr(dev);
2406         rte_intr_enable(&(dev->pci_dev->intr_handle));
2407 }
2408
2409 /**
2410  * Interrupt handler triggered by NIC  for handling
2411  * specific interrupt.
2412  *
2413  * @param handle
2414  *  Pointer to interrupt handle.
2415  * @param param
2416  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2417  *
2418  * @return
2419  *  void
2420  */
2421 static void
2422 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2423                                                         void *param)
2424 {
2425         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2426         ixgbe_dev_interrupt_get_status(dev);
2427         ixgbe_dev_interrupt_action(dev);
2428 }
2429
2430 static int
2431 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2432 {
2433         struct ixgbe_hw *hw;
2434
2435         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2436         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2437 }
2438
2439 static int
2440 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2441 {
2442         struct ixgbe_hw *hw;
2443
2444         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2445         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2446 }
2447
2448 static int
2449 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2450 {
2451         struct ixgbe_hw *hw;
2452         uint32_t mflcn_reg;
2453         uint32_t fccfg_reg;
2454         int rx_pause;
2455         int tx_pause;
2456
2457         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2458
2459         fc_conf->pause_time = hw->fc.pause_time;
2460         fc_conf->high_water = hw->fc.high_water[0];
2461         fc_conf->low_water = hw->fc.low_water[0];
2462         fc_conf->send_xon = hw->fc.send_xon;
2463         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2464
2465         /*
2466          * Return rx_pause status according to actual setting of
2467          * MFLCN register.
2468          */
2469         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2470         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2471                 rx_pause = 1;
2472         else
2473                 rx_pause = 0;
2474
2475         /*
2476          * Return tx_pause status according to actual setting of
2477          * FCCFG register.
2478          */
2479         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2480         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2481                 tx_pause = 1;
2482         else
2483                 tx_pause = 0;
2484
2485         if (rx_pause && tx_pause)
2486                 fc_conf->mode = RTE_FC_FULL;
2487         else if (rx_pause)
2488                 fc_conf->mode = RTE_FC_RX_PAUSE;
2489         else if (tx_pause)
2490                 fc_conf->mode = RTE_FC_TX_PAUSE;
2491         else
2492                 fc_conf->mode = RTE_FC_NONE;
2493
2494         return 0;
2495 }
2496
2497 static int
2498 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2499 {
2500         struct ixgbe_hw *hw;
2501         int err;
2502         uint32_t rx_buf_size;
2503         uint32_t max_high_water;
2504         uint32_t mflcn;
2505         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2506                 ixgbe_fc_none,
2507                 ixgbe_fc_rx_pause,
2508                 ixgbe_fc_tx_pause,
2509                 ixgbe_fc_full
2510         };
2511
2512         PMD_INIT_FUNC_TRACE();
2513
2514         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2515         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2516                 return -ENOTSUP;
2517         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2518         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2519
2520         /*
2521          * At least reserve one Ethernet frame for watermark
2522          * high_water/low_water in kilo bytes for ixgbe
2523          */
2524         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2525         if ((fc_conf->high_water > max_high_water) ||
2526                 (fc_conf->high_water < fc_conf->low_water)) {
2527                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2528                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2529                 return (-EINVAL);
2530         }
2531
2532         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2533         hw->fc.pause_time     = fc_conf->pause_time;
2534         hw->fc.high_water[0]  = fc_conf->high_water;
2535         hw->fc.low_water[0]   = fc_conf->low_water;
2536         hw->fc.send_xon       = fc_conf->send_xon;
2537
2538         err = ixgbe_fc_enable(hw);
2539
2540         /* Not negotiated is not an error case */
2541         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2542
2543                 /* check if we want to forward MAC frames - driver doesn't have native
2544                  * capability to do that, so we'll write the registers ourselves */
2545
2546                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2547
2548                 /* set or clear MFLCN.PMCF bit depending on configuration */
2549                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2550                         mflcn |= IXGBE_MFLCN_PMCF;
2551                 else
2552                         mflcn &= ~IXGBE_MFLCN_PMCF;
2553
2554                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2555                 IXGBE_WRITE_FLUSH(hw);
2556
2557                 return 0;
2558         }
2559
2560         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2561         return -EIO;
2562 }
2563
2564 /**
2565  *  ixgbe_pfc_enable_generic - Enable flow control
2566  *  @hw: pointer to hardware structure
2567  *  @tc_num: traffic class number
2568  *  Enable flow control according to the current settings.
2569  */
2570 static int
2571 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2572 {
2573         int ret_val = 0;
2574         uint32_t mflcn_reg, fccfg_reg;
2575         uint32_t reg;
2576         uint32_t fcrtl, fcrth;
2577         uint8_t i;
2578         uint8_t nb_rx_en;
2579
2580         /* Validate the water mark configuration */
2581         if (!hw->fc.pause_time) {
2582                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2583                 goto out;
2584         }
2585
2586         /* Low water mark of zero causes XOFF floods */
2587         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2588                  /* High/Low water can not be 0 */
2589                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2590                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2591                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2592                         goto out;
2593                 }
2594
2595                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2596                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2597                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2598                         goto out;
2599                 }
2600         }
2601         /* Negotiate the fc mode to use */
2602         ixgbe_fc_autoneg(hw);
2603
2604         /* Disable any previous flow control settings */
2605         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2606         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2607
2608         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2609         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2610
2611         switch (hw->fc.current_mode) {
2612         case ixgbe_fc_none:
2613                 /*
2614                  * If the count of enabled RX Priority Flow control >1,
2615                  * and the TX pause can not be disabled
2616                  */
2617                 nb_rx_en = 0;
2618                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2619                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2620                         if (reg & IXGBE_FCRTH_FCEN)
2621                                 nb_rx_en++;
2622                 }
2623                 if (nb_rx_en > 1)
2624                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2625                 break;
2626         case ixgbe_fc_rx_pause:
2627                 /*
2628                  * Rx Flow control is enabled and Tx Flow control is
2629                  * disabled by software override. Since there really
2630                  * isn't a way to advertise that we are capable of RX
2631                  * Pause ONLY, we will advertise that we support both
2632                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2633                  * disable the adapter's ability to send PAUSE frames.
2634                  */
2635                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2636                 /*
2637                  * If the count of enabled RX Priority Flow control >1,
2638                  * and the TX pause can not be disabled
2639                  */
2640                 nb_rx_en = 0;
2641                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2642                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2643                         if (reg & IXGBE_FCRTH_FCEN)
2644                                 nb_rx_en++;
2645                 }
2646                 if (nb_rx_en > 1)
2647                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2648                 break;
2649         case ixgbe_fc_tx_pause:
2650                 /*
2651                  * Tx Flow control is enabled, and Rx Flow control is
2652                  * disabled by software override.
2653                  */
2654                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2655                 break;
2656         case ixgbe_fc_full:
2657                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2658                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2659                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2660                 break;
2661         default:
2662                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2663                 ret_val = IXGBE_ERR_CONFIG;
2664                 goto out;
2665                 break;
2666         }
2667
2668         /* Set 802.3x based flow control settings. */
2669         mflcn_reg |= IXGBE_MFLCN_DPF;
2670         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2671         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2672
2673         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2674         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2675                 hw->fc.high_water[tc_num]) {
2676                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2677                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2678                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2679         } else {
2680                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2681                 /*
2682                  * In order to prevent Tx hangs when the internal Tx
2683                  * switch is enabled we must set the high water mark
2684                  * to the maximum FCRTH value.  This allows the Tx
2685                  * switch to function even under heavy Rx workloads.
2686                  */
2687                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2688         }
2689         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2690
2691         /* Configure pause time (2 TCs per register) */
2692         reg = hw->fc.pause_time * 0x00010001;
2693         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2694                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2695
2696         /* Configure flow control refresh threshold value */
2697         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2698
2699 out:
2700         return ret_val;
2701 }
2702
2703 static int
2704 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2705 {
2706         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2707         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2708
2709         if(hw->mac.type != ixgbe_mac_82598EB) {
2710                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2711         }
2712         return ret_val;
2713 }
2714
2715 static int
2716 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2717 {
2718         int err;
2719         uint32_t rx_buf_size;
2720         uint32_t max_high_water;
2721         uint8_t tc_num;
2722         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2723         struct ixgbe_hw *hw =
2724                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2725         struct ixgbe_dcb_config *dcb_config =
2726                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2727
2728         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2729                 ixgbe_fc_none,
2730                 ixgbe_fc_rx_pause,
2731                 ixgbe_fc_tx_pause,
2732                 ixgbe_fc_full
2733         };
2734
2735         PMD_INIT_FUNC_TRACE();
2736
2737         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2738         tc_num = map[pfc_conf->priority];
2739         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2740         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2741         /*
2742          * At least reserve one Ethernet frame for watermark
2743          * high_water/low_water in kilo bytes for ixgbe
2744          */
2745         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2746         if ((pfc_conf->fc.high_water > max_high_water) ||
2747             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2748                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2749                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2750                 return (-EINVAL);
2751         }
2752
2753         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2754         hw->fc.pause_time = pfc_conf->fc.pause_time;
2755         hw->fc.send_xon = pfc_conf->fc.send_xon;
2756         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2757         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2758
2759         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2760
2761         /* Not negotiated is not an error case */
2762         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2763                 return 0;
2764
2765         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2766         return -EIO;
2767 }
2768
2769 static int
2770 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2771                           struct rte_eth_rss_reta_entry64 *reta_conf,
2772                           uint16_t reta_size)
2773 {
2774         uint8_t i, j, mask;
2775         uint32_t reta, r;
2776         uint16_t idx, shift;
2777         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2778
2779         PMD_INIT_FUNC_TRACE();
2780         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2781                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2782                         "(%d) doesn't match the number hardware can supported "
2783                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2784                 return -EINVAL;
2785         }
2786
2787         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2788                 idx = i / RTE_RETA_GROUP_SIZE;
2789                 shift = i % RTE_RETA_GROUP_SIZE;
2790                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2791                                                 IXGBE_4_BIT_MASK);
2792                 if (!mask)
2793                         continue;
2794                 if (mask == IXGBE_4_BIT_MASK)
2795                         r = 0;
2796                 else
2797                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2798                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2799                         if (mask & (0x1 << j))
2800                                 reta |= reta_conf[idx].reta[shift + j] <<
2801                                                         (CHAR_BIT * j);
2802                         else
2803                                 reta |= r & (IXGBE_8_BIT_MASK <<
2804                                                 (CHAR_BIT * j));
2805                 }
2806                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2807         }
2808
2809         return 0;
2810 }
2811
2812 static int
2813 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2814                          struct rte_eth_rss_reta_entry64 *reta_conf,
2815                          uint16_t reta_size)
2816 {
2817         uint8_t i, j, mask;
2818         uint32_t reta;
2819         uint16_t idx, shift;
2820         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2821
2822         PMD_INIT_FUNC_TRACE();
2823         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2824                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2825                         "(%d) doesn't match the number hardware can supported "
2826                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2827                 return -EINVAL;
2828         }
2829
2830         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2831                 idx = i / RTE_RETA_GROUP_SIZE;
2832                 shift = i % RTE_RETA_GROUP_SIZE;
2833                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2834                                                 IXGBE_4_BIT_MASK);
2835                 if (!mask)
2836                         continue;
2837
2838                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2839                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2840                         if (mask & (0x1 << j))
2841                                 reta_conf[idx].reta[shift + j] =
2842                                         ((reta >> (CHAR_BIT * j)) &
2843                                                 IXGBE_8_BIT_MASK);
2844                 }
2845         }
2846
2847         return 0;
2848 }
2849
2850 static void
2851 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2852                                 uint32_t index, uint32_t pool)
2853 {
2854         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2855         uint32_t enable_addr = 1;
2856
2857         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2858 }
2859
2860 static void
2861 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2862 {
2863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2864
2865         ixgbe_clear_rar(hw, index);
2866 }
2867
2868 static int
2869 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2870 {
2871         uint32_t hlreg0;
2872         uint32_t maxfrs;
2873         struct ixgbe_hw *hw;
2874         struct rte_eth_dev_info dev_info;
2875         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2876
2877         ixgbe_dev_info_get(dev, &dev_info);
2878
2879         /* check that mtu is within the allowed range */
2880         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2881                 return -EINVAL;
2882
2883         /* refuse mtu that requires the support of scattered packets when this
2884          * feature has not been enabled before. */
2885         if (!dev->data->scattered_rx &&
2886             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2887              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2888                 return -EINVAL;
2889
2890         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2891         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2892
2893         /* switch to jumbo mode if needed */
2894         if (frame_size > ETHER_MAX_LEN) {
2895                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2896                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2897         } else {
2898                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2899                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2900         }
2901         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2902
2903         /* update max frame size */
2904         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2905
2906         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2907         maxfrs &= 0x0000FFFF;
2908         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2909         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2910
2911         return 0;
2912 }
2913
2914 /*
2915  * Virtual Function operations
2916  */
2917 static void
2918 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2919 {
2920         PMD_INIT_FUNC_TRACE();
2921
2922         /* Clear interrupt mask to stop from interrupts being generated */
2923         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2924
2925         IXGBE_WRITE_FLUSH(hw);
2926 }
2927
2928 static int
2929 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2930 {
2931         struct rte_eth_conf* conf = &dev->data->dev_conf;
2932
2933         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2934                      dev->data->port_id);
2935
2936         /*
2937          * VF has no ability to enable/disable HW CRC
2938          * Keep the persistent behavior the same as Host PF
2939          */
2940 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2941         if (!conf->rxmode.hw_strip_crc) {
2942                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2943                 conf->rxmode.hw_strip_crc = 1;
2944         }
2945 #else
2946         if (conf->rxmode.hw_strip_crc) {
2947                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2948                 conf->rxmode.hw_strip_crc = 0;
2949         }
2950 #endif
2951
2952         return 0;
2953 }
2954
2955 static int
2956 ixgbevf_dev_start(struct rte_eth_dev *dev)
2957 {
2958         struct ixgbe_hw *hw =
2959                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2960         int err, mask = 0;
2961
2962         PMD_INIT_FUNC_TRACE();
2963
2964         hw->mac.ops.reset_hw(hw);
2965         hw->mac.get_link_status = true;
2966
2967         /* negotiate mailbox API version to use with the PF. */
2968         ixgbevf_negotiate_api(hw);
2969
2970         ixgbevf_dev_tx_init(dev);
2971
2972         /* This can fail when allocating mbufs for descriptor rings */
2973         err = ixgbevf_dev_rx_init(dev);
2974         if (err) {
2975                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2976                 ixgbe_dev_clear_queues(dev);
2977                 return err;
2978         }
2979
2980         /* Set vfta */
2981         ixgbevf_set_vfta_all(dev,1);
2982
2983         /* Set HW strip */
2984         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2985                 ETH_VLAN_EXTEND_MASK;
2986         ixgbevf_vlan_offload_set(dev, mask);
2987
2988         ixgbevf_dev_rxtx_start(dev);
2989
2990         return 0;
2991 }
2992
2993 static void
2994 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2995 {
2996         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2997
2998         PMD_INIT_FUNC_TRACE();
2999
3000         hw->adapter_stopped = TRUE;
3001         ixgbe_stop_adapter(hw);
3002
3003         /*
3004           * Clear what we set, but we still keep shadow_vfta to
3005           * restore after device starts
3006           */
3007         ixgbevf_set_vfta_all(dev,0);
3008
3009         /* Clear stored conf */
3010         dev->data->scattered_rx = 0;
3011
3012         ixgbe_dev_clear_queues(dev);
3013 }
3014
3015 static void
3016 ixgbevf_dev_close(struct rte_eth_dev *dev)
3017 {
3018         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3019
3020         PMD_INIT_FUNC_TRACE();
3021
3022         ixgbe_reset_hw(hw);
3023
3024         ixgbevf_dev_stop(dev);
3025
3026         /* reprogram the RAR[0] in case user changed it. */
3027         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3028 }
3029
3030 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3031 {
3032         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3033         struct ixgbe_vfta * shadow_vfta =
3034                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3035         int i = 0, j = 0, vfta = 0, mask = 1;
3036
3037         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3038                 vfta = shadow_vfta->vfta[i];
3039                 if(vfta){
3040                         mask = 1;
3041                         for (j = 0; j < 32; j++){
3042                                 if(vfta & mask)
3043                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3044                                 mask<<=1;
3045                         }
3046                 }
3047         }
3048
3049 }
3050
3051 static int
3052 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3053 {
3054         struct ixgbe_hw *hw =
3055                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3056         struct ixgbe_vfta * shadow_vfta =
3057                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3058         uint32_t vid_idx = 0;
3059         uint32_t vid_bit = 0;
3060         int ret = 0;
3061
3062         PMD_INIT_FUNC_TRACE();
3063
3064         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3065         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3066         if(ret){
3067                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3068                 return ret;
3069         }
3070         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3071         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3072
3073         /* Save what we set and retore it after device reset */
3074         if (on)
3075                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3076         else
3077                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3078
3079         return 0;
3080 }
3081
3082 static void
3083 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3084 {
3085         struct ixgbe_hw *hw =
3086                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3087         uint32_t ctrl;
3088
3089         PMD_INIT_FUNC_TRACE();
3090
3091         if(queue >= hw->mac.max_rx_queues)
3092                 return;
3093
3094         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3095         if(on)
3096                 ctrl |= IXGBE_RXDCTL_VME;
3097         else
3098                 ctrl &= ~IXGBE_RXDCTL_VME;
3099         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3100
3101         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3102 }
3103
3104 static void
3105 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3106 {
3107         struct ixgbe_hw *hw =
3108                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3109         uint16_t i;
3110         int on = 0;
3111
3112         /* VF function only support hw strip feature, others are not support */
3113         if(mask & ETH_VLAN_STRIP_MASK){
3114                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3115
3116                 for(i=0; i < hw->mac.max_rx_queues; i++)
3117                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3118         }
3119 }
3120
3121 static int
3122 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3123 {
3124         uint32_t reg_val;
3125
3126         /* we only need to do this if VMDq is enabled */
3127         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3128         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3129                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3130                 return (-1);
3131         }
3132
3133         return 0;
3134 }
3135
3136 static uint32_t
3137 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3138 {
3139         uint32_t vector = 0;
3140         switch (hw->mac.mc_filter_type) {
3141         case 0:   /* use bits [47:36] of the address */
3142                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3143                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3144                 break;
3145         case 1:   /* use bits [46:35] of the address */
3146                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3147                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3148                 break;
3149         case 2:   /* use bits [45:34] of the address */
3150                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3151                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3152                 break;
3153         case 3:   /* use bits [43:32] of the address */
3154                 vector = ((uc_addr->addr_bytes[4]) |
3155                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3156                 break;
3157         default:  /* Invalid mc_filter_type */
3158                 break;
3159         }
3160
3161         /* vector can only be 12-bits or boundary will be exceeded */
3162         vector &= 0xFFF;
3163         return vector;
3164 }
3165
3166 static int
3167 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3168                                uint8_t on)
3169 {
3170         uint32_t vector;
3171         uint32_t uta_idx;
3172         uint32_t reg_val;
3173         uint32_t uta_shift;
3174         uint32_t rc;
3175         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3176         const uint32_t ixgbe_uta_bit_shift = 5;
3177         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3178         const uint32_t bit1 = 0x1;
3179
3180         struct ixgbe_hw *hw =
3181                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3182         struct ixgbe_uta_info *uta_info =
3183                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3184
3185         /* The UTA table only exists on 82599 hardware and newer */
3186         if (hw->mac.type < ixgbe_mac_82599EB)
3187                 return (-ENOTSUP);
3188
3189         vector = ixgbe_uta_vector(hw,mac_addr);
3190         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3191         uta_shift = vector & ixgbe_uta_bit_mask;
3192
3193         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3194         if(rc == on)
3195                 return 0;
3196
3197         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3198         if (on) {
3199                 uta_info->uta_in_use++;
3200                 reg_val |= (bit1 << uta_shift);
3201                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3202         } else {
3203                 uta_info->uta_in_use--;
3204                 reg_val &= ~(bit1 << uta_shift);
3205                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3206         }
3207
3208         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3209
3210         if (uta_info->uta_in_use > 0)
3211                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3212                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3213         else
3214                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3215
3216         return 0;
3217 }
3218
3219 static int
3220 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3221 {
3222         int i;
3223         struct ixgbe_hw *hw =
3224                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3225         struct ixgbe_uta_info *uta_info =
3226                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3227
3228         /* The UTA table only exists on 82599 hardware and newer */
3229         if (hw->mac.type < ixgbe_mac_82599EB)
3230                 return (-ENOTSUP);
3231
3232         if(on) {
3233                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3234                         uta_info->uta_shadow[i] = ~0;
3235                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3236                 }
3237         } else {
3238                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3239                         uta_info->uta_shadow[i] = 0;
3240                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3241                 }
3242         }
3243         return 0;
3244
3245 }
3246
3247 uint32_t
3248 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3249 {
3250         uint32_t new_val = orig_val;
3251
3252         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3253                 new_val |= IXGBE_VMOLR_AUPE;
3254         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3255                 new_val |= IXGBE_VMOLR_ROMPE;
3256         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3257                 new_val |= IXGBE_VMOLR_ROPE;
3258         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3259                 new_val |= IXGBE_VMOLR_BAM;
3260         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3261                 new_val |= IXGBE_VMOLR_MPE;
3262
3263         return new_val;
3264 }
3265
3266 static int
3267 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3268                                uint16_t rx_mask, uint8_t on)
3269 {
3270         int val = 0;
3271
3272         struct ixgbe_hw *hw =
3273                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3274         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3275
3276         if (hw->mac.type == ixgbe_mac_82598EB) {
3277                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3278                              " on 82599 hardware and newer");
3279                 return (-ENOTSUP);
3280         }
3281         if (ixgbe_vmdq_mode_check(hw) < 0)
3282                 return (-ENOTSUP);
3283
3284         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3285
3286         if (on)
3287                 vmolr |= val;
3288         else
3289                 vmolr &= ~val;
3290
3291         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3292
3293         return 0;
3294 }
3295
3296 static int
3297 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3298 {
3299         uint32_t reg,addr;
3300         uint32_t val;
3301         const uint8_t bit1 = 0x1;
3302
3303         struct ixgbe_hw *hw =
3304                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3305
3306         if (ixgbe_vmdq_mode_check(hw) < 0)
3307                 return (-ENOTSUP);
3308
3309         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3310         reg = IXGBE_READ_REG(hw, addr);
3311         val = bit1 << pool;
3312
3313         if (on)
3314                 reg |= val;
3315         else
3316                 reg &= ~val;
3317
3318         IXGBE_WRITE_REG(hw, addr,reg);
3319
3320         return 0;
3321 }
3322
3323 static int
3324 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3325 {
3326         uint32_t reg,addr;
3327         uint32_t val;
3328         const uint8_t bit1 = 0x1;
3329
3330         struct ixgbe_hw *hw =
3331                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3332
3333         if (ixgbe_vmdq_mode_check(hw) < 0)
3334                 return (-ENOTSUP);
3335
3336         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3337         reg = IXGBE_READ_REG(hw, addr);
3338         val = bit1 << pool;
3339
3340         if (on)
3341                 reg |= val;
3342         else
3343                 reg &= ~val;
3344
3345         IXGBE_WRITE_REG(hw, addr,reg);
3346
3347         return 0;
3348 }
3349
3350 static int
3351 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3352                         uint64_t pool_mask, uint8_t vlan_on)
3353 {
3354         int ret = 0;
3355         uint16_t pool_idx;
3356         struct ixgbe_hw *hw =
3357                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3358
3359         if (ixgbe_vmdq_mode_check(hw) < 0)
3360                 return (-ENOTSUP);
3361         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3362                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3363                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3364                         if (ret < 0)
3365                                 return ret;
3366         }
3367
3368         return ret;
3369 }
3370
3371 static int
3372 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3373                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3374                         uint8_t rule_id, uint8_t on)
3375 {
3376         uint32_t mr_ctl,vlvf;
3377         uint32_t mp_lsb = 0;
3378         uint32_t mv_msb = 0;
3379         uint32_t mv_lsb = 0;
3380         uint32_t mp_msb = 0;
3381         uint8_t i = 0;
3382         int reg_index = 0;
3383         uint64_t vlan_mask = 0;
3384
3385         const uint8_t pool_mask_offset = 32;
3386         const uint8_t vlan_mask_offset = 32;
3387         const uint8_t dst_pool_offset = 8;
3388         const uint8_t rule_mr_offset  = 4;
3389         const uint8_t mirror_rule_mask= 0x0F;
3390
3391         struct ixgbe_mirror_info *mr_info =
3392                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3393         struct ixgbe_hw *hw =
3394                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3395
3396         if (ixgbe_vmdq_mode_check(hw) < 0)
3397                 return (-ENOTSUP);
3398
3399         /* Check if vlan mask is valid */
3400         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3401                 if (mirror_conf->vlan.vlan_mask == 0)
3402                         return (-EINVAL);
3403         }
3404
3405         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3406         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3407                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3408                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3409                                 /* search vlan id related pool vlan filter index */
3410                                 reg_index = ixgbe_find_vlvf_slot(hw,
3411                                                 mirror_conf->vlan.vlan_id[i]);
3412                                 if(reg_index < 0)
3413                                         return (-EINVAL);
3414                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3415                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3416                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3417                                                 == mirror_conf->vlan.vlan_id[i]))
3418                                         vlan_mask |= (1ULL << reg_index);
3419                                 else
3420                                         return (-EINVAL);
3421                         }
3422                 }
3423
3424                 if (on) {
3425                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3426                         mv_msb = vlan_mask >> vlan_mask_offset;
3427
3428                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3429                                                 mirror_conf->vlan.vlan_mask;
3430                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3431                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3432                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3433                                                 mirror_conf->vlan.vlan_id[i];
3434                         }
3435                 } else {
3436                         mv_lsb = 0;
3437                         mv_msb = 0;
3438                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3439                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3440                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3441                 }
3442         }
3443
3444         /*
3445          * if enable pool mirror, write related pool mask register,if disable
3446          * pool mirror, clear PFMRVM register
3447          */
3448         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3449                 if (on) {
3450                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3451                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3452                         mr_info->mr_conf[rule_id].pool_mask =
3453                                         mirror_conf->pool_mask;
3454
3455                 } else {
3456                         mp_lsb = 0;
3457                         mp_msb = 0;
3458                         mr_info->mr_conf[rule_id].pool_mask = 0;
3459                 }
3460         }
3461
3462         /* read  mirror control register and recalculate it */
3463         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3464
3465         if (on) {
3466                 mr_ctl |= mirror_conf->rule_type_mask;
3467                 mr_ctl &= mirror_rule_mask;
3468                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3469         } else
3470                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3471
3472         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3473         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3474
3475         /* write mirrror control  register */
3476         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3477
3478         /* write pool mirrror control  register */
3479         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3480                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3481                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3482                                 mp_msb);
3483         }
3484         /* write VLAN mirrror control  register */
3485         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3486                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3487                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3488                                 mv_msb);
3489         }
3490
3491         return 0;
3492 }
3493
3494 static int
3495 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3496 {
3497         int mr_ctl = 0;
3498         uint32_t lsb_val = 0;
3499         uint32_t msb_val = 0;
3500         const uint8_t rule_mr_offset = 4;
3501
3502         struct ixgbe_hw *hw =
3503                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3504         struct ixgbe_mirror_info *mr_info =
3505                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3506
3507         if (ixgbe_vmdq_mode_check(hw) < 0)
3508                 return (-ENOTSUP);
3509
3510         memset(&mr_info->mr_conf[rule_id], 0,
3511                 sizeof(struct rte_eth_vmdq_mirror_conf));
3512
3513         /* clear PFVMCTL register */
3514         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3515
3516         /* clear pool mask register */
3517         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3518         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3519
3520         /* clear vlan mask register */
3521         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3522         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3523
3524         return 0;
3525 }
3526
3527 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3528         uint16_t queue_idx, uint16_t tx_rate)
3529 {
3530         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3531         uint32_t rf_dec, rf_int;
3532         uint32_t bcnrc_val;
3533         uint16_t link_speed = dev->data->dev_link.link_speed;
3534
3535         if (queue_idx >= hw->mac.max_tx_queues)
3536                 return -EINVAL;
3537
3538         if (tx_rate != 0) {
3539                 /* Calculate the rate factor values to set */
3540                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3541                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3542                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3543
3544                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3545                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3546                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3547                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3548         } else {
3549                 bcnrc_val = 0;
3550         }
3551
3552         /*
3553          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3554          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3555          * set as 0x4.
3556          */
3557         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3558                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3559                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3560                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3561                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3562         else
3563                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3564                         IXGBE_MMW_SIZE_DEFAULT);
3565
3566         /* Set RTTBCNRC of queue X */
3567         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3568         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3569         IXGBE_WRITE_FLUSH(hw);
3570
3571         return 0;
3572 }
3573
3574 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3575         uint16_t tx_rate, uint64_t q_msk)
3576 {
3577         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3578         struct ixgbe_vf_info *vfinfo =
3579                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3580         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3581         uint32_t queue_stride =
3582                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3583         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3584         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3585         uint16_t total_rate = 0;
3586
3587         if (queue_end >= hw->mac.max_tx_queues)
3588                 return -EINVAL;
3589
3590         if (vfinfo != NULL) {
3591                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3592                         if (vf_idx == vf)
3593                                 continue;
3594                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3595                                 idx++)
3596                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3597                 }
3598         } else
3599                 return -EINVAL;
3600
3601         /* Store tx_rate for this vf. */
3602         for (idx = 0; idx < nb_q_per_pool; idx++) {
3603                 if (((uint64_t)0x1 << idx) & q_msk) {
3604                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3605                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3606                         total_rate += tx_rate;
3607                 }
3608         }
3609
3610         if (total_rate > dev->data->dev_link.link_speed) {
3611                 /*
3612                  * Reset stored TX rate of the VF if it causes exceed
3613                  * link speed.
3614                  */
3615                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3616                 return -EINVAL;
3617         }
3618
3619         /* Set RTTBCNRC of each queue/pool for vf X  */
3620         for (; queue_idx <= queue_end; queue_idx++) {
3621                 if (0x1 & q_msk)
3622                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3623                 q_msk = q_msk >> 1;
3624         }
3625
3626         return 0;
3627 }
3628
3629 static void
3630 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3631                      __attribute__((unused)) uint32_t index,
3632                      __attribute__((unused)) uint32_t pool)
3633 {
3634         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3635         int diag;
3636
3637         /*
3638          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3639          * operation. Trap this case to avoid exhausting the [very limited]
3640          * set of PF resources used to store VF MAC addresses.
3641          */
3642         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3643                 return;
3644         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3645         if (diag == 0)
3646                 return;
3647         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3648 }
3649
3650 static void
3651 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3652 {
3653         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3654         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3655         struct ether_addr *mac_addr;
3656         uint32_t i;
3657         int diag;
3658
3659         /*
3660          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3661          * not support the deletion of a given MAC address.
3662          * Instead, it imposes to delete all MAC addresses, then to add again
3663          * all MAC addresses with the exception of the one to be deleted.
3664          */
3665         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3666
3667         /*
3668          * Add again all MAC addresses, with the exception of the deleted one
3669          * and of the permanent MAC address.
3670          */
3671         for (i = 0, mac_addr = dev->data->mac_addrs;
3672              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3673                 /* Skip the deleted MAC address */
3674                 if (i == index)
3675                         continue;
3676                 /* Skip NULL MAC addresses */
3677                 if (is_zero_ether_addr(mac_addr))
3678                         continue;
3679                 /* Skip the permanent MAC address */
3680                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3681                         continue;
3682                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3683                 if (diag != 0)
3684                         PMD_DRV_LOG(ERR,
3685                                     "Adding again MAC address "
3686                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3687                                     "diag=%d",
3688                                     mac_addr->addr_bytes[0],
3689                                     mac_addr->addr_bytes[1],
3690                                     mac_addr->addr_bytes[2],
3691                                     mac_addr->addr_bytes[3],
3692                                     mac_addr->addr_bytes[4],
3693                                     mac_addr->addr_bytes[5],
3694                                     diag);
3695         }
3696 }
3697
3698 #define MAC_TYPE_FILTER_SUP(type)    do {\
3699         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
3700                 (type) != ixgbe_mac_X550)\
3701                 return -ENOTSUP;\
3702 } while (0)
3703
3704 static int
3705 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
3706                         struct rte_eth_syn_filter *filter,
3707                         bool add)
3708 {
3709         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3710         uint32_t synqf;
3711
3712         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
3713                 return -EINVAL;
3714
3715         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3716
3717         if (add) {
3718                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3719                         return -EINVAL;
3720                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3721                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3722
3723                 if (filter->hig_pri)
3724                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
3725                 else
3726                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3727         } else {
3728                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
3729                         return -ENOENT;
3730                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3731         }
3732         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3733         IXGBE_WRITE_FLUSH(hw);
3734         return 0;
3735 }
3736
3737 static int
3738 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
3739                         struct rte_eth_syn_filter *filter)
3740 {
3741         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3742         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3743
3744         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3745                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3746                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3747                 return 0;
3748         }
3749         return -ENOENT;
3750 }
3751
3752 static int
3753 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
3754                         enum rte_filter_op filter_op,
3755                         void *arg)
3756 {
3757         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3758         int ret;
3759
3760         MAC_TYPE_FILTER_SUP(hw->mac.type);
3761
3762         if (filter_op == RTE_ETH_FILTER_NOP)
3763                 return 0;
3764
3765         if (arg == NULL) {
3766                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3767                             filter_op);
3768                 return -EINVAL;
3769         }
3770
3771         switch (filter_op) {
3772         case RTE_ETH_FILTER_ADD:
3773                 ret = ixgbe_syn_filter_set(dev,
3774                                 (struct rte_eth_syn_filter *)arg,
3775                                 TRUE);
3776                 break;
3777         case RTE_ETH_FILTER_DELETE:
3778                 ret = ixgbe_syn_filter_set(dev,
3779                                 (struct rte_eth_syn_filter *)arg,
3780                                 FALSE);
3781                 break;
3782         case RTE_ETH_FILTER_GET:
3783                 ret = ixgbe_syn_filter_get(dev,
3784                                 (struct rte_eth_syn_filter *)arg);
3785                 break;
3786         default:
3787                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3788                 ret = -EINVAL;
3789                 break;
3790         }
3791
3792         return ret;
3793 }
3794
3795
3796 static inline enum ixgbe_5tuple_protocol
3797 convert_protocol_type(uint8_t protocol_value)
3798 {
3799         if (protocol_value == IPPROTO_TCP)
3800                 return IXGBE_FILTER_PROTOCOL_TCP;
3801         else if (protocol_value == IPPROTO_UDP)
3802                 return IXGBE_FILTER_PROTOCOL_UDP;
3803         else if (protocol_value == IPPROTO_SCTP)
3804                 return IXGBE_FILTER_PROTOCOL_SCTP;
3805         else
3806                 return IXGBE_FILTER_PROTOCOL_NONE;
3807 }
3808
3809 /*
3810  * add a 5tuple filter
3811  *
3812  * @param
3813  * dev: Pointer to struct rte_eth_dev.
3814  * index: the index the filter allocates.
3815  * filter: ponter to the filter that will be added.
3816  * rx_queue: the queue id the filter assigned to.
3817  *
3818  * @return
3819  *    - On success, zero.
3820  *    - On failure, a negative value.
3821  */
3822 static int
3823 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3824                         struct ixgbe_5tuple_filter *filter)
3825 {
3826         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3827         struct ixgbe_filter_info *filter_info =
3828                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3829         int i, idx, shift;
3830         uint32_t ftqf, sdpqf;
3831         uint32_t l34timir = 0;
3832         uint8_t mask = 0xff;
3833
3834         /*
3835          * look for an unused 5tuple filter index,
3836          * and insert the filter to list.
3837          */
3838         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
3839                 idx = i / (sizeof(uint32_t) * NBBY);
3840                 shift = i % (sizeof(uint32_t) * NBBY);
3841                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3842                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3843                         filter->index = i;
3844                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3845                                           filter,
3846                                           entries);
3847                         break;
3848                 }
3849         }
3850         if (i >= IXGBE_MAX_FTQF_FILTERS) {
3851                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3852                 return -ENOSYS;
3853         }
3854
3855         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
3856                                 IXGBE_SDPQF_DSTPORT_SHIFT);
3857         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
3858
3859         ftqf = (uint32_t)(filter->filter_info.proto &
3860                 IXGBE_FTQF_PROTOCOL_MASK);
3861         ftqf |= (uint32_t)((filter->filter_info.priority &
3862                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
3863         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3864                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3865         if (filter->filter_info.dst_ip_mask == 0)
3866                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3867         if (filter->filter_info.src_port_mask == 0)
3868                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3869         if (filter->filter_info.dst_port_mask == 0)
3870                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3871         if (filter->filter_info.proto_mask == 0)
3872                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3873         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3874         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3875         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3876
3877         IXGBE_WRITE_REG(hw, IXGBE_DAQF(idx), filter->filter_info.dst_ip);
3878         IXGBE_WRITE_REG(hw, IXGBE_SAQF(idx), filter->filter_info.src_ip);
3879         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(idx), sdpqf);
3880         IXGBE_WRITE_REG(hw, IXGBE_FTQF(idx), ftqf);
3881
3882         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3883         l34timir |= (uint32_t)(filter->queue <<
3884                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
3885         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
3886         return 0;
3887 }
3888
3889 /*
3890  * remove a 5tuple filter
3891  *
3892  * @param
3893  * dev: Pointer to struct rte_eth_dev.
3894  * filter: the pointer of the filter will be removed.
3895  */
3896 static void
3897 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3898                         struct ixgbe_5tuple_filter *filter)
3899 {
3900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3901         struct ixgbe_filter_info *filter_info =
3902                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3903         uint16_t index = filter->index;
3904
3905         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3906                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3907         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3908         rte_free(filter);
3909
3910         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3911         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3912         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3913         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3914         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3915 }
3916
3917 static int
3918 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3919 {
3920         struct ixgbe_hw *hw;
3921         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3922
3923         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3924
3925         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3926                 return -EINVAL;
3927
3928         /* refuse mtu that requires the support of scattered packets when this
3929          * feature has not been enabled before. */
3930         if (!dev->data->scattered_rx &&
3931             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3932              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3933                 return -EINVAL;
3934
3935         /*
3936          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3937          * request of the version 2.0 of the mailbox API.
3938          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3939          * of the mailbox API.
3940          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3941          * prior to 3.11.33 which contains the following change:
3942          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3943          */
3944         ixgbevf_rlpml_set_vf(hw, max_frame);
3945
3946         /* update max frame size */
3947         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
3948         return 0;
3949 }
3950
3951 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3952         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
3953                 return -ENOTSUP;\
3954 } while (0)
3955
3956 static inline struct ixgbe_5tuple_filter *
3957 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
3958                         struct ixgbe_5tuple_filter_info *key)
3959 {
3960         struct ixgbe_5tuple_filter *it;
3961
3962         TAILQ_FOREACH(it, filter_list, entries) {
3963                 if (memcmp(key, &it->filter_info,
3964                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
3965                         return it;
3966                 }
3967         }
3968         return NULL;
3969 }
3970
3971 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
3972 static inline int
3973 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3974                         struct ixgbe_5tuple_filter_info *filter_info)
3975 {
3976         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3977                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3978                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3979                 return -EINVAL;
3980
3981         switch (filter->dst_ip_mask) {
3982         case UINT32_MAX:
3983                 filter_info->dst_ip_mask = 0;
3984                 filter_info->dst_ip = filter->dst_ip;
3985                 break;
3986         case 0:
3987                 filter_info->dst_ip_mask = 1;
3988                 break;
3989         default:
3990                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3991                 return -EINVAL;
3992         }
3993
3994         switch (filter->src_ip_mask) {
3995         case UINT32_MAX:
3996                 filter_info->src_ip_mask = 0;
3997                 filter_info->src_ip = filter->src_ip;
3998                 break;
3999         case 0:
4000                 filter_info->src_ip_mask = 1;
4001                 break;
4002         default:
4003                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4004                 return -EINVAL;
4005         }
4006
4007         switch (filter->dst_port_mask) {
4008         case UINT16_MAX:
4009                 filter_info->dst_port_mask = 0;
4010                 filter_info->dst_port = filter->dst_port;
4011                 break;
4012         case 0:
4013                 filter_info->dst_port_mask = 1;
4014                 break;
4015         default:
4016                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4017                 return -EINVAL;
4018         }
4019
4020         switch (filter->src_port_mask) {
4021         case UINT16_MAX:
4022                 filter_info->src_port_mask = 0;
4023                 filter_info->src_port = filter->src_port;
4024                 break;
4025         case 0:
4026                 filter_info->src_port_mask = 1;
4027                 break;
4028         default:
4029                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4030                 return -EINVAL;
4031         }
4032
4033         switch (filter->proto_mask) {
4034         case UINT8_MAX:
4035                 filter_info->proto_mask = 0;
4036                 filter_info->proto =
4037                         convert_protocol_type(filter->proto);
4038                 break;
4039         case 0:
4040                 filter_info->proto_mask = 1;
4041                 break;
4042         default:
4043                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4044                 return -EINVAL;
4045         }
4046
4047         filter_info->priority = (uint8_t)filter->priority;
4048         return 0;
4049 }
4050
4051 /*
4052  * add or delete a ntuple filter
4053  *
4054  * @param
4055  * dev: Pointer to struct rte_eth_dev.
4056  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4057  * add: if true, add filter, if false, remove filter
4058  *
4059  * @return
4060  *    - On success, zero.
4061  *    - On failure, a negative value.
4062  */
4063 static int
4064 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4065                         struct rte_eth_ntuple_filter *ntuple_filter,
4066                         bool add)
4067 {
4068         struct ixgbe_filter_info *filter_info =
4069                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4070         struct ixgbe_5tuple_filter_info filter_5tuple;
4071         struct ixgbe_5tuple_filter *filter;
4072         int ret;
4073
4074         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4075                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4076                 return -EINVAL;
4077         }
4078
4079         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4080         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4081         if (ret < 0)
4082                 return ret;
4083
4084         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4085                                          &filter_5tuple);
4086         if (filter != NULL && add) {
4087                 PMD_DRV_LOG(ERR, "filter exists.");
4088                 return -EEXIST;
4089         }
4090         if (filter == NULL && !add) {
4091                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4092                 return -ENOENT;
4093         }
4094
4095         if (add) {
4096                 filter = rte_zmalloc("ixgbe_5tuple_filter",
4097                                 sizeof(struct ixgbe_5tuple_filter), 0);
4098                 if (filter == NULL)
4099                         return -ENOMEM;
4100                 (void)rte_memcpy(&filter->filter_info,
4101                                  &filter_5tuple,
4102                                  sizeof(struct ixgbe_5tuple_filter_info));
4103                 filter->queue = ntuple_filter->queue;
4104                 ret = ixgbe_add_5tuple_filter(dev, filter);
4105                 if (ret < 0) {
4106                         rte_free(filter);
4107                         return ret;
4108                 }
4109         } else
4110                 ixgbe_remove_5tuple_filter(dev, filter);
4111
4112         return 0;
4113 }
4114
4115 /*
4116  * get a ntuple filter
4117  *
4118  * @param
4119  * dev: Pointer to struct rte_eth_dev.
4120  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4121  *
4122  * @return
4123  *    - On success, zero.
4124  *    - On failure, a negative value.
4125  */
4126 static int
4127 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4128                         struct rte_eth_ntuple_filter *ntuple_filter)
4129 {
4130         struct ixgbe_filter_info *filter_info =
4131                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4132         struct ixgbe_5tuple_filter_info filter_5tuple;
4133         struct ixgbe_5tuple_filter *filter;
4134         int ret;
4135
4136         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4137                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4138                 return -EINVAL;
4139         }
4140
4141         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4142         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4143         if (ret < 0)
4144                 return ret;
4145
4146         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4147                                          &filter_5tuple);
4148         if (filter == NULL) {
4149                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4150                 return -ENOENT;
4151         }
4152         ntuple_filter->queue = filter->queue;
4153         return 0;
4154 }
4155
4156 /*
4157  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4158  * @dev: pointer to rte_eth_dev structure
4159  * @filter_op:operation will be taken.
4160  * @arg: a pointer to specific structure corresponding to the filter_op
4161  *
4162  * @return
4163  *    - On success, zero.
4164  *    - On failure, a negative value.
4165  */
4166 static int
4167 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4168                                 enum rte_filter_op filter_op,
4169                                 void *arg)
4170 {
4171         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4172         int ret;
4173
4174         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4175
4176         if (filter_op == RTE_ETH_FILTER_NOP)
4177                 return 0;
4178
4179         if (arg == NULL) {
4180                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4181                             filter_op);
4182                 return -EINVAL;
4183         }
4184
4185         switch (filter_op) {
4186         case RTE_ETH_FILTER_ADD:
4187                 ret = ixgbe_add_del_ntuple_filter(dev,
4188                         (struct rte_eth_ntuple_filter *)arg,
4189                         TRUE);
4190                 break;
4191         case RTE_ETH_FILTER_DELETE:
4192                 ret = ixgbe_add_del_ntuple_filter(dev,
4193                         (struct rte_eth_ntuple_filter *)arg,
4194                         FALSE);
4195                 break;
4196         case RTE_ETH_FILTER_GET:
4197                 ret = ixgbe_get_ntuple_filter(dev,
4198                         (struct rte_eth_ntuple_filter *)arg);
4199                 break;
4200         default:
4201                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4202                 ret = -EINVAL;
4203                 break;
4204         }
4205         return ret;
4206 }
4207
4208 static inline int
4209 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4210                         uint16_t ethertype)
4211 {
4212         int i;
4213
4214         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4215                 if (filter_info->ethertype_filters[i] == ethertype &&
4216                     (filter_info->ethertype_mask & (1 << i)))
4217                         return i;
4218         }
4219         return -1;
4220 }
4221
4222 static inline int
4223 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4224                         uint16_t ethertype)
4225 {
4226         int i;
4227
4228         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4229                 if (!(filter_info->ethertype_mask & (1 << i))) {
4230                         filter_info->ethertype_mask |= 1 << i;
4231                         filter_info->ethertype_filters[i] = ethertype;
4232                         return i;
4233                 }
4234         }
4235         return -1;
4236 }
4237
4238 static inline int
4239 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4240                         uint8_t idx)
4241 {
4242         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4243                 return -1;
4244         filter_info->ethertype_mask &= ~(1 << idx);
4245         filter_info->ethertype_filters[idx] = 0;
4246         return idx;
4247 }
4248
4249 static int
4250 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4251                         struct rte_eth_ethertype_filter *filter,
4252                         bool add)
4253 {
4254         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4255         struct ixgbe_filter_info *filter_info =
4256                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4257         uint32_t etqf = 0;
4258         uint32_t etqs = 0;
4259         int ret;
4260
4261         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4262                 return -EINVAL;
4263
4264         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4265                 filter->ether_type == ETHER_TYPE_IPv6) {
4266                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4267                         " ethertype filter.", filter->ether_type);
4268                 return -EINVAL;
4269         }
4270
4271         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4272                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4273                 return -EINVAL;
4274         }
4275         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4276                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4277                 return -EINVAL;
4278         }
4279
4280         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4281         if (ret >= 0 && add) {
4282                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4283                             filter->ether_type);
4284                 return -EEXIST;
4285         }
4286         if (ret < 0 && !add) {
4287                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4288                             filter->ether_type);
4289                 return -ENOENT;
4290         }
4291
4292         if (add) {
4293                 ret = ixgbe_ethertype_filter_insert(filter_info,
4294                         filter->ether_type);
4295                 if (ret < 0) {
4296                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4297                         return -ENOSYS;
4298                 }
4299                 etqf = IXGBE_ETQF_FILTER_EN;
4300                 etqf |= (uint32_t)filter->ether_type;
4301                 etqs |= (uint32_t)((filter->queue <<
4302                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4303                                     IXGBE_ETQS_RX_QUEUE);
4304                 etqs |= IXGBE_ETQS_QUEUE_EN;
4305         } else {
4306                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4307                 if (ret < 0)
4308                         return -ENOSYS;
4309         }
4310         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4311         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4312         IXGBE_WRITE_FLUSH(hw);
4313
4314         return 0;
4315 }
4316
4317 static int
4318 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4319                         struct rte_eth_ethertype_filter *filter)
4320 {
4321         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4322         struct ixgbe_filter_info *filter_info =
4323                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4324         uint32_t etqf, etqs;
4325         int ret;
4326
4327         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4328         if (ret < 0) {
4329                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4330                             filter->ether_type);
4331                 return -ENOENT;
4332         }
4333
4334         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4335         if (etqf & IXGBE_ETQF_FILTER_EN) {
4336                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4337                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4338                 filter->flags = 0;
4339                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4340                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4341                 return 0;
4342         }
4343         return -ENOENT;
4344 }
4345
4346 /*
4347  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4348  * @dev: pointer to rte_eth_dev structure
4349  * @filter_op:operation will be taken.
4350  * @arg: a pointer to specific structure corresponding to the filter_op
4351  */
4352 static int
4353 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4354                                 enum rte_filter_op filter_op,
4355                                 void *arg)
4356 {
4357         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4358         int ret;
4359
4360         MAC_TYPE_FILTER_SUP(hw->mac.type);
4361
4362         if (filter_op == RTE_ETH_FILTER_NOP)
4363                 return 0;
4364
4365         if (arg == NULL) {
4366                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4367                             filter_op);
4368                 return -EINVAL;
4369         }
4370
4371         switch (filter_op) {
4372         case RTE_ETH_FILTER_ADD:
4373                 ret = ixgbe_add_del_ethertype_filter(dev,
4374                         (struct rte_eth_ethertype_filter *)arg,
4375                         TRUE);
4376                 break;
4377         case RTE_ETH_FILTER_DELETE:
4378                 ret = ixgbe_add_del_ethertype_filter(dev,
4379                         (struct rte_eth_ethertype_filter *)arg,
4380                         FALSE);
4381                 break;
4382         case RTE_ETH_FILTER_GET:
4383                 ret = ixgbe_get_ethertype_filter(dev,
4384                         (struct rte_eth_ethertype_filter *)arg);
4385                 break;
4386         default:
4387                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4388                 ret = -EINVAL;
4389                 break;
4390         }
4391         return ret;
4392 }
4393
4394 static int
4395 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4396                      enum rte_filter_type filter_type,
4397                      enum rte_filter_op filter_op,
4398                      void *arg)
4399 {
4400         int ret = -EINVAL;
4401
4402         switch (filter_type) {
4403         case RTE_ETH_FILTER_NTUPLE:
4404                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4405                 break;
4406         case RTE_ETH_FILTER_ETHERTYPE:
4407                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4408                 break;
4409         case RTE_ETH_FILTER_SYN:
4410                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4411                 break;
4412         case RTE_ETH_FILTER_FDIR:
4413                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4414                 break;
4415         default:
4416                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4417                                                         filter_type);
4418                 break;
4419         }
4420
4421         return ret;
4422 }
4423
4424 static struct rte_driver rte_ixgbe_driver = {
4425         .type = PMD_PDEV,
4426         .init = rte_ixgbe_pmd_init,
4427 };
4428
4429 static struct rte_driver rte_ixgbevf_driver = {
4430         .type = PMD_PDEV,
4431         .init = rte_ixgbevf_pmd_init,
4432 };
4433
4434 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4435 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);