lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_tailq.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_dev.h>
  62
  63 #include "ixgbe_logs.h"
  64 #include "ixgbe/ixgbe_api.h"
  65 #include "ixgbe/ixgbe_vf.h"
  66 #include "ixgbe/ixgbe_common.h"
  67 #include "ixgbe_ethdev.h"
  68 #include "ixgbe_bypass.h"
  69
  70 /*
  71  * High threshold controlling when to start sending XOFF frames. Must be at
  72  * least 8 bytes less than receive packet buffer size. This value is in units
  73  * of 1024 bytes.
  74  */
  75 #define IXGBE_FC_HI    0x80
  76
  77 /*
  78  * Low threshold controlling when to start sending XON frames. This value is
  79  * in units of 1024 bytes.
  80  */
  81 #define IXGBE_FC_LO    0x40
  82
  83 /* Timer value included in XOFF frames. */
  84 #define IXGBE_FC_PAUSE 0x680
  85
  86 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  87 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  88 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  89
  90
  91 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  92
  93 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  94
  95 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
  96                 struct rte_eth_dev *eth_dev);
  97 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
  98 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
  99 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 100 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 101 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 102 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 103 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 104 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 105 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 106                                 int wait_to_complete);
 107 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_stats *stats);
 109 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 110 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 111                                              uint16_t queue_id,
 112                                              uint8_t stat_idx,
 113                                              uint8_t is_rx);
 114 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 115                                 struct rte_eth_dev_info *dev_info);
 116 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 117                 uint16_t vlan_id, int on);
 118 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 119 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 120                 uint16_t queue, bool on);
 121 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 122                 int on);
 123 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 124 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 125 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 126 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 127 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 128
 129 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 130 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 131 static int  ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 132                 struct rte_eth_fc_conf *fc_conf);
 133 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 134                 struct rte_eth_pfc_conf *pfc_conf);
 135 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 136                 struct rte_eth_rss_reta *reta_conf);
 137 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 138                 struct rte_eth_rss_reta *reta_conf);
 139 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 140 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 141 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 142 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 144                 void *param);
 145 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 146 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 147                 uint32_t index, uint32_t pool);
 148 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 149 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 150
 151 /* For Virtual Function support */
 152 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 153                 struct rte_eth_dev *eth_dev);
 154 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 155 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 156 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 157 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 158 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 159 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 160                 struct rte_eth_stats *stats);
 161 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 162 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 163                 uint16_t vlan_id, int on);
 164 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 165                 uint16_t queue, int on);
 166 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 167 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 168
 169 /* For Eth VMDQ APIs support */
 170 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 171                 ether_addr* mac_addr,uint8_t on);
 172 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 173 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 174                 uint16_t rx_mask, uint8_t on);
 175 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 176 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 177 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 178                 uint64_t pool_mask,uint8_t vlan_on);
 179 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 180                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 181                 uint8_t rule_id, uint8_t on);
 182 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 183                 uint8_t rule_id);
 184
 185 /*
 186  * Define VF Stats MACRO for Non "cleared on read" register
 187  */
 188 #define UPDATE_VF_STAT(reg, last, cur)                          \
 189 {                                                               \
 190         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 191         cur += latest - last;                                   \
 192         last = latest;                                          \
 193 }
 194
 195 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 196 {                                                                \
 197         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 198         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 199         u64 latest = ((new_msb << 32) | new_lsb);                \
 200         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 201         last = latest;                                           \
 202 }
 203
 204 #define IXGBE_SET_HWSTRIP(h, q) do{\
 205                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 206                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 207                 (h)->bitmap[idx] |= 1 << bit;\
 208         }while(0)
 209
 210 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 211                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 212                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 213                 (h)->bitmap[idx] &= ~(1 << bit);\
 214         }while(0)
 215
 216 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 217                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 218                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 219                 (r) = (h)->bitmap[idx] >> bit & 1;\
 220         }while(0)
 221
 222 /*
 223  * The set of PCI devices this driver supports
 224  */
 225 static struct rte_pci_id pci_id_ixgbe_map[] = {
 226
 227 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 228 #include "rte_pci_dev_ids.h"
 229
 230 { .vendor_id = 0, /* sentinel */ },
 231 };
 232
 233
 234 /*
 235  * The set of PCI devices this driver supports (for 82599 VF)
 236  */
 237 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 238
 239 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 240 #include "rte_pci_dev_ids.h"
 241 { .vendor_id = 0, /* sentinel */ },
 242
 243 };
 244
 245 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 246         .dev_configure        = ixgbe_dev_configure,
 247         .dev_start            = ixgbe_dev_start,
 248         .dev_stop             = ixgbe_dev_stop,
 249         .dev_close            = ixgbe_dev_close,
 250         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 251         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 252         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 253         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 254         .link_update          = ixgbe_dev_link_update,
 255         .stats_get            = ixgbe_dev_stats_get,
 256         .stats_reset          = ixgbe_dev_stats_reset,
 257         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 258         .dev_infos_get        = ixgbe_dev_info_get,
 259         .vlan_filter_set      = ixgbe_vlan_filter_set,
 260         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 261         .vlan_offload_set     = ixgbe_vlan_offload_set,
 262         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 263         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 264         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 265         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 266         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 267         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 268         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 269         .dev_led_on           = ixgbe_dev_led_on,
 270         .dev_led_off          = ixgbe_dev_led_off,
 271         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 272         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 273         .mac_addr_add         = ixgbe_add_rar,
 274         .mac_addr_remove      = ixgbe_remove_rar,
 275         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 276         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 277         .mirror_rule_set        = ixgbe_mirror_rule_set,
 278         .mirror_rule_reset      = ixgbe_mirror_rule_reset,
 279         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 280         .set_vf_rx            = ixgbe_set_pool_rx,
 281         .set_vf_tx            = ixgbe_set_pool_tx,
 282         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 283         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 284         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 285         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 286         .fdir_infos_get               = ixgbe_fdir_info_get,
 287         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 288         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 289         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 290         .fdir_set_masks               = ixgbe_fdir_set_masks,
 291         .reta_update          = ixgbe_dev_rss_reta_update,
 292         .reta_query           = ixgbe_dev_rss_reta_query,
 293 #ifdef RTE_NIC_BYPASS
 294         .bypass_init          = ixgbe_bypass_init,
 295         .bypass_state_set     = ixgbe_bypass_state_store,
 296         .bypass_state_show    = ixgbe_bypass_state_show,
 297         .bypass_event_set     = ixgbe_bypass_event_store,
 298         .bypass_event_show    = ixgbe_bypass_event_show,
 299         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 300         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 301         .bypass_ver_show      = ixgbe_bypass_ver_show,
 302         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 303 #endif /* RTE_NIC_BYPASS */
 304 };
 305
 306 /*
 307  * dev_ops for virtual function, bare necessities for basic vf
 308  * operation have been implemented
 309  */
 310 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 311
 312         .dev_configure        = ixgbevf_dev_configure,
 313         .dev_start            = ixgbevf_dev_start,
 314         .dev_stop             = ixgbevf_dev_stop,
 315         .link_update          = ixgbe_dev_link_update,
 316         .stats_get            = ixgbevf_dev_stats_get,
 317         .stats_reset          = ixgbevf_dev_stats_reset,
 318         .dev_close            = ixgbevf_dev_close,
 319         .dev_infos_get        = ixgbe_dev_info_get,
 320         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 321         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 322         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 323         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 324         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 325         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 326         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 327 };
 328
 329 /**
 330  * Atomically reads the link status information from global
 331  * structure rte_eth_dev.
 332  *
 333  * @param dev
 334  *   - Pointer to the structure rte_eth_dev to read from.
 335  *   - Pointer to the buffer to be saved with the link status.
 336  *
 337  * @return
 338  *   - On success, zero.
 339  *   - On failure, negative value.
 340  */
 341 static inline int
 342 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 343                                 struct rte_eth_link *link)
 344 {
 345         struct rte_eth_link *dst = link;
 346         struct rte_eth_link *src = &(dev->data->dev_link);
 347
 348         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 349                                         *(uint64_t *)src) == 0)
 350                 return -1;
 351
 352         return 0;
 353 }
 354
 355 /**
 356  * Atomically writes the link status information into global
 357  * structure rte_eth_dev.
 358  *
 359  * @param dev
 360  *   - Pointer to the structure rte_eth_dev to read from.
 361  *   - Pointer to the buffer to be saved with the link status.
 362  *
 363  * @return
 364  *   - On success, zero.
 365  *   - On failure, negative value.
 366  */
 367 static inline int
 368 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 369                                 struct rte_eth_link *link)
 370 {
 371         struct rte_eth_link *dst = &(dev->data->dev_link);
 372         struct rte_eth_link *src = link;
 373
 374         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 375                                         *(uint64_t *)src) == 0)
 376                 return -1;
 377
 378         return 0;
 379 }
 380
 381 /*
 382  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 383  */
 384 static inline int
 385 ixgbe_is_sfp(struct ixgbe_hw *hw)
 386 {
 387         switch (hw->phy.type) {
 388         case ixgbe_phy_sfp_avago:
 389         case ixgbe_phy_sfp_ftl:
 390         case ixgbe_phy_sfp_intel:
 391         case ixgbe_phy_sfp_unknown:
 392         case ixgbe_phy_sfp_passive_tyco:
 393         case ixgbe_phy_sfp_passive_unknown:
 394                 return 1;
 395         default:
 396                 return 0;
 397         }
 398 }
 399
 400 static inline int32_t
 401 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 402 {
 403         uint32_t ctrl_ext;
 404         int32_t status;
 405
 406         status = ixgbe_reset_hw(hw);
 407
 408         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 409         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 410         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 411         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 412         IXGBE_WRITE_FLUSH(hw);
 413
 414         return status;
 415 }
 416
 417 static inline void
 418 ixgbe_enable_intr(struct rte_eth_dev *dev)
 419 {
 420         struct ixgbe_interrupt *intr =
 421                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 422         struct ixgbe_hw *hw =
 423                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 424
 425         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 426         IXGBE_WRITE_FLUSH(hw);
 427 }
 428
 429 /*
 430  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 431  */
 432 static void
 433 ixgbe_disable_intr(struct ixgbe_hw *hw)
 434 {
 435         PMD_INIT_FUNC_TRACE();
 436
 437         if (hw->mac.type == ixgbe_mac_82598EB) {
 438                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 439         } else {
 440                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 441                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 442                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 443         }
 444         IXGBE_WRITE_FLUSH(hw);
 445 }
 446
 447 /*
 448  * This function resets queue statistics mapping registers.
 449  * From Niantic datasheet, Initialization of Statistics section:
 450  * "...if software requires the queue counters, the RQSMR and TQSM registers
 451  * must be re-programmed following a device reset.
 452  */
 453 static void
 454 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 455 {
 456         uint32_t i;
 457
 458         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 459                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 460                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 461         }
 462 }
 463
 464
 465 static int
 466 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 467                                   uint16_t queue_id,
 468                                   uint8_t stat_idx,
 469                                   uint8_t is_rx)
 470 {
 471 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 472 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 473 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 474
 475         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 476         struct ixgbe_stat_mapping_registers *stat_mappings =
 477                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 478         uint32_t qsmr_mask = 0;
 479         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 480         uint32_t q_map;
 481         uint8_t n, offset;
 482
 483         if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
 484                 return -ENOSYS;
 485
 486         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
 487                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
 488
 489         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 490         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 491                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
 492                 return -EIO;
 493         }
 494         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 495
 496         /* Now clear any previous stat_idx set */
 497         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 498         if (!is_rx)
 499                 stat_mappings->tqsm[n] &= ~clearing_mask;
 500         else
 501                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 502
 503         q_map = (uint32_t)stat_idx;
 504         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 505         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 506         if (!is_rx)
 507                 stat_mappings->tqsm[n] |= qsmr_mask;
 508         else
 509                 stat_mappings->rqsmr[n] |= qsmr_mask;
 510
 511         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
 512                      "%s[%d] = 0x%08x\n",
 513                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
 514                      is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 515
 516         /* Now write the mapping in the appropriate register */
 517         if (is_rx) {
 518                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
 519                              stat_mappings->rqsmr[n], n);
 520                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 521         }
 522         else {
 523                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
 524                              stat_mappings->tqsm[n], n);
 525                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 526         }
 527         return 0;
 528 }
 529
 530 static void
 531 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 532 {
 533         struct ixgbe_stat_mapping_registers *stat_mappings =
 534                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 535         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 536         int i;
 537
 538         /* write whatever was in stat mapping table to the NIC */
 539         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 540                 /* rx */
 541                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 542
 543                 /* tx */
 544                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 545         }
 546 }
 547
 548 static void
 549 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 550 {
 551         uint8_t i;
 552         struct ixgbe_dcb_tc_config *tc;
 553         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 554
 555         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 556         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 557         for (i = 0; i < dcb_max_tc; i++) {
 558                 tc = &dcb_config->tc_config[i];
 559                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 560                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 561                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 562                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 563                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 564                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 565                 tc->pfc = ixgbe_dcb_pfc_disabled;
 566         }
 567
 568         /* Initialize default user to priority mapping, UPx->TC0 */
 569         tc = &dcb_config->tc_config[0];
 570         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 571         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 572         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 573                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 574                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 575         }
 576         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 577         dcb_config->pfc_mode_enable = false;
 578         dcb_config->vt_mode = true;
 579         dcb_config->round_robin_enable = false;
 580         /* support all DCB capabilities in 82599 */
 581         dcb_config->support.capabilities = 0xFF;
 582
 583         /*we only support 4 Tcs for X540*/
 584         if (hw->mac.type == ixgbe_mac_X540) {
 585                 dcb_config->num_tcs.pg_tcs = 4;
 586                 dcb_config->num_tcs.pfc_tcs = 4;
 587         }
 588 }
 589
 590 /*
 591  * Ensure that all locks are released before first NVM or PHY access
 592  */
 593 static void
 594 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 595 {
 596         uint16_t mask;
 597
 598         /*
 599          * Phy lock should not fail in this early stage. If this is the case,
 600          * it is due to an improper exit of the application.
 601          * So force the release of the faulty lock. Release of common lock
 602          * is done automatically by swfw_sync function.
 603          */
 604         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 605         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 606                    DEBUGOUT1("SWFW phy%d lock released", hw->bus.func);
 607         }
 608         ixgbe_release_swfw_semaphore(hw, mask);
 609
 610         /*
 611          * These ones are more tricky since they are common to all ports; but
 612          * swfw_sync retries last long enough (1s) to be almost sure that if
 613          * lock can not be taken it is due to an improper lock of the
 614          * semaphore.
 615          */
 616         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 617         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 618                    DEBUGOUT("SWFW common locks released");
 619         }
 620         ixgbe_release_swfw_semaphore(hw, mask);
 621 }
 622
 623 /*
 624  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 625  * It returns 0 on success.
 626  */
 627 static int
 628 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 629                      struct rte_eth_dev *eth_dev)
 630 {
 631         struct rte_pci_device *pci_dev;
 632         struct ixgbe_hw *hw =
 633                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 634         struct ixgbe_vfta * shadow_vfta =
 635                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 636         struct ixgbe_hwstrip *hwstrip =
 637                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 638         struct ixgbe_dcb_config *dcb_config =
 639                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 640         uint32_t ctrl_ext;
 641         uint16_t csum;
 642         int diag, i;
 643
 644         PMD_INIT_FUNC_TRACE();
 645
 646         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 647         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 648         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 649
 650         /* for secondary processes, we don't initialise any further as primary
 651          * has already done this work. Only check we don't need a different
 652          * RX function */
 653         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 654                 if (eth_dev->data->scattered_rx)
 655                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 656                 return 0;
 657         }
 658         pci_dev = eth_dev->pci_dev;
 659
 660         /* Vendor and Device ID need to be set before init of shared code */
 661         hw->device_id = pci_dev->id.device_id;
 662         hw->vendor_id = pci_dev->id.vendor_id;
 663         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 664 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
 665         hw->allow_unsupported_sfp = 1;
 666 #endif
 667
 668         /* Initialize the shared code */
 669 #ifdef RTE_NIC_BYPASS
 670         diag = ixgbe_bypass_init_shared_code(hw);
 671 #else
 672         diag = ixgbe_init_shared_code(hw);
 673 #endif /* RTE_NIC_BYPASS */
 674
 675         if (diag != IXGBE_SUCCESS) {
 676                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 677                 return -EIO;
 678         }
 679
 680         /* pick up the PCI bus settings for reporting later */
 681         ixgbe_get_bus_info(hw);
 682
 683         /* Unlock any pending hardware semaphore */
 684         ixgbe_swfw_lock_reset(hw);
 685
 686         /* Initialize DCB configuration*/
 687         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 688         ixgbe_dcb_init(hw,dcb_config);
 689         /* Get Hardware Flow Control setting */
 690         hw->fc.requested_mode = ixgbe_fc_full;
 691         hw->fc.current_mode = ixgbe_fc_full;
 692         hw->fc.pause_time = IXGBE_FC_PAUSE;
 693         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 694                 hw->fc.low_water[i] = IXGBE_FC_LO;
 695                 hw->fc.high_water[i] = IXGBE_FC_HI;
 696         }
 697         hw->fc.send_xon = 1;
 698
 699         /* Make sure we have a good EEPROM before we read from it */
 700         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 701         if (diag != IXGBE_SUCCESS) {
 702                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 703                 return -EIO;
 704         }
 705
 706 #ifdef RTE_NIC_BYPASS
 707         diag = ixgbe_bypass_init_hw(hw);
 708 #else
 709         diag = ixgbe_init_hw(hw);
 710 #endif /* RTE_NIC_BYPASS */
 711
 712         /*
 713          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 714          * is called too soon after the kernel driver unbinding/binding occurs.
 715          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 716          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 717          * also called. See ixgbe_identify_phy_82599(). The reason for the
 718          * failure is not known, and only occuts when virtualisation features
 719          * are disabled in the bios. A delay of 100ms  was found to be enough by
 720          * trial-and-error, and is doubled to be safe.
 721          */
 722         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 723                 rte_delay_ms(200);
 724                 diag = ixgbe_init_hw(hw);
 725         }
 726
 727         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 728                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 729                     "LOM.  Please be aware there may be issues associated "
 730                     "with your hardware.\n If you are experiencing problems "
 731                     "please contact your Intel or hardware representative "
 732                     "who provided you with this hardware.\n");
 733         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 734                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
 735         if (diag) {
 736                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 737                 return -EIO;
 738         }
 739
 740         /* disable interrupt */
 741         ixgbe_disable_intr(hw);
 742
 743         /* reset mappings for queue statistics hw counters*/
 744         ixgbe_reset_qstat_mappings(hw);
 745
 746         /* Allocate memory for storing MAC addresses */
 747         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 748                         hw->mac.num_rar_entries, 0);
 749         if (eth_dev->data->mac_addrs == NULL) {
 750                 PMD_INIT_LOG(ERR,
 751                         "Failed to allocate %u bytes needed to store "
 752                         "MAC addresses",
 753                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 754                 return -ENOMEM;
 755         }
 756         /* Copy the permanent MAC address */
 757         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 758                         &eth_dev->data->mac_addrs[0]);
 759
 760         /* Allocate memory for storing hash filter MAC addresses */
 761         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 762                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 763         if (eth_dev->data->hash_mac_addrs == NULL) {
 764                 PMD_INIT_LOG(ERR,
 765                         "Failed to allocate %d bytes needed to store MAC addresses",
 766                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 767                 return -ENOMEM;
 768         }
 769
 770         /* initialize the vfta */
 771         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 772
 773         /* initialize the hw strip bitmap*/
 774         memset(hwstrip, 0, sizeof(*hwstrip));
 775
 776         /* initialize PF if max_vfs not zero */
 777         ixgbe_pf_host_init(eth_dev);
 778
 779         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 780         /* let hardware know driver is loaded */
 781         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 782         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 783         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 784         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 785         IXGBE_WRITE_FLUSH(hw);
 786
 787         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 788                 PMD_INIT_LOG(DEBUG,
 789                              "MAC: %d, PHY: %d, SFP+: %d<n",
 790                              (int) hw->mac.type, (int) hw->phy.type,
 791                              (int) hw->phy.sfp_type);
 792         else
 793                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
 794                              (int) hw->mac.type, (int) hw->phy.type);
 795
 796         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 797                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 798                         pci_dev->id.device_id);
 799
 800         rte_intr_callback_register(&(pci_dev->intr_handle),
 801                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 802
 803         /* enable uio intr after callback register */
 804         rte_intr_enable(&(pci_dev->intr_handle));
 805
 806         /* enable support intr */
 807         ixgbe_enable_intr(eth_dev);
 808
 809         return 0;
 810 }
 811
 812 static void ixgbevf_get_queue_num(struct ixgbe_hw *hw)
 813 {
 814         /* Traffic classes are not supported by now */
 815         unsigned int tcs, tc;
 816
 817         /*
 818          * Must let PF know we are at mailbox API version 1.1.
 819          * Otherwise PF won't answer properly.
 820          * In case that PF fails to provide Rx/Tx queue number,
 821          * max_tx_queues and max_rx_queues remain to be 1.
 822          */
 823         if (!ixgbevf_negotiate_api_version(hw, ixgbe_mbox_api_11))
 824                 ixgbevf_get_queues(hw, &tcs, &tc);
 825 }
 826
 827 /*
 828  * Virtual Function device init
 829  */
 830 static int
 831 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 832                      struct rte_eth_dev *eth_dev)
 833 {
 834         struct rte_pci_device *pci_dev;
 835         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 836         int diag;
 837         struct ixgbe_vfta * shadow_vfta =
 838                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 839         struct ixgbe_hwstrip *hwstrip =
 840                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 841
 842         PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
 843
 844         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 845         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 846         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 847
 848         /* for secondary processes, we don't initialise any further as primary
 849          * has already done this work. Only check we don't need a different
 850          * RX function */
 851         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 852                 if (eth_dev->data->scattered_rx)
 853                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 854                 return 0;
 855         }
 856
 857         pci_dev = eth_dev->pci_dev;
 858
 859         hw->device_id = pci_dev->id.device_id;
 860         hw->vendor_id = pci_dev->id.vendor_id;
 861         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 862
 863         /* initialize the vfta */
 864         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 865
 866         /* initialize the hw strip bitmap*/
 867         memset(hwstrip, 0, sizeof(*hwstrip));
 868
 869         /* Initialize the shared code */
 870         diag = ixgbe_init_shared_code(hw);
 871         if (diag != IXGBE_SUCCESS) {
 872                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 873                 return -EIO;
 874         }
 875
 876         /* init_mailbox_params */
 877         hw->mbx.ops.init_params(hw);
 878
 879         /* Disable the interrupts for VF */
 880         ixgbevf_intr_disable(hw);
 881
 882         hw->mac.num_rar_entries = hw->mac.max_rx_queues;
 883         diag = hw->mac.ops.reset_hw(hw);
 884
 885         if (diag != IXGBE_SUCCESS) {
 886                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 887                         RTE_LOG(ERR, PMD, "\tThe MAC address is not valid.\n"
 888                                         "\tThe most likely cause of this error is that the VM host\n"
 889                                         "\thas not assigned a valid MAC address to this VF device.\n"
 890                                         "\tPlease consult the DPDK Release Notes (FAQ section) for\n"
 891                                         "\ta possible solution to this problem.\n");
 892                 return (diag);
 893         }
 894
 895         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
 896         ixgbevf_get_queue_num(hw);
 897
 898         /* Allocate memory for storing MAC addresses */
 899         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
 900                         hw->mac.num_rar_entries, 0);
 901         if (eth_dev->data->mac_addrs == NULL) {
 902                 PMD_INIT_LOG(ERR,
 903                         "Failed to allocate %u bytes needed to store "
 904                         "MAC addresses",
 905                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 906                 return -ENOMEM;
 907         }
 908
 909         /* Copy the permanent MAC address */
 910         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 911                         &eth_dev->data->mac_addrs[0]);
 912
 913         /* reset the hardware with the new settings */
 914         diag = hw->mac.ops.start_hw(hw);
 915         switch (diag) {
 916                 case  0:
 917                         break;
 918
 919                 default:
 920                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 921                         return (-EIO);
 922         }
 923
 924         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
 925                          eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
 926                          "ixgbe_mac_82599_vf");
 927
 928         return 0;
 929 }
 930
 931 static struct eth_driver rte_ixgbe_pmd = {
 932         {
 933                 .name = "rte_ixgbe_pmd",
 934                 .id_table = pci_id_ixgbe_map,
 935                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 936         },
 937         .eth_dev_init = eth_ixgbe_dev_init,
 938         .dev_private_size = sizeof(struct ixgbe_adapter),
 939 };
 940
 941 /*
 942  * virtual function driver struct
 943  */
 944 static struct eth_driver rte_ixgbevf_pmd = {
 945         {
 946                 .name = "rte_ixgbevf_pmd",
 947                 .id_table = pci_id_ixgbevf_map,
 948                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 949         },
 950         .eth_dev_init = eth_ixgbevf_dev_init,
 951         .dev_private_size = sizeof(struct ixgbe_adapter),
 952 };
 953
 954 /*
 955  * Driver initialization routine.
 956  * Invoked once at EAL init time.
 957  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 958  */
 959 static int
 960 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 961 {
 962         PMD_INIT_FUNC_TRACE();
 963
 964         rte_eth_driver_register(&rte_ixgbe_pmd);
 965         return 0;
 966 }
 967
 968 /*
 969  * VF Driver initialization routine.
 970  * Invoked one at EAL init time.
 971  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
 972  */
 973 static int
 974 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
 975 {
 976         DEBUGFUNC("rte_ixgbevf_pmd_init");
 977
 978         rte_eth_driver_register(&rte_ixgbevf_pmd);
 979         return (0);
 980 }
 981
 982 static int
 983 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 984 {
 985         struct ixgbe_hw *hw =
 986                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 987         struct ixgbe_vfta * shadow_vfta =
 988                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
 989         uint32_t vfta;
 990         uint32_t vid_idx;
 991         uint32_t vid_bit;
 992
 993         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
 994         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
 995         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
 996         if (on)
 997                 vfta |= vid_bit;
 998         else
 999                 vfta &= ~vid_bit;
1000         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1001
1002         /* update local VFTA copy */
1003         shadow_vfta->vfta[vid_idx] = vfta;
1004
1005         return 0;
1006 }
1007
1008 static void
1009 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1010 {
1011         if (on)
1012                 ixgbe_vlan_hw_strip_enable(dev, queue);
1013         else
1014                 ixgbe_vlan_hw_strip_disable(dev, queue);
1015 }
1016
1017 static void
1018 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1019 {
1020         struct ixgbe_hw *hw =
1021                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1022
1023         /* Only the high 16-bits is valid */
1024         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1025 }
1026
1027 void
1028 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1029 {
1030         struct ixgbe_hw *hw =
1031                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032         uint32_t vlnctrl;
1033
1034         PMD_INIT_FUNC_TRACE();
1035
1036         /* Filter Table Disable */
1037         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1038         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1039
1040         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1041 }
1042
1043 void
1044 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1045 {
1046         struct ixgbe_hw *hw =
1047                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1048         struct ixgbe_vfta * shadow_vfta =
1049                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1050         uint32_t vlnctrl;
1051         uint16_t i;
1052
1053         PMD_INIT_FUNC_TRACE();
1054
1055         /* Filter Table Enable */
1056         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1057         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1058         vlnctrl |= IXGBE_VLNCTRL_VFE;
1059
1060         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1061
1062         /* write whatever is in local vfta copy */
1063         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1064                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1065 }
1066
1067 static void
1068 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1069 {
1070         struct ixgbe_hwstrip *hwstrip =
1071                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1072
1073         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1074                 return;
1075
1076         if (on)
1077                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1078         else
1079                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1080 }
1081
1082 static void
1083 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1084 {
1085         struct ixgbe_hw *hw =
1086                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1087         uint32_t ctrl;
1088
1089         PMD_INIT_FUNC_TRACE();
1090
1091         if (hw->mac.type == ixgbe_mac_82598EB) {
1092                 /* No queue level support */
1093                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1094                 return;
1095         }
1096         else {
1097                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1098                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1099                 ctrl &= ~IXGBE_RXDCTL_VME;
1100                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1101         }
1102         /* record those setting for HW strip per queue */
1103         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1104 }
1105
1106 static void
1107 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1108 {
1109         struct ixgbe_hw *hw =
1110                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1111         uint32_t ctrl;
1112
1113         PMD_INIT_FUNC_TRACE();
1114
1115         if (hw->mac.type == ixgbe_mac_82598EB) {
1116                 /* No queue level supported */
1117                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1118                 return;
1119         }
1120         else {
1121                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1122                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1123                 ctrl |= IXGBE_RXDCTL_VME;
1124                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1125         }
1126         /* record those setting for HW strip per queue */
1127         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1128 }
1129
1130 void
1131 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1132 {
1133         struct ixgbe_hw *hw =
1134                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1135         uint32_t ctrl;
1136         uint16_t i;
1137
1138         PMD_INIT_FUNC_TRACE();
1139
1140         if (hw->mac.type == ixgbe_mac_82598EB) {
1141                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1142                 ctrl &= ~IXGBE_VLNCTRL_VME;
1143                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1144         }
1145         else {
1146                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1147                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1148                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1149                         ctrl &= ~IXGBE_RXDCTL_VME;
1150                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1151
1152                         /* record those setting for HW strip per queue */
1153                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1154                 }
1155         }
1156 }
1157
1158 void
1159 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1160 {
1161         struct ixgbe_hw *hw =
1162                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1163         uint32_t ctrl;
1164         uint16_t i;
1165
1166         PMD_INIT_FUNC_TRACE();
1167
1168         if (hw->mac.type == ixgbe_mac_82598EB) {
1169                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1170                 ctrl |= IXGBE_VLNCTRL_VME;
1171                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1172         }
1173         else {
1174                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1175                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1176                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1177                         ctrl |= IXGBE_RXDCTL_VME;
1178                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1179
1180                         /* record those setting for HW strip per queue */
1181                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1182                 }
1183         }
1184 }
1185
1186 static void
1187 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1188 {
1189         struct ixgbe_hw *hw =
1190                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1191         uint32_t ctrl;
1192
1193         PMD_INIT_FUNC_TRACE();
1194
1195         /* DMATXCTRL: Geric Double VLAN Disable */
1196         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1197         ctrl &= ~IXGBE_DMATXCTL_GDV;
1198         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1199
1200         /* CTRL_EXT: Global Double VLAN Disable */
1201         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1202         ctrl &= ~IXGBE_EXTENDED_VLAN;
1203         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1204
1205 }
1206
1207 static void
1208 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1209 {
1210         struct ixgbe_hw *hw =
1211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1212         uint32_t ctrl;
1213
1214         PMD_INIT_FUNC_TRACE();
1215
1216         /* DMATXCTRL: Geric Double VLAN Enable */
1217         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1218         ctrl |= IXGBE_DMATXCTL_GDV;
1219         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1220
1221         /* CTRL_EXT: Global Double VLAN Enable */
1222         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1223         ctrl |= IXGBE_EXTENDED_VLAN;
1224         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1225
1226         /*
1227          * VET EXT field in the EXVET register = 0x8100 by default
1228          * So no need to change. Same to VT field of DMATXCTL register
1229          */
1230 }
1231
1232 static void
1233 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1234 {
1235         if(mask & ETH_VLAN_STRIP_MASK){
1236                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1237                         ixgbe_vlan_hw_strip_enable_all(dev);
1238                 else
1239                         ixgbe_vlan_hw_strip_disable_all(dev);
1240         }
1241
1242         if(mask & ETH_VLAN_FILTER_MASK){
1243                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1244                         ixgbe_vlan_hw_filter_enable(dev);
1245                 else
1246                         ixgbe_vlan_hw_filter_disable(dev);
1247         }
1248
1249         if(mask & ETH_VLAN_EXTEND_MASK){
1250                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1251                         ixgbe_vlan_hw_extend_enable(dev);
1252                 else
1253                         ixgbe_vlan_hw_extend_disable(dev);
1254         }
1255 }
1256
1257 static void
1258 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1259 {
1260         struct ixgbe_hw *hw =
1261                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1262         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1263         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1264         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1265         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1266 }
1267
1268 static int
1269 ixgbe_dev_configure(struct rte_eth_dev *dev)
1270 {
1271         struct ixgbe_interrupt *intr =
1272                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1273
1274         PMD_INIT_FUNC_TRACE();
1275
1276         /* set flag to update link status after init */
1277         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1278
1279         return 0;
1280 }
1281
1282 /*
1283  * Configure device link speed and setup link.
1284  * It returns 0 on success.
1285  */
1286 static int
1287 ixgbe_dev_start(struct rte_eth_dev *dev)
1288 {
1289         struct ixgbe_hw *hw =
1290                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1291         int err, link_up = 0, negotiate = 0;
1292         uint32_t speed = 0;
1293         int mask = 0;
1294         int status;
1295
1296         PMD_INIT_FUNC_TRACE();
1297
1298         /* IXGBE devices don't support half duplex */
1299         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1300                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1301                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1302                                 dev->data->dev_conf.link_duplex,
1303                                 dev->data->port_id);
1304                 return -EINVAL;
1305         }
1306
1307         /* stop adapter */
1308         hw->adapter_stopped = FALSE;
1309         ixgbe_stop_adapter(hw);
1310
1311         /* reinitialize adapter
1312          * this calls reset and start */
1313         status = ixgbe_pf_reset_hw(hw);
1314         if (status != 0)
1315                 return -1;
1316         hw->mac.ops.start_hw(hw);
1317
1318         /* configure PF module if SRIOV enabled */
1319         ixgbe_pf_host_configure(dev);
1320
1321         /* initialize transmission unit */
1322         ixgbe_dev_tx_init(dev);
1323
1324         /* This can fail when allocating mbufs for descriptor rings */
1325         err = ixgbe_dev_rx_init(dev);
1326         if (err) {
1327                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1328                 goto error;
1329         }
1330
1331         ixgbe_dev_rxtx_start(dev);
1332
1333         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1334                 err = hw->mac.ops.setup_sfp(hw);
1335                 if (err)
1336                         goto error;
1337         }
1338
1339         /* Turn on the laser */
1340         ixgbe_enable_tx_laser(hw);
1341
1342         /* Skip link setup if loopback mode is enabled for 82599. */
1343         if (hw->mac.type == ixgbe_mac_82599EB &&
1344                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1345                 goto skip_link_setup;
1346
1347         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1348         if (err)
1349                 goto error;
1350         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1351         if (err)
1352                 goto error;
1353
1354         switch(dev->data->dev_conf.link_speed) {
1355         case ETH_LINK_SPEED_AUTONEG:
1356                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1357                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1358                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1359                 break;
1360         case ETH_LINK_SPEED_100:
1361                 /*
1362                  * Invalid for 82598 but error will be detected by
1363                  * ixgbe_setup_link()
1364                  */
1365                 speed = IXGBE_LINK_SPEED_100_FULL;
1366                 break;
1367         case ETH_LINK_SPEED_1000:
1368                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1369                 break;
1370         case ETH_LINK_SPEED_10000:
1371                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1372                 break;
1373         default:
1374                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1375                                 dev->data->dev_conf.link_speed,
1376                                 dev->data->port_id);
1377                 goto error;
1378         }
1379
1380         err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1381         if (err)
1382                 goto error;
1383
1384 skip_link_setup:
1385
1386         /* check if lsc interrupt is enabled */
1387         if (dev->data->dev_conf.intr_conf.lsc != 0)
1388                 ixgbe_dev_lsc_interrupt_setup(dev);
1389
1390         /* resume enabled intr since hw reset */
1391         ixgbe_enable_intr(dev);
1392
1393         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1394                 ETH_VLAN_EXTEND_MASK;
1395         ixgbe_vlan_offload_set(dev, mask);
1396
1397         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1398                 /* Enable vlan filtering for VMDq */
1399                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1400         }
1401
1402         /* Configure DCB hw */
1403         ixgbe_configure_dcb(dev);
1404
1405         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1406                 err = ixgbe_fdir_configure(dev);
1407                 if (err)
1408                         goto error;
1409         }
1410
1411         ixgbe_restore_statistics_mapping(dev);
1412
1413         return (0);
1414
1415 error:
1416         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1417         ixgbe_dev_clear_queues(dev);
1418         return -EIO;
1419 }
1420
1421 /*
1422  * Stop device: disable rx and tx functions to allow for reconfiguring.
1423  */
1424 static void
1425 ixgbe_dev_stop(struct rte_eth_dev *dev)
1426 {
1427         struct rte_eth_link link;
1428         struct ixgbe_hw *hw =
1429                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1430         struct ixgbe_vf_info *vfinfo =
1431                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1432         int vf;
1433
1434         PMD_INIT_FUNC_TRACE();
1435
1436         /* disable interrupts */
1437         ixgbe_disable_intr(hw);
1438
1439         /* reset the NIC */
1440         ixgbe_pf_reset_hw(hw);
1441         hw->adapter_stopped = FALSE;
1442
1443         /* stop adapter */
1444         ixgbe_stop_adapter(hw);
1445
1446         for (vf = 0; vfinfo != NULL &&
1447                      vf < dev->pci_dev->max_vfs; vf++)
1448                 vfinfo[vf].clear_to_send = false;
1449
1450         /* Turn off the laser */
1451         ixgbe_disable_tx_laser(hw);
1452
1453         ixgbe_dev_clear_queues(dev);
1454
1455         /* Clear recorded link status */
1456         memset(&link, 0, sizeof(link));
1457         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1458 }
1459
1460 /*
1461  * Reest and stop device.
1462  */
1463 static void
1464 ixgbe_dev_close(struct rte_eth_dev *dev)
1465 {
1466         struct ixgbe_hw *hw =
1467                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1468
1469         PMD_INIT_FUNC_TRACE();
1470
1471         ixgbe_pf_reset_hw(hw);
1472
1473         ixgbe_dev_stop(dev);
1474         hw->adapter_stopped = 1;
1475
1476         ixgbe_disable_pcie_master(hw);
1477
1478         /* reprogram the RAR[0] in case user changed it. */
1479         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1480 }
1481
1482 /*
1483  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1484  */
1485 static void
1486 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1487 {
1488         struct ixgbe_hw *hw =
1489                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1490         struct ixgbe_hw_stats *hw_stats =
1491                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1492         uint32_t bprc, lxon, lxoff, total;
1493         uint64_t total_missed_rx, total_qbrc, total_qprc;
1494         unsigned i;
1495
1496         total_missed_rx = 0;
1497         total_qbrc = 0;
1498         total_qprc = 0;
1499
1500         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1501         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1502         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1503         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1504
1505         for (i = 0; i < 8; i++) {
1506                 uint32_t mp;
1507                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1508                 /* global total per queue */
1509                 hw_stats->mpc[i] += mp;
1510                 /* Running comprehensive total for stats display */
1511                 total_missed_rx += hw_stats->mpc[i];
1512                 if (hw->mac.type == ixgbe_mac_82598EB)
1513                         hw_stats->rnbc[i] +=
1514                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1515                 hw_stats->pxontxc[i] +=
1516                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1517                 hw_stats->pxonrxc[i] +=
1518                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1519                 hw_stats->pxofftxc[i] +=
1520                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1521                 hw_stats->pxoffrxc[i] +=
1522                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1523                 hw_stats->pxon2offc[i] +=
1524                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1525         }
1526         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1527                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1528                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1529                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1530                 hw_stats->qbrc[i] +=
1531                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1532                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1533                 hw_stats->qbtc[i] +=
1534                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1535                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1536
1537                 total_qprc += hw_stats->qprc[i];
1538                 total_qbrc += hw_stats->qbrc[i];
1539         }
1540         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1541         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1542         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1543
1544         /* Note that gprc counts missed packets */
1545         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1546
1547         if (hw->mac.type != ixgbe_mac_82598EB) {
1548                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1549                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1550                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1551                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1552                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1553                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1554                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1555                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1556         } else {
1557                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1558                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1559                 /* 82598 only has a counter in the high register */
1560                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1561                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1562                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1563         }
1564
1565         /*
1566          * Workaround: mprc hardware is incorrectly counting
1567          * broadcasts, so for now we subtract those.
1568          */
1569         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1570         hw_stats->bprc += bprc;
1571         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1572         if (hw->mac.type == ixgbe_mac_82598EB)
1573                 hw_stats->mprc -= bprc;
1574
1575         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1576         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1577         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1578         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1579         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1580         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1581
1582         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1583         hw_stats->lxontxc += lxon;
1584         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1585         hw_stats->lxofftxc += lxoff;
1586         total = lxon + lxoff;
1587
1588         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1589         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1590         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1591         hw_stats->gptc -= total;
1592         hw_stats->mptc -= total;
1593         hw_stats->ptc64 -= total;
1594         hw_stats->gotc -= total * ETHER_MIN_LEN;
1595
1596         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1597         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1598         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1599         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1600         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1601         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1602         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1603         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1604         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1605         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1606         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1607         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1608         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1609         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1610         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1611         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1612         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1613         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1614         /* Only read FCOE on 82599 */
1615         if (hw->mac.type != ixgbe_mac_82598EB) {
1616                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1617                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1618                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1619                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1620                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1621         }
1622
1623         if (stats == NULL)
1624                 return;
1625
1626         /* Fill out the rte_eth_stats statistics structure */
1627         stats->ipackets = total_qprc;
1628         stats->ibytes = total_qbrc;
1629         stats->opackets = hw_stats->gptc;
1630         stats->obytes = hw_stats->gotc;
1631         stats->imcasts = hw_stats->mprc;
1632
1633         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1634                 stats->q_ipackets[i] = hw_stats->qprc[i];
1635                 stats->q_opackets[i] = hw_stats->qptc[i];
1636                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1637                 stats->q_obytes[i] = hw_stats->qbtc[i];
1638                 stats->q_errors[i] = hw_stats->qprdc[i];
1639         }
1640
1641         /* Rx Errors */
1642         stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1643                 hw_stats->rlec;
1644
1645         stats->oerrors  = 0;
1646
1647         /* XON/XOFF pause frames */
1648         stats->tx_pause_xon  = hw_stats->lxontxc;
1649         stats->rx_pause_xon  = hw_stats->lxonrxc;
1650         stats->tx_pause_xoff = hw_stats->lxofftxc;
1651         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1652
1653         /* Flow Director Stats registers */
1654         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1655         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1656         stats->fdirmatch = hw_stats->fdirmatch;
1657         stats->fdirmiss = hw_stats->fdirmiss;
1658 }
1659
1660 static void
1661 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1662 {
1663         struct ixgbe_hw_stats *stats =
1664                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1665
1666         /* HW registers are cleared on read */
1667         ixgbe_dev_stats_get(dev, NULL);
1668
1669         /* Reset software totals */
1670         memset(stats, 0, sizeof(*stats));
1671 }
1672
1673 static void
1674 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1675 {
1676         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1678                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1679
1680         /* Good Rx packet, include VF loopback */
1681         UPDATE_VF_STAT(IXGBE_VFGPRC,
1682             hw_stats->last_vfgprc, hw_stats->vfgprc);
1683
1684         /* Good Rx octets, include VF loopback */
1685         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1686             hw_stats->last_vfgorc, hw_stats->vfgorc);
1687
1688         /* Good Tx packet, include VF loopback */
1689         UPDATE_VF_STAT(IXGBE_VFGPTC,
1690             hw_stats->last_vfgptc, hw_stats->vfgptc);
1691
1692         /* Good Tx octets, include VF loopback */
1693         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1694             hw_stats->last_vfgotc, hw_stats->vfgotc);
1695
1696         /* Rx Multicst Packet */
1697         UPDATE_VF_STAT(IXGBE_VFMPRC,
1698             hw_stats->last_vfmprc, hw_stats->vfmprc);
1699
1700         if (stats == NULL)
1701                 return;
1702
1703         memset(stats, 0, sizeof(*stats));
1704         stats->ipackets = hw_stats->vfgprc;
1705         stats->ibytes = hw_stats->vfgorc;
1706         stats->opackets = hw_stats->vfgptc;
1707         stats->obytes = hw_stats->vfgotc;
1708         stats->imcasts = hw_stats->vfmprc;
1709 }
1710
1711 static void
1712 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1713 {
1714         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1715                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1716
1717         /* Sync HW register to the last stats */
1718         ixgbevf_dev_stats_get(dev, NULL);
1719
1720         /* reset HW current stats*/
1721         hw_stats->vfgprc = 0;
1722         hw_stats->vfgorc = 0;
1723         hw_stats->vfgptc = 0;
1724         hw_stats->vfgotc = 0;
1725         hw_stats->vfmprc = 0;
1726
1727 }
1728
1729 static void
1730 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1731 {
1732         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1733
1734         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1735         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1736         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1737         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1738         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1739         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1740         dev_info->max_vfs = dev->pci_dev->max_vfs;
1741         if (hw->mac.type == ixgbe_mac_82598EB)
1742                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1743         else
1744                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1745         dev_info->rx_offload_capa =
1746                 DEV_RX_OFFLOAD_VLAN_STRIP |
1747                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1748                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1749                 DEV_RX_OFFLOAD_TCP_CKSUM;
1750         dev_info->tx_offload_capa =
1751                 DEV_TX_OFFLOAD_VLAN_INSERT |
1752                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1753                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1754                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1755                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1756 }
1757
1758 /* return 0 means link status changed, -1 means not changed */
1759 static int
1760 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1761 {
1762         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1763         struct rte_eth_link link, old;
1764         ixgbe_link_speed link_speed;
1765         int link_up;
1766         int diag;
1767
1768         link.link_status = 0;
1769         link.link_speed = 0;
1770         link.link_duplex = 0;
1771         memset(&old, 0, sizeof(old));
1772         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1773
1774         /* check if it needs to wait to complete, if lsc interrupt is enabled */
1775         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1776                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1777         else
1778                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1779         if (diag != 0) {
1780                 link.link_speed = ETH_LINK_SPEED_100;
1781                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1782                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1783                 if (link.link_status == old.link_status)
1784                         return -1;
1785                 return 0;
1786         }
1787
1788         if (link_up == 0) {
1789                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1790                 if (link.link_status == old.link_status)
1791                         return -1;
1792                 return 0;
1793         }
1794         link.link_status = 1;
1795         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1796
1797         switch (link_speed) {
1798         default:
1799         case IXGBE_LINK_SPEED_UNKNOWN:
1800                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1801                 link.link_speed = ETH_LINK_SPEED_100;
1802                 break;
1803
1804         case IXGBE_LINK_SPEED_100_FULL:
1805                 link.link_speed = ETH_LINK_SPEED_100;
1806                 break;
1807
1808         case IXGBE_LINK_SPEED_1GB_FULL:
1809                 link.link_speed = ETH_LINK_SPEED_1000;
1810                 break;
1811
1812         case IXGBE_LINK_SPEED_10GB_FULL:
1813                 link.link_speed = ETH_LINK_SPEED_10000;
1814                 break;
1815         }
1816         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1817
1818         if (link.link_status == old.link_status)
1819                 return -1;
1820
1821         return 0;
1822 }
1823
1824 static void
1825 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1826 {
1827         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1828         uint32_t fctrl;
1829
1830         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1831         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1832         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1833 }
1834
1835 static void
1836 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1837 {
1838         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1839         uint32_t fctrl;
1840
1841         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1842         fctrl &= (~IXGBE_FCTRL_UPE);
1843         if (dev->data->all_multicast == 1)
1844                 fctrl |= IXGBE_FCTRL_MPE;
1845         else
1846                 fctrl &= (~IXGBE_FCTRL_MPE);
1847         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1848 }
1849
1850 static void
1851 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1852 {
1853         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1854         uint32_t fctrl;
1855
1856         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1857         fctrl |= IXGBE_FCTRL_MPE;
1858         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1859 }
1860
1861 static void
1862 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1863 {
1864         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1865         uint32_t fctrl;
1866
1867         if (dev->data->promiscuous == 1)
1868                 return; /* must remain in all_multicast mode */
1869
1870         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1871         fctrl &= (~IXGBE_FCTRL_MPE);
1872         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1873 }
1874
1875 /**
1876  * It clears the interrupt causes and enables the interrupt.
1877  * It will be called once only during nic initialized.
1878  *
1879  * @param dev
1880  *  Pointer to struct rte_eth_dev.
1881  *
1882  * @return
1883  *  - On success, zero.
1884  *  - On failure, a negative value.
1885  */
1886 static int
1887 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
1888 {
1889         struct ixgbe_interrupt *intr =
1890                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1891
1892         ixgbe_dev_link_status_print(dev);
1893         intr->mask |= IXGBE_EICR_LSC;
1894
1895         return 0;
1896 }
1897
1898 /*
1899  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1900  *
1901  * @param dev
1902  *  Pointer to struct rte_eth_dev.
1903  *
1904  * @return
1905  *  - On success, zero.
1906  *  - On failure, a negative value.
1907  */
1908 static int
1909 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1910 {
1911         uint32_t eicr;
1912         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913         struct ixgbe_interrupt *intr =
1914                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1915
1916         /* clear all cause mask */
1917         ixgbe_disable_intr(hw);
1918
1919         /* read-on-clear nic registers here */
1920         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1921         PMD_DRV_LOG(INFO, "eicr %x", eicr);
1922
1923         intr->flags = 0;
1924         if (eicr & IXGBE_EICR_LSC) {
1925                 /* set flag for async link update */
1926                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1927         }
1928
1929         if (eicr & IXGBE_EICR_MAILBOX)
1930                 intr->flags |= IXGBE_FLAG_MAILBOX;
1931
1932         return 0;
1933 }
1934
1935 /**
1936  * It gets and then prints the link status.
1937  *
1938  * @param dev
1939  *  Pointer to struct rte_eth_dev.
1940  *
1941  * @return
1942  *  - On success, zero.
1943  *  - On failure, a negative value.
1944  */
1945 static void
1946 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1947 {
1948         struct rte_eth_link link;
1949
1950         memset(&link, 0, sizeof(link));
1951         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1952         if (link.link_status) {
1953                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1954                                         (int)(dev->data->port_id),
1955                                         (unsigned)link.link_speed,
1956                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1957                                         "full-duplex" : "half-duplex");
1958         } else {
1959                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1960                                 (int)(dev->data->port_id));
1961         }
1962         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1963                                 dev->pci_dev->addr.domain,
1964                                 dev->pci_dev->addr.bus,
1965                                 dev->pci_dev->addr.devid,
1966                                 dev->pci_dev->addr.function);
1967 }
1968
1969 /*
1970  * It executes link_update after knowing an interrupt occurred.
1971  *
1972  * @param dev
1973  *  Pointer to struct rte_eth_dev.
1974  *
1975  * @return
1976  *  - On success, zero.
1977  *  - On failure, a negative value.
1978  */
1979 static int
1980 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1981 {
1982         struct ixgbe_interrupt *intr =
1983                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1984         int64_t timeout;
1985         struct rte_eth_link link;
1986         int intr_enable_delay = false;
1987
1988         PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
1989
1990         if (intr->flags & IXGBE_FLAG_MAILBOX) {
1991                 ixgbe_pf_mbx_process(dev);
1992                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
1993         }
1994
1995         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1996                 /* get the link status before link update, for predicting later */
1997                 memset(&link, 0, sizeof(link));
1998                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1999
2000                 ixgbe_dev_link_update(dev, 0);
2001
2002                 /* likely to up */
2003                 if (!link.link_status)
2004                         /* handle it 1 sec later, wait it being stable */
2005                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2006                 /* likely to down */
2007                 else
2008                         /* handle it 4 sec later, wait it being stable */
2009                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2010
2011                 ixgbe_dev_link_status_print(dev);
2012
2013                 intr_enable_delay = true;
2014         }
2015
2016         if (intr_enable_delay) {
2017                 if (rte_eal_alarm_set(timeout * 1000,
2018                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2019                         PMD_DRV_LOG(ERR, "Error setting alarm");
2020         } else {
2021                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2022                 ixgbe_enable_intr(dev);
2023                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2024         }
2025
2026
2027         return 0;
2028 }
2029
2030 /**
2031  * Interrupt handler which shall be registered for alarm callback for delayed
2032  * handling specific interrupt to wait for the stable nic state. As the
2033  * NIC interrupt state is not stable for ixgbe after link is just down,
2034  * it needs to wait 4 seconds to get the stable status.
2035  *
2036  * @param handle
2037  *  Pointer to interrupt handle.
2038  * @param param
2039  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2040  *
2041  * @return
2042  *  void
2043  */
2044 static void
2045 ixgbe_dev_interrupt_delayed_handler(void *param)
2046 {
2047         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2048         struct ixgbe_interrupt *intr =
2049                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2050         struct ixgbe_hw *hw =
2051                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052         uint32_t eicr;
2053
2054         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2055         if (eicr & IXGBE_EICR_MAILBOX)
2056                 ixgbe_pf_mbx_process(dev);
2057
2058         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2059                 ixgbe_dev_link_update(dev, 0);
2060                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2061                 ixgbe_dev_link_status_print(dev);
2062                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2063         }
2064
2065         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
2066         ixgbe_enable_intr(dev);
2067         rte_intr_enable(&(dev->pci_dev->intr_handle));
2068 }
2069
2070 /**
2071  * Interrupt handler triggered by NIC  for handling
2072  * specific interrupt.
2073  *
2074  * @param handle
2075  *  Pointer to interrupt handle.
2076  * @param param
2077  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2078  *
2079  * @return
2080  *  void
2081  */
2082 static void
2083 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2084                                                         void *param)
2085 {
2086         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2087         ixgbe_dev_interrupt_get_status(dev);
2088         ixgbe_dev_interrupt_action(dev);
2089 }
2090
2091 static int
2092 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2093 {
2094         struct ixgbe_hw *hw;
2095
2096         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2097         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2098 }
2099
2100 static int
2101 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2102 {
2103         struct ixgbe_hw *hw;
2104
2105         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2107 }
2108
2109 static int
2110 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2111 {
2112         struct ixgbe_hw *hw;
2113         int err;
2114         uint32_t rx_buf_size;
2115         uint32_t max_high_water;
2116         uint32_t mflcn;
2117         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2118                 ixgbe_fc_none,
2119                 ixgbe_fc_rx_pause,
2120                 ixgbe_fc_tx_pause,
2121                 ixgbe_fc_full
2122         };
2123
2124         PMD_INIT_FUNC_TRACE();
2125
2126         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2127         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2128         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2129
2130         /*
2131          * At least reserve one Ethernet frame for watermark
2132          * high_water/low_water in kilo bytes for ixgbe
2133          */
2134         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2135         if ((fc_conf->high_water > max_high_water) ||
2136                 (fc_conf->high_water < fc_conf->low_water)) {
2137                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2138                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2139                 return (-EINVAL);
2140         }
2141
2142         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2143         hw->fc.pause_time     = fc_conf->pause_time;
2144         hw->fc.high_water[0]  = fc_conf->high_water;
2145         hw->fc.low_water[0]   = fc_conf->low_water;
2146         hw->fc.send_xon       = fc_conf->send_xon;
2147
2148         err = ixgbe_fc_enable(hw);
2149
2150         /* Not negotiated is not an error case */
2151         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2152
2153                 /* check if we want to forward MAC frames - driver doesn't have native
2154                  * capability to do that, so we'll write the registers ourselves */
2155
2156                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2157
2158                 /* set or clear MFLCN.PMCF bit depending on configuration */
2159                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2160                         mflcn |= IXGBE_MFLCN_PMCF;
2161                 else
2162                         mflcn &= ~IXGBE_MFLCN_PMCF;
2163
2164                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2165                 IXGBE_WRITE_FLUSH(hw);
2166
2167                 return 0;
2168         }
2169
2170         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2171         return -EIO;
2172 }
2173
2174 /**
2175  *  ixgbe_pfc_enable_generic - Enable flow control
2176  *  @hw: pointer to hardware structure
2177  *  @tc_num: traffic class number
2178  *  Enable flow control according to the current settings.
2179  */
2180 static int
2181 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2182 {
2183         int ret_val = 0;
2184         uint32_t mflcn_reg, fccfg_reg;
2185         uint32_t reg;
2186         uint32_t fcrtl, fcrth;
2187         uint8_t i;
2188         uint8_t nb_rx_en;
2189
2190         /* Validate the water mark configuration */
2191         if (!hw->fc.pause_time) {
2192                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2193                 goto out;
2194         }
2195
2196         /* Low water mark of zero causes XOFF floods */
2197         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2198                  /* High/Low water can not be 0 */
2199                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2200                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2201                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2202                         goto out;
2203                 }
2204
2205                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2206                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2207                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2208                         goto out;
2209                 }
2210         }
2211         /* Negotiate the fc mode to use */
2212         ixgbe_fc_autoneg(hw);
2213
2214         /* Disable any previous flow control settings */
2215         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2216         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2217
2218         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2219         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2220
2221         switch (hw->fc.current_mode) {
2222         case ixgbe_fc_none:
2223                 /*
2224                  * If the count of enabled RX Priority Flow control >1,
2225                  * and the TX pause can not be disabled
2226                  */
2227                 nb_rx_en = 0;
2228                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2229                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2230                         if (reg & IXGBE_FCRTH_FCEN)
2231                                 nb_rx_en++;
2232                 }
2233                 if (nb_rx_en > 1)
2234                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2235                 break;
2236         case ixgbe_fc_rx_pause:
2237                 /*
2238                  * Rx Flow control is enabled and Tx Flow control is
2239                  * disabled by software override. Since there really
2240                  * isn't a way to advertise that we are capable of RX
2241                  * Pause ONLY, we will advertise that we support both
2242                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2243                  * disable the adapter's ability to send PAUSE frames.
2244                  */
2245                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2246                 /*
2247                  * If the count of enabled RX Priority Flow control >1,
2248                  * and the TX pause can not be disabled
2249                  */
2250                 nb_rx_en = 0;
2251                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2252                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2253                         if (reg & IXGBE_FCRTH_FCEN)
2254                                 nb_rx_en++;
2255                 }
2256                 if (nb_rx_en > 1)
2257                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2258                 break;
2259         case ixgbe_fc_tx_pause:
2260                 /*
2261                  * Tx Flow control is enabled, and Rx Flow control is
2262                  * disabled by software override.
2263                  */
2264                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2265                 break;
2266         case ixgbe_fc_full:
2267                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2268                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2269                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2270                 break;
2271         default:
2272                 DEBUGOUT("Flow control param set incorrectly\n");
2273                 ret_val = IXGBE_ERR_CONFIG;
2274                 goto out;
2275                 break;
2276         }
2277
2278         /* Set 802.3x based flow control settings. */
2279         mflcn_reg |= IXGBE_MFLCN_DPF;
2280         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2281         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2282
2283         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2284         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2285                 hw->fc.high_water[tc_num]) {
2286                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2287                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2288                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2289         } else {
2290                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2291                 /*
2292                  * In order to prevent Tx hangs when the internal Tx
2293                  * switch is enabled we must set the high water mark
2294                  * to the maximum FCRTH value.  This allows the Tx
2295                  * switch to function even under heavy Rx workloads.
2296                  */
2297                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2298         }
2299         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2300
2301         /* Configure pause time (2 TCs per register) */
2302         reg = hw->fc.pause_time * 0x00010001;
2303         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2304                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2305
2306         /* Configure flow control refresh threshold value */
2307         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2308
2309 out:
2310         return ret_val;
2311 }
2312
2313 static int
2314 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2315 {
2316         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2317         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2318
2319         if(hw->mac.type != ixgbe_mac_82598EB) {
2320                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2321         }
2322         return ret_val;
2323 }
2324
2325 static int
2326 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2327 {
2328         int err;
2329         uint32_t rx_buf_size;
2330         uint32_t max_high_water;
2331         uint8_t tc_num;
2332         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2333         struct ixgbe_hw *hw =
2334                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2335         struct ixgbe_dcb_config *dcb_config =
2336                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2337
2338         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2339                 ixgbe_fc_none,
2340                 ixgbe_fc_rx_pause,
2341                 ixgbe_fc_tx_pause,
2342                 ixgbe_fc_full
2343         };
2344
2345         PMD_INIT_FUNC_TRACE();
2346
2347         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2348         tc_num = map[pfc_conf->priority];
2349         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2350         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2351         /*
2352          * At least reserve one Ethernet frame for watermark
2353          * high_water/low_water in kilo bytes for ixgbe
2354          */
2355         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2356         if ((pfc_conf->fc.high_water > max_high_water) ||
2357                 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2358                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2359                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2360                 return (-EINVAL);
2361         }
2362
2363         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2364         hw->fc.pause_time = pfc_conf->fc.pause_time;
2365         hw->fc.send_xon = pfc_conf->fc.send_xon;
2366         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2367         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2368
2369         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2370
2371         /* Not negotiated is not an error case */
2372         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2373                 return 0;
2374
2375         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2376         return -EIO;
2377 }
2378
2379 static int
2380 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2381                                 struct rte_eth_rss_reta *reta_conf)
2382 {
2383         uint8_t i,j,mask;
2384         uint32_t reta;
2385         struct ixgbe_hw *hw =
2386                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2387
2388         PMD_INIT_FUNC_TRACE();
2389         /*
2390         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2391         * 128-entries in 32 registers
2392          */
2393         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2394                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2395                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2396                 else
2397                         mask = (uint8_t)((reta_conf->mask_hi >>
2398                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2399                 if (mask != 0) {
2400                         reta = 0;
2401                         if (mask != 0xF)
2402                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2403
2404                         for (j = 0; j < 4; j++) {
2405                                 if (mask & (0x1 << j)) {
2406                                         if (mask != 0xF)
2407                                                 reta &= ~(0xFF << 8 * j);
2408                                         reta |= reta_conf->reta[i + j] << 8*j;
2409                                 }
2410                         }
2411                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2412                 }
2413         }
2414
2415         return 0;
2416 }
2417
2418 static int
2419 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2420                                 struct rte_eth_rss_reta *reta_conf)
2421 {
2422         uint8_t i,j,mask;
2423         uint32_t reta;
2424         struct ixgbe_hw *hw =
2425                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2426
2427         PMD_INIT_FUNC_TRACE();
2428         /*
2429          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2430          * 128-entries in 32 registers
2431          */
2432         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2433                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2434                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2435                 else
2436                         mask = (uint8_t)((reta_conf->mask_hi >>
2437                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2438
2439                 if (mask != 0) {
2440                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2441                         for (j = 0; j < 4; j++) {
2442                                 if (mask & (0x1 << j))
2443                                         reta_conf->reta[i + j] =
2444                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2445                         }
2446                 }
2447         }
2448
2449         return 0;
2450 }
2451
2452 static void
2453 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2454                                 uint32_t index, uint32_t pool)
2455 {
2456         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457         uint32_t enable_addr = 1;
2458
2459         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2460 }
2461
2462 static void
2463 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2464 {
2465         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466
2467         ixgbe_clear_rar(hw, index);
2468 }
2469
2470 /*
2471  * Virtual Function operations
2472  */
2473 static void
2474 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2475 {
2476         PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2477
2478         /* Clear interrupt mask to stop from interrupts being generated */
2479         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2480
2481         IXGBE_WRITE_FLUSH(hw);
2482 }
2483
2484 static int
2485 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2486 {
2487         struct rte_eth_conf* conf = &dev->data->dev_conf;
2488
2489         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2490                 dev->data->port_id);
2491
2492         /*
2493          * VF has no ability to enable/disable HW CRC
2494          * Keep the persistent behavior the same as Host PF
2495          */
2496 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2497         if (!conf->rxmode.hw_strip_crc) {
2498                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2499                 conf->rxmode.hw_strip_crc = 1;
2500         }
2501 #else
2502         if (conf->rxmode.hw_strip_crc) {
2503                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2504                 conf->rxmode.hw_strip_crc = 0;
2505         }
2506 #endif
2507
2508         return 0;
2509 }
2510
2511 static int
2512 ixgbevf_dev_start(struct rte_eth_dev *dev)
2513 {
2514         struct ixgbe_hw *hw =
2515                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2516         int err, mask = 0;
2517
2518         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2519
2520         hw->mac.ops.reset_hw(hw);
2521
2522         ixgbevf_dev_tx_init(dev);
2523
2524         /* This can fail when allocating mbufs for descriptor rings */
2525         err = ixgbevf_dev_rx_init(dev);
2526         if (err) {
2527                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2528                 ixgbe_dev_clear_queues(dev);
2529                 return err;
2530         }
2531
2532         /* Set vfta */
2533         ixgbevf_set_vfta_all(dev,1);
2534
2535         /* Set HW strip */
2536         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2537                 ETH_VLAN_EXTEND_MASK;
2538         ixgbevf_vlan_offload_set(dev, mask);
2539
2540         ixgbevf_dev_rxtx_start(dev);
2541
2542         return 0;
2543 }
2544
2545 static void
2546 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2547 {
2548         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549
2550         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2551
2552         hw->adapter_stopped = TRUE;
2553         ixgbe_stop_adapter(hw);
2554
2555         /*
2556           * Clear what we set, but we still keep shadow_vfta to
2557           * restore after device starts
2558           */
2559         ixgbevf_set_vfta_all(dev,0);
2560
2561         ixgbe_dev_clear_queues(dev);
2562 }
2563
2564 static void
2565 ixgbevf_dev_close(struct rte_eth_dev *dev)
2566 {
2567         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2568
2569         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2570
2571         ixgbe_reset_hw(hw);
2572
2573         ixgbevf_dev_stop(dev);
2574
2575         /* reprogram the RAR[0] in case user changed it. */
2576         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2577 }
2578
2579 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2580 {
2581         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2582         struct ixgbe_vfta * shadow_vfta =
2583                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2584         int i = 0, j = 0, vfta = 0, mask = 1;
2585
2586         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2587                 vfta = shadow_vfta->vfta[i];
2588                 if(vfta){
2589                         mask = 1;
2590                         for (j = 0; j < 32; j++){
2591                                 if(vfta & mask)
2592                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2593                                 mask<<=1;
2594                         }
2595                 }
2596         }
2597
2598 }
2599
2600 static int
2601 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2602 {
2603         struct ixgbe_hw *hw =
2604                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2605         struct ixgbe_vfta * shadow_vfta =
2606                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2607         uint32_t vid_idx = 0;
2608         uint32_t vid_bit = 0;
2609         int ret = 0;
2610
2611         PMD_INIT_FUNC_TRACE();
2612
2613         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2614         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2615         if(ret){
2616                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2617                 return ret;
2618         }
2619         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2620         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2621
2622         /* Save what we set and retore it after device reset */
2623         if (on)
2624                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2625         else
2626                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2627
2628         return 0;
2629 }
2630
2631 static void
2632 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2633 {
2634         struct ixgbe_hw *hw =
2635                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636         uint32_t ctrl;
2637
2638         PMD_INIT_FUNC_TRACE();
2639
2640         if(queue >= hw->mac.max_rx_queues)
2641                 return;
2642
2643         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2644         if(on)
2645                 ctrl |= IXGBE_RXDCTL_VME;
2646         else
2647                 ctrl &= ~IXGBE_RXDCTL_VME;
2648         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2649
2650         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2651 }
2652
2653 static void
2654 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2655 {
2656         struct ixgbe_hw *hw =
2657                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2658         uint16_t i;
2659         int on = 0;
2660
2661         /* VF function only support hw strip feature, others are not support */
2662         if(mask & ETH_VLAN_STRIP_MASK){
2663                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2664
2665                 for(i=0; i < hw->mac.max_rx_queues; i++)
2666                         ixgbevf_vlan_strip_queue_set(dev,i,on);
2667         }
2668 }
2669
2670 static int
2671 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2672 {
2673         uint32_t reg_val;
2674
2675         /* we only need to do this if VMDq is enabled */
2676         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2677         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2678                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2679                 return (-1);
2680         }
2681
2682         return 0;
2683 }
2684
2685 static uint32_t
2686 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2687 {
2688         uint32_t vector = 0;
2689         switch (hw->mac.mc_filter_type) {
2690         case 0:   /* use bits [47:36] of the address */
2691                 vector = ((uc_addr->addr_bytes[4] >> 4) |
2692                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2693                 break;
2694         case 1:   /* use bits [46:35] of the address */
2695                 vector = ((uc_addr->addr_bytes[4] >> 3) |
2696                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2697                 break;
2698         case 2:   /* use bits [45:34] of the address */
2699                 vector = ((uc_addr->addr_bytes[4] >> 2) |
2700                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2701                 break;
2702         case 3:   /* use bits [43:32] of the address */
2703                 vector = ((uc_addr->addr_bytes[4]) |
2704                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2705                 break;
2706         default:  /* Invalid mc_filter_type */
2707                 break;
2708         }
2709
2710         /* vector can only be 12-bits or boundary will be exceeded */
2711         vector &= 0xFFF;
2712         return vector;
2713 }
2714
2715 static int
2716 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
2717                                uint8_t on)
2718 {
2719         uint32_t vector;
2720         uint32_t uta_idx;
2721         uint32_t reg_val;
2722         uint32_t uta_shift;
2723         uint32_t rc;
2724         const uint32_t ixgbe_uta_idx_mask = 0x7F;
2725         const uint32_t ixgbe_uta_bit_shift = 5;
2726         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
2727         const uint32_t bit1 = 0x1;
2728
2729         struct ixgbe_hw *hw =
2730                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2731         struct ixgbe_uta_info *uta_info =
2732                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2733
2734         /* The UTA table only exists on 82599 hardware and newer */
2735         if (hw->mac.type < ixgbe_mac_82599EB)
2736                 return (-ENOTSUP);
2737
2738         vector = ixgbe_uta_vector(hw,mac_addr);
2739         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
2740         uta_shift = vector & ixgbe_uta_bit_mask;
2741
2742         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
2743         if(rc == on)
2744                 return 0;
2745
2746         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
2747         if (on) {
2748                 uta_info->uta_in_use++;
2749                 reg_val |= (bit1 << uta_shift);
2750                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
2751         } else {
2752                 uta_info->uta_in_use--;
2753                 reg_val &= ~(bit1 << uta_shift);
2754                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
2755         }
2756
2757         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
2758
2759         if (uta_info->uta_in_use > 0)
2760                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2761                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2762         else
2763                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
2764
2765         return 0;
2766 }
2767
2768 static int
2769 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
2770 {
2771         int i;
2772         struct ixgbe_hw *hw =
2773                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774         struct ixgbe_uta_info *uta_info =
2775                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2776
2777         /* The UTA table only exists on 82599 hardware and newer */
2778         if (hw->mac.type < ixgbe_mac_82599EB)
2779                 return (-ENOTSUP);
2780
2781         if(on) {
2782                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2783                         uta_info->uta_shadow[i] = ~0;
2784                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2785                 }
2786         } else {
2787                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2788                         uta_info->uta_shadow[i] = 0;
2789                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2790                 }
2791         }
2792         return 0;
2793
2794 }
2795 static int
2796 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
2797                                uint16_t rx_mask, uint8_t on)
2798 {
2799         int val = 0;
2800
2801         struct ixgbe_hw *hw =
2802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2803         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
2804
2805         if (hw->mac.type == ixgbe_mac_82598EB) {
2806                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
2807                         " on 82599 hardware and newer\n");
2808                 return (-ENOTSUP);
2809         }
2810         if (ixgbe_vmdq_mode_check(hw) < 0)
2811                 return (-ENOTSUP);
2812
2813         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
2814                 val |= IXGBE_VMOLR_AUPE;
2815         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
2816                 val |= IXGBE_VMOLR_ROMPE;
2817         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
2818                 val |= IXGBE_VMOLR_ROPE;
2819         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
2820                 val |= IXGBE_VMOLR_BAM;
2821         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
2822                 val |= IXGBE_VMOLR_MPE;
2823
2824         if (on)
2825                 vmolr |= val;
2826         else
2827                 vmolr &= ~val;
2828
2829         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
2830
2831         return 0;
2832 }
2833
2834 static int
2835 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2836 {
2837         uint32_t reg,addr;
2838         uint32_t val;
2839         const uint8_t bit1 = 0x1;
2840
2841         struct ixgbe_hw *hw =
2842                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843
2844         if (ixgbe_vmdq_mode_check(hw) < 0)
2845                 return (-ENOTSUP);
2846
2847         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
2848         reg = IXGBE_READ_REG(hw, addr);
2849         val = bit1 << pool;
2850
2851         if (on)
2852                 reg |= val;
2853         else
2854                 reg &= ~val;
2855
2856         IXGBE_WRITE_REG(hw, addr,reg);
2857
2858         return 0;
2859 }
2860
2861 static int
2862 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2863 {
2864         uint32_t reg,addr;
2865         uint32_t val;
2866         const uint8_t bit1 = 0x1;
2867
2868         struct ixgbe_hw *hw =
2869                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2870
2871         if (ixgbe_vmdq_mode_check(hw) < 0)
2872                 return (-ENOTSUP);
2873
2874         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
2875         reg = IXGBE_READ_REG(hw, addr);
2876         val = bit1 << pool;
2877
2878         if (on)
2879                 reg |= val;
2880         else
2881                 reg &= ~val;
2882
2883         IXGBE_WRITE_REG(hw, addr,reg);
2884
2885         return 0;
2886 }
2887
2888 static int
2889 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
2890                         uint64_t pool_mask, uint8_t vlan_on)
2891 {
2892         int ret = 0;
2893         uint16_t pool_idx;
2894         struct ixgbe_hw *hw =
2895                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896
2897         if (ixgbe_vmdq_mode_check(hw) < 0)
2898                 return (-ENOTSUP);
2899         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
2900                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
2901                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
2902                         if (ret < 0)
2903                                 return ret;
2904         }
2905
2906         return ret;
2907 }
2908
2909 static int
2910 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
2911                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
2912                         uint8_t rule_id, uint8_t on)
2913 {
2914         uint32_t mr_ctl,vlvf;
2915         uint32_t mp_lsb = 0;
2916         uint32_t mv_msb = 0;
2917         uint32_t mv_lsb = 0;
2918         uint32_t mp_msb = 0;
2919         uint8_t i = 0;
2920         int reg_index = 0;
2921         uint64_t vlan_mask = 0;
2922
2923         const uint8_t pool_mask_offset = 32;
2924         const uint8_t vlan_mask_offset = 32;
2925         const uint8_t dst_pool_offset = 8;
2926         const uint8_t rule_mr_offset  = 4;
2927         const uint8_t mirror_rule_mask= 0x0F;
2928
2929         struct ixgbe_mirror_info *mr_info =
2930                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
2931         struct ixgbe_hw *hw =
2932                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2933
2934         if (ixgbe_vmdq_mode_check(hw) < 0)
2935                 return (-ENOTSUP);
2936
2937         /* Check if vlan mask is valid */
2938         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
2939                 if (mirror_conf->vlan.vlan_mask == 0)
2940                         return (-EINVAL);
2941         }
2942
2943         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
2944         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2945                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
2946                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
2947                                 /* search vlan id related pool vlan filter index */
2948                                 reg_index = ixgbe_find_vlvf_slot(hw,
2949                                                 mirror_conf->vlan.vlan_id[i]);
2950                                 if(reg_index < 0)
2951                                         return (-EINVAL);
2952                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
2953                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
2954                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
2955                                                 == mirror_conf->vlan.vlan_id[i]))
2956                                         vlan_mask |= (1ULL << reg_index);
2957                                 else
2958                                         return (-EINVAL);
2959                         }
2960                 }
2961
2962                 if (on) {
2963                         mv_lsb = vlan_mask & 0xFFFFFFFF;
2964                         mv_msb = vlan_mask >> vlan_mask_offset;
2965
2966                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
2967                                                 mirror_conf->vlan.vlan_mask;
2968                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
2969                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
2970                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
2971                                                 mirror_conf->vlan.vlan_id[i];
2972                         }
2973                 } else {
2974                         mv_lsb = 0;
2975                         mv_msb = 0;
2976                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
2977                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
2978                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
2979                 }
2980         }
2981
2982         /*
2983          * if enable pool mirror, write related pool mask register,if disable
2984          * pool mirror, clear PFMRVM register
2985          */
2986         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
2987                 if (on) {
2988                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
2989                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
2990                         mr_info->mr_conf[rule_id].pool_mask =
2991                                         mirror_conf->pool_mask;
2992
2993                 } else {
2994                         mp_lsb = 0;
2995                         mp_msb = 0;
2996                         mr_info->mr_conf[rule_id].pool_mask = 0;
2997                 }
2998         }
2999
3000         /* read  mirror control register and recalculate it */
3001         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3002
3003         if (on) {
3004                 mr_ctl |= mirror_conf->rule_type_mask;
3005                 mr_ctl &= mirror_rule_mask;
3006                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3007         } else
3008                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3009
3010         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3011         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3012
3013         /* write mirrror control  register */
3014         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3015
3016         /* write pool mirrror control  register */
3017         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3018                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3019                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3020                                 mp_msb);
3021         }
3022         /* write VLAN mirrror control  register */
3023         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3024                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3025                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3026                                 mv_msb);
3027         }
3028
3029         return 0;
3030 }
3031
3032 static int
3033 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3034 {
3035         int mr_ctl = 0;
3036         uint32_t lsb_val = 0;
3037         uint32_t msb_val = 0;
3038         const uint8_t rule_mr_offset = 4;
3039
3040         struct ixgbe_hw *hw =
3041                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3042         struct ixgbe_mirror_info *mr_info =
3043                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3044
3045         if (ixgbe_vmdq_mode_check(hw) < 0)
3046                 return (-ENOTSUP);
3047
3048         memset(&mr_info->mr_conf[rule_id], 0,
3049                 sizeof(struct rte_eth_vmdq_mirror_conf));
3050
3051         /* clear PFVMCTL register */
3052         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3053
3054         /* clear pool mask register */
3055         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3056         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3057
3058         /* clear vlan mask register */
3059         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3060         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3061
3062         return 0;
3063 }
3064
3065 static struct rte_driver rte_ixgbe_driver = {
3066         .type = PMD_PDEV,
3067         .init = rte_ixgbe_pmd_init,
3068 };
3069
3070 static struct rte_driver rte_ixgbevf_driver = {
3071         .type = PMD_PDEV,
3072         .init = rte_ixgbevf_pmd_init,
3073 };
3074
3075 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
3076 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);