lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_tailq.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61
  62 #include "ixgbe_logs.h"
  63 #include "ixgbe/ixgbe_api.h"
  64 #include "ixgbe/ixgbe_vf.h"
  65 #include "ixgbe/ixgbe_common.h"
  66 #include "ixgbe_ethdev.h"
  67
  68 /*
  69  * High threshold controlling when to start sending XOFF frames. Must be at
  70  * least 8 bytes less than receive packet buffer size. This value is in units
  71  * of 1024 bytes.
  72  */
  73 #define IXGBE_FC_HI    0x80
  74
  75 /*
  76  * Low threshold controlling when to start sending XON frames. This value is
  77  * in units of 1024 bytes.
  78  */
  79 #define IXGBE_FC_LO    0x40
  80
  81 /* Timer value included in XOFF frames. */
  82 #define IXGBE_FC_PAUSE 0x680
  83
  84 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  85 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  86
  87 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  88
  89 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  90
  91 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
  92                 struct rte_eth_dev *eth_dev);
  93 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
  94 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
  95 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
  96 static void ixgbe_dev_close(struct rte_eth_dev *dev);
  97 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
  98 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
  99 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 100 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 101 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 102                                 int wait_to_complete);
 103 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 104                                 struct rte_eth_stats *stats);
 105 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 106 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 107                                              uint16_t queue_id,
 108                                              uint8_t stat_idx,
 109                                              uint8_t is_rx);
 110 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_dev_info *dev_info);
 112 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 113                 uint16_t vlan_id, int on);
 114 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 115 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 116                 uint16_t queue, bool on);
 117 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 118                 int on);
 119 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 120 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 121 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 122 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 123 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 124
 125 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 126 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 127 static int  ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 128                 struct rte_eth_fc_conf *fc_conf);
 129 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 130                 struct rte_eth_pfc_conf *pfc_conf);
 131 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 132                 struct rte_eth_rss_reta *reta_conf);
 133 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 134                 struct rte_eth_rss_reta *reta_conf);
 135 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 136 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 137 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 138 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 139 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 140                 void *param);
 141 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 142 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 143                 uint32_t index, uint32_t pool);
 144 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 145 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 146
 147 /* For Virtual Function support */
 148 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 149                 struct rte_eth_dev *eth_dev);
 150 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 151 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 152 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 153 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 154 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 155 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 156                 struct rte_eth_stats *stats);
 157 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 158 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 159                 uint16_t vlan_id, int on);
 160 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 161                 uint16_t queue, int on);
 162 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 163 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 164
 165 /*
 166  * Define VF Stats MACRO for Non "cleared on read" register
 167  */
 168 #define UPDATE_VF_STAT(reg, last, cur)                          \
 169 {                                                               \
 170         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 171         cur += latest - last;                                   \
 172         last = latest;                                          \
 173 }
 174
 175 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 176 {                                                                \
 177         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 178         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 179         u64 latest = ((new_msb << 32) | new_lsb);                \
 180         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 181         last = latest;                                           \
 182 }
 183
 184 #define IXGBE_SET_HWSTRIP(h, q) do{\
 185                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 186                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 187                 (h)->bitmap[idx] |= 1 << bit;\
 188         }while(0)
 189
 190 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 191                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 192                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 193                 (h)->bitmap[idx] &= ~(1 << bit);\
 194         }while(0)
 195
 196 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 197                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 198                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 199                 (r) = (h)->bitmap[idx] >> bit & 1;\
 200         }while(0)
 201
 202 /*
 203  * The set of PCI devices this driver supports
 204  */
 205 static struct rte_pci_id pci_id_ixgbe_map[] = {
 206
 207 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 208 #include "rte_pci_dev_ids.h"
 209
 210 { .vendor_id = 0, /* sentinel */ },
 211 };
 212
 213
 214 /*
 215  * The set of PCI devices this driver supports (for 82599 VF)
 216  */
 217 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 218
 219 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 220 #include "rte_pci_dev_ids.h"
 221 { .vendor_id = 0, /* sentinel */ },
 222
 223 };
 224
 225 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 226         .dev_configure        = ixgbe_dev_configure,
 227         .dev_start            = ixgbe_dev_start,
 228         .dev_stop             = ixgbe_dev_stop,
 229         .dev_close            = ixgbe_dev_close,
 230         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 231         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 232         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 233         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 234         .link_update          = ixgbe_dev_link_update,
 235         .stats_get            = ixgbe_dev_stats_get,
 236         .stats_reset          = ixgbe_dev_stats_reset,
 237         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 238         .dev_infos_get        = ixgbe_dev_info_get,
 239         .vlan_filter_set      = ixgbe_vlan_filter_set,
 240         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 241         .vlan_offload_set     = ixgbe_vlan_offload_set,
 242         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 243         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 244         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 245         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 246         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 247         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 248         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 249         .dev_led_on           = ixgbe_dev_led_on,
 250         .dev_led_off          = ixgbe_dev_led_off,
 251         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 252         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 253         .mac_addr_add         = ixgbe_add_rar,
 254         .mac_addr_remove      = ixgbe_remove_rar,
 255         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 256         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 257         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 258         .fdir_infos_get               = ixgbe_fdir_info_get,
 259         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 260         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 261         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 262         .fdir_set_masks               = ixgbe_fdir_set_masks,
 263         .reta_update          = ixgbe_dev_rss_reta_update,
 264         .reta_query           = ixgbe_dev_rss_reta_query,
 265 };
 266
 267 /*
 268  * dev_ops for virtual function, bare necessities for basic vf
 269  * operation have been implemented
 270  */
 271 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 272
 273         .dev_configure        = ixgbevf_dev_configure,
 274         .dev_start            = ixgbevf_dev_start,
 275         .dev_stop             = ixgbevf_dev_stop,
 276         .link_update          = ixgbe_dev_link_update,
 277         .stats_get            = ixgbevf_dev_stats_get,
 278         .stats_reset          = ixgbevf_dev_stats_reset,
 279         .dev_close            = ixgbevf_dev_close,
 280         .dev_infos_get        = ixgbe_dev_info_get,
 281         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 282         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 283         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 284         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 285         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 286         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 287         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 288 };
 289
 290 /**
 291  * Atomically reads the link status information from global
 292  * structure rte_eth_dev.
 293  *
 294  * @param dev
 295  *   - Pointer to the structure rte_eth_dev to read from.
 296  *   - Pointer to the buffer to be saved with the link status.
 297  *
 298  * @return
 299  *   - On success, zero.
 300  *   - On failure, negative value.
 301  */
 302 static inline int
 303 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 304                                 struct rte_eth_link *link)
 305 {
 306         struct rte_eth_link *dst = link;
 307         struct rte_eth_link *src = &(dev->data->dev_link);
 308
 309         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 310                                         *(uint64_t *)src) == 0)
 311                 return -1;
 312
 313         return 0;
 314 }
 315
 316 /**
 317  * Atomically writes the link status information into global
 318  * structure rte_eth_dev.
 319  *
 320  * @param dev
 321  *   - Pointer to the structure rte_eth_dev to read from.
 322  *   - Pointer to the buffer to be saved with the link status.
 323  *
 324  * @return
 325  *   - On success, zero.
 326  *   - On failure, negative value.
 327  */
 328 static inline int
 329 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 330                                 struct rte_eth_link *link)
 331 {
 332         struct rte_eth_link *dst = &(dev->data->dev_link);
 333         struct rte_eth_link *src = link;
 334
 335         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 336                                         *(uint64_t *)src) == 0)
 337                 return -1;
 338
 339         return 0;
 340 }
 341
 342 /*
 343  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 344  */
 345 static inline int
 346 ixgbe_is_sfp(struct ixgbe_hw *hw)
 347 {
 348         switch (hw->phy.type) {
 349         case ixgbe_phy_sfp_avago:
 350         case ixgbe_phy_sfp_ftl:
 351         case ixgbe_phy_sfp_intel:
 352         case ixgbe_phy_sfp_unknown:
 353         case ixgbe_phy_sfp_passive_tyco:
 354         case ixgbe_phy_sfp_passive_unknown:
 355                 return 1;
 356         default:
 357                 return 0;
 358         }
 359 }
 360
 361 static inline int32_t
 362 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 363 {
 364         uint32_t ctrl_ext;
 365         int32_t status;
 366
 367         status = ixgbe_reset_hw(hw);
 368
 369         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 370         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 371         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 372         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 373         IXGBE_WRITE_FLUSH(hw);
 374
 375         return status;
 376 }
 377
 378 static inline void
 379 ixgbe_enable_intr(struct rte_eth_dev *dev)
 380 {
 381         struct ixgbe_interrupt *intr =
 382                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 383         struct ixgbe_hw *hw =
 384                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 385
 386         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 387         IXGBE_WRITE_FLUSH(hw);
 388 }
 389
 390 /*
 391  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 392  */
 393 static void
 394 ixgbe_disable_intr(struct ixgbe_hw *hw)
 395 {
 396         PMD_INIT_FUNC_TRACE();
 397
 398         if (hw->mac.type == ixgbe_mac_82598EB) {
 399                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 400         } else {
 401                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 402                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 403                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 404         }
 405         IXGBE_WRITE_FLUSH(hw);
 406 }
 407
 408 /*
 409  * This function resets queue statistics mapping registers.
 410  * From Niantic datasheet, Initialization of Statistics section:
 411  * "...if software requires the queue counters, the RQSMR and TQSM registers
 412  * must be re-programmed following a device reset.
 413  */
 414 static void
 415 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 416 {
 417         uint32_t i;
 418
 419         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 420                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 421                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 422         }
 423 }
 424
 425
 426 static int
 427 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 428                                   uint16_t queue_id,
 429                                   uint8_t stat_idx,
 430                                   uint8_t is_rx)
 431 {
 432 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 433 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 434 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 435
 436         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 437         struct ixgbe_stat_mapping_registers *stat_mappings =
 438                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 439         uint32_t qsmr_mask = 0;
 440         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 441         uint32_t q_map;
 442         uint8_t n, offset;
 443
 444         if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
 445                 return -ENOSYS;
 446
 447         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
 448                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
 449
 450         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 451         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 452                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
 453                 return -EIO;
 454         }
 455         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 456
 457         /* Now clear any previous stat_idx set */
 458         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 459         if (!is_rx)
 460                 stat_mappings->tqsm[n] &= ~clearing_mask;
 461         else
 462                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 463
 464         q_map = (uint32_t)stat_idx;
 465         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 466         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 467         if (!is_rx)
 468                 stat_mappings->tqsm[n] |= qsmr_mask;
 469         else
 470                 stat_mappings->rqsmr[n] |= qsmr_mask;
 471
 472         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
 473                      "%s[%d] = 0x%08x\n",
 474                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
 475                      is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 476
 477         /* Now write the mapping in the appropriate register */
 478         if (is_rx) {
 479                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
 480                              stat_mappings->rqsmr[n], n);
 481                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 482         }
 483         else {
 484                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
 485                              stat_mappings->tqsm[n], n);
 486                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 487         }
 488         return 0;
 489 }
 490
 491 static void
 492 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 493 {
 494         struct ixgbe_stat_mapping_registers *stat_mappings =
 495                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 496         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 497         int i;
 498
 499         /* write whatever was in stat mapping table to the NIC */
 500         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 501                 /* rx */
 502                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 503
 504                 /* tx */
 505                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 506         }
 507 }
 508
 509 static void
 510 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 511 {
 512         uint8_t i;
 513         struct ixgbe_dcb_tc_config *tc;
 514         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 515
 516         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 517         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 518         for (i = 0; i < dcb_max_tc; i++) {
 519                 tc = &dcb_config->tc_config[i];
 520                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 521                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 522                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 523                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 524                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 525                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 526                 tc->pfc = ixgbe_dcb_pfc_disabled;
 527         }
 528
 529         /* Initialize default user to priority mapping, UPx->TC0 */
 530         tc = &dcb_config->tc_config[0];
 531         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 532         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 533         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 534                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 535                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 536         }
 537         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 538         dcb_config->pfc_mode_enable = false;
 539         dcb_config->vt_mode = true;
 540         dcb_config->round_robin_enable = false;
 541         /* support all DCB capabilities in 82599 */
 542         dcb_config->support.capabilities = 0xFF;
 543
 544         /*we only support 4 Tcs for X540*/
 545         if (hw->mac.type == ixgbe_mac_X540) {
 546                 dcb_config->num_tcs.pg_tcs = 4;
 547                 dcb_config->num_tcs.pfc_tcs = 4;
 548         }
 549 }
 550
 551 /*
 552  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 553  * It returns 0 on success.
 554  */
 555 static int
 556 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 557                      struct rte_eth_dev *eth_dev)
 558 {
 559         struct rte_pci_device *pci_dev;
 560         struct ixgbe_hw *hw =
 561                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 562         struct ixgbe_vfta * shadow_vfta =
 563                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 564         struct ixgbe_hwstrip *hwstrip =
 565                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 566         struct ixgbe_dcb_config *dcb_config =
 567                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 568         uint32_t ctrl_ext;
 569         uint16_t csum;
 570         int diag, i;
 571
 572         PMD_INIT_FUNC_TRACE();
 573
 574         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 575         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 576         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 577
 578         /* for secondary processes, we don't initialise any further as primary
 579          * has already done this work. Only check we don't need a different
 580          * RX function */
 581         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 582                 if (eth_dev->data->scattered_rx)
 583                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 584                 return 0;
 585         }
 586         pci_dev = eth_dev->pci_dev;
 587
 588         /* Vendor and Device ID need to be set before init of shared code */
 589         hw->device_id = pci_dev->id.device_id;
 590         hw->vendor_id = pci_dev->id.vendor_id;
 591         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 592 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
 593         hw->allow_unsupported_sfp = 1;
 594 #endif
 595
 596         /* Initialize the shared code */
 597         diag = ixgbe_init_shared_code(hw);
 598         if (diag != IXGBE_SUCCESS) {
 599                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 600                 return -EIO;
 601         }
 602
 603         /* Initialize DCB configuration*/
 604         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 605         ixgbe_dcb_init(hw,dcb_config);
 606         /* Get Hardware Flow Control setting */
 607         hw->fc.requested_mode = ixgbe_fc_full;
 608         hw->fc.current_mode = ixgbe_fc_full;
 609         hw->fc.pause_time = IXGBE_FC_PAUSE;
 610         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 611                 hw->fc.low_water[i] = IXGBE_FC_LO;
 612                 hw->fc.high_water[i] = IXGBE_FC_HI;
 613         }
 614         hw->fc.send_xon = 1;
 615
 616         /* Make sure we have a good EEPROM before we read from it */
 617         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 618         if (diag != IXGBE_SUCCESS) {
 619                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 620                 return -EIO;
 621         }
 622
 623         diag = ixgbe_init_hw(hw);
 624
 625         /*
 626          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 627          * is called too soon after the kernel driver unbinding/binding occurs.
 628          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 629          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 630          * also called. See ixgbe_identify_phy_82599(). The reason for the
 631          * failure is not known, and only occuts when virtualisation features
 632          * are disabled in the bios. A delay of 100ms  was found to be enough by
 633          * trial-and-error, and is doubled to be safe.
 634          */
 635         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 636                 rte_delay_ms(200);
 637                 diag = ixgbe_init_hw(hw);
 638         }
 639
 640         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 641                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 642                     "LOM.  Please be aware there may be issues associated "
 643                     "with your hardware.\n If you are experiencing problems "
 644                     "please contact your Intel or hardware representative "
 645                     "who provided you with this hardware.\n");
 646         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 647                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
 648         if (diag) {
 649                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 650                 return -EIO;
 651         }
 652
 653         /* disable interrupt */
 654         ixgbe_disable_intr(hw);
 655
 656         /* pick up the PCI bus settings for reporting later */
 657         ixgbe_get_bus_info(hw);
 658
 659         /* reset mappings for queue statistics hw counters*/
 660         ixgbe_reset_qstat_mappings(hw);
 661
 662         /* Allocate memory for storing MAC addresses */
 663         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 664                         hw->mac.num_rar_entries, 0);
 665         if (eth_dev->data->mac_addrs == NULL) {
 666                 PMD_INIT_LOG(ERR,
 667                         "Failed to allocate %d bytes needed to store MAC addresses",
 668                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 669                 return -ENOMEM;
 670         }
 671         /* Copy the permanent MAC address */
 672         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 673                         &eth_dev->data->mac_addrs[0]);
 674
 675         /* initialize the vfta */
 676         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 677
 678         /* initialize the hw strip bitmap*/
 679         memset(hwstrip, 0, sizeof(*hwstrip));
 680
 681         /* initialize PF if max_vfs not zero */
 682         ixgbe_pf_host_init(eth_dev);
 683
 684         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 685         /* let hardware know driver is loaded */
 686         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 687         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 688         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 689         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 690         IXGBE_WRITE_FLUSH(hw);
 691
 692         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 693                 PMD_INIT_LOG(DEBUG,
 694                              "MAC: %d, PHY: %d, SFP+: %d<n",
 695                              (int) hw->mac.type, (int) hw->phy.type,
 696                              (int) hw->phy.sfp_type);
 697         else
 698                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
 699                              (int) hw->mac.type, (int) hw->phy.type);
 700
 701         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 702                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 703                         pci_dev->id.device_id);
 704
 705         rte_intr_callback_register(&(pci_dev->intr_handle),
 706                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 707
 708         /* enable uio intr after callback register */
 709         rte_intr_enable(&(pci_dev->intr_handle));
 710
 711         /* enable support intr */
 712         ixgbe_enable_intr(eth_dev);
 713
 714         return 0;
 715 }
 716
 717 /*
 718  * Virtual Function device init
 719  */
 720 static int
 721 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 722                      struct rte_eth_dev *eth_dev)
 723 {
 724         struct rte_pci_device *pci_dev;
 725         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 726         int diag;
 727         struct ixgbe_vfta * shadow_vfta =
 728                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 729         struct ixgbe_hwstrip *hwstrip =
 730                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 731
 732         PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
 733
 734         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 735         pci_dev = eth_dev->pci_dev;
 736
 737         hw->device_id = pci_dev->id.device_id;
 738         hw->vendor_id = pci_dev->id.vendor_id;
 739         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 740
 741         /* initialize the vfta */
 742         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 743
 744         /* initialize the hw strip bitmap*/
 745         memset(hwstrip, 0, sizeof(*hwstrip));
 746
 747         /* Initialize the shared code */
 748         diag = ixgbe_init_shared_code(hw);
 749         if (diag != IXGBE_SUCCESS) {
 750                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 751                 return -EIO;
 752         }
 753
 754         /* init_mailbox_params */
 755         hw->mbx.ops.init_params(hw);
 756
 757         /* Disable the interrupts for VF */
 758         ixgbevf_intr_disable(hw);
 759
 760         hw->mac.num_rar_entries = hw->mac.max_rx_queues;
 761         diag = hw->mac.ops.reset_hw(hw);
 762
 763         if (diag != IXGBE_SUCCESS) {
 764                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 765                         RTE_LOG(ERR, PMD, "\tThe MAC address is not valid.\n"
 766                                         "\tThe most likely cause of this error is that the VM host\n"
 767                                         "\thas not assigned a valid MAC address to this VF device.\n"
 768                                         "\tPlease consult the DPDK Release Notes (FAQ section) for\n"
 769                                         "\ta possible solution to this problem.\n");
 770                 return (diag);
 771         }
 772
 773         /* Allocate memory for storing MAC addresses */
 774         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
 775                         hw->mac.num_rar_entries, 0);
 776         if (eth_dev->data->mac_addrs == NULL) {
 777                 PMD_INIT_LOG(ERR,
 778                         "Failed to allocate %d bytes needed to store MAC addresses",
 779                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 780                 return -ENOMEM;
 781         }
 782
 783         /* Copy the permanent MAC address */
 784         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 785                         &eth_dev->data->mac_addrs[0]);
 786
 787         /* reset the hardware with the new settings */
 788         diag = hw->mac.ops.start_hw(hw);
 789         switch (diag) {
 790                 case  0:
 791                         break;
 792
 793                 default:
 794                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 795                         return (-EIO);
 796         }
 797
 798         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
 799                          eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
 800                          "ixgbe_mac_82599_vf");
 801
 802         return 0;
 803 }
 804
 805 static struct eth_driver rte_ixgbe_pmd = {
 806         {
 807                 .name = "rte_ixgbe_pmd",
 808                 .id_table = pci_id_ixgbe_map,
 809 #ifdef RTE_EAL_UNBIND_PORTS
 810                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 811 #endif
 812         },
 813         .eth_dev_init = eth_ixgbe_dev_init,
 814         .dev_private_size = sizeof(struct ixgbe_adapter),
 815 };
 816
 817 /*
 818  * virtual function driver struct
 819  */
 820 static struct eth_driver rte_ixgbevf_pmd = {
 821         {
 822                 .name = "rte_ixgbevf_pmd",
 823                 .id_table = pci_id_ixgbevf_map,
 824 #ifdef RTE_EAL_UNBIND_PORTS
 825                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 826 #endif
 827         },
 828         .eth_dev_init = eth_ixgbevf_dev_init,
 829         .dev_private_size = sizeof(struct ixgbe_adapter),
 830 };
 831
 832 /*
 833  * Driver initialization routine.
 834  * Invoked once at EAL init time.
 835  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 836  */
 837 int
 838 rte_ixgbe_pmd_init(void)
 839 {
 840         PMD_INIT_FUNC_TRACE();
 841
 842         rte_eth_driver_register(&rte_ixgbe_pmd);
 843         return 0;
 844 }
 845
 846 /*
 847  * VF Driver initialization routine.
 848  * Invoked one at EAL init time.
 849  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
 850  */
 851 int
 852 rte_ixgbevf_pmd_init(void)
 853 {
 854         DEBUGFUNC("rte_ixgbevf_pmd_init");
 855
 856         rte_eth_driver_register(&rte_ixgbevf_pmd);
 857         return (0);
 858 }
 859
 860 static int
 861 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 862 {
 863         struct ixgbe_hw *hw =
 864                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 865         struct ixgbe_vfta * shadow_vfta =
 866                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
 867         uint32_t vfta;
 868         uint32_t vid_idx;
 869         uint32_t vid_bit;
 870
 871         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
 872         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
 873         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
 874         if (on)
 875                 vfta |= vid_bit;
 876         else
 877                 vfta &= ~vid_bit;
 878         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
 879
 880         /* update local VFTA copy */
 881         shadow_vfta->vfta[vid_idx] = vfta;
 882
 883         return 0;
 884 }
 885
 886 static void
 887 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 888 {
 889         if (on)
 890                 ixgbe_vlan_hw_strip_enable(dev, queue);
 891         else
 892                 ixgbe_vlan_hw_strip_disable(dev, queue);
 893 }
 894
 895 static void
 896 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
 897 {
 898         struct ixgbe_hw *hw =
 899                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 900
 901         /* Only the high 16-bits is valid */
 902         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
 903 }
 904
 905 void
 906 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
 907 {
 908         struct ixgbe_hw *hw =
 909                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 910         uint32_t vlnctrl;
 911
 912         PMD_INIT_FUNC_TRACE();
 913
 914         /* Filter Table Disable */
 915         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 916         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
 917
 918         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
 919 }
 920
 921 void
 922 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 923 {
 924         struct ixgbe_hw *hw =
 925                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 926         struct ixgbe_vfta * shadow_vfta =
 927                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
 928         uint32_t vlnctrl;
 929         uint16_t i;
 930
 931         PMD_INIT_FUNC_TRACE();
 932
 933         /* Filter Table Enable */
 934         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 935         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
 936         vlnctrl |= IXGBE_VLNCTRL_VFE;
 937
 938         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
 939
 940         /* write whatever is in local vfta copy */
 941         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
 942                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
 943 }
 944
 945 static void
 946 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
 947 {
 948         struct ixgbe_hwstrip *hwstrip =
 949                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
 950
 951         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
 952                 return;
 953
 954         if (on)
 955                 IXGBE_SET_HWSTRIP(hwstrip, queue);
 956         else
 957                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
 958 }
 959
 960 static void
 961 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
 962 {
 963         struct ixgbe_hw *hw =
 964                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 965         uint32_t ctrl;
 966
 967         PMD_INIT_FUNC_TRACE();
 968
 969         if (hw->mac.type == ixgbe_mac_82598EB) {
 970                 /* No queue level support */
 971                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
 972                 return;
 973         }
 974         else {
 975                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
 976                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
 977                 ctrl &= ~IXGBE_RXDCTL_VME;
 978                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
 979         }
 980         /* record those setting for HW strip per queue */
 981         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
 982 }
 983
 984 static void
 985 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
 986 {
 987         struct ixgbe_hw *hw =
 988                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 989         uint32_t ctrl;
 990
 991         PMD_INIT_FUNC_TRACE();
 992
 993         if (hw->mac.type == ixgbe_mac_82598EB) {
 994                 /* No queue level supported */
 995                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
 996                 return;
 997         }
 998         else {
 999                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1000                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1001                 ctrl |= IXGBE_RXDCTL_VME;
1002                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1003         }
1004         /* record those setting for HW strip per queue */
1005         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1006 }
1007
1008 void
1009 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1010 {
1011         struct ixgbe_hw *hw =
1012                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1013         uint32_t ctrl;
1014         uint16_t i;
1015
1016         PMD_INIT_FUNC_TRACE();
1017
1018         if (hw->mac.type == ixgbe_mac_82598EB) {
1019                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1020                 ctrl &= ~IXGBE_VLNCTRL_VME;
1021                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1022         }
1023         else {
1024                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1025                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1026                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1027                         ctrl &= ~IXGBE_RXDCTL_VME;
1028                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1029
1030                         /* record those setting for HW strip per queue */
1031                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1032                 }
1033         }
1034 }
1035
1036 void
1037 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1038 {
1039         struct ixgbe_hw *hw =
1040                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1041         uint32_t ctrl;
1042         uint16_t i;
1043
1044         PMD_INIT_FUNC_TRACE();
1045
1046         if (hw->mac.type == ixgbe_mac_82598EB) {
1047                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1048                 ctrl |= IXGBE_VLNCTRL_VME;
1049                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1050         }
1051         else {
1052                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1053                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1054                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1055                         ctrl |= IXGBE_RXDCTL_VME;
1056                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1057
1058                         /* record those setting for HW strip per queue */
1059                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1060                 }
1061         }
1062 }
1063
1064 static void
1065 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1066 {
1067         struct ixgbe_hw *hw =
1068                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1069         uint32_t ctrl;
1070
1071         PMD_INIT_FUNC_TRACE();
1072
1073         /* DMATXCTRL: Geric Double VLAN Disable */
1074         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1075         ctrl &= ~IXGBE_DMATXCTL_GDV;
1076         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1077
1078         /* CTRL_EXT: Global Double VLAN Disable */
1079         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1080         ctrl &= ~IXGBE_EXTENDED_VLAN;
1081         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1082
1083 }
1084
1085 static void
1086 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1087 {
1088         struct ixgbe_hw *hw =
1089                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1090         uint32_t ctrl;
1091
1092         PMD_INIT_FUNC_TRACE();
1093
1094         /* DMATXCTRL: Geric Double VLAN Enable */
1095         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1096         ctrl |= IXGBE_DMATXCTL_GDV;
1097         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1098
1099         /* CTRL_EXT: Global Double VLAN Enable */
1100         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1101         ctrl |= IXGBE_EXTENDED_VLAN;
1102         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1103
1104         /*
1105          * VET EXT field in the EXVET register = 0x8100 by default
1106          * So no need to change. Same to VT field of DMATXCTL register
1107          */
1108 }
1109
1110 static void
1111 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1112 {
1113         if(mask & ETH_VLAN_STRIP_MASK){
1114                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1115                         ixgbe_vlan_hw_strip_enable_all(dev);
1116                 else
1117                         ixgbe_vlan_hw_strip_disable_all(dev);
1118         }
1119
1120         if(mask & ETH_VLAN_FILTER_MASK){
1121                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1122                         ixgbe_vlan_hw_filter_enable(dev);
1123                 else
1124                         ixgbe_vlan_hw_filter_disable(dev);
1125         }
1126
1127         if(mask & ETH_VLAN_EXTEND_MASK){
1128                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1129                         ixgbe_vlan_hw_extend_enable(dev);
1130                 else
1131                         ixgbe_vlan_hw_extend_disable(dev);
1132         }
1133 }
1134
1135 static int
1136 ixgbe_dev_configure(struct rte_eth_dev *dev)
1137 {
1138         struct ixgbe_interrupt *intr =
1139                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1140
1141         PMD_INIT_FUNC_TRACE();
1142
1143         /* set flag to update link status after init */
1144         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1145
1146         return 0;
1147 }
1148
1149 /*
1150  * Configure device link speed and setup link.
1151  * It returns 0 on success.
1152  */
1153 static int
1154 ixgbe_dev_start(struct rte_eth_dev *dev)
1155 {
1156         struct ixgbe_hw *hw =
1157                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1158         int err, link_up = 0, negotiate = 0;
1159         uint32_t speed = 0;
1160         int mask = 0;
1161         int status;
1162
1163         PMD_INIT_FUNC_TRACE();
1164
1165         /* IXGBE devices don't support half duplex */
1166         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1167                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1168                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%u) for port %u\n",
1169                                 dev->data->dev_conf.link_duplex,
1170                                 dev->data->port_id);
1171                 return -EINVAL;
1172         }
1173
1174         /* stop adapter */
1175         hw->adapter_stopped = FALSE;
1176         ixgbe_stop_adapter(hw);
1177
1178         /* reinitialize adapter
1179          * this calls reset and start */
1180         status = ixgbe_pf_reset_hw(hw);
1181         if (status != 0)
1182                 return -1;
1183         hw->mac.ops.start_hw(hw);
1184
1185         /* configure PF module if SRIOV enabled */
1186         ixgbe_pf_host_configure(dev);
1187
1188         /* initialize transmission unit */
1189         ixgbe_dev_tx_init(dev);
1190
1191         /* This can fail when allocating mbufs for descriptor rings */
1192         err = ixgbe_dev_rx_init(dev);
1193         if (err) {
1194                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1195                 goto error;
1196         }
1197
1198         ixgbe_dev_rxtx_start(dev);
1199
1200         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1201                 err = hw->mac.ops.setup_sfp(hw);
1202                 if (err)
1203                         goto error;
1204         }
1205
1206         /* Turn on the laser */
1207         ixgbe_enable_tx_laser(hw);
1208
1209         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1210         if (err)
1211                 goto error;
1212         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1213         if (err)
1214                 goto error;
1215
1216         switch(dev->data->dev_conf.link_speed) {
1217         case ETH_LINK_SPEED_AUTONEG:
1218                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1219                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1220                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1221                 break;
1222         case ETH_LINK_SPEED_100:
1223                 /*
1224                  * Invalid for 82598 but error will be detected by
1225                  * ixgbe_setup_link()
1226                  */
1227                 speed = IXGBE_LINK_SPEED_100_FULL;
1228                 break;
1229         case ETH_LINK_SPEED_1000:
1230                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1231                 break;
1232         case ETH_LINK_SPEED_10000:
1233                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1234                 break;
1235         default:
1236                 PMD_INIT_LOG(ERR, "Invalid link_speed (%u) for port %u\n",
1237                                 dev->data->dev_conf.link_speed, dev->data->port_id);
1238                 goto error;
1239         }
1240
1241         err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1242         if (err)
1243                 goto error;
1244
1245         /* check if lsc interrupt is enabled */
1246         if (dev->data->dev_conf.intr_conf.lsc != 0)
1247                 ixgbe_dev_lsc_interrupt_setup(dev);
1248
1249         /* resume enabled intr since hw reset */
1250         ixgbe_enable_intr(dev);
1251
1252         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1253                 ETH_VLAN_EXTEND_MASK;
1254         ixgbe_vlan_offload_set(dev, mask);
1255
1256         /* Configure DCB hw */
1257         ixgbe_configure_dcb(dev);
1258
1259         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1260                 err = ixgbe_fdir_configure(dev);
1261                 if (err)
1262                         goto error;
1263         }
1264
1265         ixgbe_restore_statistics_mapping(dev);
1266
1267         return (0);
1268
1269 error:
1270         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1271         ixgbe_dev_clear_queues(dev);
1272         return -EIO;
1273 }
1274
1275 /*
1276  * Stop device: disable rx and tx functions to allow for reconfiguring.
1277  */
1278 static void
1279 ixgbe_dev_stop(struct rte_eth_dev *dev)
1280 {
1281         struct rte_eth_link link;
1282         struct ixgbe_hw *hw =
1283                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1284
1285         PMD_INIT_FUNC_TRACE();
1286
1287         /* disable interrupts */
1288         ixgbe_disable_intr(hw);
1289
1290         /* reset the NIC */
1291         ixgbe_pf_reset_hw(hw);
1292         hw->adapter_stopped = FALSE;
1293
1294         /* stop adapter */
1295         ixgbe_stop_adapter(hw);
1296
1297         /* Turn off the laser */
1298         ixgbe_disable_tx_laser(hw);
1299
1300         ixgbe_dev_clear_queues(dev);
1301
1302         /* Clear recorded link status */
1303         memset(&link, 0, sizeof(link));
1304         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1305 }
1306
1307 /*
1308  * Reest and stop device.
1309  */
1310 static void
1311 ixgbe_dev_close(struct rte_eth_dev *dev)
1312 {
1313         struct ixgbe_hw *hw =
1314                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1315
1316         PMD_INIT_FUNC_TRACE();
1317
1318         ixgbe_pf_reset_hw(hw);
1319
1320         ixgbe_dev_stop(dev);
1321         hw->adapter_stopped = 1;
1322
1323         ixgbe_disable_pcie_master(hw);
1324
1325         /* reprogram the RAR[0] in case user changed it. */
1326         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1327 }
1328
1329 /*
1330  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1331  */
1332 static void
1333 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1334 {
1335         struct ixgbe_hw *hw =
1336                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1337         struct ixgbe_hw_stats *hw_stats =
1338                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1339         uint32_t bprc, lxon, lxoff, total;
1340         uint64_t total_missed_rx, total_qbrc, total_qprc;
1341         unsigned i;
1342
1343         total_missed_rx = 0;
1344         total_qbrc = 0;
1345         total_qprc = 0;
1346
1347         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1348         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1349         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1350         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1351
1352         for (i = 0; i < 8; i++) {
1353                 uint32_t mp;
1354                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1355                 /* global total per queue */
1356                 hw_stats->mpc[i] += mp;
1357                 /* Running comprehensive total for stats display */
1358                 total_missed_rx += hw_stats->mpc[i];
1359                 if (hw->mac.type == ixgbe_mac_82598EB)
1360                         hw_stats->rnbc[i] +=
1361                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1362                 hw_stats->pxontxc[i] +=
1363                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1364                 hw_stats->pxonrxc[i] +=
1365                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1366                 hw_stats->pxofftxc[i] +=
1367                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1368                 hw_stats->pxoffrxc[i] +=
1369                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1370                 hw_stats->pxon2offc[i] +=
1371                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1372         }
1373         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1374                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1375                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1376                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1377                 hw_stats->qbrc[i] +=
1378                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1379                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1380                 hw_stats->qbtc[i] +=
1381                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1382                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1383
1384                 total_qprc += hw_stats->qprc[i];
1385                 total_qbrc += hw_stats->qbrc[i];
1386         }
1387         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1388         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1389         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1390
1391         /* Note that gprc counts missed packets */
1392         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1393
1394         if (hw->mac.type != ixgbe_mac_82598EB) {
1395                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1396                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1397                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1398                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1399                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1400                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1401                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1402                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1403         } else {
1404                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1405                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1406                 /* 82598 only has a counter in the high register */
1407                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1408                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1409                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1410         }
1411
1412         /*
1413          * Workaround: mprc hardware is incorrectly counting
1414          * broadcasts, so for now we subtract those.
1415          */
1416         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1417         hw_stats->bprc += bprc;
1418         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1419         if (hw->mac.type == ixgbe_mac_82598EB)
1420                 hw_stats->mprc -= bprc;
1421
1422         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1423         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1424         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1425         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1426         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1427         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1428
1429         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1430         hw_stats->lxontxc += lxon;
1431         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1432         hw_stats->lxofftxc += lxoff;
1433         total = lxon + lxoff;
1434
1435         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1436         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1437         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1438         hw_stats->gptc -= total;
1439         hw_stats->mptc -= total;
1440         hw_stats->ptc64 -= total;
1441         hw_stats->gotc -= total * ETHER_MIN_LEN;
1442
1443         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1444         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1445         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1446         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1447         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1448         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1449         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1450         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1451         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1452         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1453         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1454         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1455         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1456         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1457         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1458         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1459         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1460         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1461         /* Only read FCOE on 82599 */
1462         if (hw->mac.type != ixgbe_mac_82598EB) {
1463                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1464                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1465                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1466                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1467                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1468         }
1469
1470         if (stats == NULL)
1471                 return;
1472
1473         /* Fill out the rte_eth_stats statistics structure */
1474         stats->ipackets = total_qprc;
1475         stats->ibytes = total_qbrc;
1476         stats->opackets = hw_stats->gptc;
1477         stats->obytes = hw_stats->gotc;
1478         stats->imcasts = hw_stats->mprc;
1479
1480         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1481                 stats->q_ipackets[i] = hw_stats->qprc[i];
1482                 stats->q_opackets[i] = hw_stats->qptc[i];
1483                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1484                 stats->q_obytes[i] = hw_stats->qbtc[i];
1485                 stats->q_errors[i] = hw_stats->qprdc[i];
1486         }
1487
1488         /* Rx Errors */
1489         stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1490                 hw_stats->rlec;
1491
1492         stats->oerrors  = 0;
1493
1494         /* Flow Director Stats registers */
1495         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1496         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1497         stats->fdirmatch = hw_stats->fdirmatch;
1498         stats->fdirmiss = hw_stats->fdirmiss;
1499 }
1500
1501 static void
1502 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1503 {
1504         struct ixgbe_hw_stats *stats =
1505                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1506
1507         /* HW registers are cleared on read */
1508         ixgbe_dev_stats_get(dev, NULL);
1509
1510         /* Reset software totals */
1511         memset(stats, 0, sizeof(*stats));
1512 }
1513
1514 static void
1515 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1516 {
1517         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1519                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1520
1521         /* Good Rx packet, include VF loopback */
1522         UPDATE_VF_STAT(IXGBE_VFGPRC,
1523             hw_stats->last_vfgprc, hw_stats->vfgprc);
1524
1525         /* Good Rx octets, include VF loopback */
1526         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1527             hw_stats->last_vfgorc, hw_stats->vfgorc);
1528
1529         /* Good Tx packet, include VF loopback */
1530         UPDATE_VF_STAT(IXGBE_VFGPTC,
1531             hw_stats->last_vfgptc, hw_stats->vfgptc);
1532
1533         /* Good Tx octets, include VF loopback */
1534         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1535             hw_stats->last_vfgotc, hw_stats->vfgotc);
1536
1537         /* Rx Multicst Packet */
1538         UPDATE_VF_STAT(IXGBE_VFMPRC,
1539             hw_stats->last_vfmprc, hw_stats->vfmprc);
1540
1541         if (stats == NULL)
1542                 return;
1543
1544         memset(stats, 0, sizeof(*stats));
1545         stats->ipackets = hw_stats->vfgprc;
1546         stats->ibytes = hw_stats->vfgorc;
1547         stats->opackets = hw_stats->vfgptc;
1548         stats->obytes = hw_stats->vfgotc;
1549         stats->imcasts = hw_stats->vfmprc;
1550 }
1551
1552 static void
1553 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1554 {
1555         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1556                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1557
1558         /* Sync HW register to the last stats */
1559         ixgbevf_dev_stats_get(dev, NULL);
1560
1561         /* reset HW current stats*/
1562         hw_stats->vfgprc = 0;
1563         hw_stats->vfgorc = 0;
1564         hw_stats->vfgptc = 0;
1565         hw_stats->vfgotc = 0;
1566         hw_stats->vfmprc = 0;
1567
1568 }
1569
1570 static void
1571 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1572 {
1573         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1574
1575         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1576         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1577         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1578         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1579         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1580 }
1581
1582 /* return 0 means link status changed, -1 means not changed */
1583 static int
1584 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1585 {
1586         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1587         struct rte_eth_link link, old;
1588         ixgbe_link_speed link_speed;
1589         int link_up;
1590         int diag;
1591
1592         link.link_status = 0;
1593         link.link_speed = 0;
1594         link.link_duplex = 0;
1595         memset(&old, 0, sizeof(old));
1596         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1597
1598         /* check if it needs to wait to complete, if lsc interrupt is enabled */
1599         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1600                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1601         else
1602                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1603         if (diag != 0) {
1604                 link.link_speed = ETH_LINK_SPEED_100;
1605                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1606                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1607                 if (link.link_status == old.link_status)
1608                         return -1;
1609                 return 0;
1610         }
1611
1612         if (link_up == 0) {
1613                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1614                 if (link.link_status == old.link_status)
1615                         return -1;
1616                 return 0;
1617         }
1618         link.link_status = 1;
1619         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1620
1621         switch (link_speed) {
1622         default:
1623         case IXGBE_LINK_SPEED_UNKNOWN:
1624                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1625                 link.link_speed = ETH_LINK_SPEED_100;
1626                 break;
1627
1628         case IXGBE_LINK_SPEED_100_FULL:
1629                 link.link_speed = ETH_LINK_SPEED_100;
1630                 break;
1631
1632         case IXGBE_LINK_SPEED_1GB_FULL:
1633                 link.link_speed = ETH_LINK_SPEED_1000;
1634                 break;
1635
1636         case IXGBE_LINK_SPEED_10GB_FULL:
1637                 link.link_speed = ETH_LINK_SPEED_10000;
1638                 break;
1639         }
1640         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1641
1642         if (link.link_status == old.link_status)
1643                 return -1;
1644
1645         return 0;
1646 }
1647
1648 static void
1649 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1650 {
1651         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1652         uint32_t fctrl;
1653
1654         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1655         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1656         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1657 }
1658
1659 static void
1660 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1661 {
1662         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663         uint32_t fctrl;
1664
1665         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1666         fctrl &= (~IXGBE_FCTRL_UPE);
1667         if (dev->data->all_multicast == 1)
1668                 fctrl |= IXGBE_FCTRL_MPE;
1669         else
1670                 fctrl &= (~IXGBE_FCTRL_MPE);
1671         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1672 }
1673
1674 static void
1675 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1676 {
1677         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1678         uint32_t fctrl;
1679
1680         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1681         fctrl |= IXGBE_FCTRL_MPE;
1682         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1683 }
1684
1685 static void
1686 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1687 {
1688         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1689         uint32_t fctrl;
1690
1691         if (dev->data->promiscuous == 1)
1692                 return; /* must remain in all_multicast mode */
1693
1694         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1695         fctrl &= (~IXGBE_FCTRL_MPE);
1696         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1697 }
1698
1699 /**
1700  * It clears the interrupt causes and enables the interrupt.
1701  * It will be called once only during nic initialized.
1702  *
1703  * @param dev
1704  *  Pointer to struct rte_eth_dev.
1705  *
1706  * @return
1707  *  - On success, zero.
1708  *  - On failure, a negative value.
1709  */
1710 static int
1711 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
1712 {
1713         struct ixgbe_interrupt *intr =
1714                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1715
1716         ixgbe_dev_link_status_print(dev);
1717         intr->mask |= IXGBE_EICR_LSC;
1718
1719         return 0;
1720 }
1721
1722 /*
1723  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1724  *
1725  * @param dev
1726  *  Pointer to struct rte_eth_dev.
1727  *
1728  * @return
1729  *  - On success, zero.
1730  *  - On failure, a negative value.
1731  */
1732 static int
1733 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1734 {
1735         uint32_t eicr;
1736         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1737         struct ixgbe_interrupt *intr =
1738                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1739
1740         /* clear all cause mask */
1741         ixgbe_disable_intr(hw);
1742
1743         /* read-on-clear nic registers here */
1744         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1745         PMD_DRV_LOG(INFO, "eicr %x", eicr);
1746
1747         intr->flags = 0;
1748         if (eicr & IXGBE_EICR_LSC) {
1749                 /* set flag for async link update */
1750                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1751         }
1752
1753         if (eicr & IXGBE_EICR_MAILBOX)
1754                 intr->flags |= IXGBE_FLAG_MAILBOX;
1755
1756         return 0;
1757 }
1758
1759 /**
1760  * It gets and then prints the link status.
1761  *
1762  * @param dev
1763  *  Pointer to struct rte_eth_dev.
1764  *
1765  * @return
1766  *  - On success, zero.
1767  *  - On failure, a negative value.
1768  */
1769 static void
1770 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1771 {
1772         struct rte_eth_link link;
1773
1774         memset(&link, 0, sizeof(link));
1775         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1776         if (link.link_status) {
1777                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1778                                         (int)(dev->data->port_id),
1779                                         (unsigned)link.link_speed,
1780                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1781                                         "full-duplex" : "half-duplex");
1782         } else {
1783                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1784                                 (int)(dev->data->port_id));
1785         }
1786         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1787                                 dev->pci_dev->addr.domain,
1788                                 dev->pci_dev->addr.bus,
1789                                 dev->pci_dev->addr.devid,
1790                                 dev->pci_dev->addr.function);
1791 }
1792
1793 /*
1794  * It executes link_update after knowing an interrupt occured.
1795  *
1796  * @param dev
1797  *  Pointer to struct rte_eth_dev.
1798  *
1799  * @return
1800  *  - On success, zero.
1801  *  - On failure, a negative value.
1802  */
1803 static int
1804 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1805 {
1806         struct ixgbe_interrupt *intr =
1807                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1808         int64_t timeout;
1809         struct rte_eth_link link;
1810         int intr_enable_delay = false;
1811
1812         PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
1813
1814         if (intr->flags & IXGBE_FLAG_MAILBOX) {
1815                 ixgbe_pf_mbx_process(dev);
1816                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
1817         }
1818
1819         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1820                 /* get the link status before link update, for predicting later */
1821                 memset(&link, 0, sizeof(link));
1822                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1823
1824                 ixgbe_dev_link_update(dev, 0);
1825
1826                 /* likely to up */
1827                 if (!link.link_status)
1828                         /* handle it 1 sec later, wait it being stable */
1829                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
1830                 /* likely to down */
1831                 else
1832                         /* handle it 4 sec later, wait it being stable */
1833                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
1834
1835                 ixgbe_dev_link_status_print(dev);
1836
1837                 intr_enable_delay = true;
1838         }
1839
1840         if (intr_enable_delay) {
1841                 if (rte_eal_alarm_set(timeout * 1000,
1842                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
1843                         PMD_DRV_LOG(ERR, "Error setting alarm");
1844         } else {
1845                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
1846                 ixgbe_enable_intr(dev);
1847                 rte_intr_enable(&(dev->pci_dev->intr_handle));
1848         }
1849
1850
1851         return 0;
1852 }
1853
1854 /**
1855  * Interrupt handler which shall be registered for alarm callback for delayed
1856  * handling specific interrupt to wait for the stable nic state. As the
1857  * NIC interrupt state is not stable for ixgbe after link is just down,
1858  * it needs to wait 4 seconds to get the stable status.
1859  *
1860  * @param handle
1861  *  Pointer to interrupt handle.
1862  * @param param
1863  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1864  *
1865  * @return
1866  *  void
1867  */
1868 static void
1869 ixgbe_dev_interrupt_delayed_handler(void *param)
1870 {
1871         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1872         struct ixgbe_interrupt *intr =
1873                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1874         struct ixgbe_hw *hw =
1875                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1876         uint32_t eicr;
1877
1878         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1879         if (eicr & IXGBE_EICR_MAILBOX)
1880                 ixgbe_pf_mbx_process(dev);
1881
1882         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1883                 ixgbe_dev_link_update(dev, 0);
1884                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
1885                 ixgbe_dev_link_status_print(dev);
1886                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1887         }
1888
1889         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
1890         ixgbe_enable_intr(dev);
1891         rte_intr_enable(&(dev->pci_dev->intr_handle));
1892 }
1893
1894 /**
1895  * Interrupt handler triggered by NIC  for handling
1896  * specific interrupt.
1897  *
1898  * @param handle
1899  *  Pointer to interrupt handle.
1900  * @param param
1901  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1902  *
1903  * @return
1904  *  void
1905  */
1906 static void
1907 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1908                                                         void *param)
1909 {
1910         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1911         ixgbe_dev_interrupt_get_status(dev);
1912         ixgbe_dev_interrupt_action(dev);
1913 }
1914
1915 static int
1916 ixgbe_dev_led_on(struct rte_eth_dev *dev)
1917 {
1918         struct ixgbe_hw *hw;
1919
1920         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1921         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
1922 }
1923
1924 static int
1925 ixgbe_dev_led_off(struct rte_eth_dev *dev)
1926 {
1927         struct ixgbe_hw *hw;
1928
1929         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
1931 }
1932
1933 static int
1934 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1935 {
1936         struct ixgbe_hw *hw;
1937         int err;
1938         uint32_t rx_buf_size;
1939         uint32_t max_high_water;
1940         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
1941                 ixgbe_fc_none,
1942                 ixgbe_fc_rx_pause,
1943                 ixgbe_fc_tx_pause,
1944                 ixgbe_fc_full
1945         };
1946
1947         PMD_INIT_FUNC_TRACE();
1948
1949         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1950         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
1951         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1952
1953         /*
1954          * At least reserve one Ethernet frame for watermark
1955          * high_water/low_water in kilo bytes for ixgbe
1956          */
1957         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
1958         if ((fc_conf->high_water > max_high_water) ||
1959                 (fc_conf->high_water < fc_conf->low_water)) {
1960                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
1961                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
1962                 return (-EINVAL);
1963         }
1964
1965         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
1966         hw->fc.pause_time     = fc_conf->pause_time;
1967         hw->fc.high_water[0]  = fc_conf->high_water;
1968         hw->fc.low_water[0]   = fc_conf->low_water;
1969         hw->fc.send_xon       = fc_conf->send_xon;
1970
1971         err = ixgbe_fc_enable(hw);
1972         /* Not negotiated is not an error case */
1973         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
1974                 return 0;
1975         }
1976
1977         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
1978         return -EIO;
1979 }
1980
1981 /**
1982  *  ixgbe_pfc_enable_generic - Enable flow control
1983  *  @hw: pointer to hardware structure
1984  *  @tc_num: traffic class number
1985  *  Enable flow control according to the current settings.
1986  */
1987 static int
1988 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
1989 {
1990         int ret_val = 0;
1991         uint32_t mflcn_reg, fccfg_reg;
1992         uint32_t reg;
1993         uint32_t fcrtl, fcrth;
1994         uint8_t i;
1995         uint8_t nb_rx_en;
1996
1997         /* Validate the water mark configuration */
1998         if (!hw->fc.pause_time) {
1999                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2000                 goto out;
2001         }
2002
2003         /* Low water mark of zero causes XOFF floods */
2004         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2005                  /* High/Low water can not be 0 */
2006                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2007                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2008                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2009                         goto out;
2010                 }
2011
2012                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2013                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2014                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2015                         goto out;
2016                 }
2017         }
2018         /* Negotiate the fc mode to use */
2019         ixgbe_fc_autoneg(hw);
2020
2021         /* Disable any previous flow control settings */
2022         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2023         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2024
2025         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2026         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2027
2028         switch (hw->fc.current_mode) {
2029         case ixgbe_fc_none:
2030                 /*
2031                  * If the count of enabled RX Priority Flow control >1,
2032                  * and the TX pause can not be disabled
2033                  */
2034                 nb_rx_en = 0;
2035                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2036                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2037                         if (reg & IXGBE_FCRTH_FCEN)
2038                                 nb_rx_en++;
2039                 }
2040                 if (nb_rx_en > 1)
2041                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2042                 break;
2043         case ixgbe_fc_rx_pause:
2044                 /*
2045                  * Rx Flow control is enabled and Tx Flow control is
2046                  * disabled by software override. Since there really
2047                  * isn't a way to advertise that we are capable of RX
2048                  * Pause ONLY, we will advertise that we support both
2049                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2050                  * disable the adapter's ability to send PAUSE frames.
2051                  */
2052                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2053                 /*
2054                  * If the count of enabled RX Priority Flow control >1,
2055                  * and the TX pause can not be disabled
2056                  */
2057                 nb_rx_en = 0;
2058                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2059                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2060                         if (reg & IXGBE_FCRTH_FCEN)
2061                                 nb_rx_en++;
2062                 }
2063                 if (nb_rx_en > 1)
2064                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2065                 break;
2066         case ixgbe_fc_tx_pause:
2067                 /*
2068                  * Tx Flow control is enabled, and Rx Flow control is
2069                  * disabled by software override.
2070                  */
2071                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2072                 break;
2073         case ixgbe_fc_full:
2074                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2075                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2076                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2077                 break;
2078         default:
2079                 DEBUGOUT("Flow control param set incorrectly\n");
2080                 ret_val = IXGBE_ERR_CONFIG;
2081                 goto out;
2082                 break;
2083         }
2084
2085         /* Set 802.3x based flow control settings. */
2086         mflcn_reg |= IXGBE_MFLCN_DPF;
2087         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2088         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2089
2090         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2091         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2092                 hw->fc.high_water[tc_num]) {
2093                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2094                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2095                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2096         } else {
2097                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2098                 /*
2099                  * In order to prevent Tx hangs when the internal Tx
2100                  * switch is enabled we must set the high water mark
2101                  * to the maximum FCRTH value.  This allows the Tx
2102                  * switch to function even under heavy Rx workloads.
2103                  */
2104                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2105         }
2106         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2107
2108         /* Configure pause time (2 TCs per register) */
2109         reg = hw->fc.pause_time * 0x00010001;
2110         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2111                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2112
2113         /* Configure flow control refresh threshold value */
2114         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2115
2116 out:
2117         return ret_val;
2118 }
2119
2120 static int
2121 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2122 {
2123         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2124         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2125
2126         if(hw->mac.type != ixgbe_mac_82598EB) {
2127                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2128         }
2129         return ret_val;
2130 }
2131
2132 static int
2133 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2134 {
2135         int err;
2136         uint32_t rx_buf_size;
2137         uint32_t max_high_water;
2138         uint8_t tc_num;
2139         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2140         struct ixgbe_hw *hw =
2141                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2142         struct ixgbe_dcb_config *dcb_config =
2143                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2144
2145         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2146                 ixgbe_fc_none,
2147                 ixgbe_fc_rx_pause,
2148                 ixgbe_fc_tx_pause,
2149                 ixgbe_fc_full
2150         };
2151
2152         PMD_INIT_FUNC_TRACE();
2153
2154         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2155         tc_num = map[pfc_conf->priority];
2156         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2157         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2158         /*
2159          * At least reserve one Ethernet frame for watermark
2160          * high_water/low_water in kilo bytes for ixgbe
2161          */
2162         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2163         if ((pfc_conf->fc.high_water > max_high_water) ||
2164                 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2165                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2166                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2167                 return (-EINVAL);
2168         }
2169
2170         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2171         hw->fc.pause_time = pfc_conf->fc.pause_time;
2172         hw->fc.send_xon = pfc_conf->fc.send_xon;
2173         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2174         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2175
2176         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2177
2178         /* Not negotiated is not an error case */
2179         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2180                 return 0;
2181
2182         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2183         return -EIO;
2184 }
2185
2186 static int
2187 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2188                                 struct rte_eth_rss_reta *reta_conf)
2189 {
2190         uint8_t i,j,mask;
2191         uint32_t reta;
2192         struct ixgbe_hw *hw =
2193                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2194
2195         PMD_INIT_FUNC_TRACE();
2196         /*
2197         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2198         * 128-entries in 32 registers
2199          */
2200         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2201                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2202                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2203                 else
2204                         mask = (uint8_t)((reta_conf->mask_hi >>
2205                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2206                 if (mask != 0) {
2207                         reta = 0;
2208                         if (mask != 0xF)
2209                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2210
2211                         for (j = 0; j < 4; j++) {
2212                                 if (mask & (0x1 << j)) {
2213                                         if (mask != 0xF)
2214                                                 reta &= ~(0xFF << 8 * j);
2215                                         reta |= reta_conf->reta[i + j] << 8*j;
2216                                 }
2217                         }
2218                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2219                 }
2220         }
2221
2222         return 0;
2223 }
2224
2225 static int
2226 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2227                                 struct rte_eth_rss_reta *reta_conf)
2228 {
2229         uint8_t i,j,mask;
2230         uint32_t reta;
2231         struct ixgbe_hw *hw =
2232                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2233
2234         PMD_INIT_FUNC_TRACE();
2235         /*
2236          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2237          * 128-entries in 32 registers
2238          */
2239         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2240                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2241                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2242                 else
2243                         mask = (uint8_t)((reta_conf->mask_hi >>
2244                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2245
2246                 if (mask != 0) {
2247                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2248                         for (j = 0; j < 4; j++) {
2249                                 if (mask & (0x1 << j))
2250                                         reta_conf->reta[i + j] =
2251                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2252                         }
2253                 }
2254         }
2255
2256         return 0;
2257 }
2258
2259 static void
2260 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2261                                 uint32_t index, uint32_t pool)
2262 {
2263         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2264         uint32_t enable_addr = 1;
2265
2266         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2267 }
2268
2269 static void
2270 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2271 {
2272         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2273
2274         ixgbe_clear_rar(hw, index);
2275 }
2276
2277 /*
2278  * Virtual Function operations
2279  */
2280 static void
2281 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2282 {
2283         PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2284
2285         /* Clear interrupt mask to stop from interrupts being generated */
2286         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2287
2288         IXGBE_WRITE_FLUSH(hw);
2289 }
2290
2291 static int
2292 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2293 {
2294         struct rte_eth_conf* conf = &dev->data->dev_conf;
2295
2296         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2297                 dev->data->port_id);
2298
2299         /*
2300          * VF has no ability to enable/disable HW CRC
2301          * Keep the persistent behavior the same as Host PF
2302          */
2303 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2304         if (!conf->rxmode.hw_strip_crc) {
2305                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2306                 conf->rxmode.hw_strip_crc = 1;
2307         }
2308 #else
2309         if (conf->rxmode.hw_strip_crc) {
2310                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2311                 conf->rxmode.hw_strip_crc = 0;
2312         }
2313 #endif
2314
2315         return 0;
2316 }
2317
2318 static int
2319 ixgbevf_dev_start(struct rte_eth_dev *dev)
2320 {
2321         struct ixgbe_hw *hw =
2322                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2323         int err, mask = 0;
2324
2325         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2326
2327         hw->mac.ops.reset_hw(hw);
2328
2329         ixgbevf_dev_tx_init(dev);
2330
2331         /* This can fail when allocating mbufs for descriptor rings */
2332         err = ixgbevf_dev_rx_init(dev);
2333         if (err) {
2334                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2335                 ixgbe_dev_clear_queues(dev);
2336                 return err;
2337         }
2338
2339         /* Set vfta */
2340         ixgbevf_set_vfta_all(dev,1);
2341
2342         /* Set HW strip */
2343         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2344                 ETH_VLAN_EXTEND_MASK;
2345         ixgbevf_vlan_offload_set(dev, mask);
2346
2347         ixgbevf_dev_rxtx_start(dev);
2348
2349         return 0;
2350 }
2351
2352 static void
2353 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2354 {
2355         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2356
2357         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2358
2359         hw->adapter_stopped = TRUE;
2360         ixgbe_stop_adapter(hw);
2361
2362         /*
2363           * Clear what we set, but we still keep shadow_vfta to
2364           * restore after device starts
2365           */
2366         ixgbevf_set_vfta_all(dev,0);
2367
2368         ixgbe_dev_clear_queues(dev);
2369 }
2370
2371 static void
2372 ixgbevf_dev_close(struct rte_eth_dev *dev)
2373 {
2374         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2375
2376         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2377
2378         ixgbe_reset_hw(hw);
2379
2380         ixgbevf_dev_stop(dev);
2381
2382         /* reprogram the RAR[0] in case user changed it. */
2383         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2384 }
2385
2386 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2387 {
2388         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389         struct ixgbe_vfta * shadow_vfta =
2390                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2391         int i = 0, j = 0, vfta = 0, mask = 1;
2392
2393         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2394                 vfta = shadow_vfta->vfta[i];
2395                 if(vfta){
2396                         mask = 1;
2397                         for (j = 0; j < 32; j++){
2398                                 if(vfta & mask)
2399                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2400                                 mask<<=1;
2401                         }
2402                 }
2403         }
2404
2405 }
2406
2407 static int
2408 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2409 {
2410         struct ixgbe_hw *hw =
2411                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2412         struct ixgbe_vfta * shadow_vfta =
2413                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2414         uint32_t vid_idx = 0;
2415         uint32_t vid_bit = 0;
2416         int ret = 0;
2417
2418         PMD_INIT_FUNC_TRACE();
2419
2420         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2421         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2422         if(ret){
2423                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2424                 return ret;
2425         }
2426         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2427         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2428
2429         /* Save what we set and retore it after device reset */
2430         if (on)
2431                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2432         else
2433                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2434
2435         return 0;
2436 }
2437
2438 static void
2439 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2440 {
2441         struct ixgbe_hw *hw =
2442                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2443         uint32_t ctrl;
2444
2445         PMD_INIT_FUNC_TRACE();
2446
2447         if(queue >= hw->mac.max_rx_queues)
2448                 return;
2449
2450         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2451         if(on)
2452                 ctrl |= IXGBE_RXDCTL_VME;
2453         else
2454                 ctrl &= ~IXGBE_RXDCTL_VME;
2455         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2456
2457         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2458 }
2459
2460 static void
2461 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2462 {
2463         struct ixgbe_hw *hw =
2464                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465         uint16_t i;
2466         int on = 0;
2467
2468         /* VF function only support hw strip feature, others are not support */
2469         if(mask & ETH_VLAN_STRIP_MASK){
2470                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2471
2472                 for(i=0; i < hw->mac.max_rx_queues; i++)
2473                         ixgbevf_vlan_strip_queue_set(dev,i,on);
2474         }
2475 }