lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  96
  97 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  98
  99 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 100                 struct rte_eth_dev *eth_dev);
 101 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 102 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 103 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 104 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 105 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 106 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 107 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 108 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 109 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 110 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 111 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 112                                 int wait_to_complete);
 113 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 114                                 struct rte_eth_stats *stats);
 115 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 116 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 117                                              uint16_t queue_id,
 118                                              uint8_t stat_idx,
 119                                              uint8_t is_rx);
 120 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 121                                 struct rte_eth_dev_info *dev_info);
 122
 123 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 124
 125 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 126                 uint16_t vlan_id, int on);
 127 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 128 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 129                 uint16_t queue, bool on);
 130 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 131                 int on);
 132 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 133 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 134 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 135 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 136 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 137
 138 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 139 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 140 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 141                                struct rte_eth_fc_conf *fc_conf);
 142 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 143                                struct rte_eth_fc_conf *fc_conf);
 144 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 145                 struct rte_eth_pfc_conf *pfc_conf);
 146 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 147                 struct rte_eth_rss_reta *reta_conf);
 148 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 149                 struct rte_eth_rss_reta *reta_conf);
 150 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 154 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 155                 void *param);
 156 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 157 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 158                 uint32_t index, uint32_t pool);
 159 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 160 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 161
 162 /* For Virtual Function support */
 163 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 164                 struct rte_eth_dev *eth_dev);
 165 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 166 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 167 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 168 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 169 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 170 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 171                 struct rte_eth_stats *stats);
 172 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 173 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 174                 uint16_t vlan_id, int on);
 175 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 176                 uint16_t queue, int on);
 177 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 178 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 179
 180 /* For Eth VMDQ APIs support */
 181 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 182                 ether_addr* mac_addr,uint8_t on);
 183 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 184 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 185                 uint16_t rx_mask, uint8_t on);
 186 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 187 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 188 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 189                 uint64_t pool_mask,uint8_t vlan_on);
 190 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 191                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 192                 uint8_t rule_id, uint8_t on);
 193 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 194                 uint8_t rule_id);
 195
 196 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 197                 uint16_t queue_idx, uint16_t tx_rate);
 198 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 199                 uint16_t tx_rate, uint64_t q_msk);
 200
 201 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 202                                  struct ether_addr *mac_addr,
 203                                  uint32_t index, uint32_t pool);
 204 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 205 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
 206                         struct rte_syn_filter *filter, uint16_t rx_queue);
 207 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
 208 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
 209                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 210 static int ixgbe_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 211                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 212 static int ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
 213                         uint16_t index);
 214 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 215                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 216 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 217                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 218 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 219                         uint16_t index);
 220 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 221                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 222
 223 /*
 224  * Define VF Stats MACRO for Non "cleared on read" register
 225  */
 226 #define UPDATE_VF_STAT(reg, last, cur)                          \
 227 {                                                               \
 228         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 229         cur += latest - last;                                   \
 230         last = latest;                                          \
 231 }
 232
 233 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 234 {                                                                \
 235         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 236         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 237         u64 latest = ((new_msb << 32) | new_lsb);                \
 238         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 239         last = latest;                                           \
 240 }
 241
 242 #define IXGBE_SET_HWSTRIP(h, q) do{\
 243                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 244                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 245                 (h)->bitmap[idx] |= 1 << bit;\
 246         }while(0)
 247
 248 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 249                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 250                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 251                 (h)->bitmap[idx] &= ~(1 << bit);\
 252         }while(0)
 253
 254 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 255                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 256                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 257                 (r) = (h)->bitmap[idx] >> bit & 1;\
 258         }while(0)
 259
 260 /*
 261  * The set of PCI devices this driver supports
 262  */
 263 static struct rte_pci_id pci_id_ixgbe_map[] = {
 264
 265 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 266 #include "rte_pci_dev_ids.h"
 267
 268 { .vendor_id = 0, /* sentinel */ },
 269 };
 270
 271
 272 /*
 273  * The set of PCI devices this driver supports (for 82599 VF)
 274  */
 275 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 276
 277 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 278 #include "rte_pci_dev_ids.h"
 279 { .vendor_id = 0, /* sentinel */ },
 280
 281 };
 282
 283 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 284         .dev_configure        = ixgbe_dev_configure,
 285         .dev_start            = ixgbe_dev_start,
 286         .dev_stop             = ixgbe_dev_stop,
 287         .dev_set_link_up    = ixgbe_dev_set_link_up,
 288         .dev_set_link_down  = ixgbe_dev_set_link_down,
 289         .dev_close            = ixgbe_dev_close,
 290         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 291         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 292         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 293         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 294         .link_update          = ixgbe_dev_link_update,
 295         .stats_get            = ixgbe_dev_stats_get,
 296         .stats_reset          = ixgbe_dev_stats_reset,
 297         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 298         .dev_infos_get        = ixgbe_dev_info_get,
 299         .mtu_set              = ixgbe_dev_mtu_set,
 300         .vlan_filter_set      = ixgbe_vlan_filter_set,
 301         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 302         .vlan_offload_set     = ixgbe_vlan_offload_set,
 303         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 304         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 305         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 306         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 307         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 308         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 309         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 310         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 311         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 312         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 313         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 314         .dev_led_on           = ixgbe_dev_led_on,
 315         .dev_led_off          = ixgbe_dev_led_off,
 316         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 317         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 318         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 319         .mac_addr_add         = ixgbe_add_rar,
 320         .mac_addr_remove      = ixgbe_remove_rar,
 321         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 322         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 323         .mirror_rule_set      = ixgbe_mirror_rule_set,
 324         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 325         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 326         .set_vf_rx            = ixgbe_set_pool_rx,
 327         .set_vf_tx            = ixgbe_set_pool_tx,
 328         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 329         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 330         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 331         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 332         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 333         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 334         .fdir_infos_get               = ixgbe_fdir_info_get,
 335         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 336         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 337         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 338         .fdir_set_masks               = ixgbe_fdir_set_masks,
 339         .reta_update          = ixgbe_dev_rss_reta_update,
 340         .reta_query           = ixgbe_dev_rss_reta_query,
 341 #ifdef RTE_NIC_BYPASS
 342         .bypass_init          = ixgbe_bypass_init,
 343         .bypass_state_set     = ixgbe_bypass_state_store,
 344         .bypass_state_show    = ixgbe_bypass_state_show,
 345         .bypass_event_set     = ixgbe_bypass_event_store,
 346         .bypass_event_show    = ixgbe_bypass_event_show,
 347         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 348         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 349         .bypass_ver_show      = ixgbe_bypass_ver_show,
 350         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 351 #endif /* RTE_NIC_BYPASS */
 352         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 353         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 354         .add_syn_filter          = ixgbe_add_syn_filter,
 355         .remove_syn_filter       = ixgbe_remove_syn_filter,
 356         .get_syn_filter          = ixgbe_get_syn_filter,
 357         .add_ethertype_filter    = ixgbe_add_ethertype_filter,
 358         .remove_ethertype_filter = ixgbe_remove_ethertype_filter,
 359         .get_ethertype_filter    = ixgbe_get_ethertype_filter,
 360         .add_5tuple_filter       = ixgbe_add_5tuple_filter,
 361         .remove_5tuple_filter    = ixgbe_remove_5tuple_filter,
 362         .get_5tuple_filter       = ixgbe_get_5tuple_filter,
 363 };
 364
 365 /*
 366  * dev_ops for virtual function, bare necessities for basic vf
 367  * operation have been implemented
 368  */
 369 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 370
 371         .dev_configure        = ixgbevf_dev_configure,
 372         .dev_start            = ixgbevf_dev_start,
 373         .dev_stop             = ixgbevf_dev_stop,
 374         .link_update          = ixgbe_dev_link_update,
 375         .stats_get            = ixgbevf_dev_stats_get,
 376         .stats_reset          = ixgbevf_dev_stats_reset,
 377         .dev_close            = ixgbevf_dev_close,
 378         .dev_infos_get        = ixgbe_dev_info_get,
 379         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 380         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 381         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 382         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 383         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 384         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 385         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 386         .mac_addr_add         = ixgbevf_add_mac_addr,
 387         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 388 };
 389
 390 /**
 391  * Atomically reads the link status information from global
 392  * structure rte_eth_dev.
 393  *
 394  * @param dev
 395  *   - Pointer to the structure rte_eth_dev to read from.
 396  *   - Pointer to the buffer to be saved with the link status.
 397  *
 398  * @return
 399  *   - On success, zero.
 400  *   - On failure, negative value.
 401  */
 402 static inline int
 403 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 404                                 struct rte_eth_link *link)
 405 {
 406         struct rte_eth_link *dst = link;
 407         struct rte_eth_link *src = &(dev->data->dev_link);
 408
 409         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 410                                         *(uint64_t *)src) == 0)
 411                 return -1;
 412
 413         return 0;
 414 }
 415
 416 /**
 417  * Atomically writes the link status information into global
 418  * structure rte_eth_dev.
 419  *
 420  * @param dev
 421  *   - Pointer to the structure rte_eth_dev to read from.
 422  *   - Pointer to the buffer to be saved with the link status.
 423  *
 424  * @return
 425  *   - On success, zero.
 426  *   - On failure, negative value.
 427  */
 428 static inline int
 429 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 430                                 struct rte_eth_link *link)
 431 {
 432         struct rte_eth_link *dst = &(dev->data->dev_link);
 433         struct rte_eth_link *src = link;
 434
 435         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 436                                         *(uint64_t *)src) == 0)
 437                 return -1;
 438
 439         return 0;
 440 }
 441
 442 /*
 443  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 444  */
 445 static inline int
 446 ixgbe_is_sfp(struct ixgbe_hw *hw)
 447 {
 448         switch (hw->phy.type) {
 449         case ixgbe_phy_sfp_avago:
 450         case ixgbe_phy_sfp_ftl:
 451         case ixgbe_phy_sfp_intel:
 452         case ixgbe_phy_sfp_unknown:
 453         case ixgbe_phy_sfp_passive_tyco:
 454         case ixgbe_phy_sfp_passive_unknown:
 455                 return 1;
 456         default:
 457                 return 0;
 458         }
 459 }
 460
 461 static inline int32_t
 462 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 463 {
 464         uint32_t ctrl_ext;
 465         int32_t status;
 466
 467         status = ixgbe_reset_hw(hw);
 468
 469         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 470         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 471         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 472         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 473         IXGBE_WRITE_FLUSH(hw);
 474
 475         return status;
 476 }
 477
 478 static inline void
 479 ixgbe_enable_intr(struct rte_eth_dev *dev)
 480 {
 481         struct ixgbe_interrupt *intr =
 482                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 483         struct ixgbe_hw *hw =
 484                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 485
 486         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 487         IXGBE_WRITE_FLUSH(hw);
 488 }
 489
 490 /*
 491  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 492  */
 493 static void
 494 ixgbe_disable_intr(struct ixgbe_hw *hw)
 495 {
 496         PMD_INIT_FUNC_TRACE();
 497
 498         if (hw->mac.type == ixgbe_mac_82598EB) {
 499                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 500         } else {
 501                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 502                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 503                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 504         }
 505         IXGBE_WRITE_FLUSH(hw);
 506 }
 507
 508 /*
 509  * This function resets queue statistics mapping registers.
 510  * From Niantic datasheet, Initialization of Statistics section:
 511  * "...if software requires the queue counters, the RQSMR and TQSM registers
 512  * must be re-programmed following a device reset.
 513  */
 514 static void
 515 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 516 {
 517         uint32_t i;
 518
 519         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 520                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 521                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 522         }
 523 }
 524
 525
 526 static int
 527 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 528                                   uint16_t queue_id,
 529                                   uint8_t stat_idx,
 530                                   uint8_t is_rx)
 531 {
 532 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 533 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 534 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 535
 536         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 537         struct ixgbe_stat_mapping_registers *stat_mappings =
 538                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 539         uint32_t qsmr_mask = 0;
 540         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 541         uint32_t q_map;
 542         uint8_t n, offset;
 543
 544         if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
 545                 return -ENOSYS;
 546
 547         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
 548                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
 549
 550         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 551         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 552                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
 553                 return -EIO;
 554         }
 555         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 556
 557         /* Now clear any previous stat_idx set */
 558         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 559         if (!is_rx)
 560                 stat_mappings->tqsm[n] &= ~clearing_mask;
 561         else
 562                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 563
 564         q_map = (uint32_t)stat_idx;
 565         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 566         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 567         if (!is_rx)
 568                 stat_mappings->tqsm[n] |= qsmr_mask;
 569         else
 570                 stat_mappings->rqsmr[n] |= qsmr_mask;
 571
 572         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
 573                      "%s[%d] = 0x%08x\n",
 574                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
 575                      is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 576
 577         /* Now write the mapping in the appropriate register */
 578         if (is_rx) {
 579                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
 580                              stat_mappings->rqsmr[n], n);
 581                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 582         }
 583         else {
 584                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
 585                              stat_mappings->tqsm[n], n);
 586                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 587         }
 588         return 0;
 589 }
 590
 591 static void
 592 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 593 {
 594         struct ixgbe_stat_mapping_registers *stat_mappings =
 595                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 596         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 597         int i;
 598
 599         /* write whatever was in stat mapping table to the NIC */
 600         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 601                 /* rx */
 602                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 603
 604                 /* tx */
 605                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 606         }
 607 }
 608
 609 static void
 610 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 611 {
 612         uint8_t i;
 613         struct ixgbe_dcb_tc_config *tc;
 614         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 615
 616         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 617         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 618         for (i = 0; i < dcb_max_tc; i++) {
 619                 tc = &dcb_config->tc_config[i];
 620                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 621                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 622                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 623                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 624                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 625                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 626                 tc->pfc = ixgbe_dcb_pfc_disabled;
 627         }
 628
 629         /* Initialize default user to priority mapping, UPx->TC0 */
 630         tc = &dcb_config->tc_config[0];
 631         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 632         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 633         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 634                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 635                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 636         }
 637         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 638         dcb_config->pfc_mode_enable = false;
 639         dcb_config->vt_mode = true;
 640         dcb_config->round_robin_enable = false;
 641         /* support all DCB capabilities in 82599 */
 642         dcb_config->support.capabilities = 0xFF;
 643
 644         /*we only support 4 Tcs for X540*/
 645         if (hw->mac.type == ixgbe_mac_X540) {
 646                 dcb_config->num_tcs.pg_tcs = 4;
 647                 dcb_config->num_tcs.pfc_tcs = 4;
 648         }
 649 }
 650
 651 /*
 652  * Ensure that all locks are released before first NVM or PHY access
 653  */
 654 static void
 655 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 656 {
 657         uint16_t mask;
 658
 659         /*
 660          * Phy lock should not fail in this early stage. If this is the case,
 661          * it is due to an improper exit of the application.
 662          * So force the release of the faulty lock. Release of common lock
 663          * is done automatically by swfw_sync function.
 664          */
 665         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 666         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 667                    DEBUGOUT1("SWFW phy%d lock released", hw->bus.func);
 668         }
 669         ixgbe_release_swfw_semaphore(hw, mask);
 670
 671         /*
 672          * These ones are more tricky since they are common to all ports; but
 673          * swfw_sync retries last long enough (1s) to be almost sure that if
 674          * lock can not be taken it is due to an improper lock of the
 675          * semaphore.
 676          */
 677         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 678         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 679                    DEBUGOUT("SWFW common locks released");
 680         }
 681         ixgbe_release_swfw_semaphore(hw, mask);
 682 }
 683
 684 /*
 685  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 686  * It returns 0 on success.
 687  */
 688 static int
 689 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 690                      struct rte_eth_dev *eth_dev)
 691 {
 692         struct rte_pci_device *pci_dev;
 693         struct ixgbe_hw *hw =
 694                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 695         struct ixgbe_vfta * shadow_vfta =
 696                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 697         struct ixgbe_hwstrip *hwstrip =
 698                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 699         struct ixgbe_dcb_config *dcb_config =
 700                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 701         uint32_t ctrl_ext;
 702         uint16_t csum;
 703         int diag, i;
 704
 705         PMD_INIT_FUNC_TRACE();
 706
 707         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 708         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 709         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 710
 711         /* for secondary processes, we don't initialise any further as primary
 712          * has already done this work. Only check we don't need a different
 713          * RX function */
 714         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 715                 if (eth_dev->data->scattered_rx)
 716                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 717                 return 0;
 718         }
 719         pci_dev = eth_dev->pci_dev;
 720
 721         /* Vendor and Device ID need to be set before init of shared code */
 722         hw->device_id = pci_dev->id.device_id;
 723         hw->vendor_id = pci_dev->id.vendor_id;
 724         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 725 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
 726         hw->allow_unsupported_sfp = 1;
 727 #endif
 728
 729         /* Initialize the shared code */
 730 #ifdef RTE_NIC_BYPASS
 731         diag = ixgbe_bypass_init_shared_code(hw);
 732 #else
 733         diag = ixgbe_init_shared_code(hw);
 734 #endif /* RTE_NIC_BYPASS */
 735
 736         if (diag != IXGBE_SUCCESS) {
 737                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 738                 return -EIO;
 739         }
 740
 741         /* pick up the PCI bus settings for reporting later */
 742         ixgbe_get_bus_info(hw);
 743
 744         /* Unlock any pending hardware semaphore */
 745         ixgbe_swfw_lock_reset(hw);
 746
 747         /* Initialize DCB configuration*/
 748         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 749         ixgbe_dcb_init(hw,dcb_config);
 750         /* Get Hardware Flow Control setting */
 751         hw->fc.requested_mode = ixgbe_fc_full;
 752         hw->fc.current_mode = ixgbe_fc_full;
 753         hw->fc.pause_time = IXGBE_FC_PAUSE;
 754         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 755                 hw->fc.low_water[i] = IXGBE_FC_LO;
 756                 hw->fc.high_water[i] = IXGBE_FC_HI;
 757         }
 758         hw->fc.send_xon = 1;
 759
 760         /* Make sure we have a good EEPROM before we read from it */
 761         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 762         if (diag != IXGBE_SUCCESS) {
 763                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 764                 return -EIO;
 765         }
 766
 767 #ifdef RTE_NIC_BYPASS
 768         diag = ixgbe_bypass_init_hw(hw);
 769 #else
 770         diag = ixgbe_init_hw(hw);
 771 #endif /* RTE_NIC_BYPASS */
 772
 773         /*
 774          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 775          * is called too soon after the kernel driver unbinding/binding occurs.
 776          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 777          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 778          * also called. See ixgbe_identify_phy_82599(). The reason for the
 779          * failure is not known, and only occuts when virtualisation features
 780          * are disabled in the bios. A delay of 100ms  was found to be enough by
 781          * trial-and-error, and is doubled to be safe.
 782          */
 783         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 784                 rte_delay_ms(200);
 785                 diag = ixgbe_init_hw(hw);
 786         }
 787
 788         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 789                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 790                     "LOM.  Please be aware there may be issues associated "
 791                     "with your hardware.\n If you are experiencing problems "
 792                     "please contact your Intel or hardware representative "
 793                     "who provided you with this hardware.\n");
 794         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 795                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
 796         if (diag) {
 797                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 798                 return -EIO;
 799         }
 800
 801         /* disable interrupt */
 802         ixgbe_disable_intr(hw);
 803
 804         /* reset mappings for queue statistics hw counters*/
 805         ixgbe_reset_qstat_mappings(hw);
 806
 807         /* Allocate memory for storing MAC addresses */
 808         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 809                         hw->mac.num_rar_entries, 0);
 810         if (eth_dev->data->mac_addrs == NULL) {
 811                 PMD_INIT_LOG(ERR,
 812                         "Failed to allocate %u bytes needed to store "
 813                         "MAC addresses",
 814                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 815                 return -ENOMEM;
 816         }
 817         /* Copy the permanent MAC address */
 818         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 819                         &eth_dev->data->mac_addrs[0]);
 820
 821         /* Allocate memory for storing hash filter MAC addresses */
 822         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 823                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 824         if (eth_dev->data->hash_mac_addrs == NULL) {
 825                 PMD_INIT_LOG(ERR,
 826                         "Failed to allocate %d bytes needed to store MAC addresses",
 827                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 828                 return -ENOMEM;
 829         }
 830
 831         /* initialize the vfta */
 832         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 833
 834         /* initialize the hw strip bitmap*/
 835         memset(hwstrip, 0, sizeof(*hwstrip));
 836
 837         /* initialize PF if max_vfs not zero */
 838         ixgbe_pf_host_init(eth_dev);
 839
 840         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 841         /* let hardware know driver is loaded */
 842         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 843         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 844         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 845         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 846         IXGBE_WRITE_FLUSH(hw);
 847
 848         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 849                 PMD_INIT_LOG(DEBUG,
 850                              "MAC: %d, PHY: %d, SFP+: %d<n",
 851                              (int) hw->mac.type, (int) hw->phy.type,
 852                              (int) hw->phy.sfp_type);
 853         else
 854                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
 855                              (int) hw->mac.type, (int) hw->phy.type);
 856
 857         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 858                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 859                         pci_dev->id.device_id);
 860
 861         rte_intr_callback_register(&(pci_dev->intr_handle),
 862                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 863
 864         /* enable uio intr after callback register */
 865         rte_intr_enable(&(pci_dev->intr_handle));
 866
 867         /* enable support intr */
 868         ixgbe_enable_intr(eth_dev);
 869
 870         return 0;
 871 }
 872
 873
 874 /*
 875  * Negotiate mailbox API version with the PF.
 876  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 877  * Then we try to negotiate starting with the most recent one.
 878  * If all negotiation attempts fail, then we will proceed with
 879  * the default one (ixgbe_mbox_api_10).
 880  */
 881 static void
 882 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 883 {
 884         int32_t i;
 885
 886         /* start with highest supported, proceed down */
 887         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 888                 ixgbe_mbox_api_11,
 889                 ixgbe_mbox_api_10,
 890         };
 891
 892         for (i = 0;
 893                         i != RTE_DIM(sup_ver) &&
 894                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 895                         i++)
 896                 ;
 897 }
 898
 899 static void
 900 generate_random_mac_addr(struct ether_addr *mac_addr)
 901 {
 902         uint64_t random;
 903
 904         /* Set Organizationally Unique Identifier (OUI) prefix. */
 905         mac_addr->addr_bytes[0] = 0x00;
 906         mac_addr->addr_bytes[1] = 0x09;
 907         mac_addr->addr_bytes[2] = 0xC0;
 908         /* Force indication of locally assigned MAC address. */
 909         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 910         /* Generate the last 3 bytes of the MAC address with a random number. */
 911         random = rte_rand();
 912         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 913 }
 914
 915 /*
 916  * Virtual Function device init
 917  */
 918 static int
 919 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 920                      struct rte_eth_dev *eth_dev)
 921 {
 922         int diag;
 923         uint32_t tc, tcs;
 924         struct rte_pci_device *pci_dev;
 925         struct ixgbe_hw *hw =
 926                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 927         struct ixgbe_vfta * shadow_vfta =
 928                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 929         struct ixgbe_hwstrip *hwstrip =
 930                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 931         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 932
 933         PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
 934
 935         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 936         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 937         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 938
 939         /* for secondary processes, we don't initialise any further as primary
 940          * has already done this work. Only check we don't need a different
 941          * RX function */
 942         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 943                 if (eth_dev->data->scattered_rx)
 944                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 945                 return 0;
 946         }
 947
 948         pci_dev = eth_dev->pci_dev;
 949
 950         hw->device_id = pci_dev->id.device_id;
 951         hw->vendor_id = pci_dev->id.vendor_id;
 952         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 953
 954         /* initialize the vfta */
 955         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 956
 957         /* initialize the hw strip bitmap*/
 958         memset(hwstrip, 0, sizeof(*hwstrip));
 959
 960         /* Initialize the shared code */
 961         diag = ixgbe_init_shared_code(hw);
 962         if (diag != IXGBE_SUCCESS) {
 963                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 964                 return -EIO;
 965         }
 966
 967         /* init_mailbox_params */
 968         hw->mbx.ops.init_params(hw);
 969
 970         /* Disable the interrupts for VF */
 971         ixgbevf_intr_disable(hw);
 972
 973         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
 974         diag = hw->mac.ops.reset_hw(hw);
 975
 976         /*
 977          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
 978          * the underlying PF driver has not assigned a MAC address to the VF.
 979          * In this case, assign a random MAC address.
 980          */
 981         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
 982                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 983                 return (diag);
 984         }
 985
 986         /* negotiate mailbox API version to use with the PF. */
 987         ixgbevf_negotiate_api(hw);
 988
 989         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
 990         ixgbevf_get_queues(hw, &tcs, &tc);
 991
 992         /* Allocate memory for storing MAC addresses */
 993         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
 994                         hw->mac.num_rar_entries, 0);
 995         if (eth_dev->data->mac_addrs == NULL) {
 996                 PMD_INIT_LOG(ERR,
 997                         "Failed to allocate %u bytes needed to store "
 998                         "MAC addresses",
 999                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1000                 return -ENOMEM;
1001         }
1002
1003         /* Generate a random MAC address, if none was assigned by PF. */
1004         if (is_zero_ether_addr(perm_addr)) {
1005                 generate_random_mac_addr(perm_addr);
1006                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1007                 if (diag) {
1008                         rte_free(eth_dev->data->mac_addrs);
1009                         eth_dev->data->mac_addrs = NULL;
1010                         return diag;
1011                 }
1012                 RTE_LOG(INFO, PMD,
1013                         "\tVF MAC address not assigned by Host PF\n"
1014                         "\tAssign randomly generated MAC address "
1015                         "%02x:%02x:%02x:%02x:%02x:%02x\n",
1016                         perm_addr->addr_bytes[0],
1017                         perm_addr->addr_bytes[1],
1018                         perm_addr->addr_bytes[2],
1019                         perm_addr->addr_bytes[3],
1020                         perm_addr->addr_bytes[4],
1021                         perm_addr->addr_bytes[5]);
1022         }
1023
1024         /* Copy the permanent MAC address */
1025         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1026
1027         /* reset the hardware with the new settings */
1028         diag = hw->mac.ops.start_hw(hw);
1029         switch (diag) {
1030                 case  0:
1031                         break;
1032
1033                 default:
1034                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1035                         return (-EIO);
1036         }
1037
1038         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
1039                          eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
1040                          "ixgbe_mac_82599_vf");
1041
1042         return 0;
1043 }
1044
1045 static struct eth_driver rte_ixgbe_pmd = {
1046         {
1047                 .name = "rte_ixgbe_pmd",
1048                 .id_table = pci_id_ixgbe_map,
1049                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1050         },
1051         .eth_dev_init = eth_ixgbe_dev_init,
1052         .dev_private_size = sizeof(struct ixgbe_adapter),
1053 };
1054
1055 /*
1056  * virtual function driver struct
1057  */
1058 static struct eth_driver rte_ixgbevf_pmd = {
1059         {
1060                 .name = "rte_ixgbevf_pmd",
1061                 .id_table = pci_id_ixgbevf_map,
1062                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1063         },
1064         .eth_dev_init = eth_ixgbevf_dev_init,
1065         .dev_private_size = sizeof(struct ixgbe_adapter),
1066 };
1067
1068 /*
1069  * Driver initialization routine.
1070  * Invoked once at EAL init time.
1071  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1072  */
1073 static int
1074 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1075 {
1076         PMD_INIT_FUNC_TRACE();
1077
1078         rte_eth_driver_register(&rte_ixgbe_pmd);
1079         return 0;
1080 }
1081
1082 /*
1083  * VF Driver initialization routine.
1084  * Invoked one at EAL init time.
1085  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1086  */
1087 static int
1088 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1089 {
1090         DEBUGFUNC("rte_ixgbevf_pmd_init");
1091
1092         rte_eth_driver_register(&rte_ixgbevf_pmd);
1093         return (0);
1094 }
1095
1096 static int
1097 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1098 {
1099         struct ixgbe_hw *hw =
1100                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1101         struct ixgbe_vfta * shadow_vfta =
1102                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1103         uint32_t vfta;
1104         uint32_t vid_idx;
1105         uint32_t vid_bit;
1106
1107         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1108         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1109         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1110         if (on)
1111                 vfta |= vid_bit;
1112         else
1113                 vfta &= ~vid_bit;
1114         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1115
1116         /* update local VFTA copy */
1117         shadow_vfta->vfta[vid_idx] = vfta;
1118
1119         return 0;
1120 }
1121
1122 static void
1123 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1124 {
1125         if (on)
1126                 ixgbe_vlan_hw_strip_enable(dev, queue);
1127         else
1128                 ixgbe_vlan_hw_strip_disable(dev, queue);
1129 }
1130
1131 static void
1132 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1133 {
1134         struct ixgbe_hw *hw =
1135                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1136
1137         /* Only the high 16-bits is valid */
1138         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1139 }
1140
1141 void
1142 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1143 {
1144         struct ixgbe_hw *hw =
1145                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1146         uint32_t vlnctrl;
1147
1148         PMD_INIT_FUNC_TRACE();
1149
1150         /* Filter Table Disable */
1151         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1152         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1153
1154         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1155 }
1156
1157 void
1158 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1159 {
1160         struct ixgbe_hw *hw =
1161                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1162         struct ixgbe_vfta * shadow_vfta =
1163                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1164         uint32_t vlnctrl;
1165         uint16_t i;
1166
1167         PMD_INIT_FUNC_TRACE();
1168
1169         /* Filter Table Enable */
1170         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1171         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1172         vlnctrl |= IXGBE_VLNCTRL_VFE;
1173
1174         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1175
1176         /* write whatever is in local vfta copy */
1177         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1178                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1179 }
1180
1181 static void
1182 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1183 {
1184         struct ixgbe_hwstrip *hwstrip =
1185                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1186
1187         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1188                 return;
1189
1190         if (on)
1191                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1192         else
1193                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1194 }
1195
1196 static void
1197 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1198 {
1199         struct ixgbe_hw *hw =
1200                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1201         uint32_t ctrl;
1202
1203         PMD_INIT_FUNC_TRACE();
1204
1205         if (hw->mac.type == ixgbe_mac_82598EB) {
1206                 /* No queue level support */
1207                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1208                 return;
1209         }
1210         else {
1211                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1212                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1213                 ctrl &= ~IXGBE_RXDCTL_VME;
1214                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1215         }
1216         /* record those setting for HW strip per queue */
1217         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1218 }
1219
1220 static void
1221 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1222 {
1223         struct ixgbe_hw *hw =
1224                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1225         uint32_t ctrl;
1226
1227         PMD_INIT_FUNC_TRACE();
1228
1229         if (hw->mac.type == ixgbe_mac_82598EB) {
1230                 /* No queue level supported */
1231                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1232                 return;
1233         }
1234         else {
1235                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1236                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1237                 ctrl |= IXGBE_RXDCTL_VME;
1238                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1239         }
1240         /* record those setting for HW strip per queue */
1241         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1242 }
1243
1244 void
1245 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1246 {
1247         struct ixgbe_hw *hw =
1248                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1249         uint32_t ctrl;
1250         uint16_t i;
1251
1252         PMD_INIT_FUNC_TRACE();
1253
1254         if (hw->mac.type == ixgbe_mac_82598EB) {
1255                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1256                 ctrl &= ~IXGBE_VLNCTRL_VME;
1257                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1258         }
1259         else {
1260                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1261                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1262                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1263                         ctrl &= ~IXGBE_RXDCTL_VME;
1264                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1265
1266                         /* record those setting for HW strip per queue */
1267                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1268                 }
1269         }
1270 }
1271
1272 void
1273 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1274 {
1275         struct ixgbe_hw *hw =
1276                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1277         uint32_t ctrl;
1278         uint16_t i;
1279
1280         PMD_INIT_FUNC_TRACE();
1281
1282         if (hw->mac.type == ixgbe_mac_82598EB) {
1283                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1284                 ctrl |= IXGBE_VLNCTRL_VME;
1285                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1286         }
1287         else {
1288                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1289                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1290                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1291                         ctrl |= IXGBE_RXDCTL_VME;
1292                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1293
1294                         /* record those setting for HW strip per queue */
1295                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1296                 }
1297         }
1298 }
1299
1300 static void
1301 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1302 {
1303         struct ixgbe_hw *hw =
1304                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1305         uint32_t ctrl;
1306
1307         PMD_INIT_FUNC_TRACE();
1308
1309         /* DMATXCTRL: Geric Double VLAN Disable */
1310         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1311         ctrl &= ~IXGBE_DMATXCTL_GDV;
1312         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1313
1314         /* CTRL_EXT: Global Double VLAN Disable */
1315         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1316         ctrl &= ~IXGBE_EXTENDED_VLAN;
1317         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1318
1319 }
1320
1321 static void
1322 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1323 {
1324         struct ixgbe_hw *hw =
1325                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1326         uint32_t ctrl;
1327
1328         PMD_INIT_FUNC_TRACE();
1329
1330         /* DMATXCTRL: Geric Double VLAN Enable */
1331         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1332         ctrl |= IXGBE_DMATXCTL_GDV;
1333         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1334
1335         /* CTRL_EXT: Global Double VLAN Enable */
1336         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1337         ctrl |= IXGBE_EXTENDED_VLAN;
1338         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1339
1340         /*
1341          * VET EXT field in the EXVET register = 0x8100 by default
1342          * So no need to change. Same to VT field of DMATXCTL register
1343          */
1344 }
1345
1346 static void
1347 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1348 {
1349         if(mask & ETH_VLAN_STRIP_MASK){
1350                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1351                         ixgbe_vlan_hw_strip_enable_all(dev);
1352                 else
1353                         ixgbe_vlan_hw_strip_disable_all(dev);
1354         }
1355
1356         if(mask & ETH_VLAN_FILTER_MASK){
1357                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1358                         ixgbe_vlan_hw_filter_enable(dev);
1359                 else
1360                         ixgbe_vlan_hw_filter_disable(dev);
1361         }
1362
1363         if(mask & ETH_VLAN_EXTEND_MASK){
1364                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1365                         ixgbe_vlan_hw_extend_enable(dev);
1366                 else
1367                         ixgbe_vlan_hw_extend_disable(dev);
1368         }
1369 }
1370
1371 static void
1372 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1373 {
1374         struct ixgbe_hw *hw =
1375                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1376         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1377         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1378         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1379         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1380 }
1381
1382 static int
1383 ixgbe_dev_configure(struct rte_eth_dev *dev)
1384 {
1385         struct ixgbe_interrupt *intr =
1386                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1387
1388         PMD_INIT_FUNC_TRACE();
1389
1390         /* set flag to update link status after init */
1391         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1392
1393         return 0;
1394 }
1395
1396 /*
1397  * Configure device link speed and setup link.
1398  * It returns 0 on success.
1399  */
1400 static int
1401 ixgbe_dev_start(struct rte_eth_dev *dev)
1402 {
1403         struct ixgbe_hw *hw =
1404                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1405         struct ixgbe_vf_info *vfinfo =
1406                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1407         int err, link_up = 0, negotiate = 0;
1408         uint32_t speed = 0;
1409         int mask = 0;
1410         int status;
1411         uint16_t vf, idx;
1412
1413         PMD_INIT_FUNC_TRACE();
1414
1415         /* IXGBE devices don't support half duplex */
1416         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1417                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1418                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1419                                 dev->data->dev_conf.link_duplex,
1420                                 dev->data->port_id);
1421                 return -EINVAL;
1422         }
1423
1424         /* stop adapter */
1425         hw->adapter_stopped = FALSE;
1426         ixgbe_stop_adapter(hw);
1427
1428         /* reinitialize adapter
1429          * this calls reset and start */
1430         status = ixgbe_pf_reset_hw(hw);
1431         if (status != 0)
1432                 return -1;
1433         hw->mac.ops.start_hw(hw);
1434
1435         /* configure PF module if SRIOV enabled */
1436         ixgbe_pf_host_configure(dev);
1437
1438         /* initialize transmission unit */
1439         ixgbe_dev_tx_init(dev);
1440
1441         /* This can fail when allocating mbufs for descriptor rings */
1442         err = ixgbe_dev_rx_init(dev);
1443         if (err) {
1444                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1445                 goto error;
1446         }
1447
1448         ixgbe_dev_rxtx_start(dev);
1449
1450         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1451                 err = hw->mac.ops.setup_sfp(hw);
1452                 if (err)
1453                         goto error;
1454         }
1455
1456         /* Turn on the laser */
1457         ixgbe_enable_tx_laser(hw);
1458
1459         /* Skip link setup if loopback mode is enabled for 82599. */
1460         if (hw->mac.type == ixgbe_mac_82599EB &&
1461                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1462                 goto skip_link_setup;
1463
1464         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1465         if (err)
1466                 goto error;
1467         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1468         if (err)
1469                 goto error;
1470
1471         switch(dev->data->dev_conf.link_speed) {
1472         case ETH_LINK_SPEED_AUTONEG:
1473                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1474                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1475                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1476                 break;
1477         case ETH_LINK_SPEED_100:
1478                 /*
1479                  * Invalid for 82598 but error will be detected by
1480                  * ixgbe_setup_link()
1481                  */
1482                 speed = IXGBE_LINK_SPEED_100_FULL;
1483                 break;
1484         case ETH_LINK_SPEED_1000:
1485                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1486                 break;
1487         case ETH_LINK_SPEED_10000:
1488                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1489                 break;
1490         default:
1491                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1492                                 dev->data->dev_conf.link_speed,
1493                                 dev->data->port_id);
1494                 goto error;
1495         }
1496
1497         err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1498         if (err)
1499                 goto error;
1500
1501 skip_link_setup:
1502
1503         /* check if lsc interrupt is enabled */
1504         if (dev->data->dev_conf.intr_conf.lsc != 0)
1505                 ixgbe_dev_lsc_interrupt_setup(dev);
1506
1507         /* resume enabled intr since hw reset */
1508         ixgbe_enable_intr(dev);
1509
1510         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1511                 ETH_VLAN_EXTEND_MASK;
1512         ixgbe_vlan_offload_set(dev, mask);
1513
1514         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1515                 /* Enable vlan filtering for VMDq */
1516                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1517         }
1518
1519         /* Configure DCB hw */
1520         ixgbe_configure_dcb(dev);
1521
1522         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1523                 err = ixgbe_fdir_configure(dev);
1524                 if (err)
1525                         goto error;
1526         }
1527
1528         /* Restore vf rate limit */
1529         if (vfinfo != NULL) {
1530                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1531                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1532                                 if (vfinfo[vf].tx_rate[idx] != 0)
1533                                         ixgbe_set_vf_rate_limit(dev, vf,
1534                                                 vfinfo[vf].tx_rate[idx],
1535                                                 1 << idx);
1536         }
1537
1538         ixgbe_restore_statistics_mapping(dev);
1539
1540         return (0);
1541
1542 error:
1543         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1544         ixgbe_dev_clear_queues(dev);
1545         return -EIO;
1546 }
1547
1548 /*
1549  * Stop device: disable rx and tx functions to allow for reconfiguring.
1550  */
1551 static void
1552 ixgbe_dev_stop(struct rte_eth_dev *dev)
1553 {
1554         struct rte_eth_link link;
1555         struct ixgbe_hw *hw =
1556                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1557         struct ixgbe_vf_info *vfinfo =
1558                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1559         int vf;
1560
1561         PMD_INIT_FUNC_TRACE();
1562
1563         /* disable interrupts */
1564         ixgbe_disable_intr(hw);
1565
1566         /* reset the NIC */
1567         ixgbe_pf_reset_hw(hw);
1568         hw->adapter_stopped = FALSE;
1569
1570         /* stop adapter */
1571         ixgbe_stop_adapter(hw);
1572
1573         for (vf = 0; vfinfo != NULL &&
1574                      vf < dev->pci_dev->max_vfs; vf++)
1575                 vfinfo[vf].clear_to_send = false;
1576
1577         /* Turn off the laser */
1578         ixgbe_disable_tx_laser(hw);
1579
1580         ixgbe_dev_clear_queues(dev);
1581
1582         /* Clear recorded link status */
1583         memset(&link, 0, sizeof(link));
1584         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1585 }
1586
1587 /*
1588  * Set device link up: enable tx laser.
1589  */
1590 static int
1591 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1592 {
1593         struct ixgbe_hw *hw =
1594                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595         if (hw->mac.type == ixgbe_mac_82599EB) {
1596 #ifdef RTE_NIC_BYPASS
1597                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1598                         /* Not suported in bypass mode */
1599                         PMD_INIT_LOG(ERR,
1600                                 "\nSet link up is not supported "
1601                                 "by device id 0x%x\n",
1602                                 hw->device_id);
1603                         return -ENOTSUP;
1604                 }
1605 #endif
1606                 /* Turn on the laser */
1607                 ixgbe_enable_tx_laser(hw);
1608                 return 0;
1609         }
1610
1611         PMD_INIT_LOG(ERR, "\nSet link up is not supported by device id 0x%x\n",
1612                 hw->device_id);
1613         return -ENOTSUP;
1614 }
1615
1616 /*
1617  * Set device link down: disable tx laser.
1618  */
1619 static int
1620 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1621 {
1622         struct ixgbe_hw *hw =
1623                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1624         if (hw->mac.type == ixgbe_mac_82599EB) {
1625 #ifdef RTE_NIC_BYPASS
1626                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1627                         /* Not suported in bypass mode */
1628                         PMD_INIT_LOG(ERR,
1629                                 "\nSet link down is not supported "
1630                                 "by device id 0x%x\n",
1631                                  hw->device_id);
1632                         return -ENOTSUP;
1633                 }
1634 #endif
1635                 /* Turn off the laser */
1636                 ixgbe_disable_tx_laser(hw);
1637                 return 0;
1638         }
1639
1640         PMD_INIT_LOG(ERR,
1641                 "\nSet link down is not supported by device id 0x%x\n",
1642                  hw->device_id);
1643         return -ENOTSUP;
1644 }
1645
1646 /*
1647  * Reest and stop device.
1648  */
1649 static void
1650 ixgbe_dev_close(struct rte_eth_dev *dev)
1651 {
1652         struct ixgbe_hw *hw =
1653                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654
1655         PMD_INIT_FUNC_TRACE();
1656
1657         ixgbe_pf_reset_hw(hw);
1658
1659         ixgbe_dev_stop(dev);
1660         hw->adapter_stopped = 1;
1661
1662         ixgbe_disable_pcie_master(hw);
1663
1664         /* reprogram the RAR[0] in case user changed it. */
1665         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1666 }
1667
1668 /*
1669  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1670  */
1671 static void
1672 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1673 {
1674         struct ixgbe_hw *hw =
1675                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1676         struct ixgbe_hw_stats *hw_stats =
1677                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1678         uint32_t bprc, lxon, lxoff, total;
1679         uint64_t total_missed_rx, total_qbrc, total_qprc;
1680         unsigned i;
1681
1682         total_missed_rx = 0;
1683         total_qbrc = 0;
1684         total_qprc = 0;
1685
1686         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1687         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1688         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1689         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1690
1691         for (i = 0; i < 8; i++) {
1692                 uint32_t mp;
1693                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1694                 /* global total per queue */
1695                 hw_stats->mpc[i] += mp;
1696                 /* Running comprehensive total for stats display */
1697                 total_missed_rx += hw_stats->mpc[i];
1698                 if (hw->mac.type == ixgbe_mac_82598EB)
1699                         hw_stats->rnbc[i] +=
1700                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1701                 hw_stats->pxontxc[i] +=
1702                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1703                 hw_stats->pxonrxc[i] +=
1704                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1705                 hw_stats->pxofftxc[i] +=
1706                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1707                 hw_stats->pxoffrxc[i] +=
1708                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1709                 hw_stats->pxon2offc[i] +=
1710                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1711         }
1712         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1713                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1714                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1715                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1716                 hw_stats->qbrc[i] +=
1717                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1718                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1719                 hw_stats->qbtc[i] +=
1720                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1721                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1722
1723                 total_qprc += hw_stats->qprc[i];
1724                 total_qbrc += hw_stats->qbrc[i];
1725         }
1726         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1727         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1728         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1729
1730         /* Note that gprc counts missed packets */
1731         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1732
1733         if (hw->mac.type != ixgbe_mac_82598EB) {
1734                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1735                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1736                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1737                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1738                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1739                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1740                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1741                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1742         } else {
1743                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1744                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1745                 /* 82598 only has a counter in the high register */
1746                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1747                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1748                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1749         }
1750
1751         /*
1752          * Workaround: mprc hardware is incorrectly counting
1753          * broadcasts, so for now we subtract those.
1754          */
1755         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1756         hw_stats->bprc += bprc;
1757         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1758         if (hw->mac.type == ixgbe_mac_82598EB)
1759                 hw_stats->mprc -= bprc;
1760
1761         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1762         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1763         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1764         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1765         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1766         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1767
1768         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1769         hw_stats->lxontxc += lxon;
1770         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1771         hw_stats->lxofftxc += lxoff;
1772         total = lxon + lxoff;
1773
1774         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1775         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1776         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1777         hw_stats->gptc -= total;
1778         hw_stats->mptc -= total;
1779         hw_stats->ptc64 -= total;
1780         hw_stats->gotc -= total * ETHER_MIN_LEN;
1781
1782         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1783         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1784         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1785         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1786         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1787         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1788         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1789         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1790         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1791         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1792         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1793         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1794         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1795         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1796         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1797         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1798         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1799         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1800         /* Only read FCOE on 82599 */
1801         if (hw->mac.type != ixgbe_mac_82598EB) {
1802                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1803                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1804                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1805                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1806                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1807         }
1808
1809         if (stats == NULL)
1810                 return;
1811
1812         /* Fill out the rte_eth_stats statistics structure */
1813         stats->ipackets = total_qprc;
1814         stats->ibytes = total_qbrc;
1815         stats->opackets = hw_stats->gptc;
1816         stats->obytes = hw_stats->gotc;
1817         stats->imcasts = hw_stats->mprc;
1818
1819         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1820                 stats->q_ipackets[i] = hw_stats->qprc[i];
1821                 stats->q_opackets[i] = hw_stats->qptc[i];
1822                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1823                 stats->q_obytes[i] = hw_stats->qbtc[i];
1824                 stats->q_errors[i] = hw_stats->qprdc[i];
1825         }
1826
1827         /* Rx Errors */
1828         stats->ibadcrc  = hw_stats->crcerrs;
1829         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1830         stats->imissed  = total_missed_rx;
1831         stats->ierrors  = stats->ibadcrc +
1832                           stats->ibadlen +
1833                           stats->imissed +
1834                           hw_stats->illerrc + hw_stats->errbc;
1835
1836         /* Tx Errors */
1837         stats->oerrors  = 0;
1838
1839         /* XON/XOFF pause frames */
1840         stats->tx_pause_xon  = hw_stats->lxontxc;
1841         stats->rx_pause_xon  = hw_stats->lxonrxc;
1842         stats->tx_pause_xoff = hw_stats->lxofftxc;
1843         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1844
1845         /* Flow Director Stats registers */
1846         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1847         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1848         stats->fdirmatch = hw_stats->fdirmatch;
1849         stats->fdirmiss = hw_stats->fdirmiss;
1850 }
1851
1852 static void
1853 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1854 {
1855         struct ixgbe_hw_stats *stats =
1856                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1857
1858         /* HW registers are cleared on read */
1859         ixgbe_dev_stats_get(dev, NULL);
1860
1861         /* Reset software totals */
1862         memset(stats, 0, sizeof(*stats));
1863 }
1864
1865 static void
1866 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1867 {
1868         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1870                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1871
1872         /* Good Rx packet, include VF loopback */
1873         UPDATE_VF_STAT(IXGBE_VFGPRC,
1874             hw_stats->last_vfgprc, hw_stats->vfgprc);
1875
1876         /* Good Rx octets, include VF loopback */
1877         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1878             hw_stats->last_vfgorc, hw_stats->vfgorc);
1879
1880         /* Good Tx packet, include VF loopback */
1881         UPDATE_VF_STAT(IXGBE_VFGPTC,
1882             hw_stats->last_vfgptc, hw_stats->vfgptc);
1883
1884         /* Good Tx octets, include VF loopback */
1885         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1886             hw_stats->last_vfgotc, hw_stats->vfgotc);
1887
1888         /* Rx Multicst Packet */
1889         UPDATE_VF_STAT(IXGBE_VFMPRC,
1890             hw_stats->last_vfmprc, hw_stats->vfmprc);
1891
1892         if (stats == NULL)
1893                 return;
1894
1895         memset(stats, 0, sizeof(*stats));
1896         stats->ipackets = hw_stats->vfgprc;
1897         stats->ibytes = hw_stats->vfgorc;
1898         stats->opackets = hw_stats->vfgptc;
1899         stats->obytes = hw_stats->vfgotc;
1900         stats->imcasts = hw_stats->vfmprc;
1901 }
1902
1903 static void
1904 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1905 {
1906         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1907                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1908
1909         /* Sync HW register to the last stats */
1910         ixgbevf_dev_stats_get(dev, NULL);
1911
1912         /* reset HW current stats*/
1913         hw_stats->vfgprc = 0;
1914         hw_stats->vfgorc = 0;
1915         hw_stats->vfgptc = 0;
1916         hw_stats->vfgotc = 0;
1917         hw_stats->vfmprc = 0;
1918
1919 }
1920
1921 static void
1922 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1923 {
1924         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1925
1926         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1927         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1928         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1929         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1930         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1931         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1932         dev_info->max_vfs = dev->pci_dev->max_vfs;
1933         if (hw->mac.type == ixgbe_mac_82598EB)
1934                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1935         else
1936                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1937         dev_info->rx_offload_capa =
1938                 DEV_RX_OFFLOAD_VLAN_STRIP |
1939                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1940                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1941                 DEV_RX_OFFLOAD_TCP_CKSUM;
1942         dev_info->tx_offload_capa =
1943                 DEV_TX_OFFLOAD_VLAN_INSERT |
1944                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1945                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1946                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1947                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1948 }
1949
1950 /* return 0 means link status changed, -1 means not changed */
1951 static int
1952 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1953 {
1954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1955         struct rte_eth_link link, old;
1956         ixgbe_link_speed link_speed;
1957         int link_up;
1958         int diag;
1959
1960         link.link_status = 0;
1961         link.link_speed = 0;
1962         link.link_duplex = 0;
1963         memset(&old, 0, sizeof(old));
1964         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1965
1966         /* check if it needs to wait to complete, if lsc interrupt is enabled */
1967         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1968                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1969         else
1970                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1971         if (diag != 0) {
1972                 link.link_speed = ETH_LINK_SPEED_100;
1973                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1974                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1975                 if (link.link_status == old.link_status)
1976                         return -1;
1977                 return 0;
1978         }
1979
1980         if (link_up == 0) {
1981                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1982                 if (link.link_status == old.link_status)
1983                         return -1;
1984                 return 0;
1985         }
1986         link.link_status = 1;
1987         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1988
1989         switch (link_speed) {
1990         default:
1991         case IXGBE_LINK_SPEED_UNKNOWN:
1992                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1993                 link.link_speed = ETH_LINK_SPEED_100;
1994                 break;
1995
1996         case IXGBE_LINK_SPEED_100_FULL:
1997                 link.link_speed = ETH_LINK_SPEED_100;
1998                 break;
1999
2000         case IXGBE_LINK_SPEED_1GB_FULL:
2001                 link.link_speed = ETH_LINK_SPEED_1000;
2002                 break;
2003
2004         case IXGBE_LINK_SPEED_10GB_FULL:
2005                 link.link_speed = ETH_LINK_SPEED_10000;
2006                 break;
2007         }
2008         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2009
2010         if (link.link_status == old.link_status)
2011                 return -1;
2012
2013         return 0;
2014 }
2015
2016 static void
2017 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2018 {
2019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2020         uint32_t fctrl;
2021
2022         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2023         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2024         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2025 }
2026
2027 static void
2028 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2029 {
2030         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2031         uint32_t fctrl;
2032
2033         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2034         fctrl &= (~IXGBE_FCTRL_UPE);
2035         if (dev->data->all_multicast == 1)
2036                 fctrl |= IXGBE_FCTRL_MPE;
2037         else
2038                 fctrl &= (~IXGBE_FCTRL_MPE);
2039         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2040 }
2041
2042 static void
2043 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2044 {
2045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2046         uint32_t fctrl;
2047
2048         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2049         fctrl |= IXGBE_FCTRL_MPE;
2050         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2051 }
2052
2053 static void
2054 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2055 {
2056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057         uint32_t fctrl;
2058
2059         if (dev->data->promiscuous == 1)
2060                 return; /* must remain in all_multicast mode */
2061
2062         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2063         fctrl &= (~IXGBE_FCTRL_MPE);
2064         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2065 }
2066
2067 /**
2068  * It clears the interrupt causes and enables the interrupt.
2069  * It will be called once only during nic initialized.
2070  *
2071  * @param dev
2072  *  Pointer to struct rte_eth_dev.
2073  *
2074  * @return
2075  *  - On success, zero.
2076  *  - On failure, a negative value.
2077  */
2078 static int
2079 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2080 {
2081         struct ixgbe_interrupt *intr =
2082                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2083
2084         ixgbe_dev_link_status_print(dev);
2085         intr->mask |= IXGBE_EICR_LSC;
2086
2087         return 0;
2088 }
2089
2090 /*
2091  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2092  *
2093  * @param dev
2094  *  Pointer to struct rte_eth_dev.
2095  *
2096  * @return
2097  *  - On success, zero.
2098  *  - On failure, a negative value.
2099  */
2100 static int
2101 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2102 {
2103         uint32_t eicr;
2104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105         struct ixgbe_interrupt *intr =
2106                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2107
2108         /* clear all cause mask */
2109         ixgbe_disable_intr(hw);
2110
2111         /* read-on-clear nic registers here */
2112         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2113         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2114
2115         intr->flags = 0;
2116         if (eicr & IXGBE_EICR_LSC) {
2117                 /* set flag for async link update */
2118                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2119         }
2120
2121         if (eicr & IXGBE_EICR_MAILBOX)
2122                 intr->flags |= IXGBE_FLAG_MAILBOX;
2123
2124         return 0;
2125 }
2126
2127 /**
2128  * It gets and then prints the link status.
2129  *
2130  * @param dev
2131  *  Pointer to struct rte_eth_dev.
2132  *
2133  * @return
2134  *  - On success, zero.
2135  *  - On failure, a negative value.
2136  */
2137 static void
2138 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2139 {
2140         struct rte_eth_link link;
2141
2142         memset(&link, 0, sizeof(link));
2143         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2144         if (link.link_status) {
2145                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2146                                         (int)(dev->data->port_id),
2147                                         (unsigned)link.link_speed,
2148                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2149                                         "full-duplex" : "half-duplex");
2150         } else {
2151                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2152                                 (int)(dev->data->port_id));
2153         }
2154         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2155                                 dev->pci_dev->addr.domain,
2156                                 dev->pci_dev->addr.bus,
2157                                 dev->pci_dev->addr.devid,
2158                                 dev->pci_dev->addr.function);
2159 }
2160
2161 /*
2162  * It executes link_update after knowing an interrupt occurred.
2163  *
2164  * @param dev
2165  *  Pointer to struct rte_eth_dev.
2166  *
2167  * @return
2168  *  - On success, zero.
2169  *  - On failure, a negative value.
2170  */
2171 static int
2172 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2173 {
2174         struct ixgbe_interrupt *intr =
2175                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2176         int64_t timeout;
2177         struct rte_eth_link link;
2178         int intr_enable_delay = false;
2179
2180         PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
2181
2182         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2183                 ixgbe_pf_mbx_process(dev);
2184                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2185         }
2186
2187         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2188                 /* get the link status before link update, for predicting later */
2189                 memset(&link, 0, sizeof(link));
2190                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2191
2192                 ixgbe_dev_link_update(dev, 0);
2193
2194                 /* likely to up */
2195                 if (!link.link_status)
2196                         /* handle it 1 sec later, wait it being stable */
2197                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2198                 /* likely to down */
2199                 else
2200                         /* handle it 4 sec later, wait it being stable */
2201                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2202
2203                 ixgbe_dev_link_status_print(dev);
2204
2205                 intr_enable_delay = true;
2206         }
2207
2208         if (intr_enable_delay) {
2209                 if (rte_eal_alarm_set(timeout * 1000,
2210                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2211                         PMD_DRV_LOG(ERR, "Error setting alarm");
2212         } else {
2213                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2214                 ixgbe_enable_intr(dev);
2215                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2216         }
2217
2218
2219         return 0;
2220 }
2221
2222 /**
2223  * Interrupt handler which shall be registered for alarm callback for delayed
2224  * handling specific interrupt to wait for the stable nic state. As the
2225  * NIC interrupt state is not stable for ixgbe after link is just down,
2226  * it needs to wait 4 seconds to get the stable status.
2227  *
2228  * @param handle
2229  *  Pointer to interrupt handle.
2230  * @param param
2231  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2232  *
2233  * @return
2234  *  void
2235  */
2236 static void
2237 ixgbe_dev_interrupt_delayed_handler(void *param)
2238 {
2239         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2240         struct ixgbe_interrupt *intr =
2241                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2242         struct ixgbe_hw *hw =
2243                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2244         uint32_t eicr;
2245
2246         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2247         if (eicr & IXGBE_EICR_MAILBOX)
2248                 ixgbe_pf_mbx_process(dev);
2249
2250         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2251                 ixgbe_dev_link_update(dev, 0);
2252                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2253                 ixgbe_dev_link_status_print(dev);
2254                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2255         }
2256
2257         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
2258         ixgbe_enable_intr(dev);
2259         rte_intr_enable(&(dev->pci_dev->intr_handle));
2260 }
2261
2262 /**
2263  * Interrupt handler triggered by NIC  for handling
2264  * specific interrupt.
2265  *
2266  * @param handle
2267  *  Pointer to interrupt handle.
2268  * @param param
2269  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2270  *
2271  * @return
2272  *  void
2273  */
2274 static void
2275 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2276                                                         void *param)
2277 {
2278         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2279         ixgbe_dev_interrupt_get_status(dev);
2280         ixgbe_dev_interrupt_action(dev);
2281 }
2282
2283 static int
2284 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2285 {
2286         struct ixgbe_hw *hw;
2287
2288         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2289         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2290 }
2291
2292 static int
2293 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2294 {
2295         struct ixgbe_hw *hw;
2296
2297         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2298         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2299 }
2300
2301 static int
2302 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2303 {
2304         struct ixgbe_hw *hw;
2305         uint32_t mflcn_reg;
2306         uint32_t fccfg_reg;
2307         int rx_pause;
2308         int tx_pause;
2309
2310         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2311
2312         fc_conf->pause_time = hw->fc.pause_time;
2313         fc_conf->high_water = hw->fc.high_water[0];
2314         fc_conf->low_water = hw->fc.low_water[0];
2315         fc_conf->send_xon = hw->fc.send_xon;
2316         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2317
2318         /*
2319          * Return rx_pause status according to actual setting of
2320          * MFLCN register.
2321          */
2322         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2323         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2324                 rx_pause = 1;
2325         else
2326                 rx_pause = 0;
2327
2328         /*
2329          * Return tx_pause status according to actual setting of
2330          * FCCFG register.
2331          */
2332         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2333         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2334                 tx_pause = 1;
2335         else
2336                 tx_pause = 0;
2337
2338         if (rx_pause && tx_pause)
2339                 fc_conf->mode = RTE_FC_FULL;
2340         else if (rx_pause)
2341                 fc_conf->mode = RTE_FC_RX_PAUSE;
2342         else if (tx_pause)
2343                 fc_conf->mode = RTE_FC_TX_PAUSE;
2344         else
2345                 fc_conf->mode = RTE_FC_NONE;
2346
2347         return 0;
2348 }
2349
2350 static int
2351 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2352 {
2353         struct ixgbe_hw *hw;
2354         int err;
2355         uint32_t rx_buf_size;
2356         uint32_t max_high_water;
2357         uint32_t mflcn;
2358         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2359                 ixgbe_fc_none,
2360                 ixgbe_fc_rx_pause,
2361                 ixgbe_fc_tx_pause,
2362                 ixgbe_fc_full
2363         };
2364
2365         PMD_INIT_FUNC_TRACE();
2366
2367         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2368         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2369                 return -ENOTSUP;
2370         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2371         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2372
2373         /*
2374          * At least reserve one Ethernet frame for watermark
2375          * high_water/low_water in kilo bytes for ixgbe
2376          */
2377         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2378         if ((fc_conf->high_water > max_high_water) ||
2379                 (fc_conf->high_water < fc_conf->low_water)) {
2380                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2381                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2382                 return (-EINVAL);
2383         }
2384
2385         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2386         hw->fc.pause_time     = fc_conf->pause_time;
2387         hw->fc.high_water[0]  = fc_conf->high_water;
2388         hw->fc.low_water[0]   = fc_conf->low_water;
2389         hw->fc.send_xon       = fc_conf->send_xon;
2390
2391         err = ixgbe_fc_enable(hw);
2392
2393         /* Not negotiated is not an error case */
2394         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2395
2396                 /* check if we want to forward MAC frames - driver doesn't have native
2397                  * capability to do that, so we'll write the registers ourselves */
2398
2399                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2400
2401                 /* set or clear MFLCN.PMCF bit depending on configuration */
2402                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2403                         mflcn |= IXGBE_MFLCN_PMCF;
2404                 else
2405                         mflcn &= ~IXGBE_MFLCN_PMCF;
2406
2407                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2408                 IXGBE_WRITE_FLUSH(hw);
2409
2410                 return 0;
2411         }
2412
2413         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2414         return -EIO;
2415 }
2416
2417 /**
2418  *  ixgbe_pfc_enable_generic - Enable flow control
2419  *  @hw: pointer to hardware structure
2420  *  @tc_num: traffic class number
2421  *  Enable flow control according to the current settings.
2422  */
2423 static int
2424 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2425 {
2426         int ret_val = 0;
2427         uint32_t mflcn_reg, fccfg_reg;
2428         uint32_t reg;
2429         uint32_t fcrtl, fcrth;
2430         uint8_t i;
2431         uint8_t nb_rx_en;
2432
2433         /* Validate the water mark configuration */
2434         if (!hw->fc.pause_time) {
2435                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2436                 goto out;
2437         }
2438
2439         /* Low water mark of zero causes XOFF floods */
2440         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2441                  /* High/Low water can not be 0 */
2442                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2443                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2444                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2445                         goto out;
2446                 }
2447
2448                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2449                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2450                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2451                         goto out;
2452                 }
2453         }
2454         /* Negotiate the fc mode to use */
2455         ixgbe_fc_autoneg(hw);
2456
2457         /* Disable any previous flow control settings */
2458         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2459         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2460
2461         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2462         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2463
2464         switch (hw->fc.current_mode) {
2465         case ixgbe_fc_none:
2466                 /*
2467                  * If the count of enabled RX Priority Flow control >1,
2468                  * and the TX pause can not be disabled
2469                  */
2470                 nb_rx_en = 0;
2471                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2472                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2473                         if (reg & IXGBE_FCRTH_FCEN)
2474                                 nb_rx_en++;
2475                 }
2476                 if (nb_rx_en > 1)
2477                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2478                 break;
2479         case ixgbe_fc_rx_pause:
2480                 /*
2481                  * Rx Flow control is enabled and Tx Flow control is
2482                  * disabled by software override. Since there really
2483                  * isn't a way to advertise that we are capable of RX
2484                  * Pause ONLY, we will advertise that we support both
2485                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2486                  * disable the adapter's ability to send PAUSE frames.
2487                  */
2488                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2489                 /*
2490                  * If the count of enabled RX Priority Flow control >1,
2491                  * and the TX pause can not be disabled
2492                  */
2493                 nb_rx_en = 0;
2494                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2495                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2496                         if (reg & IXGBE_FCRTH_FCEN)
2497                                 nb_rx_en++;
2498                 }
2499                 if (nb_rx_en > 1)
2500                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2501                 break;
2502         case ixgbe_fc_tx_pause:
2503                 /*
2504                  * Tx Flow control is enabled, and Rx Flow control is
2505                  * disabled by software override.
2506                  */
2507                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2508                 break;
2509         case ixgbe_fc_full:
2510                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2511                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2512                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2513                 break;
2514         default:
2515                 DEBUGOUT("Flow control param set incorrectly\n");
2516                 ret_val = IXGBE_ERR_CONFIG;
2517                 goto out;
2518                 break;
2519         }
2520
2521         /* Set 802.3x based flow control settings. */
2522         mflcn_reg |= IXGBE_MFLCN_DPF;
2523         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2524         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2525
2526         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2527         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2528                 hw->fc.high_water[tc_num]) {
2529                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2530                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2531                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2532         } else {
2533                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2534                 /*
2535                  * In order to prevent Tx hangs when the internal Tx
2536                  * switch is enabled we must set the high water mark
2537                  * to the maximum FCRTH value.  This allows the Tx
2538                  * switch to function even under heavy Rx workloads.
2539                  */
2540                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2541         }
2542         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2543
2544         /* Configure pause time (2 TCs per register) */
2545         reg = hw->fc.pause_time * 0x00010001;
2546         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2547                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2548
2549         /* Configure flow control refresh threshold value */
2550         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2551
2552 out:
2553         return ret_val;
2554 }
2555
2556 static int
2557 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2558 {
2559         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2560         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2561
2562         if(hw->mac.type != ixgbe_mac_82598EB) {
2563                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2564         }
2565         return ret_val;
2566 }
2567
2568 static int
2569 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2570 {
2571         int err;
2572         uint32_t rx_buf_size;
2573         uint32_t max_high_water;
2574         uint8_t tc_num;
2575         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2576         struct ixgbe_hw *hw =
2577                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578         struct ixgbe_dcb_config *dcb_config =
2579                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2580
2581         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2582                 ixgbe_fc_none,
2583                 ixgbe_fc_rx_pause,
2584                 ixgbe_fc_tx_pause,
2585                 ixgbe_fc_full
2586         };
2587
2588         PMD_INIT_FUNC_TRACE();
2589
2590         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2591         tc_num = map[pfc_conf->priority];
2592         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2593         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2594         /*
2595          * At least reserve one Ethernet frame for watermark
2596          * high_water/low_water in kilo bytes for ixgbe
2597          */
2598         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2599         if ((pfc_conf->fc.high_water > max_high_water) ||
2600                 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2601                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2602                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2603                 return (-EINVAL);
2604         }
2605
2606         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2607         hw->fc.pause_time = pfc_conf->fc.pause_time;
2608         hw->fc.send_xon = pfc_conf->fc.send_xon;
2609         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2610         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2611
2612         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2613
2614         /* Not negotiated is not an error case */
2615         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2616                 return 0;
2617
2618         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2619         return -EIO;
2620 }
2621
2622 static int
2623 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2624                                 struct rte_eth_rss_reta *reta_conf)
2625 {
2626         uint8_t i,j,mask;
2627         uint32_t reta;
2628         struct ixgbe_hw *hw =
2629                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2630
2631         PMD_INIT_FUNC_TRACE();
2632         /*
2633         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2634         * 128-entries in 32 registers
2635          */
2636         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2637                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2638                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2639                 else
2640                         mask = (uint8_t)((reta_conf->mask_hi >>
2641                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2642                 if (mask != 0) {
2643                         reta = 0;
2644                         if (mask != 0xF)
2645                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2646
2647                         for (j = 0; j < 4; j++) {
2648                                 if (mask & (0x1 << j)) {
2649                                         if (mask != 0xF)
2650                                                 reta &= ~(0xFF << 8 * j);
2651                                         reta |= reta_conf->reta[i + j] << 8*j;
2652                                 }
2653                         }
2654                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2655                 }
2656         }
2657
2658         return 0;
2659 }
2660
2661 static int
2662 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2663                                 struct rte_eth_rss_reta *reta_conf)
2664 {
2665         uint8_t i,j,mask;
2666         uint32_t reta;
2667         struct ixgbe_hw *hw =
2668                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2669
2670         PMD_INIT_FUNC_TRACE();
2671         /*
2672          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2673          * 128-entries in 32 registers
2674          */
2675         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2676                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2677                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2678                 else
2679                         mask = (uint8_t)((reta_conf->mask_hi >>
2680                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2681
2682                 if (mask != 0) {
2683                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2684                         for (j = 0; j < 4; j++) {
2685                                 if (mask & (0x1 << j))
2686                                         reta_conf->reta[i + j] =
2687                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2688                         }
2689                 }
2690         }
2691
2692         return 0;
2693 }
2694
2695 static void
2696 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2697                                 uint32_t index, uint32_t pool)
2698 {
2699         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2700         uint32_t enable_addr = 1;
2701
2702         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2703 }
2704
2705 static void
2706 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2707 {
2708         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2709
2710         ixgbe_clear_rar(hw, index);
2711 }
2712
2713 static int
2714 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2715 {
2716         uint32_t hlreg0;
2717         uint32_t maxfrs;
2718         struct ixgbe_hw *hw;
2719         struct rte_eth_dev_info dev_info;
2720         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2721
2722         ixgbe_dev_info_get(dev, &dev_info);
2723
2724         /* check that mtu is within the allowed range */
2725         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2726                 return -EINVAL;
2727
2728         /* refuse mtu that requires the support of scattered packets when this
2729          * feature has not been enabled before. */
2730         if (!dev->data->scattered_rx &&
2731             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2732              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2733                 return -EINVAL;
2734
2735         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2736         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2737
2738         /* switch to jumbo mode if needed */
2739         if (frame_size > ETHER_MAX_LEN) {
2740                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2741                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2742         } else {
2743                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2744                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2745         }
2746         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2747
2748         /* update max frame size */
2749         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2750
2751         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2752         maxfrs &= 0x0000FFFF;
2753         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2754         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2755
2756         return 0;
2757 }
2758
2759 /*
2760  * Virtual Function operations
2761  */
2762 static void
2763 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2764 {
2765         PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2766
2767         /* Clear interrupt mask to stop from interrupts being generated */
2768         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2769
2770         IXGBE_WRITE_FLUSH(hw);
2771 }
2772
2773 static int
2774 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2775 {
2776         struct rte_eth_conf* conf = &dev->data->dev_conf;
2777
2778         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2779                 dev->data->port_id);
2780
2781         /*
2782          * VF has no ability to enable/disable HW CRC
2783          * Keep the persistent behavior the same as Host PF
2784          */
2785 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2786         if (!conf->rxmode.hw_strip_crc) {
2787                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2788                 conf->rxmode.hw_strip_crc = 1;
2789         }
2790 #else
2791         if (conf->rxmode.hw_strip_crc) {
2792                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2793                 conf->rxmode.hw_strip_crc = 0;
2794         }
2795 #endif
2796
2797         return 0;
2798 }
2799
2800 static int
2801 ixgbevf_dev_start(struct rte_eth_dev *dev)
2802 {
2803         struct ixgbe_hw *hw =
2804                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2805         int err, mask = 0;
2806
2807         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2808
2809         hw->mac.ops.reset_hw(hw);
2810
2811         /* negotiate mailbox API version to use with the PF. */
2812         ixgbevf_negotiate_api(hw);
2813
2814         ixgbevf_dev_tx_init(dev);
2815
2816         /* This can fail when allocating mbufs for descriptor rings */
2817         err = ixgbevf_dev_rx_init(dev);
2818         if (err) {
2819                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2820                 ixgbe_dev_clear_queues(dev);
2821                 return err;
2822         }
2823
2824         /* Set vfta */
2825         ixgbevf_set_vfta_all(dev,1);
2826
2827         /* Set HW strip */
2828         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2829                 ETH_VLAN_EXTEND_MASK;
2830         ixgbevf_vlan_offload_set(dev, mask);
2831
2832         ixgbevf_dev_rxtx_start(dev);
2833
2834         return 0;
2835 }
2836
2837 static void
2838 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2839 {
2840         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841
2842         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2843
2844         hw->adapter_stopped = TRUE;
2845         ixgbe_stop_adapter(hw);
2846
2847         /*
2848           * Clear what we set, but we still keep shadow_vfta to
2849           * restore after device starts
2850           */
2851         ixgbevf_set_vfta_all(dev,0);
2852
2853         ixgbe_dev_clear_queues(dev);
2854 }
2855
2856 static void
2857 ixgbevf_dev_close(struct rte_eth_dev *dev)
2858 {
2859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2860
2861         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2862
2863         ixgbe_reset_hw(hw);
2864
2865         ixgbevf_dev_stop(dev);
2866
2867         /* reprogram the RAR[0] in case user changed it. */
2868         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2869 }
2870
2871 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2872 {
2873         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2874         struct ixgbe_vfta * shadow_vfta =
2875                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2876         int i = 0, j = 0, vfta = 0, mask = 1;
2877
2878         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2879                 vfta = shadow_vfta->vfta[i];
2880                 if(vfta){
2881                         mask = 1;
2882                         for (j = 0; j < 32; j++){
2883                                 if(vfta & mask)
2884                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2885                                 mask<<=1;
2886                         }
2887                 }
2888         }
2889
2890 }
2891
2892 static int
2893 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2894 {
2895         struct ixgbe_hw *hw =
2896                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2897         struct ixgbe_vfta * shadow_vfta =
2898                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2899         uint32_t vid_idx = 0;
2900         uint32_t vid_bit = 0;
2901         int ret = 0;
2902
2903         PMD_INIT_FUNC_TRACE();
2904
2905         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2906         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2907         if(ret){
2908                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2909                 return ret;
2910         }
2911         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2912         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2913
2914         /* Save what we set and retore it after device reset */
2915         if (on)
2916                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2917         else
2918                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2919
2920         return 0;
2921 }
2922
2923 static void
2924 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2925 {
2926         struct ixgbe_hw *hw =
2927                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2928         uint32_t ctrl;
2929
2930         PMD_INIT_FUNC_TRACE();
2931
2932         if(queue >= hw->mac.max_rx_queues)
2933                 return;
2934
2935         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2936         if(on)
2937                 ctrl |= IXGBE_RXDCTL_VME;
2938         else
2939                 ctrl &= ~IXGBE_RXDCTL_VME;
2940         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2941
2942         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2943 }
2944
2945 static void
2946 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2947 {
2948         struct ixgbe_hw *hw =
2949                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2950         uint16_t i;
2951         int on = 0;
2952
2953         /* VF function only support hw strip feature, others are not support */
2954         if(mask & ETH_VLAN_STRIP_MASK){
2955                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2956
2957                 for(i=0; i < hw->mac.max_rx_queues; i++)
2958                         ixgbevf_vlan_strip_queue_set(dev,i,on);
2959         }
2960 }
2961
2962 static int
2963 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2964 {
2965         uint32_t reg_val;
2966
2967         /* we only need to do this if VMDq is enabled */
2968         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2969         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2970                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2971                 return (-1);
2972         }
2973
2974         return 0;
2975 }
2976
2977 static uint32_t
2978 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2979 {
2980         uint32_t vector = 0;
2981         switch (hw->mac.mc_filter_type) {
2982         case 0:   /* use bits [47:36] of the address */
2983                 vector = ((uc_addr->addr_bytes[4] >> 4) |
2984                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2985                 break;
2986         case 1:   /* use bits [46:35] of the address */
2987                 vector = ((uc_addr->addr_bytes[4] >> 3) |
2988                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2989                 break;
2990         case 2:   /* use bits [45:34] of the address */
2991                 vector = ((uc_addr->addr_bytes[4] >> 2) |
2992                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2993                 break;
2994         case 3:   /* use bits [43:32] of the address */
2995                 vector = ((uc_addr->addr_bytes[4]) |
2996                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2997                 break;
2998         default:  /* Invalid mc_filter_type */
2999                 break;
3000         }
3001
3002         /* vector can only be 12-bits or boundary will be exceeded */
3003         vector &= 0xFFF;
3004         return vector;
3005 }
3006
3007 static int
3008 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3009                                uint8_t on)
3010 {
3011         uint32_t vector;
3012         uint32_t uta_idx;
3013         uint32_t reg_val;
3014         uint32_t uta_shift;
3015         uint32_t rc;
3016         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3017         const uint32_t ixgbe_uta_bit_shift = 5;
3018         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3019         const uint32_t bit1 = 0x1;
3020
3021         struct ixgbe_hw *hw =
3022                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3023         struct ixgbe_uta_info *uta_info =
3024                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3025
3026         /* The UTA table only exists on 82599 hardware and newer */
3027         if (hw->mac.type < ixgbe_mac_82599EB)
3028                 return (-ENOTSUP);
3029
3030         vector = ixgbe_uta_vector(hw,mac_addr);
3031         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3032         uta_shift = vector & ixgbe_uta_bit_mask;
3033
3034         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3035         if(rc == on)
3036                 return 0;
3037
3038         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3039         if (on) {
3040                 uta_info->uta_in_use++;
3041                 reg_val |= (bit1 << uta_shift);
3042                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3043         } else {
3044                 uta_info->uta_in_use--;
3045                 reg_val &= ~(bit1 << uta_shift);
3046                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3047         }
3048
3049         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3050
3051         if (uta_info->uta_in_use > 0)
3052                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3053                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3054         else
3055                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3056
3057         return 0;
3058 }
3059
3060 static int
3061 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3062 {
3063         int i;
3064         struct ixgbe_hw *hw =
3065                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3066         struct ixgbe_uta_info *uta_info =
3067                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3068
3069         /* The UTA table only exists on 82599 hardware and newer */
3070         if (hw->mac.type < ixgbe_mac_82599EB)
3071                 return (-ENOTSUP);
3072
3073         if(on) {
3074                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3075                         uta_info->uta_shadow[i] = ~0;
3076                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3077                 }
3078         } else {
3079                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3080                         uta_info->uta_shadow[i] = 0;
3081                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3082                 }
3083         }
3084         return 0;
3085
3086 }
3087 static int
3088 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3089                                uint16_t rx_mask, uint8_t on)
3090 {
3091         int val = 0;
3092
3093         struct ixgbe_hw *hw =
3094                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3095         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3096
3097         if (hw->mac.type == ixgbe_mac_82598EB) {
3098                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3099                         " on 82599 hardware and newer\n");
3100                 return (-ENOTSUP);
3101         }
3102         if (ixgbe_vmdq_mode_check(hw) < 0)
3103                 return (-ENOTSUP);
3104
3105         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
3106                 val |= IXGBE_VMOLR_AUPE;
3107         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
3108                 val |= IXGBE_VMOLR_ROMPE;
3109         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3110                 val |= IXGBE_VMOLR_ROPE;
3111         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3112                 val |= IXGBE_VMOLR_BAM;
3113         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3114                 val |= IXGBE_VMOLR_MPE;
3115
3116         if (on)
3117                 vmolr |= val;
3118         else
3119                 vmolr &= ~val;
3120
3121         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3122
3123         return 0;
3124 }
3125
3126 static int
3127 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3128 {
3129         uint32_t reg,addr;
3130         uint32_t val;
3131         const uint8_t bit1 = 0x1;
3132
3133         struct ixgbe_hw *hw =
3134                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3135
3136         if (ixgbe_vmdq_mode_check(hw) < 0)
3137                 return (-ENOTSUP);
3138
3139         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3140         reg = IXGBE_READ_REG(hw, addr);
3141         val = bit1 << pool;
3142
3143         if (on)
3144                 reg |= val;
3145         else
3146                 reg &= ~val;
3147
3148         IXGBE_WRITE_REG(hw, addr,reg);
3149
3150         return 0;
3151 }
3152
3153 static int
3154 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3155 {
3156         uint32_t reg,addr;
3157         uint32_t val;
3158         const uint8_t bit1 = 0x1;
3159
3160         struct ixgbe_hw *hw =
3161                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3162
3163         if (ixgbe_vmdq_mode_check(hw) < 0)
3164                 return (-ENOTSUP);
3165
3166         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3167         reg = IXGBE_READ_REG(hw, addr);
3168         val = bit1 << pool;
3169
3170         if (on)
3171                 reg |= val;
3172         else
3173                 reg &= ~val;
3174
3175         IXGBE_WRITE_REG(hw, addr,reg);
3176
3177         return 0;
3178 }
3179
3180 static int
3181 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3182                         uint64_t pool_mask, uint8_t vlan_on)
3183 {
3184         int ret = 0;
3185         uint16_t pool_idx;
3186         struct ixgbe_hw *hw =
3187                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3188
3189         if (ixgbe_vmdq_mode_check(hw) < 0)
3190                 return (-ENOTSUP);
3191         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3192                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3193                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3194                         if (ret < 0)
3195                                 return ret;
3196         }
3197
3198         return ret;
3199 }
3200
3201 static int
3202 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3203                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3204                         uint8_t rule_id, uint8_t on)
3205 {
3206         uint32_t mr_ctl,vlvf;
3207         uint32_t mp_lsb = 0;
3208         uint32_t mv_msb = 0;
3209         uint32_t mv_lsb = 0;
3210         uint32_t mp_msb = 0;
3211         uint8_t i = 0;
3212         int reg_index = 0;
3213         uint64_t vlan_mask = 0;
3214
3215         const uint8_t pool_mask_offset = 32;
3216         const uint8_t vlan_mask_offset = 32;
3217         const uint8_t dst_pool_offset = 8;
3218         const uint8_t rule_mr_offset  = 4;
3219         const uint8_t mirror_rule_mask= 0x0F;
3220
3221         struct ixgbe_mirror_info *mr_info =
3222                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3223         struct ixgbe_hw *hw =
3224                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3225
3226         if (ixgbe_vmdq_mode_check(hw) < 0)
3227                 return (-ENOTSUP);
3228
3229         /* Check if vlan mask is valid */
3230         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3231                 if (mirror_conf->vlan.vlan_mask == 0)
3232                         return (-EINVAL);
3233         }
3234
3235         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3236         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3237                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3238                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3239                                 /* search vlan id related pool vlan filter index */
3240                                 reg_index = ixgbe_find_vlvf_slot(hw,
3241                                                 mirror_conf->vlan.vlan_id[i]);
3242                                 if(reg_index < 0)
3243                                         return (-EINVAL);
3244                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3245                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3246                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3247                                                 == mirror_conf->vlan.vlan_id[i]))
3248                                         vlan_mask |= (1ULL << reg_index);
3249                                 else
3250                                         return (-EINVAL);
3251                         }
3252                 }
3253
3254                 if (on) {
3255                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3256                         mv_msb = vlan_mask >> vlan_mask_offset;
3257
3258                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3259                                                 mirror_conf->vlan.vlan_mask;
3260                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3261                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3262                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3263                                                 mirror_conf->vlan.vlan_id[i];
3264                         }
3265                 } else {
3266                         mv_lsb = 0;
3267                         mv_msb = 0;
3268                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3269                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3270                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3271                 }
3272         }
3273
3274         /*
3275          * if enable pool mirror, write related pool mask register,if disable
3276          * pool mirror, clear PFMRVM register
3277          */
3278         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3279                 if (on) {
3280                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3281                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3282                         mr_info->mr_conf[rule_id].pool_mask =
3283                                         mirror_conf->pool_mask;
3284
3285                 } else {
3286                         mp_lsb = 0;
3287                         mp_msb = 0;
3288                         mr_info->mr_conf[rule_id].pool_mask = 0;
3289                 }
3290         }
3291
3292         /* read  mirror control register and recalculate it */
3293         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3294
3295         if (on) {
3296                 mr_ctl |= mirror_conf->rule_type_mask;
3297                 mr_ctl &= mirror_rule_mask;
3298                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3299         } else
3300                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3301
3302         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3303         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3304
3305         /* write mirrror control  register */
3306         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3307
3308         /* write pool mirrror control  register */
3309         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3310                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3311                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3312                                 mp_msb);
3313         }
3314         /* write VLAN mirrror control  register */
3315         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3316                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3317                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3318                                 mv_msb);
3319         }
3320
3321         return 0;
3322 }
3323
3324 static int
3325 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3326 {
3327         int mr_ctl = 0;
3328         uint32_t lsb_val = 0;
3329         uint32_t msb_val = 0;
3330         const uint8_t rule_mr_offset = 4;
3331
3332         struct ixgbe_hw *hw =
3333                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3334         struct ixgbe_mirror_info *mr_info =
3335                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3336
3337         if (ixgbe_vmdq_mode_check(hw) < 0)
3338                 return (-ENOTSUP);
3339
3340         memset(&mr_info->mr_conf[rule_id], 0,
3341                 sizeof(struct rte_eth_vmdq_mirror_conf));
3342
3343         /* clear PFVMCTL register */
3344         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3345
3346         /* clear pool mask register */
3347         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3348         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3349
3350         /* clear vlan mask register */
3351         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3352         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3353
3354         return 0;
3355 }
3356
3357 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3358         uint16_t queue_idx, uint16_t tx_rate)
3359 {
3360         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3361         uint32_t rf_dec, rf_int;
3362         uint32_t bcnrc_val;
3363         uint16_t link_speed = dev->data->dev_link.link_speed;
3364
3365         if (queue_idx >= hw->mac.max_tx_queues)
3366                 return -EINVAL;
3367
3368         if (tx_rate != 0) {
3369                 /* Calculate the rate factor values to set */
3370                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3371                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3372                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3373
3374                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3375                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3376                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3377                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3378         } else {
3379                 bcnrc_val = 0;
3380         }
3381
3382         /*
3383          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3384          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3385          * set as 0x4.
3386          */
3387         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3388                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3389                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3390                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3391                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3392         else
3393                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3394                         IXGBE_MMW_SIZE_DEFAULT);
3395
3396         /* Set RTTBCNRC of queue X */
3397         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3398         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3399         IXGBE_WRITE_FLUSH(hw);
3400
3401         return 0;
3402 }
3403
3404 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3405         uint16_t tx_rate, uint64_t q_msk)
3406 {
3407         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3408         struct ixgbe_vf_info *vfinfo =
3409                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3410         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3411         uint32_t queue_stride =
3412                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3413         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3414         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3415         uint16_t total_rate = 0;
3416
3417         if (queue_end >= hw->mac.max_tx_queues)
3418                 return -EINVAL;
3419
3420         if (vfinfo != NULL) {
3421                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3422                         if (vf_idx == vf)
3423                                 continue;
3424                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3425                                 idx++)
3426                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3427                 }
3428         } else
3429                 return -EINVAL;
3430
3431         /* Store tx_rate for this vf. */
3432         for (idx = 0; idx < nb_q_per_pool; idx++) {
3433                 if (((uint64_t)0x1 << idx) & q_msk) {
3434                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3435                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3436                         total_rate += tx_rate;
3437                 }
3438         }
3439
3440         if (total_rate > dev->data->dev_link.link_speed) {
3441                 /*
3442                  * Reset stored TX rate of the VF if it causes exceed
3443                  * link speed.
3444                  */
3445                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3446                 return -EINVAL;
3447         }
3448
3449         /* Set RTTBCNRC of each queue/pool for vf X  */
3450         for (; queue_idx <= queue_end; queue_idx++) {
3451                 if (0x1 & q_msk)
3452                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3453                 q_msk = q_msk >> 1;
3454         }
3455
3456         return 0;
3457 }
3458
3459 static void
3460 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3461                      __attribute__((unused)) uint32_t index,
3462                      __attribute__((unused)) uint32_t pool)
3463 {
3464         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3465         int diag;
3466
3467         /*
3468          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3469          * operation. Trap this case to avoid exhausting the [very limited]
3470          * set of PF resources used to store VF MAC addresses.
3471          */
3472         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3473                 return;
3474         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3475         if (diag == 0)
3476                 return;
3477         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3478 }
3479
3480 static void
3481 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3482 {
3483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3484         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3485         struct ether_addr *mac_addr;
3486         uint32_t i;
3487         int diag;
3488
3489         /*
3490          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3491          * not support the deletion of a given MAC address.
3492          * Instead, it imposes to delete all MAC addresses, then to add again
3493          * all MAC addresses with the exception of the one to be deleted.
3494          */
3495         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3496
3497         /*
3498          * Add again all MAC addresses, with the exception of the deleted one
3499          * and of the permanent MAC address.
3500          */
3501         for (i = 0, mac_addr = dev->data->mac_addrs;
3502              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3503                 /* Skip the deleted MAC address */
3504                 if (i == index)
3505                         continue;
3506                 /* Skip NULL MAC addresses */
3507                 if (is_zero_ether_addr(mac_addr))
3508                         continue;
3509                 /* Skip the permanent MAC address */
3510                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3511                         continue;
3512                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3513                 if (diag != 0)
3514                         PMD_DRV_LOG(ERR,
3515                                     "Adding again MAC address "
3516                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3517                                     "diag=%d",
3518                                     mac_addr->addr_bytes[0],
3519                                     mac_addr->addr_bytes[1],
3520                                     mac_addr->addr_bytes[2],
3521                                     mac_addr->addr_bytes[3],
3522                                     mac_addr->addr_bytes[4],
3523                                     mac_addr->addr_bytes[5],
3524                                     diag);
3525         }
3526 }
3527
3528 /*
3529  * add syn filter
3530  *
3531  * @param
3532  * dev: Pointer to struct rte_eth_dev.
3533  * filter: ponter to the filter that will be added.
3534  * rx_queue: the queue id the filter assigned to.
3535  *
3536  * @return
3537  *    - On success, zero.
3538  *    - On failure, a negative value.
3539  */
3540 static int
3541 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3542                         struct rte_syn_filter *filter, uint16_t rx_queue)
3543 {
3544         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3545         uint32_t synqf;
3546
3547         if (hw->mac.type != ixgbe_mac_82599EB)
3548                 return -ENOSYS;
3549
3550         if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3551                 return -EINVAL;
3552
3553         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3554
3555         if (synqf & IXGBE_SYN_FILTER_ENABLE)
3556                 return -EINVAL;
3557
3558         synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3559                 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3560
3561         if (filter->hig_pri)
3562                 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3563         else
3564                 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3565
3566         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3567         return 0;
3568 }
3569
3570 /*
3571  * remove syn filter
3572  *
3573  * @param
3574  * dev: Pointer to struct rte_eth_dev.
3575  *
3576  * @return
3577  *    - On success, zero.
3578  *    - On failure, a negative value.
3579  */
3580 static int
3581 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3582 {
3583         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3584         uint32_t synqf;
3585
3586         if (hw->mac.type != ixgbe_mac_82599EB)
3587                 return -ENOSYS;
3588
3589         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3590
3591         synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3592
3593         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3594         return 0;
3595 }
3596
3597 /*
3598  * get the syn filter's info
3599  *
3600  * @param
3601  * dev: Pointer to struct rte_eth_dev.
3602  * filter: ponter to the filter that returns.
3603  * *rx_queue: pointer to the queue id the filter assigned to.
3604  *
3605  * @return
3606  *    - On success, zero.
3607  *    - On failure, a negative value.
3608  */
3609 static int
3610 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3611                         struct rte_syn_filter *filter, uint16_t *rx_queue)
3612
3613 {
3614         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3615         uint32_t synqf;
3616
3617         if (hw->mac.type != ixgbe_mac_82599EB)
3618                 return -ENOSYS;
3619
3620         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3621         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3622                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3623                 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3624                 return 0;
3625         }
3626         return -ENOENT;
3627 }
3628
3629 /*
3630  * add an ethertype filter
3631  *
3632  * @param
3633  * dev: Pointer to struct rte_eth_dev.
3634  * index: the index the filter allocates.
3635  * filter: ponter to the filter that will be added.
3636  * rx_queue: the queue id the filter assigned to.
3637  *
3638  * @return
3639  *    - On success, zero.
3640  *    - On failure, a negative value.
3641  */
3642 static int
3643 ixgbe_add_ethertype_filter(struct rte_eth_dev *dev,
3644                         uint16_t index, struct rte_ethertype_filter *filter,
3645                         uint16_t rx_queue)
3646 {
3647         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3648         uint32_t etqf, etqs = 0;
3649
3650         if (hw->mac.type != ixgbe_mac_82599EB)
3651                 return -ENOSYS;
3652
3653         if (index >= IXGBE_MAX_ETQF_FILTERS ||
3654                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3655                 return -EINVAL;
3656
3657         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3658         if (etqf & IXGBE_ETQF_FILTER_EN)
3659                 return -EINVAL;  /* filter index is in use. */
3660
3661         etqf = 0;
3662         etqf |= IXGBE_ETQF_FILTER_EN;
3663         etqf |= (uint32_t)filter->ethertype;
3664
3665         if (filter->priority_en) {
3666                 if (filter->priority > IXGBE_ETQF_MAX_PRI)
3667                         return -EINVAL;
3668                 etqf |= (uint32_t)((filter->priority << IXGBE_ETQF_SHIFT) & IXGBE_ETQF_UP);
3669                 etqf |= IXGBE_ETQF_UP_EN;
3670         }
3671         etqs |= (uint32_t)((rx_queue << IXGBE_ETQS_RX_QUEUE_SHIFT) & IXGBE_ETQS_RX_QUEUE);
3672         etqs |= IXGBE_ETQS_QUEUE_EN;
3673
3674         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), etqf);
3675         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), etqs);
3676         return 0;
3677 }
3678
3679 /*
3680  * remove an ethertype filter
3681  *
3682  * @param
3683  * dev: Pointer to struct rte_eth_dev.
3684  * index: the index the filter allocates.
3685  *
3686  * @return
3687  *    - On success, zero.
3688  *    - On failure, a negative value.
3689  */
3690 static int
3691 ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
3692                         uint16_t index)
3693 {
3694         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3695
3696         if (hw->mac.type != ixgbe_mac_82599EB)
3697                 return -ENOSYS;
3698
3699         if (index >= IXGBE_MAX_ETQF_FILTERS)
3700                 return -EINVAL;
3701
3702         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), 0);
3703         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), 0);
3704
3705         return 0;
3706 }
3707
3708 /*
3709  * get an ethertype filter
3710  *
3711  * @param
3712  * dev: Pointer to struct rte_eth_dev.
3713  * index: the index the filter allocates.
3714  * filter: ponter to the filter that will be gotten.
3715  * *rx_queue: the ponited of the queue id the filter assigned to.
3716  *
3717  * @return
3718  *    - On success, zero.
3719  *    - On failure, a negative value.
3720  */
3721 static int
3722 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
3723                         uint16_t index, struct rte_ethertype_filter *filter,
3724                         uint16_t *rx_queue)
3725 {
3726         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3727         uint32_t etqf, etqs;
3728
3729         if (hw->mac.type != ixgbe_mac_82599EB)
3730                 return -ENOSYS;
3731
3732         if (index >= IXGBE_MAX_ETQF_FILTERS)
3733                 return -EINVAL;
3734
3735         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3736         etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(index));
3737         if (etqf & IXGBE_ETQF_FILTER_EN) {
3738                 filter->ethertype = etqf & IXGBE_ETQF_ETHERTYPE;
3739                 filter->priority_en = (etqf & IXGBE_ETQF_UP_EN) ? 1 : 0;
3740                 if (filter->priority_en)
3741                         filter->priority = (etqf & IXGBE_ETQF_UP) >> 16;
3742                 *rx_queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> IXGBE_ETQS_RX_QUEUE_SHIFT;
3743                 return 0;
3744         }
3745         return -ENOENT;
3746 }
3747
3748 static inline enum ixgbe_5tuple_protocol
3749 convert_protocol_type(uint8_t protocol_value)
3750 {
3751         if (protocol_value == IPPROTO_TCP)
3752                 return IXGBE_FILTER_PROTOCOL_TCP;
3753         else if (protocol_value == IPPROTO_UDP)
3754                 return IXGBE_FILTER_PROTOCOL_UDP;
3755         else if (protocol_value == IPPROTO_SCTP)
3756                 return IXGBE_FILTER_PROTOCOL_SCTP;
3757         else
3758                 return IXGBE_FILTER_PROTOCOL_NONE;
3759 }
3760
3761 static inline uint8_t
3762 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3763 {
3764         if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3765                 return IPPROTO_TCP;
3766         else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3767                 return IPPROTO_UDP;
3768         else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3769                 return IPPROTO_SCTP;
3770         else
3771                 return 0;
3772 }
3773
3774 /*
3775  * add a 5tuple filter
3776  *
3777  * @param
3778  * dev: Pointer to struct rte_eth_dev.
3779  * index: the index the filter allocates.
3780  * filter: ponter to the filter that will be added.
3781  * rx_queue: the queue id the filter assigned to.
3782  *
3783  * @return
3784  *    - On success, zero.
3785  *    - On failure, a negative value.
3786  */
3787 static int
3788 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3789                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
3790 {
3791         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3792         uint32_t ftqf, sdpqf = 0;
3793         uint32_t l34timir = 0;
3794         uint8_t mask = 0xff;
3795
3796         if (hw->mac.type != ixgbe_mac_82599EB)
3797                 return -ENOSYS;
3798
3799         if (index >= IXGBE_MAX_FTQF_FILTERS ||
3800                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3801                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3802                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3803                 return -EINVAL;  /* filter index is out of range. */
3804
3805         if (filter->tcp_flags) {
3806                 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3807                 return -EINVAL;
3808         }
3809
3810         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3811         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3812                 return -EINVAL;  /* filter index is in use. */
3813
3814         ftqf = 0;
3815         sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3816         sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3817
3818         ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3819                 IXGBE_FTQF_PROTOCOL_MASK);
3820         ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3821                 IXGBE_FTQF_PRIORITY_SHIFT);
3822         if (filter->src_ip_mask == 0) /* 0 means compare. */
3823                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3824         if (filter->dst_ip_mask == 0)
3825                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3826         if (filter->src_port_mask == 0)
3827                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3828         if (filter->dst_port_mask == 0)
3829                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3830         if (filter->protocol_mask == 0)
3831                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3832         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3833         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3834         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3835
3836         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3837         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3838         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3839         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3840
3841         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3842         l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3843         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3844         return 0;
3845 }
3846
3847 /*
3848  * remove a 5tuple filter
3849  *
3850  * @param
3851  * dev: Pointer to struct rte_eth_dev.
3852  * index: the index the filter allocates.
3853  *
3854  * @return
3855  *    - On success, zero.
3856  *    - On failure, a negative value.
3857  */
3858 static int
3859 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3860                         uint16_t index)
3861 {
3862         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3863
3864         if (hw->mac.type != ixgbe_mac_82599EB)
3865                 return -ENOSYS;
3866
3867         if (index >= IXGBE_MAX_FTQF_FILTERS)
3868                 return -EINVAL;  /* filter index is out of range. */
3869
3870         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3871         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3872         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3873         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3874         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3875         return 0;
3876 }
3877
3878 /*
3879  * get a 5tuple filter
3880  *
3881  * @param
3882  * dev: Pointer to struct rte_eth_dev.
3883  * index: the index the filter allocates
3884  * filter: ponter to the filter that returns.
3885  * *rx_queue: pointer of the queue id the filter assigned to.
3886  *
3887  * @return
3888  *    - On success, zero.
3889  *    - On failure, a negative value.
3890  */
3891 static int
3892 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3893                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3894 {
3895         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3896         uint32_t sdpqf, ftqf, l34timir;
3897         uint8_t mask;
3898         enum ixgbe_5tuple_protocol proto;
3899
3900         if (hw->mac.type != ixgbe_mac_82599EB)
3901                 return -ENOSYS;
3902
3903         if (index >= IXGBE_MAX_FTQF_FILTERS)
3904                 return -EINVAL;  /* filter index is out of range. */
3905
3906         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3907         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3908                 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3909                 filter->protocol = revert_protocol_type(proto);
3910                 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3911                                         IXGBE_FTQF_PRIORITY_MASK;
3912                 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3913                                         IXGBE_FTQF_5TUPLE_MASK_MASK);
3914                 filter->src_ip_mask =
3915                         (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3916                 filter->dst_ip_mask =
3917                         (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3918                 filter->src_port_mask =
3919                         (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3920                 filter->dst_port_mask =
3921                         (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3922                 filter->protocol_mask =
3923                         (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3924
3925                 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3926                 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3927                                         IXGBE_SDPQF_DSTPORT_SHIFT;
3928                 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3929                 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3930                 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3931
3932                 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3933                 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3934                                         IXGBE_L34T_IMIR_QUEUE_SHIFT;
3935                 return 0;
3936         }
3937         return -ENOENT;
3938 }
3939
3940 static struct rte_driver rte_ixgbe_driver = {
3941         .type = PMD_PDEV,
3942         .init = rte_ixgbe_pmd_init,
3943 };
3944
3945 static struct rte_driver rte_ixgbevf_driver = {
3946         .type = PMD_PDEV,
3947         .init = rte_ixgbevf_pmd_init,
3948 };
3949
3950 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
3951 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);