lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  96
  97 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  98
  99 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 100                 struct rte_eth_dev *eth_dev);
 101 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 102 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 103 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 104 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 105 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 106 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 107 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 108 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 109 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 110 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 111 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 112                                 int wait_to_complete);
 113 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 114                                 struct rte_eth_stats *stats);
 115 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 116 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 117                                              uint16_t queue_id,
 118                                              uint8_t stat_idx,
 119                                              uint8_t is_rx);
 120 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 121                                 struct rte_eth_dev_info *dev_info);
 122 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 123                 uint16_t vlan_id, int on);
 124 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 125 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 126                 uint16_t queue, bool on);
 127 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 128                 int on);
 129 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 130 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 131 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 132 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 133 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 134
 135 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 136 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 137 static int  ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 138                 struct rte_eth_fc_conf *fc_conf);
 139 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 140                 struct rte_eth_pfc_conf *pfc_conf);
 141 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 142                 struct rte_eth_rss_reta *reta_conf);
 143 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 144                 struct rte_eth_rss_reta *reta_conf);
 145 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 150                 void *param);
 151 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 152 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 153                 uint32_t index, uint32_t pool);
 154 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 155 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 156
 157 /* For Virtual Function support */
 158 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 159                 struct rte_eth_dev *eth_dev);
 160 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 161 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 162 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 163 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 164 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 165 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 166                 struct rte_eth_stats *stats);
 167 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 169                 uint16_t vlan_id, int on);
 170 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 171                 uint16_t queue, int on);
 172 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 173 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 174
 175 /* For Eth VMDQ APIs support */
 176 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 177                 ether_addr* mac_addr,uint8_t on);
 178 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 179 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 180                 uint16_t rx_mask, uint8_t on);
 181 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 182 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 183 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 184                 uint64_t pool_mask,uint8_t vlan_on);
 185 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 186                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 187                 uint8_t rule_id, uint8_t on);
 188 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 189                 uint8_t rule_id);
 190
 191 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 192                 uint16_t queue_idx, uint16_t tx_rate);
 193 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 194                 uint16_t tx_rate, uint64_t q_msk);
 195
 196 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 197                                  struct ether_addr *mac_addr,
 198                                  uint32_t index, uint32_t pool);
 199 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 200 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
 201                         struct rte_syn_filter *filter, uint16_t rx_queue);
 202 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
 203 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
 204                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 205 static int ixgbe_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 206                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 207 static int ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
 208                         uint16_t index);
 209 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 210                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 211 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 212                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 213 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 214                         uint16_t index);
 215 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 216                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 217
 218 /*
 219  * Define VF Stats MACRO for Non "cleared on read" register
 220  */
 221 #define UPDATE_VF_STAT(reg, last, cur)                          \
 222 {                                                               \
 223         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 224         cur += latest - last;                                   \
 225         last = latest;                                          \
 226 }
 227
 228 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 229 {                                                                \
 230         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 231         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 232         u64 latest = ((new_msb << 32) | new_lsb);                \
 233         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 234         last = latest;                                           \
 235 }
 236
 237 #define IXGBE_SET_HWSTRIP(h, q) do{\
 238                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 239                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 240                 (h)->bitmap[idx] |= 1 << bit;\
 241         }while(0)
 242
 243 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 244                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 245                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 246                 (h)->bitmap[idx] &= ~(1 << bit);\
 247         }while(0)
 248
 249 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 250                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 251                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 252                 (r) = (h)->bitmap[idx] >> bit & 1;\
 253         }while(0)
 254
 255 /*
 256  * The set of PCI devices this driver supports
 257  */
 258 static struct rte_pci_id pci_id_ixgbe_map[] = {
 259
 260 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 261 #include "rte_pci_dev_ids.h"
 262
 263 { .vendor_id = 0, /* sentinel */ },
 264 };
 265
 266
 267 /*
 268  * The set of PCI devices this driver supports (for 82599 VF)
 269  */
 270 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 271
 272 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 273 #include "rte_pci_dev_ids.h"
 274 { .vendor_id = 0, /* sentinel */ },
 275
 276 };
 277
 278 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 279         .dev_configure        = ixgbe_dev_configure,
 280         .dev_start            = ixgbe_dev_start,
 281         .dev_stop             = ixgbe_dev_stop,
 282         .dev_set_link_up    = ixgbe_dev_set_link_up,
 283         .dev_set_link_down  = ixgbe_dev_set_link_down,
 284         .dev_close            = ixgbe_dev_close,
 285         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 286         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 287         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 288         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 289         .link_update          = ixgbe_dev_link_update,
 290         .stats_get            = ixgbe_dev_stats_get,
 291         .stats_reset          = ixgbe_dev_stats_reset,
 292         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 293         .dev_infos_get        = ixgbe_dev_info_get,
 294         .vlan_filter_set      = ixgbe_vlan_filter_set,
 295         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 296         .vlan_offload_set     = ixgbe_vlan_offload_set,
 297         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 298         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 299         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 300         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 301         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 302         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 303         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 304         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 305         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 306         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 307         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 308         .dev_led_on           = ixgbe_dev_led_on,
 309         .dev_led_off          = ixgbe_dev_led_off,
 310         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 311         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 312         .mac_addr_add         = ixgbe_add_rar,
 313         .mac_addr_remove      = ixgbe_remove_rar,
 314         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 315         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 316         .mirror_rule_set      = ixgbe_mirror_rule_set,
 317         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 318         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 319         .set_vf_rx            = ixgbe_set_pool_rx,
 320         .set_vf_tx            = ixgbe_set_pool_tx,
 321         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 322         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 323         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 324         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 325         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 326         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 327         .fdir_infos_get               = ixgbe_fdir_info_get,
 328         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 329         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 330         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 331         .fdir_set_masks               = ixgbe_fdir_set_masks,
 332         .reta_update          = ixgbe_dev_rss_reta_update,
 333         .reta_query           = ixgbe_dev_rss_reta_query,
 334 #ifdef RTE_NIC_BYPASS
 335         .bypass_init          = ixgbe_bypass_init,
 336         .bypass_state_set     = ixgbe_bypass_state_store,
 337         .bypass_state_show    = ixgbe_bypass_state_show,
 338         .bypass_event_set     = ixgbe_bypass_event_store,
 339         .bypass_event_show    = ixgbe_bypass_event_show,
 340         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 341         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 342         .bypass_ver_show      = ixgbe_bypass_ver_show,
 343         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 344 #endif /* RTE_NIC_BYPASS */
 345         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 346         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 347         .add_syn_filter          = ixgbe_add_syn_filter,
 348         .remove_syn_filter       = ixgbe_remove_syn_filter,
 349         .get_syn_filter          = ixgbe_get_syn_filter,
 350         .add_ethertype_filter    = ixgbe_add_ethertype_filter,
 351         .remove_ethertype_filter = ixgbe_remove_ethertype_filter,
 352         .get_ethertype_filter    = ixgbe_get_ethertype_filter,
 353         .add_5tuple_filter       = ixgbe_add_5tuple_filter,
 354         .remove_5tuple_filter    = ixgbe_remove_5tuple_filter,
 355         .get_5tuple_filter       = ixgbe_get_5tuple_filter,
 356 };
 357
 358 /*
 359  * dev_ops for virtual function, bare necessities for basic vf
 360  * operation have been implemented
 361  */
 362 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 363
 364         .dev_configure        = ixgbevf_dev_configure,
 365         .dev_start            = ixgbevf_dev_start,
 366         .dev_stop             = ixgbevf_dev_stop,
 367         .link_update          = ixgbe_dev_link_update,
 368         .stats_get            = ixgbevf_dev_stats_get,
 369         .stats_reset          = ixgbevf_dev_stats_reset,
 370         .dev_close            = ixgbevf_dev_close,
 371         .dev_infos_get        = ixgbe_dev_info_get,
 372         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 373         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 374         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 375         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 376         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 377         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 378         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 379         .mac_addr_add         = ixgbevf_add_mac_addr,
 380         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 381 };
 382
 383 /**
 384  * Atomically reads the link status information from global
 385  * structure rte_eth_dev.
 386  *
 387  * @param dev
 388  *   - Pointer to the structure rte_eth_dev to read from.
 389  *   - Pointer to the buffer to be saved with the link status.
 390  *
 391  * @return
 392  *   - On success, zero.
 393  *   - On failure, negative value.
 394  */
 395 static inline int
 396 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 397                                 struct rte_eth_link *link)
 398 {
 399         struct rte_eth_link *dst = link;
 400         struct rte_eth_link *src = &(dev->data->dev_link);
 401
 402         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 403                                         *(uint64_t *)src) == 0)
 404                 return -1;
 405
 406         return 0;
 407 }
 408
 409 /**
 410  * Atomically writes the link status information into global
 411  * structure rte_eth_dev.
 412  *
 413  * @param dev
 414  *   - Pointer to the structure rte_eth_dev to read from.
 415  *   - Pointer to the buffer to be saved with the link status.
 416  *
 417  * @return
 418  *   - On success, zero.
 419  *   - On failure, negative value.
 420  */
 421 static inline int
 422 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 423                                 struct rte_eth_link *link)
 424 {
 425         struct rte_eth_link *dst = &(dev->data->dev_link);
 426         struct rte_eth_link *src = link;
 427
 428         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 429                                         *(uint64_t *)src) == 0)
 430                 return -1;
 431
 432         return 0;
 433 }
 434
 435 /*
 436  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 437  */
 438 static inline int
 439 ixgbe_is_sfp(struct ixgbe_hw *hw)
 440 {
 441         switch (hw->phy.type) {
 442         case ixgbe_phy_sfp_avago:
 443         case ixgbe_phy_sfp_ftl:
 444         case ixgbe_phy_sfp_intel:
 445         case ixgbe_phy_sfp_unknown:
 446         case ixgbe_phy_sfp_passive_tyco:
 447         case ixgbe_phy_sfp_passive_unknown:
 448                 return 1;
 449         default:
 450                 return 0;
 451         }
 452 }
 453
 454 static inline int32_t
 455 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 456 {
 457         uint32_t ctrl_ext;
 458         int32_t status;
 459
 460         status = ixgbe_reset_hw(hw);
 461
 462         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 463         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 464         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 465         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 466         IXGBE_WRITE_FLUSH(hw);
 467
 468         return status;
 469 }
 470
 471 static inline void
 472 ixgbe_enable_intr(struct rte_eth_dev *dev)
 473 {
 474         struct ixgbe_interrupt *intr =
 475                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 476         struct ixgbe_hw *hw =
 477                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 478
 479         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 480         IXGBE_WRITE_FLUSH(hw);
 481 }
 482
 483 /*
 484  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 485  */
 486 static void
 487 ixgbe_disable_intr(struct ixgbe_hw *hw)
 488 {
 489         PMD_INIT_FUNC_TRACE();
 490
 491         if (hw->mac.type == ixgbe_mac_82598EB) {
 492                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 493         } else {
 494                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 495                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 496                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 497         }
 498         IXGBE_WRITE_FLUSH(hw);
 499 }
 500
 501 /*
 502  * This function resets queue statistics mapping registers.
 503  * From Niantic datasheet, Initialization of Statistics section:
 504  * "...if software requires the queue counters, the RQSMR and TQSM registers
 505  * must be re-programmed following a device reset.
 506  */
 507 static void
 508 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 509 {
 510         uint32_t i;
 511
 512         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 513                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 514                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 515         }
 516 }
 517
 518
 519 static int
 520 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 521                                   uint16_t queue_id,
 522                                   uint8_t stat_idx,
 523                                   uint8_t is_rx)
 524 {
 525 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 526 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 527 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 528
 529         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 530         struct ixgbe_stat_mapping_registers *stat_mappings =
 531                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 532         uint32_t qsmr_mask = 0;
 533         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 534         uint32_t q_map;
 535         uint8_t n, offset;
 536
 537         if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
 538                 return -ENOSYS;
 539
 540         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
 541                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
 542
 543         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 544         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 545                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
 546                 return -EIO;
 547         }
 548         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 549
 550         /* Now clear any previous stat_idx set */
 551         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 552         if (!is_rx)
 553                 stat_mappings->tqsm[n] &= ~clearing_mask;
 554         else
 555                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 556
 557         q_map = (uint32_t)stat_idx;
 558         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 559         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 560         if (!is_rx)
 561                 stat_mappings->tqsm[n] |= qsmr_mask;
 562         else
 563                 stat_mappings->rqsmr[n] |= qsmr_mask;
 564
 565         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
 566                      "%s[%d] = 0x%08x\n",
 567                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
 568                      is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 569
 570         /* Now write the mapping in the appropriate register */
 571         if (is_rx) {
 572                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
 573                              stat_mappings->rqsmr[n], n);
 574                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 575         }
 576         else {
 577                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
 578                              stat_mappings->tqsm[n], n);
 579                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 580         }
 581         return 0;
 582 }
 583
 584 static void
 585 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 586 {
 587         struct ixgbe_stat_mapping_registers *stat_mappings =
 588                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 590         int i;
 591
 592         /* write whatever was in stat mapping table to the NIC */
 593         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 594                 /* rx */
 595                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 596
 597                 /* tx */
 598                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 599         }
 600 }
 601
 602 static void
 603 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 604 {
 605         uint8_t i;
 606         struct ixgbe_dcb_tc_config *tc;
 607         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 608
 609         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 610         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 611         for (i = 0; i < dcb_max_tc; i++) {
 612                 tc = &dcb_config->tc_config[i];
 613                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 614                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 615                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 616                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 617                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 618                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 619                 tc->pfc = ixgbe_dcb_pfc_disabled;
 620         }
 621
 622         /* Initialize default user to priority mapping, UPx->TC0 */
 623         tc = &dcb_config->tc_config[0];
 624         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 625         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 626         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 627                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 628                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 629         }
 630         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 631         dcb_config->pfc_mode_enable = false;
 632         dcb_config->vt_mode = true;
 633         dcb_config->round_robin_enable = false;
 634         /* support all DCB capabilities in 82599 */
 635         dcb_config->support.capabilities = 0xFF;
 636
 637         /*we only support 4 Tcs for X540*/
 638         if (hw->mac.type == ixgbe_mac_X540) {
 639                 dcb_config->num_tcs.pg_tcs = 4;
 640                 dcb_config->num_tcs.pfc_tcs = 4;
 641         }
 642 }
 643
 644 /*
 645  * Ensure that all locks are released before first NVM or PHY access
 646  */
 647 static void
 648 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 649 {
 650         uint16_t mask;
 651
 652         /*
 653          * Phy lock should not fail in this early stage. If this is the case,
 654          * it is due to an improper exit of the application.
 655          * So force the release of the faulty lock. Release of common lock
 656          * is done automatically by swfw_sync function.
 657          */
 658         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 659         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 660                    DEBUGOUT1("SWFW phy%d lock released", hw->bus.func);
 661         }
 662         ixgbe_release_swfw_semaphore(hw, mask);
 663
 664         /*
 665          * These ones are more tricky since they are common to all ports; but
 666          * swfw_sync retries last long enough (1s) to be almost sure that if
 667          * lock can not be taken it is due to an improper lock of the
 668          * semaphore.
 669          */
 670         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 671         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 672                    DEBUGOUT("SWFW common locks released");
 673         }
 674         ixgbe_release_swfw_semaphore(hw, mask);
 675 }
 676
 677 /*
 678  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 679  * It returns 0 on success.
 680  */
 681 static int
 682 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 683                      struct rte_eth_dev *eth_dev)
 684 {
 685         struct rte_pci_device *pci_dev;
 686         struct ixgbe_hw *hw =
 687                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 688         struct ixgbe_vfta * shadow_vfta =
 689                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 690         struct ixgbe_hwstrip *hwstrip =
 691                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 692         struct ixgbe_dcb_config *dcb_config =
 693                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 694         uint32_t ctrl_ext;
 695         uint16_t csum;
 696         int diag, i;
 697
 698         PMD_INIT_FUNC_TRACE();
 699
 700         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 701         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 702         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 703
 704         /* for secondary processes, we don't initialise any further as primary
 705          * has already done this work. Only check we don't need a different
 706          * RX function */
 707         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 708                 if (eth_dev->data->scattered_rx)
 709                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 710                 return 0;
 711         }
 712         pci_dev = eth_dev->pci_dev;
 713
 714         /* Vendor and Device ID need to be set before init of shared code */
 715         hw->device_id = pci_dev->id.device_id;
 716         hw->vendor_id = pci_dev->id.vendor_id;
 717         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 718 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
 719         hw->allow_unsupported_sfp = 1;
 720 #endif
 721
 722         /* Initialize the shared code */
 723 #ifdef RTE_NIC_BYPASS
 724         diag = ixgbe_bypass_init_shared_code(hw);
 725 #else
 726         diag = ixgbe_init_shared_code(hw);
 727 #endif /* RTE_NIC_BYPASS */
 728
 729         if (diag != IXGBE_SUCCESS) {
 730                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 731                 return -EIO;
 732         }
 733
 734         /* pick up the PCI bus settings for reporting later */
 735         ixgbe_get_bus_info(hw);
 736
 737         /* Unlock any pending hardware semaphore */
 738         ixgbe_swfw_lock_reset(hw);
 739
 740         /* Initialize DCB configuration*/
 741         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 742         ixgbe_dcb_init(hw,dcb_config);
 743         /* Get Hardware Flow Control setting */
 744         hw->fc.requested_mode = ixgbe_fc_full;
 745         hw->fc.current_mode = ixgbe_fc_full;
 746         hw->fc.pause_time = IXGBE_FC_PAUSE;
 747         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 748                 hw->fc.low_water[i] = IXGBE_FC_LO;
 749                 hw->fc.high_water[i] = IXGBE_FC_HI;
 750         }
 751         hw->fc.send_xon = 1;
 752
 753         /* Make sure we have a good EEPROM before we read from it */
 754         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 755         if (diag != IXGBE_SUCCESS) {
 756                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 757                 return -EIO;
 758         }
 759
 760 #ifdef RTE_NIC_BYPASS
 761         diag = ixgbe_bypass_init_hw(hw);
 762 #else
 763         diag = ixgbe_init_hw(hw);
 764 #endif /* RTE_NIC_BYPASS */
 765
 766         /*
 767          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 768          * is called too soon after the kernel driver unbinding/binding occurs.
 769          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 770          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 771          * also called. See ixgbe_identify_phy_82599(). The reason for the
 772          * failure is not known, and only occuts when virtualisation features
 773          * are disabled in the bios. A delay of 100ms  was found to be enough by
 774          * trial-and-error, and is doubled to be safe.
 775          */
 776         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 777                 rte_delay_ms(200);
 778                 diag = ixgbe_init_hw(hw);
 779         }
 780
 781         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 782                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 783                     "LOM.  Please be aware there may be issues associated "
 784                     "with your hardware.\n If you are experiencing problems "
 785                     "please contact your Intel or hardware representative "
 786                     "who provided you with this hardware.\n");
 787         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 788                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
 789         if (diag) {
 790                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 791                 return -EIO;
 792         }
 793
 794         /* disable interrupt */
 795         ixgbe_disable_intr(hw);
 796
 797         /* reset mappings for queue statistics hw counters*/
 798         ixgbe_reset_qstat_mappings(hw);
 799
 800         /* Allocate memory for storing MAC addresses */
 801         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 802                         hw->mac.num_rar_entries, 0);
 803         if (eth_dev->data->mac_addrs == NULL) {
 804                 PMD_INIT_LOG(ERR,
 805                         "Failed to allocate %u bytes needed to store "
 806                         "MAC addresses",
 807                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 808                 return -ENOMEM;
 809         }
 810         /* Copy the permanent MAC address */
 811         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 812                         &eth_dev->data->mac_addrs[0]);
 813
 814         /* Allocate memory for storing hash filter MAC addresses */
 815         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 816                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 817         if (eth_dev->data->hash_mac_addrs == NULL) {
 818                 PMD_INIT_LOG(ERR,
 819                         "Failed to allocate %d bytes needed to store MAC addresses",
 820                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 821                 return -ENOMEM;
 822         }
 823
 824         /* initialize the vfta */
 825         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 826
 827         /* initialize the hw strip bitmap*/
 828         memset(hwstrip, 0, sizeof(*hwstrip));
 829
 830         /* initialize PF if max_vfs not zero */
 831         ixgbe_pf_host_init(eth_dev);
 832
 833         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 834         /* let hardware know driver is loaded */
 835         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 836         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 837         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 838         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 839         IXGBE_WRITE_FLUSH(hw);
 840
 841         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 842                 PMD_INIT_LOG(DEBUG,
 843                              "MAC: %d, PHY: %d, SFP+: %d<n",
 844                              (int) hw->mac.type, (int) hw->phy.type,
 845                              (int) hw->phy.sfp_type);
 846         else
 847                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
 848                              (int) hw->mac.type, (int) hw->phy.type);
 849
 850         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 851                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 852                         pci_dev->id.device_id);
 853
 854         rte_intr_callback_register(&(pci_dev->intr_handle),
 855                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 856
 857         /* enable uio intr after callback register */
 858         rte_intr_enable(&(pci_dev->intr_handle));
 859
 860         /* enable support intr */
 861         ixgbe_enable_intr(eth_dev);
 862
 863         return 0;
 864 }
 865
 866
 867 /*
 868  * Negotiate mailbox API version with the PF.
 869  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 870  * Then we try to negotiate starting with the most recent one.
 871  * If all negotiation attempts fail, then we will proceed with
 872  * the default one (ixgbe_mbox_api_10).
 873  */
 874 static void
 875 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 876 {
 877         int32_t i;
 878
 879         /* start with highest supported, proceed down */
 880         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 881                 ixgbe_mbox_api_11,
 882                 ixgbe_mbox_api_10,
 883         };
 884
 885         for (i = 0;
 886                         i != RTE_DIM(sup_ver) &&
 887                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 888                         i++)
 889                 ;
 890 }
 891
 892 static void
 893 generate_random_mac_addr(struct ether_addr *mac_addr)
 894 {
 895         uint64_t random;
 896
 897         /* Set Organizationally Unique Identifier (OUI) prefix. */
 898         mac_addr->addr_bytes[0] = 0x00;
 899         mac_addr->addr_bytes[1] = 0x09;
 900         mac_addr->addr_bytes[2] = 0xC0;
 901         /* Force indication of locally assigned MAC address. */
 902         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 903         /* Generate the last 3 bytes of the MAC address with a random number. */
 904         random = rte_rand();
 905         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 906 }
 907
 908 /*
 909  * Virtual Function device init
 910  */
 911 static int
 912 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 913                      struct rte_eth_dev *eth_dev)
 914 {
 915         int diag;
 916         uint32_t tc, tcs;
 917         struct rte_pci_device *pci_dev;
 918         struct ixgbe_hw *hw =
 919                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 920         struct ixgbe_vfta * shadow_vfta =
 921                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 922         struct ixgbe_hwstrip *hwstrip =
 923                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 924         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 925
 926         PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
 927
 928         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 929         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 930         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 931
 932         /* for secondary processes, we don't initialise any further as primary
 933          * has already done this work. Only check we don't need a different
 934          * RX function */
 935         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 936                 if (eth_dev->data->scattered_rx)
 937                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 938                 return 0;
 939         }
 940
 941         pci_dev = eth_dev->pci_dev;
 942
 943         hw->device_id = pci_dev->id.device_id;
 944         hw->vendor_id = pci_dev->id.vendor_id;
 945         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 946
 947         /* initialize the vfta */
 948         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 949
 950         /* initialize the hw strip bitmap*/
 951         memset(hwstrip, 0, sizeof(*hwstrip));
 952
 953         /* Initialize the shared code */
 954         diag = ixgbe_init_shared_code(hw);
 955         if (diag != IXGBE_SUCCESS) {
 956                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 957                 return -EIO;
 958         }
 959
 960         /* init_mailbox_params */
 961         hw->mbx.ops.init_params(hw);
 962
 963         /* Disable the interrupts for VF */
 964         ixgbevf_intr_disable(hw);
 965
 966         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
 967         diag = hw->mac.ops.reset_hw(hw);
 968
 969         /*
 970          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
 971          * the underlying PF driver has not assigned a MAC address to the VF.
 972          * In this case, assign a random MAC address.
 973          */
 974         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
 975                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 976                 return (diag);
 977         }
 978
 979         /* negotiate mailbox API version to use with the PF. */
 980         ixgbevf_negotiate_api(hw);
 981
 982         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
 983         ixgbevf_get_queues(hw, &tcs, &tc);
 984
 985         /* Allocate memory for storing MAC addresses */
 986         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
 987                         hw->mac.num_rar_entries, 0);
 988         if (eth_dev->data->mac_addrs == NULL) {
 989                 PMD_INIT_LOG(ERR,
 990                         "Failed to allocate %u bytes needed to store "
 991                         "MAC addresses",
 992                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 993                 return -ENOMEM;
 994         }
 995
 996         /* Generate a random MAC address, if none was assigned by PF. */
 997         if (is_zero_ether_addr(perm_addr)) {
 998                 generate_random_mac_addr(perm_addr);
 999                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1000                 if (diag) {
1001                         rte_free(eth_dev->data->mac_addrs);
1002                         eth_dev->data->mac_addrs = NULL;
1003                         return diag;
1004                 }
1005                 RTE_LOG(INFO, PMD,
1006                         "\tVF MAC address not assigned by Host PF\n"
1007                         "\tAssign randomly generated MAC address "
1008                         "%02x:%02x:%02x:%02x:%02x:%02x\n",
1009                         perm_addr->addr_bytes[0],
1010                         perm_addr->addr_bytes[1],
1011                         perm_addr->addr_bytes[2],
1012                         perm_addr->addr_bytes[3],
1013                         perm_addr->addr_bytes[4],
1014                         perm_addr->addr_bytes[5]);
1015         }
1016
1017         /* Copy the permanent MAC address */
1018         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1019
1020         /* reset the hardware with the new settings */
1021         diag = hw->mac.ops.start_hw(hw);
1022         switch (diag) {
1023                 case  0:
1024                         break;
1025
1026                 default:
1027                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1028                         return (-EIO);
1029         }
1030
1031         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
1032                          eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
1033                          "ixgbe_mac_82599_vf");
1034
1035         return 0;
1036 }
1037
1038 static struct eth_driver rte_ixgbe_pmd = {
1039         {
1040                 .name = "rte_ixgbe_pmd",
1041                 .id_table = pci_id_ixgbe_map,
1042                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1043         },
1044         .eth_dev_init = eth_ixgbe_dev_init,
1045         .dev_private_size = sizeof(struct ixgbe_adapter),
1046 };
1047
1048 /*
1049  * virtual function driver struct
1050  */
1051 static struct eth_driver rte_ixgbevf_pmd = {
1052         {
1053                 .name = "rte_ixgbevf_pmd",
1054                 .id_table = pci_id_ixgbevf_map,
1055                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1056         },
1057         .eth_dev_init = eth_ixgbevf_dev_init,
1058         .dev_private_size = sizeof(struct ixgbe_adapter),
1059 };
1060
1061 /*
1062  * Driver initialization routine.
1063  * Invoked once at EAL init time.
1064  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1065  */
1066 static int
1067 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1068 {
1069         PMD_INIT_FUNC_TRACE();
1070
1071         rte_eth_driver_register(&rte_ixgbe_pmd);
1072         return 0;
1073 }
1074
1075 /*
1076  * VF Driver initialization routine.
1077  * Invoked one at EAL init time.
1078  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1079  */
1080 static int
1081 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1082 {
1083         DEBUGFUNC("rte_ixgbevf_pmd_init");
1084
1085         rte_eth_driver_register(&rte_ixgbevf_pmd);
1086         return (0);
1087 }
1088
1089 static int
1090 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1091 {
1092         struct ixgbe_hw *hw =
1093                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1094         struct ixgbe_vfta * shadow_vfta =
1095                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1096         uint32_t vfta;
1097         uint32_t vid_idx;
1098         uint32_t vid_bit;
1099
1100         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1101         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1102         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1103         if (on)
1104                 vfta |= vid_bit;
1105         else
1106                 vfta &= ~vid_bit;
1107         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1108
1109         /* update local VFTA copy */
1110         shadow_vfta->vfta[vid_idx] = vfta;
1111
1112         return 0;
1113 }
1114
1115 static void
1116 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1117 {
1118         if (on)
1119                 ixgbe_vlan_hw_strip_enable(dev, queue);
1120         else
1121                 ixgbe_vlan_hw_strip_disable(dev, queue);
1122 }
1123
1124 static void
1125 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1126 {
1127         struct ixgbe_hw *hw =
1128                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1129
1130         /* Only the high 16-bits is valid */
1131         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1132 }
1133
1134 void
1135 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1136 {
1137         struct ixgbe_hw *hw =
1138                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1139         uint32_t vlnctrl;
1140
1141         PMD_INIT_FUNC_TRACE();
1142
1143         /* Filter Table Disable */
1144         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1145         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1146
1147         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1148 }
1149
1150 void
1151 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1152 {
1153         struct ixgbe_hw *hw =
1154                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1155         struct ixgbe_vfta * shadow_vfta =
1156                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1157         uint32_t vlnctrl;
1158         uint16_t i;
1159
1160         PMD_INIT_FUNC_TRACE();
1161
1162         /* Filter Table Enable */
1163         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1164         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1165         vlnctrl |= IXGBE_VLNCTRL_VFE;
1166
1167         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1168
1169         /* write whatever is in local vfta copy */
1170         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1171                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1172 }
1173
1174 static void
1175 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1176 {
1177         struct ixgbe_hwstrip *hwstrip =
1178                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1179
1180         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1181                 return;
1182
1183         if (on)
1184                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1185         else
1186                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1187 }
1188
1189 static void
1190 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1191 {
1192         struct ixgbe_hw *hw =
1193                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1194         uint32_t ctrl;
1195
1196         PMD_INIT_FUNC_TRACE();
1197
1198         if (hw->mac.type == ixgbe_mac_82598EB) {
1199                 /* No queue level support */
1200                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1201                 return;
1202         }
1203         else {
1204                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1205                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1206                 ctrl &= ~IXGBE_RXDCTL_VME;
1207                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1208         }
1209         /* record those setting for HW strip per queue */
1210         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1211 }
1212
1213 static void
1214 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1215 {
1216         struct ixgbe_hw *hw =
1217                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218         uint32_t ctrl;
1219
1220         PMD_INIT_FUNC_TRACE();
1221
1222         if (hw->mac.type == ixgbe_mac_82598EB) {
1223                 /* No queue level supported */
1224                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1225                 return;
1226         }
1227         else {
1228                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1229                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1230                 ctrl |= IXGBE_RXDCTL_VME;
1231                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1232         }
1233         /* record those setting for HW strip per queue */
1234         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1235 }
1236
1237 void
1238 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1239 {
1240         struct ixgbe_hw *hw =
1241                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1242         uint32_t ctrl;
1243         uint16_t i;
1244
1245         PMD_INIT_FUNC_TRACE();
1246
1247         if (hw->mac.type == ixgbe_mac_82598EB) {
1248                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1249                 ctrl &= ~IXGBE_VLNCTRL_VME;
1250                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1251         }
1252         else {
1253                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1254                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1255                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1256                         ctrl &= ~IXGBE_RXDCTL_VME;
1257                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1258
1259                         /* record those setting for HW strip per queue */
1260                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1261                 }
1262         }
1263 }
1264
1265 void
1266 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1267 {
1268         struct ixgbe_hw *hw =
1269                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1270         uint32_t ctrl;
1271         uint16_t i;
1272
1273         PMD_INIT_FUNC_TRACE();
1274
1275         if (hw->mac.type == ixgbe_mac_82598EB) {
1276                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1277                 ctrl |= IXGBE_VLNCTRL_VME;
1278                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1279         }
1280         else {
1281                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1282                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1283                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1284                         ctrl |= IXGBE_RXDCTL_VME;
1285                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1286
1287                         /* record those setting for HW strip per queue */
1288                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1289                 }
1290         }
1291 }
1292
1293 static void
1294 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1295 {
1296         struct ixgbe_hw *hw =
1297                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1298         uint32_t ctrl;
1299
1300         PMD_INIT_FUNC_TRACE();
1301
1302         /* DMATXCTRL: Geric Double VLAN Disable */
1303         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1304         ctrl &= ~IXGBE_DMATXCTL_GDV;
1305         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1306
1307         /* CTRL_EXT: Global Double VLAN Disable */
1308         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1309         ctrl &= ~IXGBE_EXTENDED_VLAN;
1310         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1311
1312 }
1313
1314 static void
1315 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1316 {
1317         struct ixgbe_hw *hw =
1318                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1319         uint32_t ctrl;
1320
1321         PMD_INIT_FUNC_TRACE();
1322
1323         /* DMATXCTRL: Geric Double VLAN Enable */
1324         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1325         ctrl |= IXGBE_DMATXCTL_GDV;
1326         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1327
1328         /* CTRL_EXT: Global Double VLAN Enable */
1329         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1330         ctrl |= IXGBE_EXTENDED_VLAN;
1331         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1332
1333         /*
1334          * VET EXT field in the EXVET register = 0x8100 by default
1335          * So no need to change. Same to VT field of DMATXCTL register
1336          */
1337 }
1338
1339 static void
1340 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1341 {
1342         if(mask & ETH_VLAN_STRIP_MASK){
1343                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1344                         ixgbe_vlan_hw_strip_enable_all(dev);
1345                 else
1346                         ixgbe_vlan_hw_strip_disable_all(dev);
1347         }
1348
1349         if(mask & ETH_VLAN_FILTER_MASK){
1350                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1351                         ixgbe_vlan_hw_filter_enable(dev);
1352                 else
1353                         ixgbe_vlan_hw_filter_disable(dev);
1354         }
1355
1356         if(mask & ETH_VLAN_EXTEND_MASK){
1357                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1358                         ixgbe_vlan_hw_extend_enable(dev);
1359                 else
1360                         ixgbe_vlan_hw_extend_disable(dev);
1361         }
1362 }
1363
1364 static void
1365 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1366 {
1367         struct ixgbe_hw *hw =
1368                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1369         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1370         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1371         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1372         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1373 }
1374
1375 static int
1376 ixgbe_dev_configure(struct rte_eth_dev *dev)
1377 {
1378         struct ixgbe_interrupt *intr =
1379                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1380
1381         PMD_INIT_FUNC_TRACE();
1382
1383         /* set flag to update link status after init */
1384         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1385
1386         return 0;
1387 }
1388
1389 /*
1390  * Configure device link speed and setup link.
1391  * It returns 0 on success.
1392  */
1393 static int
1394 ixgbe_dev_start(struct rte_eth_dev *dev)
1395 {
1396         struct ixgbe_hw *hw =
1397                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1398         struct ixgbe_vf_info *vfinfo =
1399                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1400         int err, link_up = 0, negotiate = 0;
1401         uint32_t speed = 0;
1402         int mask = 0;
1403         int status;
1404         uint16_t vf, idx;
1405
1406         PMD_INIT_FUNC_TRACE();
1407
1408         /* IXGBE devices don't support half duplex */
1409         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1410                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1411                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1412                                 dev->data->dev_conf.link_duplex,
1413                                 dev->data->port_id);
1414                 return -EINVAL;
1415         }
1416
1417         /* stop adapter */
1418         hw->adapter_stopped = FALSE;
1419         ixgbe_stop_adapter(hw);
1420
1421         /* reinitialize adapter
1422          * this calls reset and start */
1423         status = ixgbe_pf_reset_hw(hw);
1424         if (status != 0)
1425                 return -1;
1426         hw->mac.ops.start_hw(hw);
1427
1428         /* configure PF module if SRIOV enabled */
1429         ixgbe_pf_host_configure(dev);
1430
1431         /* initialize transmission unit */
1432         ixgbe_dev_tx_init(dev);
1433
1434         /* This can fail when allocating mbufs for descriptor rings */
1435         err = ixgbe_dev_rx_init(dev);
1436         if (err) {
1437                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1438                 goto error;
1439         }
1440
1441         ixgbe_dev_rxtx_start(dev);
1442
1443         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1444                 err = hw->mac.ops.setup_sfp(hw);
1445                 if (err)
1446                         goto error;
1447         }
1448
1449         /* Turn on the laser */
1450         ixgbe_enable_tx_laser(hw);
1451
1452         /* Skip link setup if loopback mode is enabled for 82599. */
1453         if (hw->mac.type == ixgbe_mac_82599EB &&
1454                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1455                 goto skip_link_setup;
1456
1457         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1458         if (err)
1459                 goto error;
1460         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1461         if (err)
1462                 goto error;
1463
1464         switch(dev->data->dev_conf.link_speed) {
1465         case ETH_LINK_SPEED_AUTONEG:
1466                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1467                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1468                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1469                 break;
1470         case ETH_LINK_SPEED_100:
1471                 /*
1472                  * Invalid for 82598 but error will be detected by
1473                  * ixgbe_setup_link()
1474                  */
1475                 speed = IXGBE_LINK_SPEED_100_FULL;
1476                 break;
1477         case ETH_LINK_SPEED_1000:
1478                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1479                 break;
1480         case ETH_LINK_SPEED_10000:
1481                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1482                 break;
1483         default:
1484                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1485                                 dev->data->dev_conf.link_speed,
1486                                 dev->data->port_id);
1487                 goto error;
1488         }
1489
1490         err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1491         if (err)
1492                 goto error;
1493
1494 skip_link_setup:
1495
1496         /* check if lsc interrupt is enabled */
1497         if (dev->data->dev_conf.intr_conf.lsc != 0)
1498                 ixgbe_dev_lsc_interrupt_setup(dev);
1499
1500         /* resume enabled intr since hw reset */
1501         ixgbe_enable_intr(dev);
1502
1503         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1504                 ETH_VLAN_EXTEND_MASK;
1505         ixgbe_vlan_offload_set(dev, mask);
1506
1507         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1508                 /* Enable vlan filtering for VMDq */
1509                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1510         }
1511
1512         /* Configure DCB hw */
1513         ixgbe_configure_dcb(dev);
1514
1515         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1516                 err = ixgbe_fdir_configure(dev);
1517                 if (err)
1518                         goto error;
1519         }
1520
1521         /* Restore vf rate limit */
1522         if (vfinfo != NULL) {
1523                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1524                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1525                                 if (vfinfo[vf].tx_rate[idx] != 0)
1526                                         ixgbe_set_vf_rate_limit(dev, vf,
1527                                                 vfinfo[vf].tx_rate[idx],
1528                                                 1 << idx);
1529         }
1530
1531         ixgbe_restore_statistics_mapping(dev);
1532
1533         return (0);
1534
1535 error:
1536         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1537         ixgbe_dev_clear_queues(dev);
1538         return -EIO;
1539 }
1540
1541 /*
1542  * Stop device: disable rx and tx functions to allow for reconfiguring.
1543  */
1544 static void
1545 ixgbe_dev_stop(struct rte_eth_dev *dev)
1546 {
1547         struct rte_eth_link link;
1548         struct ixgbe_hw *hw =
1549                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1550         struct ixgbe_vf_info *vfinfo =
1551                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1552         int vf;
1553
1554         PMD_INIT_FUNC_TRACE();
1555
1556         /* disable interrupts */
1557         ixgbe_disable_intr(hw);
1558
1559         /* reset the NIC */
1560         ixgbe_pf_reset_hw(hw);
1561         hw->adapter_stopped = FALSE;
1562
1563         /* stop adapter */
1564         ixgbe_stop_adapter(hw);
1565
1566         for (vf = 0; vfinfo != NULL &&
1567                      vf < dev->pci_dev->max_vfs; vf++)
1568                 vfinfo[vf].clear_to_send = false;
1569
1570         /* Turn off the laser */
1571         ixgbe_disable_tx_laser(hw);
1572
1573         ixgbe_dev_clear_queues(dev);
1574
1575         /* Clear recorded link status */
1576         memset(&link, 0, sizeof(link));
1577         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1578 }
1579
1580 /*
1581  * Set device link up: enable tx laser.
1582  */
1583 static int
1584 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1585 {
1586         struct ixgbe_hw *hw =
1587                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1588         if (hw->mac.type == ixgbe_mac_82599EB) {
1589 #ifdef RTE_NIC_BYPASS
1590                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1591                         /* Not suported in bypass mode */
1592                         PMD_INIT_LOG(ERR,
1593                                 "\nSet link up is not supported "
1594                                 "by device id 0x%x\n",
1595                                 hw->device_id);
1596                         return -ENOTSUP;
1597                 }
1598 #endif
1599                 /* Turn on the laser */
1600                 ixgbe_enable_tx_laser(hw);
1601                 return 0;
1602         }
1603
1604         PMD_INIT_LOG(ERR, "\nSet link up is not supported by device id 0x%x\n",
1605                 hw->device_id);
1606         return -ENOTSUP;
1607 }
1608
1609 /*
1610  * Set device link down: disable tx laser.
1611  */
1612 static int
1613 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1614 {
1615         struct ixgbe_hw *hw =
1616                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1617         if (hw->mac.type == ixgbe_mac_82599EB) {
1618 #ifdef RTE_NIC_BYPASS
1619                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1620                         /* Not suported in bypass mode */
1621                         PMD_INIT_LOG(ERR,
1622                                 "\nSet link down is not supported "
1623                                 "by device id 0x%x\n",
1624                                  hw->device_id);
1625                         return -ENOTSUP;
1626                 }
1627 #endif
1628                 /* Turn off the laser */
1629                 ixgbe_disable_tx_laser(hw);
1630                 return 0;
1631         }
1632
1633         PMD_INIT_LOG(ERR,
1634                 "\nSet link down is not supported by device id 0x%x\n",
1635                  hw->device_id);
1636         return -ENOTSUP;
1637 }
1638
1639 /*
1640  * Reest and stop device.
1641  */
1642 static void
1643 ixgbe_dev_close(struct rte_eth_dev *dev)
1644 {
1645         struct ixgbe_hw *hw =
1646                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1647
1648         PMD_INIT_FUNC_TRACE();
1649
1650         ixgbe_pf_reset_hw(hw);
1651
1652         ixgbe_dev_stop(dev);
1653         hw->adapter_stopped = 1;
1654
1655         ixgbe_disable_pcie_master(hw);
1656
1657         /* reprogram the RAR[0] in case user changed it. */
1658         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1659 }
1660
1661 /*
1662  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1663  */
1664 static void
1665 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1666 {
1667         struct ixgbe_hw *hw =
1668                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1669         struct ixgbe_hw_stats *hw_stats =
1670                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1671         uint32_t bprc, lxon, lxoff, total;
1672         uint64_t total_missed_rx, total_qbrc, total_qprc;
1673         unsigned i;
1674
1675         total_missed_rx = 0;
1676         total_qbrc = 0;
1677         total_qprc = 0;
1678
1679         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1680         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1681         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1682         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1683
1684         for (i = 0; i < 8; i++) {
1685                 uint32_t mp;
1686                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1687                 /* global total per queue */
1688                 hw_stats->mpc[i] += mp;
1689                 /* Running comprehensive total for stats display */
1690                 total_missed_rx += hw_stats->mpc[i];
1691                 if (hw->mac.type == ixgbe_mac_82598EB)
1692                         hw_stats->rnbc[i] +=
1693                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1694                 hw_stats->pxontxc[i] +=
1695                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1696                 hw_stats->pxonrxc[i] +=
1697                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1698                 hw_stats->pxofftxc[i] +=
1699                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1700                 hw_stats->pxoffrxc[i] +=
1701                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1702                 hw_stats->pxon2offc[i] +=
1703                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1704         }
1705         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1706                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1707                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1708                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1709                 hw_stats->qbrc[i] +=
1710                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1711                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1712                 hw_stats->qbtc[i] +=
1713                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1714                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1715
1716                 total_qprc += hw_stats->qprc[i];
1717                 total_qbrc += hw_stats->qbrc[i];
1718         }
1719         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1720         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1721         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1722
1723         /* Note that gprc counts missed packets */
1724         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1725
1726         if (hw->mac.type != ixgbe_mac_82598EB) {
1727                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1728                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1729                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1730                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1731                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1732                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1733                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1734                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1735         } else {
1736                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1737                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1738                 /* 82598 only has a counter in the high register */
1739                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1740                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1741                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1742         }
1743
1744         /*
1745          * Workaround: mprc hardware is incorrectly counting
1746          * broadcasts, so for now we subtract those.
1747          */
1748         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1749         hw_stats->bprc += bprc;
1750         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1751         if (hw->mac.type == ixgbe_mac_82598EB)
1752                 hw_stats->mprc -= bprc;
1753
1754         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1755         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1756         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1757         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1758         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1759         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1760
1761         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1762         hw_stats->lxontxc += lxon;
1763         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1764         hw_stats->lxofftxc += lxoff;
1765         total = lxon + lxoff;
1766
1767         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1768         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1769         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1770         hw_stats->gptc -= total;
1771         hw_stats->mptc -= total;
1772         hw_stats->ptc64 -= total;
1773         hw_stats->gotc -= total * ETHER_MIN_LEN;
1774
1775         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1776         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1777         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1778         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1779         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1780         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1781         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1782         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1783         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1784         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1785         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1786         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1787         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1788         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1789         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1790         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1791         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1792         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1793         /* Only read FCOE on 82599 */
1794         if (hw->mac.type != ixgbe_mac_82598EB) {
1795                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1796                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1797                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1798                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1799                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1800         }
1801
1802         if (stats == NULL)
1803                 return;
1804
1805         /* Fill out the rte_eth_stats statistics structure */
1806         stats->ipackets = total_qprc;
1807         stats->ibytes = total_qbrc;
1808         stats->opackets = hw_stats->gptc;
1809         stats->obytes = hw_stats->gotc;
1810         stats->imcasts = hw_stats->mprc;
1811
1812         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1813                 stats->q_ipackets[i] = hw_stats->qprc[i];
1814                 stats->q_opackets[i] = hw_stats->qptc[i];
1815                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1816                 stats->q_obytes[i] = hw_stats->qbtc[i];
1817                 stats->q_errors[i] = hw_stats->qprdc[i];
1818         }
1819
1820         /* Rx Errors */
1821         stats->ibadcrc  = hw_stats->crcerrs;
1822         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1823         stats->imissed  = total_missed_rx;
1824         stats->ierrors  = stats->ibadcrc +
1825                           stats->ibadlen +
1826                           stats->imissed +
1827                           hw_stats->illerrc + hw_stats->errbc;
1828
1829         /* Tx Errors */
1830         stats->oerrors  = 0;
1831
1832         /* XON/XOFF pause frames */
1833         stats->tx_pause_xon  = hw_stats->lxontxc;
1834         stats->rx_pause_xon  = hw_stats->lxonrxc;
1835         stats->tx_pause_xoff = hw_stats->lxofftxc;
1836         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1837
1838         /* Flow Director Stats registers */
1839         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1840         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1841         stats->fdirmatch = hw_stats->fdirmatch;
1842         stats->fdirmiss = hw_stats->fdirmiss;
1843 }
1844
1845 static void
1846 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1847 {
1848         struct ixgbe_hw_stats *stats =
1849                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1850
1851         /* HW registers are cleared on read */
1852         ixgbe_dev_stats_get(dev, NULL);
1853
1854         /* Reset software totals */
1855         memset(stats, 0, sizeof(*stats));
1856 }
1857
1858 static void
1859 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1860 {
1861         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1863                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1864
1865         /* Good Rx packet, include VF loopback */
1866         UPDATE_VF_STAT(IXGBE_VFGPRC,
1867             hw_stats->last_vfgprc, hw_stats->vfgprc);
1868
1869         /* Good Rx octets, include VF loopback */
1870         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1871             hw_stats->last_vfgorc, hw_stats->vfgorc);
1872
1873         /* Good Tx packet, include VF loopback */
1874         UPDATE_VF_STAT(IXGBE_VFGPTC,
1875             hw_stats->last_vfgptc, hw_stats->vfgptc);
1876
1877         /* Good Tx octets, include VF loopback */
1878         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1879             hw_stats->last_vfgotc, hw_stats->vfgotc);
1880
1881         /* Rx Multicst Packet */
1882         UPDATE_VF_STAT(IXGBE_VFMPRC,
1883             hw_stats->last_vfmprc, hw_stats->vfmprc);
1884
1885         if (stats == NULL)
1886                 return;
1887
1888         memset(stats, 0, sizeof(*stats));
1889         stats->ipackets = hw_stats->vfgprc;
1890         stats->ibytes = hw_stats->vfgorc;
1891         stats->opackets = hw_stats->vfgptc;
1892         stats->obytes = hw_stats->vfgotc;
1893         stats->imcasts = hw_stats->vfmprc;
1894 }
1895
1896 static void
1897 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1898 {
1899         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1900                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1901
1902         /* Sync HW register to the last stats */
1903         ixgbevf_dev_stats_get(dev, NULL);
1904
1905         /* reset HW current stats*/
1906         hw_stats->vfgprc = 0;
1907         hw_stats->vfgorc = 0;
1908         hw_stats->vfgptc = 0;
1909         hw_stats->vfgotc = 0;
1910         hw_stats->vfmprc = 0;
1911
1912 }
1913
1914 static void
1915 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1916 {
1917         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1918
1919         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1920         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1921         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1922         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1923         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1924         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1925         dev_info->max_vfs = dev->pci_dev->max_vfs;
1926         if (hw->mac.type == ixgbe_mac_82598EB)
1927                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1928         else
1929                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1930         dev_info->rx_offload_capa =
1931                 DEV_RX_OFFLOAD_VLAN_STRIP |
1932                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1933                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1934                 DEV_RX_OFFLOAD_TCP_CKSUM;
1935         dev_info->tx_offload_capa =
1936                 DEV_TX_OFFLOAD_VLAN_INSERT |
1937                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1938                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1939                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1940                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1941 }
1942
1943 /* return 0 means link status changed, -1 means not changed */
1944 static int
1945 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1946 {
1947         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1948         struct rte_eth_link link, old;
1949         ixgbe_link_speed link_speed;
1950         int link_up;
1951         int diag;
1952
1953         link.link_status = 0;
1954         link.link_speed = 0;
1955         link.link_duplex = 0;
1956         memset(&old, 0, sizeof(old));
1957         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1958
1959         /* check if it needs to wait to complete, if lsc interrupt is enabled */
1960         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1961                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1962         else
1963                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1964         if (diag != 0) {
1965                 link.link_speed = ETH_LINK_SPEED_100;
1966                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1967                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1968                 if (link.link_status == old.link_status)
1969                         return -1;
1970                 return 0;
1971         }
1972
1973         if (link_up == 0) {
1974                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1975                 if (link.link_status == old.link_status)
1976                         return -1;
1977                 return 0;
1978         }
1979         link.link_status = 1;
1980         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1981
1982         switch (link_speed) {
1983         default:
1984         case IXGBE_LINK_SPEED_UNKNOWN:
1985                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1986                 link.link_speed = ETH_LINK_SPEED_100;
1987                 break;
1988
1989         case IXGBE_LINK_SPEED_100_FULL:
1990                 link.link_speed = ETH_LINK_SPEED_100;
1991                 break;
1992
1993         case IXGBE_LINK_SPEED_1GB_FULL:
1994                 link.link_speed = ETH_LINK_SPEED_1000;
1995                 break;
1996
1997         case IXGBE_LINK_SPEED_10GB_FULL:
1998                 link.link_speed = ETH_LINK_SPEED_10000;
1999                 break;
2000         }
2001         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2002
2003         if (link.link_status == old.link_status)
2004                 return -1;
2005
2006         return 0;
2007 }
2008
2009 static void
2010 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2011 {
2012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013         uint32_t fctrl;
2014
2015         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2016         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2017         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2018 }
2019
2020 static void
2021 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2022 {
2023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2024         uint32_t fctrl;
2025
2026         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2027         fctrl &= (~IXGBE_FCTRL_UPE);
2028         if (dev->data->all_multicast == 1)
2029                 fctrl |= IXGBE_FCTRL_MPE;
2030         else
2031                 fctrl &= (~IXGBE_FCTRL_MPE);
2032         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2033 }
2034
2035 static void
2036 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2037 {
2038         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2039         uint32_t fctrl;
2040
2041         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2042         fctrl |= IXGBE_FCTRL_MPE;
2043         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2044 }
2045
2046 static void
2047 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2048 {
2049         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2050         uint32_t fctrl;
2051
2052         if (dev->data->promiscuous == 1)
2053                 return; /* must remain in all_multicast mode */
2054
2055         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2056         fctrl &= (~IXGBE_FCTRL_MPE);
2057         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2058 }
2059
2060 /**
2061  * It clears the interrupt causes and enables the interrupt.
2062  * It will be called once only during nic initialized.
2063  *
2064  * @param dev
2065  *  Pointer to struct rte_eth_dev.
2066  *
2067  * @return
2068  *  - On success, zero.
2069  *  - On failure, a negative value.
2070  */
2071 static int
2072 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2073 {
2074         struct ixgbe_interrupt *intr =
2075                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2076
2077         ixgbe_dev_link_status_print(dev);
2078         intr->mask |= IXGBE_EICR_LSC;
2079
2080         return 0;
2081 }
2082
2083 /*
2084  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2085  *
2086  * @param dev
2087  *  Pointer to struct rte_eth_dev.
2088  *
2089  * @return
2090  *  - On success, zero.
2091  *  - On failure, a negative value.
2092  */
2093 static int
2094 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2095 {
2096         uint32_t eicr;
2097         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098         struct ixgbe_interrupt *intr =
2099                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2100
2101         /* clear all cause mask */
2102         ixgbe_disable_intr(hw);
2103
2104         /* read-on-clear nic registers here */
2105         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2106         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2107
2108         intr->flags = 0;
2109         if (eicr & IXGBE_EICR_LSC) {
2110                 /* set flag for async link update */
2111                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2112         }
2113
2114         if (eicr & IXGBE_EICR_MAILBOX)
2115                 intr->flags |= IXGBE_FLAG_MAILBOX;
2116
2117         return 0;
2118 }
2119
2120 /**
2121  * It gets and then prints the link status.
2122  *
2123  * @param dev
2124  *  Pointer to struct rte_eth_dev.
2125  *
2126  * @return
2127  *  - On success, zero.
2128  *  - On failure, a negative value.
2129  */
2130 static void
2131 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2132 {
2133         struct rte_eth_link link;
2134
2135         memset(&link, 0, sizeof(link));
2136         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2137         if (link.link_status) {
2138                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2139                                         (int)(dev->data->port_id),
2140                                         (unsigned)link.link_speed,
2141                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2142                                         "full-duplex" : "half-duplex");
2143         } else {
2144                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2145                                 (int)(dev->data->port_id));
2146         }
2147         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2148                                 dev->pci_dev->addr.domain,
2149                                 dev->pci_dev->addr.bus,
2150                                 dev->pci_dev->addr.devid,
2151                                 dev->pci_dev->addr.function);
2152 }
2153
2154 /*
2155  * It executes link_update after knowing an interrupt occurred.
2156  *
2157  * @param dev
2158  *  Pointer to struct rte_eth_dev.
2159  *
2160  * @return
2161  *  - On success, zero.
2162  *  - On failure, a negative value.
2163  */
2164 static int
2165 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2166 {
2167         struct ixgbe_interrupt *intr =
2168                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2169         int64_t timeout;
2170         struct rte_eth_link link;
2171         int intr_enable_delay = false;
2172
2173         PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
2174
2175         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2176                 ixgbe_pf_mbx_process(dev);
2177                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2178         }
2179
2180         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2181                 /* get the link status before link update, for predicting later */
2182                 memset(&link, 0, sizeof(link));
2183                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2184
2185                 ixgbe_dev_link_update(dev, 0);
2186
2187                 /* likely to up */
2188                 if (!link.link_status)
2189                         /* handle it 1 sec later, wait it being stable */
2190                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2191                 /* likely to down */
2192                 else
2193                         /* handle it 4 sec later, wait it being stable */
2194                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2195
2196                 ixgbe_dev_link_status_print(dev);
2197
2198                 intr_enable_delay = true;
2199         }
2200
2201         if (intr_enable_delay) {
2202                 if (rte_eal_alarm_set(timeout * 1000,
2203                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2204                         PMD_DRV_LOG(ERR, "Error setting alarm");
2205         } else {
2206                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2207                 ixgbe_enable_intr(dev);
2208                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2209         }
2210
2211
2212         return 0;
2213 }
2214
2215 /**
2216  * Interrupt handler which shall be registered for alarm callback for delayed
2217  * handling specific interrupt to wait for the stable nic state. As the
2218  * NIC interrupt state is not stable for ixgbe after link is just down,
2219  * it needs to wait 4 seconds to get the stable status.
2220  *
2221  * @param handle
2222  *  Pointer to interrupt handle.
2223  * @param param
2224  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2225  *
2226  * @return
2227  *  void
2228  */
2229 static void
2230 ixgbe_dev_interrupt_delayed_handler(void *param)
2231 {
2232         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2233         struct ixgbe_interrupt *intr =
2234                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2235         struct ixgbe_hw *hw =
2236                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2237         uint32_t eicr;
2238
2239         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2240         if (eicr & IXGBE_EICR_MAILBOX)
2241                 ixgbe_pf_mbx_process(dev);
2242
2243         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2244                 ixgbe_dev_link_update(dev, 0);
2245                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2246                 ixgbe_dev_link_status_print(dev);
2247                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2248         }
2249
2250         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
2251         ixgbe_enable_intr(dev);
2252         rte_intr_enable(&(dev->pci_dev->intr_handle));
2253 }
2254
2255 /**
2256  * Interrupt handler triggered by NIC  for handling
2257  * specific interrupt.
2258  *
2259  * @param handle
2260  *  Pointer to interrupt handle.
2261  * @param param
2262  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2263  *
2264  * @return
2265  *  void
2266  */
2267 static void
2268 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2269                                                         void *param)
2270 {
2271         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2272         ixgbe_dev_interrupt_get_status(dev);
2273         ixgbe_dev_interrupt_action(dev);
2274 }
2275
2276 static int
2277 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2278 {
2279         struct ixgbe_hw *hw;
2280
2281         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2282         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2283 }
2284
2285 static int
2286 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2287 {
2288         struct ixgbe_hw *hw;
2289
2290         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2292 }
2293
2294 static int
2295 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2296 {
2297         struct ixgbe_hw *hw;
2298         int err;
2299         uint32_t rx_buf_size;
2300         uint32_t max_high_water;
2301         uint32_t mflcn;
2302         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2303                 ixgbe_fc_none,
2304                 ixgbe_fc_rx_pause,
2305                 ixgbe_fc_tx_pause,
2306                 ixgbe_fc_full
2307         };
2308
2309         PMD_INIT_FUNC_TRACE();
2310
2311         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2312         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2313         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2314
2315         /*
2316          * At least reserve one Ethernet frame for watermark
2317          * high_water/low_water in kilo bytes for ixgbe
2318          */
2319         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2320         if ((fc_conf->high_water > max_high_water) ||
2321                 (fc_conf->high_water < fc_conf->low_water)) {
2322                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2323                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2324                 return (-EINVAL);
2325         }
2326
2327         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2328         hw->fc.pause_time     = fc_conf->pause_time;
2329         hw->fc.high_water[0]  = fc_conf->high_water;
2330         hw->fc.low_water[0]   = fc_conf->low_water;
2331         hw->fc.send_xon       = fc_conf->send_xon;
2332
2333         err = ixgbe_fc_enable(hw);
2334
2335         /* Not negotiated is not an error case */
2336         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2337
2338                 /* check if we want to forward MAC frames - driver doesn't have native
2339                  * capability to do that, so we'll write the registers ourselves */
2340
2341                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2342
2343                 /* set or clear MFLCN.PMCF bit depending on configuration */
2344                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2345                         mflcn |= IXGBE_MFLCN_PMCF;
2346                 else
2347                         mflcn &= ~IXGBE_MFLCN_PMCF;
2348
2349                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2350                 IXGBE_WRITE_FLUSH(hw);
2351
2352                 return 0;
2353         }
2354
2355         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2356         return -EIO;
2357 }
2358
2359 /**
2360  *  ixgbe_pfc_enable_generic - Enable flow control
2361  *  @hw: pointer to hardware structure
2362  *  @tc_num: traffic class number
2363  *  Enable flow control according to the current settings.
2364  */
2365 static int
2366 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2367 {
2368         int ret_val = 0;
2369         uint32_t mflcn_reg, fccfg_reg;
2370         uint32_t reg;
2371         uint32_t fcrtl, fcrth;
2372         uint8_t i;
2373         uint8_t nb_rx_en;
2374
2375         /* Validate the water mark configuration */
2376         if (!hw->fc.pause_time) {
2377                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2378                 goto out;
2379         }
2380
2381         /* Low water mark of zero causes XOFF floods */
2382         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2383                  /* High/Low water can not be 0 */
2384                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2385                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2386                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2387                         goto out;
2388                 }
2389
2390                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2391                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2392                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2393                         goto out;
2394                 }
2395         }
2396         /* Negotiate the fc mode to use */
2397         ixgbe_fc_autoneg(hw);
2398
2399         /* Disable any previous flow control settings */
2400         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2401         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2402
2403         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2404         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2405
2406         switch (hw->fc.current_mode) {
2407         case ixgbe_fc_none:
2408                 /*
2409                  * If the count of enabled RX Priority Flow control >1,
2410                  * and the TX pause can not be disabled
2411                  */
2412                 nb_rx_en = 0;
2413                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2414                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2415                         if (reg & IXGBE_FCRTH_FCEN)
2416                                 nb_rx_en++;
2417                 }
2418                 if (nb_rx_en > 1)
2419                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2420                 break;
2421         case ixgbe_fc_rx_pause:
2422                 /*
2423                  * Rx Flow control is enabled and Tx Flow control is
2424                  * disabled by software override. Since there really
2425                  * isn't a way to advertise that we are capable of RX
2426                  * Pause ONLY, we will advertise that we support both
2427                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2428                  * disable the adapter's ability to send PAUSE frames.
2429                  */
2430                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2431                 /*
2432                  * If the count of enabled RX Priority Flow control >1,
2433                  * and the TX pause can not be disabled
2434                  */
2435                 nb_rx_en = 0;
2436                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2437                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2438                         if (reg & IXGBE_FCRTH_FCEN)
2439                                 nb_rx_en++;
2440                 }
2441                 if (nb_rx_en > 1)
2442                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2443                 break;
2444         case ixgbe_fc_tx_pause:
2445                 /*
2446                  * Tx Flow control is enabled, and Rx Flow control is
2447                  * disabled by software override.
2448                  */
2449                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2450                 break;
2451         case ixgbe_fc_full:
2452                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2453                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2454                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2455                 break;
2456         default:
2457                 DEBUGOUT("Flow control param set incorrectly\n");
2458                 ret_val = IXGBE_ERR_CONFIG;
2459                 goto out;
2460                 break;
2461         }
2462
2463         /* Set 802.3x based flow control settings. */
2464         mflcn_reg |= IXGBE_MFLCN_DPF;
2465         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2466         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2467
2468         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2469         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2470                 hw->fc.high_water[tc_num]) {
2471                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2472                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2473                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2474         } else {
2475                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2476                 /*
2477                  * In order to prevent Tx hangs when the internal Tx
2478                  * switch is enabled we must set the high water mark
2479                  * to the maximum FCRTH value.  This allows the Tx
2480                  * switch to function even under heavy Rx workloads.
2481                  */
2482                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2483         }
2484         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2485
2486         /* Configure pause time (2 TCs per register) */
2487         reg = hw->fc.pause_time * 0x00010001;
2488         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2489                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2490
2491         /* Configure flow control refresh threshold value */
2492         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2493
2494 out:
2495         return ret_val;
2496 }
2497
2498 static int
2499 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2500 {
2501         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2502         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2503
2504         if(hw->mac.type != ixgbe_mac_82598EB) {
2505                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2506         }
2507         return ret_val;
2508 }
2509
2510 static int
2511 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2512 {
2513         int err;
2514         uint32_t rx_buf_size;
2515         uint32_t max_high_water;
2516         uint8_t tc_num;
2517         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2518         struct ixgbe_hw *hw =
2519                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2520         struct ixgbe_dcb_config *dcb_config =
2521                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2522
2523         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2524                 ixgbe_fc_none,
2525                 ixgbe_fc_rx_pause,
2526                 ixgbe_fc_tx_pause,
2527                 ixgbe_fc_full
2528         };
2529
2530         PMD_INIT_FUNC_TRACE();
2531
2532         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2533         tc_num = map[pfc_conf->priority];
2534         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2535         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2536         /*
2537          * At least reserve one Ethernet frame for watermark
2538          * high_water/low_water in kilo bytes for ixgbe
2539          */
2540         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2541         if ((pfc_conf->fc.high_water > max_high_water) ||
2542                 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2543                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2544                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2545                 return (-EINVAL);
2546         }
2547
2548         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2549         hw->fc.pause_time = pfc_conf->fc.pause_time;
2550         hw->fc.send_xon = pfc_conf->fc.send_xon;
2551         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2552         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2553
2554         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2555
2556         /* Not negotiated is not an error case */
2557         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2558                 return 0;
2559
2560         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2561         return -EIO;
2562 }
2563
2564 static int
2565 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2566                                 struct rte_eth_rss_reta *reta_conf)
2567 {
2568         uint8_t i,j,mask;
2569         uint32_t reta;
2570         struct ixgbe_hw *hw =
2571                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2572
2573         PMD_INIT_FUNC_TRACE();
2574         /*
2575         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2576         * 128-entries in 32 registers
2577          */
2578         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2579                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2580                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2581                 else
2582                         mask = (uint8_t)((reta_conf->mask_hi >>
2583                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2584                 if (mask != 0) {
2585                         reta = 0;
2586                         if (mask != 0xF)
2587                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2588
2589                         for (j = 0; j < 4; j++) {
2590                                 if (mask & (0x1 << j)) {
2591                                         if (mask != 0xF)
2592                                                 reta &= ~(0xFF << 8 * j);
2593                                         reta |= reta_conf->reta[i + j] << 8*j;
2594                                 }
2595                         }
2596                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2597                 }
2598         }
2599
2600         return 0;
2601 }
2602
2603 static int
2604 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2605                                 struct rte_eth_rss_reta *reta_conf)
2606 {
2607         uint8_t i,j,mask;
2608         uint32_t reta;
2609         struct ixgbe_hw *hw =
2610                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2611
2612         PMD_INIT_FUNC_TRACE();
2613         /*
2614          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2615          * 128-entries in 32 registers
2616          */
2617         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2618                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2619                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2620                 else
2621                         mask = (uint8_t)((reta_conf->mask_hi >>
2622                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2623
2624                 if (mask != 0) {
2625                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2626                         for (j = 0; j < 4; j++) {
2627                                 if (mask & (0x1 << j))
2628                                         reta_conf->reta[i + j] =
2629                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2630                         }
2631                 }
2632         }
2633
2634         return 0;
2635 }
2636
2637 static void
2638 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2639                                 uint32_t index, uint32_t pool)
2640 {
2641         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2642         uint32_t enable_addr = 1;
2643
2644         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2645 }
2646
2647 static void
2648 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2649 {
2650         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2651
2652         ixgbe_clear_rar(hw, index);
2653 }
2654
2655 /*
2656  * Virtual Function operations
2657  */
2658 static void
2659 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2660 {
2661         PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2662
2663         /* Clear interrupt mask to stop from interrupts being generated */
2664         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2665
2666         IXGBE_WRITE_FLUSH(hw);
2667 }
2668
2669 static int
2670 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2671 {
2672         struct rte_eth_conf* conf = &dev->data->dev_conf;
2673
2674         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2675                 dev->data->port_id);
2676
2677         /*
2678          * VF has no ability to enable/disable HW CRC
2679          * Keep the persistent behavior the same as Host PF
2680          */
2681 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2682         if (!conf->rxmode.hw_strip_crc) {
2683                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2684                 conf->rxmode.hw_strip_crc = 1;
2685         }
2686 #else
2687         if (conf->rxmode.hw_strip_crc) {
2688                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2689                 conf->rxmode.hw_strip_crc = 0;
2690         }
2691 #endif
2692
2693         return 0;
2694 }
2695
2696 static int
2697 ixgbevf_dev_start(struct rte_eth_dev *dev)
2698 {
2699         struct ixgbe_hw *hw =
2700                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2701         int err, mask = 0;
2702
2703         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2704
2705         hw->mac.ops.reset_hw(hw);
2706
2707         /* negotiate mailbox API version to use with the PF. */
2708         ixgbevf_negotiate_api(hw);
2709
2710         ixgbevf_dev_tx_init(dev);
2711
2712         /* This can fail when allocating mbufs for descriptor rings */
2713         err = ixgbevf_dev_rx_init(dev);
2714         if (err) {
2715                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2716                 ixgbe_dev_clear_queues(dev);
2717                 return err;
2718         }
2719
2720         /* Set vfta */
2721         ixgbevf_set_vfta_all(dev,1);
2722
2723         /* Set HW strip */
2724         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2725                 ETH_VLAN_EXTEND_MASK;
2726         ixgbevf_vlan_offload_set(dev, mask);
2727
2728         ixgbevf_dev_rxtx_start(dev);
2729
2730         return 0;
2731 }
2732
2733 static void
2734 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2735 {
2736         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2737
2738         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2739
2740         hw->adapter_stopped = TRUE;
2741         ixgbe_stop_adapter(hw);
2742
2743         /*
2744           * Clear what we set, but we still keep shadow_vfta to
2745           * restore after device starts
2746           */
2747         ixgbevf_set_vfta_all(dev,0);
2748
2749         ixgbe_dev_clear_queues(dev);
2750 }
2751
2752 static void
2753 ixgbevf_dev_close(struct rte_eth_dev *dev)
2754 {
2755         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2756
2757         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2758
2759         ixgbe_reset_hw(hw);
2760
2761         ixgbevf_dev_stop(dev);
2762
2763         /* reprogram the RAR[0] in case user changed it. */
2764         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2765 }
2766
2767 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2768 {
2769         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2770         struct ixgbe_vfta * shadow_vfta =
2771                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2772         int i = 0, j = 0, vfta = 0, mask = 1;
2773
2774         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2775                 vfta = shadow_vfta->vfta[i];
2776                 if(vfta){
2777                         mask = 1;
2778                         for (j = 0; j < 32; j++){
2779                                 if(vfta & mask)
2780                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2781                                 mask<<=1;
2782                         }
2783                 }
2784         }
2785
2786 }
2787
2788 static int
2789 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2790 {
2791         struct ixgbe_hw *hw =
2792                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2793         struct ixgbe_vfta * shadow_vfta =
2794                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2795         uint32_t vid_idx = 0;
2796         uint32_t vid_bit = 0;
2797         int ret = 0;
2798
2799         PMD_INIT_FUNC_TRACE();
2800
2801         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2802         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2803         if(ret){
2804                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2805                 return ret;
2806         }
2807         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2808         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2809
2810         /* Save what we set and retore it after device reset */
2811         if (on)
2812                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2813         else
2814                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2815
2816         return 0;
2817 }
2818
2819 static void
2820 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2821 {
2822         struct ixgbe_hw *hw =
2823                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2824         uint32_t ctrl;
2825
2826         PMD_INIT_FUNC_TRACE();
2827
2828         if(queue >= hw->mac.max_rx_queues)
2829                 return;
2830
2831         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2832         if(on)
2833                 ctrl |= IXGBE_RXDCTL_VME;
2834         else
2835                 ctrl &= ~IXGBE_RXDCTL_VME;
2836         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2837
2838         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2839 }
2840
2841 static void
2842 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2843 {
2844         struct ixgbe_hw *hw =
2845                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2846         uint16_t i;
2847         int on = 0;
2848
2849         /* VF function only support hw strip feature, others are not support */
2850         if(mask & ETH_VLAN_STRIP_MASK){
2851                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2852
2853                 for(i=0; i < hw->mac.max_rx_queues; i++)
2854                         ixgbevf_vlan_strip_queue_set(dev,i,on);
2855         }
2856 }
2857
2858 static int
2859 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2860 {
2861         uint32_t reg_val;
2862
2863         /* we only need to do this if VMDq is enabled */
2864         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2865         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2866                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2867                 return (-1);
2868         }
2869
2870         return 0;
2871 }
2872
2873 static uint32_t
2874 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2875 {
2876         uint32_t vector = 0;
2877         switch (hw->mac.mc_filter_type) {
2878         case 0:   /* use bits [47:36] of the address */
2879                 vector = ((uc_addr->addr_bytes[4] >> 4) |
2880                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2881                 break;
2882         case 1:   /* use bits [46:35] of the address */
2883                 vector = ((uc_addr->addr_bytes[4] >> 3) |
2884                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2885                 break;
2886         case 2:   /* use bits [45:34] of the address */
2887                 vector = ((uc_addr->addr_bytes[4] >> 2) |
2888                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2889                 break;
2890         case 3:   /* use bits [43:32] of the address */
2891                 vector = ((uc_addr->addr_bytes[4]) |
2892                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2893                 break;
2894         default:  /* Invalid mc_filter_type */
2895                 break;
2896         }
2897
2898         /* vector can only be 12-bits or boundary will be exceeded */
2899         vector &= 0xFFF;
2900         return vector;
2901 }
2902
2903 static int
2904 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
2905                                uint8_t on)
2906 {
2907         uint32_t vector;
2908         uint32_t uta_idx;
2909         uint32_t reg_val;
2910         uint32_t uta_shift;
2911         uint32_t rc;
2912         const uint32_t ixgbe_uta_idx_mask = 0x7F;
2913         const uint32_t ixgbe_uta_bit_shift = 5;
2914         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
2915         const uint32_t bit1 = 0x1;
2916
2917         struct ixgbe_hw *hw =
2918                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2919         struct ixgbe_uta_info *uta_info =
2920                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2921
2922         /* The UTA table only exists on 82599 hardware and newer */
2923         if (hw->mac.type < ixgbe_mac_82599EB)
2924                 return (-ENOTSUP);
2925
2926         vector = ixgbe_uta_vector(hw,mac_addr);
2927         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
2928         uta_shift = vector & ixgbe_uta_bit_mask;
2929
2930         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
2931         if(rc == on)
2932                 return 0;
2933
2934         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
2935         if (on) {
2936                 uta_info->uta_in_use++;
2937                 reg_val |= (bit1 << uta_shift);
2938                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
2939         } else {
2940                 uta_info->uta_in_use--;
2941                 reg_val &= ~(bit1 << uta_shift);
2942                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
2943         }
2944
2945         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
2946
2947         if (uta_info->uta_in_use > 0)
2948                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2949                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2950         else
2951                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
2952
2953         return 0;
2954 }
2955
2956 static int
2957 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
2958 {
2959         int i;
2960         struct ixgbe_hw *hw =
2961                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2962         struct ixgbe_uta_info *uta_info =
2963                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2964
2965         /* The UTA table only exists on 82599 hardware and newer */
2966         if (hw->mac.type < ixgbe_mac_82599EB)
2967                 return (-ENOTSUP);
2968
2969         if(on) {
2970                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2971                         uta_info->uta_shadow[i] = ~0;
2972                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2973                 }
2974         } else {
2975                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2976                         uta_info->uta_shadow[i] = 0;
2977                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2978                 }
2979         }
2980         return 0;
2981
2982 }
2983 static int
2984 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
2985                                uint16_t rx_mask, uint8_t on)
2986 {
2987         int val = 0;
2988
2989         struct ixgbe_hw *hw =
2990                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2991         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
2992
2993         if (hw->mac.type == ixgbe_mac_82598EB) {
2994                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
2995                         " on 82599 hardware and newer\n");
2996                 return (-ENOTSUP);
2997         }
2998         if (ixgbe_vmdq_mode_check(hw) < 0)
2999                 return (-ENOTSUP);
3000
3001         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
3002                 val |= IXGBE_VMOLR_AUPE;
3003         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
3004                 val |= IXGBE_VMOLR_ROMPE;
3005         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3006                 val |= IXGBE_VMOLR_ROPE;
3007         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3008                 val |= IXGBE_VMOLR_BAM;
3009         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3010                 val |= IXGBE_VMOLR_MPE;
3011
3012         if (on)
3013                 vmolr |= val;
3014         else
3015                 vmolr &= ~val;
3016
3017         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3018
3019         return 0;
3020 }
3021
3022 static int
3023 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3024 {
3025         uint32_t reg,addr;
3026         uint32_t val;
3027         const uint8_t bit1 = 0x1;
3028
3029         struct ixgbe_hw *hw =
3030                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3031
3032         if (ixgbe_vmdq_mode_check(hw) < 0)
3033                 return (-ENOTSUP);
3034
3035         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3036         reg = IXGBE_READ_REG(hw, addr);
3037         val = bit1 << pool;
3038
3039         if (on)
3040                 reg |= val;
3041         else
3042                 reg &= ~val;
3043
3044         IXGBE_WRITE_REG(hw, addr,reg);
3045
3046         return 0;
3047 }
3048
3049 static int
3050 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3051 {
3052         uint32_t reg,addr;
3053         uint32_t val;
3054         const uint8_t bit1 = 0x1;
3055
3056         struct ixgbe_hw *hw =
3057                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3058
3059         if (ixgbe_vmdq_mode_check(hw) < 0)
3060                 return (-ENOTSUP);
3061
3062         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3063         reg = IXGBE_READ_REG(hw, addr);
3064         val = bit1 << pool;
3065
3066         if (on)
3067                 reg |= val;
3068         else
3069                 reg &= ~val;
3070
3071         IXGBE_WRITE_REG(hw, addr,reg);
3072
3073         return 0;
3074 }
3075
3076 static int
3077 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3078                         uint64_t pool_mask, uint8_t vlan_on)
3079 {
3080         int ret = 0;
3081         uint16_t pool_idx;
3082         struct ixgbe_hw *hw =
3083                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3084
3085         if (ixgbe_vmdq_mode_check(hw) < 0)
3086                 return (-ENOTSUP);
3087         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3088                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3089                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3090                         if (ret < 0)
3091                                 return ret;
3092         }
3093
3094         return ret;
3095 }
3096
3097 static int
3098 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3099                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3100                         uint8_t rule_id, uint8_t on)
3101 {
3102         uint32_t mr_ctl,vlvf;
3103         uint32_t mp_lsb = 0;
3104         uint32_t mv_msb = 0;
3105         uint32_t mv_lsb = 0;
3106         uint32_t mp_msb = 0;
3107         uint8_t i = 0;
3108         int reg_index = 0;
3109         uint64_t vlan_mask = 0;
3110
3111         const uint8_t pool_mask_offset = 32;
3112         const uint8_t vlan_mask_offset = 32;
3113         const uint8_t dst_pool_offset = 8;
3114         const uint8_t rule_mr_offset  = 4;
3115         const uint8_t mirror_rule_mask= 0x0F;
3116
3117         struct ixgbe_mirror_info *mr_info =
3118                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3119         struct ixgbe_hw *hw =
3120                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3121
3122         if (ixgbe_vmdq_mode_check(hw) < 0)
3123                 return (-ENOTSUP);
3124
3125         /* Check if vlan mask is valid */
3126         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3127                 if (mirror_conf->vlan.vlan_mask == 0)
3128                         return (-EINVAL);
3129         }
3130
3131         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3132         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3133                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3134                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3135                                 /* search vlan id related pool vlan filter index */
3136                                 reg_index = ixgbe_find_vlvf_slot(hw,
3137                                                 mirror_conf->vlan.vlan_id[i]);
3138                                 if(reg_index < 0)
3139                                         return (-EINVAL);
3140                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3141                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3142                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3143                                                 == mirror_conf->vlan.vlan_id[i]))
3144                                         vlan_mask |= (1ULL << reg_index);
3145                                 else
3146                                         return (-EINVAL);
3147                         }
3148                 }
3149
3150                 if (on) {
3151                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3152                         mv_msb = vlan_mask >> vlan_mask_offset;
3153
3154                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3155                                                 mirror_conf->vlan.vlan_mask;
3156                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3157                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3158                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3159                                                 mirror_conf->vlan.vlan_id[i];
3160                         }
3161                 } else {
3162                         mv_lsb = 0;
3163                         mv_msb = 0;
3164                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3165                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3166                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3167                 }
3168         }
3169
3170         /*
3171          * if enable pool mirror, write related pool mask register,if disable
3172          * pool mirror, clear PFMRVM register
3173          */
3174         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3175                 if (on) {
3176                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3177                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3178                         mr_info->mr_conf[rule_id].pool_mask =
3179                                         mirror_conf->pool_mask;
3180
3181                 } else {
3182                         mp_lsb = 0;
3183                         mp_msb = 0;
3184                         mr_info->mr_conf[rule_id].pool_mask = 0;
3185                 }
3186         }
3187
3188         /* read  mirror control register and recalculate it */
3189         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3190
3191         if (on) {
3192                 mr_ctl |= mirror_conf->rule_type_mask;
3193                 mr_ctl &= mirror_rule_mask;
3194                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3195         } else
3196                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3197
3198         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3199         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3200
3201         /* write mirrror control  register */
3202         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3203
3204         /* write pool mirrror control  register */
3205         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3206                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3207                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3208                                 mp_msb);
3209         }
3210         /* write VLAN mirrror control  register */
3211         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3212                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3213                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3214                                 mv_msb);
3215         }
3216
3217         return 0;
3218 }
3219
3220 static int
3221 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3222 {
3223         int mr_ctl = 0;
3224         uint32_t lsb_val = 0;
3225         uint32_t msb_val = 0;
3226         const uint8_t rule_mr_offset = 4;
3227
3228         struct ixgbe_hw *hw =
3229                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3230         struct ixgbe_mirror_info *mr_info =
3231                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3232
3233         if (ixgbe_vmdq_mode_check(hw) < 0)
3234                 return (-ENOTSUP);
3235
3236         memset(&mr_info->mr_conf[rule_id], 0,
3237                 sizeof(struct rte_eth_vmdq_mirror_conf));
3238
3239         /* clear PFVMCTL register */
3240         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3241
3242         /* clear pool mask register */
3243         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3244         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3245
3246         /* clear vlan mask register */
3247         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3248         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3249
3250         return 0;
3251 }
3252
3253 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3254         uint16_t queue_idx, uint16_t tx_rate)
3255 {
3256         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3257         uint32_t rf_dec, rf_int;
3258         uint32_t bcnrc_val;
3259         uint16_t link_speed = dev->data->dev_link.link_speed;
3260
3261         if (queue_idx >= hw->mac.max_tx_queues)
3262                 return -EINVAL;
3263
3264         if (tx_rate != 0) {
3265                 /* Calculate the rate factor values to set */
3266                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3267                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3268                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3269
3270                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3271                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3272                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3273                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3274         } else {
3275                 bcnrc_val = 0;
3276         }
3277
3278         /*
3279          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3280          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3281          * set as 0x4.
3282          */
3283         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3284                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3285                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3286                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3287                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3288         else
3289                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3290                         IXGBE_MMW_SIZE_DEFAULT);
3291
3292         /* Set RTTBCNRC of queue X */
3293         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3294         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3295         IXGBE_WRITE_FLUSH(hw);
3296
3297         return 0;
3298 }
3299
3300 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3301         uint16_t tx_rate, uint64_t q_msk)
3302 {
3303         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3304         struct ixgbe_vf_info *vfinfo =
3305                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3306         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3307         uint32_t queue_stride =
3308                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3309         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3310         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3311         uint16_t total_rate = 0;
3312
3313         if (queue_end >= hw->mac.max_tx_queues)
3314                 return -EINVAL;
3315
3316         if (vfinfo != NULL) {
3317                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3318                         if (vf_idx == vf)
3319                                 continue;
3320                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3321                                 idx++)
3322                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3323                 }
3324         } else
3325                 return -EINVAL;
3326
3327         /* Store tx_rate for this vf. */
3328         for (idx = 0; idx < nb_q_per_pool; idx++) {
3329                 if (((uint64_t)0x1 << idx) & q_msk) {
3330                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3331                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3332                         total_rate += tx_rate;
3333                 }
3334         }
3335
3336         if (total_rate > dev->data->dev_link.link_speed) {
3337                 /*
3338                  * Reset stored TX rate of the VF if it causes exceed
3339                  * link speed.
3340                  */
3341                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3342                 return -EINVAL;
3343         }
3344
3345         /* Set RTTBCNRC of each queue/pool for vf X  */
3346         for (; queue_idx <= queue_end; queue_idx++) {
3347                 if (0x1 & q_msk)
3348                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3349                 q_msk = q_msk >> 1;
3350         }
3351
3352         return 0;
3353 }
3354
3355 static void
3356 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3357                      __attribute__((unused)) uint32_t index,
3358                      __attribute__((unused)) uint32_t pool)
3359 {
3360         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3361         int diag;
3362
3363         /*
3364          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3365          * operation. Trap this case to avoid exhausting the [very limited]
3366          * set of PF resources used to store VF MAC addresses.
3367          */
3368         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3369                 return;
3370         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3371         if (diag == 0)
3372                 return;
3373         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3374 }
3375
3376 static void
3377 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3378 {
3379         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3380         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3381         struct ether_addr *mac_addr;
3382         uint32_t i;
3383         int diag;
3384
3385         /*
3386          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3387          * not support the deletion of a given MAC address.
3388          * Instead, it imposes to delete all MAC addresses, then to add again
3389          * all MAC addresses with the exception of the one to be deleted.
3390          */
3391         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3392
3393         /*
3394          * Add again all MAC addresses, with the exception of the deleted one
3395          * and of the permanent MAC address.
3396          */
3397         for (i = 0, mac_addr = dev->data->mac_addrs;
3398              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3399                 /* Skip the deleted MAC address */
3400                 if (i == index)
3401                         continue;
3402                 /* Skip NULL MAC addresses */
3403                 if (is_zero_ether_addr(mac_addr))
3404                         continue;
3405                 /* Skip the permanent MAC address */
3406                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3407                         continue;
3408                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3409                 if (diag != 0)
3410                         PMD_DRV_LOG(ERR,
3411                                     "Adding again MAC address "
3412                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3413                                     "diag=%d",
3414                                     mac_addr->addr_bytes[0],
3415                                     mac_addr->addr_bytes[1],
3416                                     mac_addr->addr_bytes[2],
3417                                     mac_addr->addr_bytes[3],
3418                                     mac_addr->addr_bytes[4],
3419                                     mac_addr->addr_bytes[5],
3420                                     diag);
3421         }
3422 }
3423
3424 /*
3425  * add syn filter
3426  *
3427  * @param
3428  * dev: Pointer to struct rte_eth_dev.
3429  * filter: ponter to the filter that will be added.
3430  * rx_queue: the queue id the filter assigned to.
3431  *
3432  * @return
3433  *    - On success, zero.
3434  *    - On failure, a negative value.
3435  */
3436 static int
3437 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3438                         struct rte_syn_filter *filter, uint16_t rx_queue)
3439 {
3440         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3441         uint32_t synqf;
3442
3443         if (hw->mac.type != ixgbe_mac_82599EB)
3444                 return -ENOSYS;
3445
3446         if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3447                 return -EINVAL;
3448
3449         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3450
3451         if (synqf & IXGBE_SYN_FILTER_ENABLE)
3452                 return -EINVAL;
3453
3454         synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3455                 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3456
3457         if (filter->hig_pri)
3458                 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3459         else
3460                 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3461
3462         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3463         return 0;
3464 }
3465
3466 /*
3467  * remove syn filter
3468  *
3469  * @param
3470  * dev: Pointer to struct rte_eth_dev.
3471  *
3472  * @return
3473  *    - On success, zero.
3474  *    - On failure, a negative value.
3475  */
3476 static int
3477 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3478 {
3479         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3480         uint32_t synqf;
3481
3482         if (hw->mac.type != ixgbe_mac_82599EB)
3483                 return -ENOSYS;
3484
3485         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3486
3487         synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3488
3489         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3490         return 0;
3491 }
3492
3493 /*
3494  * get the syn filter's info
3495  *
3496  * @param
3497  * dev: Pointer to struct rte_eth_dev.
3498  * filter: ponter to the filter that returns.
3499  * *rx_queue: pointer to the queue id the filter assigned to.
3500  *
3501  * @return
3502  *    - On success, zero.
3503  *    - On failure, a negative value.
3504  */
3505 static int
3506 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3507                         struct rte_syn_filter *filter, uint16_t *rx_queue)
3508
3509 {
3510         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3511         uint32_t synqf;
3512
3513         if (hw->mac.type != ixgbe_mac_82599EB)
3514                 return -ENOSYS;
3515
3516         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3517         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3518                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3519                 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3520                 return 0;
3521         }
3522         return -ENOENT;
3523 }
3524
3525 /*
3526  * add an ethertype filter
3527  *
3528  * @param
3529  * dev: Pointer to struct rte_eth_dev.
3530  * index: the index the filter allocates.
3531  * filter: ponter to the filter that will be added.
3532  * rx_queue: the queue id the filter assigned to.
3533  *
3534  * @return
3535  *    - On success, zero.
3536  *    - On failure, a negative value.
3537  */
3538 static int
3539 ixgbe_add_ethertype_filter(struct rte_eth_dev *dev,
3540                         uint16_t index, struct rte_ethertype_filter *filter,
3541                         uint16_t rx_queue)
3542 {
3543         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3544         uint32_t etqf, etqs = 0;
3545
3546         if (hw->mac.type != ixgbe_mac_82599EB)
3547                 return -ENOSYS;
3548
3549         if (index >= IXGBE_MAX_ETQF_FILTERS ||
3550                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3551                 return -EINVAL;
3552
3553         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3554         if (etqf & IXGBE_ETQF_FILTER_EN)
3555                 return -EINVAL;  /* filter index is in use. */
3556
3557         etqf = 0;
3558         etqf |= IXGBE_ETQF_FILTER_EN;
3559         etqf |= (uint32_t)filter->ethertype;
3560
3561         if (filter->priority_en) {
3562                 if (filter->priority > IXGBE_ETQF_MAX_PRI)
3563                         return -EINVAL;
3564                 etqf |= (uint32_t)((filter->priority << IXGBE_ETQF_SHIFT) & IXGBE_ETQF_UP);
3565                 etqf |= IXGBE_ETQF_UP_EN;
3566         }
3567         etqs |= (uint32_t)((rx_queue << IXGBE_ETQS_RX_QUEUE_SHIFT) & IXGBE_ETQS_RX_QUEUE);
3568         etqs |= IXGBE_ETQS_QUEUE_EN;
3569
3570         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), etqf);
3571         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), etqs);
3572         return 0;
3573 }
3574
3575 /*
3576  * remove an ethertype filter
3577  *
3578  * @param
3579  * dev: Pointer to struct rte_eth_dev.
3580  * index: the index the filter allocates.
3581  *
3582  * @return
3583  *    - On success, zero.
3584  *    - On failure, a negative value.
3585  */
3586 static int
3587 ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
3588                         uint16_t index)
3589 {
3590         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3591
3592         if (hw->mac.type != ixgbe_mac_82599EB)
3593                 return -ENOSYS;
3594
3595         if (index >= IXGBE_MAX_ETQF_FILTERS)
3596                 return -EINVAL;
3597
3598         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), 0);
3599         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), 0);
3600
3601         return 0;
3602 }
3603
3604 /*
3605  * get an ethertype filter
3606  *
3607  * @param
3608  * dev: Pointer to struct rte_eth_dev.
3609  * index: the index the filter allocates.
3610  * filter: ponter to the filter that will be gotten.
3611  * *rx_queue: the ponited of the queue id the filter assigned to.
3612  *
3613  * @return
3614  *    - On success, zero.
3615  *    - On failure, a negative value.
3616  */
3617 static int
3618 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
3619                         uint16_t index, struct rte_ethertype_filter *filter,
3620                         uint16_t *rx_queue)
3621 {
3622         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3623         uint32_t etqf, etqs;
3624
3625         if (hw->mac.type != ixgbe_mac_82599EB)
3626                 return -ENOSYS;
3627
3628         if (index >= IXGBE_MAX_ETQF_FILTERS)
3629                 return -EINVAL;
3630
3631         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3632         etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(index));
3633         if (etqf & IXGBE_ETQF_FILTER_EN) {
3634                 filter->ethertype = etqf & IXGBE_ETQF_ETHERTYPE;
3635                 filter->priority_en = (etqf & IXGBE_ETQF_UP_EN) ? 1 : 0;
3636                 if (filter->priority_en)
3637                         filter->priority = (etqf & IXGBE_ETQF_UP) >> 16;
3638                 *rx_queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> IXGBE_ETQS_RX_QUEUE_SHIFT;
3639                 return 0;
3640         }
3641         return -ENOENT;
3642 }
3643
3644 static inline enum ixgbe_5tuple_protocol
3645 convert_protocol_type(uint8_t protocol_value)
3646 {
3647         if (protocol_value == IPPROTO_TCP)
3648                 return IXGBE_FILTER_PROTOCOL_TCP;
3649         else if (protocol_value == IPPROTO_UDP)
3650                 return IXGBE_FILTER_PROTOCOL_UDP;
3651         else if (protocol_value == IPPROTO_SCTP)
3652                 return IXGBE_FILTER_PROTOCOL_SCTP;
3653         else
3654                 return IXGBE_FILTER_PROTOCOL_NONE;
3655 }
3656
3657 static inline uint8_t
3658 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3659 {
3660         if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3661                 return IPPROTO_TCP;
3662         else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3663                 return IPPROTO_UDP;
3664         else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3665                 return IPPROTO_SCTP;
3666         else
3667                 return 0;
3668 }
3669
3670 /*
3671  * add a 5tuple filter
3672  *
3673  * @param
3674  * dev: Pointer to struct rte_eth_dev.
3675  * index: the index the filter allocates.
3676  * filter: ponter to the filter that will be added.
3677  * rx_queue: the queue id the filter assigned to.
3678  *
3679  * @return
3680  *    - On success, zero.
3681  *    - On failure, a negative value.
3682  */
3683 static int
3684 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3685                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
3686 {
3687         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3688         uint32_t ftqf, sdpqf = 0;
3689         uint32_t l34timir = 0;
3690         uint8_t mask = 0xff;
3691
3692         if (hw->mac.type != ixgbe_mac_82599EB)
3693                 return -ENOSYS;
3694
3695         if (index >= IXGBE_MAX_FTQF_FILTERS ||
3696                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3697                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3698                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3699                 return -EINVAL;  /* filter index is out of range. */
3700
3701         if (filter->tcp_flags) {
3702                 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3703                 return -EINVAL;
3704         }
3705
3706         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3707         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3708                 return -EINVAL;  /* filter index is in use. */
3709
3710         ftqf = 0;
3711         sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3712         sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3713
3714         ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3715                 IXGBE_FTQF_PROTOCOL_MASK);
3716         ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3717                 IXGBE_FTQF_PRIORITY_SHIFT);
3718         if (filter->src_ip_mask == 0) /* 0 means compare. */
3719                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3720         if (filter->dst_ip_mask == 0)
3721                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3722         if (filter->src_port_mask == 0)
3723                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3724         if (filter->dst_port_mask == 0)
3725                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3726         if (filter->protocol_mask == 0)
3727                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3728         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3729         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3730         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3731
3732         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3733         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3734         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3735         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3736
3737         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3738         l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3739         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3740         return 0;
3741 }
3742
3743 /*
3744  * remove a 5tuple filter
3745  *
3746  * @param
3747  * dev: Pointer to struct rte_eth_dev.
3748  * index: the index the filter allocates.
3749  *
3750  * @return
3751  *    - On success, zero.
3752  *    - On failure, a negative value.
3753  */
3754 static int
3755 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3756                         uint16_t index)
3757 {
3758         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3759
3760         if (hw->mac.type != ixgbe_mac_82599EB)
3761                 return -ENOSYS;
3762
3763         if (index >= IXGBE_MAX_FTQF_FILTERS)
3764                 return -EINVAL;  /* filter index is out of range. */
3765
3766         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3767         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3768         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3769         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3770         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3771         return 0;
3772 }
3773
3774 /*
3775  * get a 5tuple filter
3776  *
3777  * @param
3778  * dev: Pointer to struct rte_eth_dev.
3779  * index: the index the filter allocates
3780  * filter: ponter to the filter that returns.
3781  * *rx_queue: pointer of the queue id the filter assigned to.
3782  *
3783  * @return
3784  *    - On success, zero.
3785  *    - On failure, a negative value.
3786  */
3787 static int
3788 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3789                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3790 {
3791         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3792         uint32_t sdpqf, ftqf, l34timir;
3793         uint8_t mask;
3794         enum ixgbe_5tuple_protocol proto;
3795
3796         if (hw->mac.type != ixgbe_mac_82599EB)
3797                 return -ENOSYS;
3798
3799         if (index >= IXGBE_MAX_FTQF_FILTERS)
3800                 return -EINVAL;  /* filter index is out of range. */
3801
3802         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3803         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3804                 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3805                 filter->protocol = revert_protocol_type(proto);
3806                 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3807                                         IXGBE_FTQF_PRIORITY_MASK;
3808                 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3809                                         IXGBE_FTQF_5TUPLE_MASK_MASK);
3810                 filter->src_ip_mask =
3811                         (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3812                 filter->dst_ip_mask =
3813                         (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3814                 filter->src_port_mask =
3815                         (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3816                 filter->dst_port_mask =
3817                         (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3818                 filter->protocol_mask =
3819                         (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3820
3821                 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3822                 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3823                                         IXGBE_SDPQF_DSTPORT_SHIFT;
3824                 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3825                 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3826                 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3827
3828                 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3829                 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3830                                         IXGBE_L34T_IMIR_QUEUE_SHIFT;
3831                 return 0;
3832         }
3833         return -ENOENT;
3834 }
3835
3836 static struct rte_driver rte_ixgbe_driver = {
3837         .type = PMD_PDEV,
3838         .init = rte_ixgbe_pmd_init,
3839 };
3840
3841 static struct rte_driver rte_ixgbevf_driver = {
3842         .type = PMD_PDEV,
3843         .init = rte_ixgbevf_pmd_init,
3844 };
3845
3846 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
3847 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);