lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  96
  97 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  98
  99 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 100                 struct rte_eth_dev *eth_dev);
 101 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 102 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 103 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 104 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 105 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 106 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 107 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 108 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 109 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 110 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 111 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 112                                 int wait_to_complete);
 113 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 114                                 struct rte_eth_stats *stats);
 115 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 116 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 117                                              uint16_t queue_id,
 118                                              uint8_t stat_idx,
 119                                              uint8_t is_rx);
 120 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 121                                 struct rte_eth_dev_info *dev_info);
 122
 123 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 124
 125 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 126                 uint16_t vlan_id, int on);
 127 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 128 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 129                 uint16_t queue, bool on);
 130 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 131                 int on);
 132 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 133 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 134 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 135 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 136 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 137
 138 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 139 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 140 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 141                                struct rte_eth_fc_conf *fc_conf);
 142 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 143                                struct rte_eth_fc_conf *fc_conf);
 144 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 145                 struct rte_eth_pfc_conf *pfc_conf);
 146 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 147                 struct rte_eth_rss_reta *reta_conf);
 148 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 149                 struct rte_eth_rss_reta *reta_conf);
 150 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 154 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 155                 void *param);
 156 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 157 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 158                 uint32_t index, uint32_t pool);
 159 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 160 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 161
 162 /* For Virtual Function support */
 163 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 164                 struct rte_eth_dev *eth_dev);
 165 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 166 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 167 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 168 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 169 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 170 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 171                 struct rte_eth_stats *stats);
 172 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 173 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 174                 uint16_t vlan_id, int on);
 175 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 176                 uint16_t queue, int on);
 177 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 178 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 179
 180 /* For Eth VMDQ APIs support */
 181 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 182                 ether_addr* mac_addr,uint8_t on);
 183 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 184 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 185                 uint16_t rx_mask, uint8_t on);
 186 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 187 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 188 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 189                 uint64_t pool_mask,uint8_t vlan_on);
 190 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 191                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 192                 uint8_t rule_id, uint8_t on);
 193 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 194                 uint8_t rule_id);
 195
 196 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 197                 uint16_t queue_idx, uint16_t tx_rate);
 198 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 199                 uint16_t tx_rate, uint64_t q_msk);
 200
 201 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 202                                  struct ether_addr *mac_addr,
 203                                  uint32_t index, uint32_t pool);
 204 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 205 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
 206                         struct rte_syn_filter *filter, uint16_t rx_queue);
 207 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
 208 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
 209                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 210 static int ixgbe_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 211                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 212 static int ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
 213                         uint16_t index);
 214 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 215                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 216 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 217                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 218 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 219                         uint16_t index);
 220 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 221                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 222
 223 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 224
 225 /*
 226  * Define VF Stats MACRO for Non "cleared on read" register
 227  */
 228 #define UPDATE_VF_STAT(reg, last, cur)                          \
 229 {                                                               \
 230         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 231         cur += latest - last;                                   \
 232         last = latest;                                          \
 233 }
 234
 235 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 236 {                                                                \
 237         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 238         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 239         u64 latest = ((new_msb << 32) | new_lsb);                \
 240         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 241         last = latest;                                           \
 242 }
 243
 244 #define IXGBE_SET_HWSTRIP(h, q) do{\
 245                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 246                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 247                 (h)->bitmap[idx] |= 1 << bit;\
 248         }while(0)
 249
 250 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 251                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 252                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 253                 (h)->bitmap[idx] &= ~(1 << bit);\
 254         }while(0)
 255
 256 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 257                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 258                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 259                 (r) = (h)->bitmap[idx] >> bit & 1;\
 260         }while(0)
 261
 262 /*
 263  * The set of PCI devices this driver supports
 264  */
 265 static struct rte_pci_id pci_id_ixgbe_map[] = {
 266
 267 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 268 #include "rte_pci_dev_ids.h"
 269
 270 { .vendor_id = 0, /* sentinel */ },
 271 };
 272
 273
 274 /*
 275  * The set of PCI devices this driver supports (for 82599 VF)
 276  */
 277 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 278
 279 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 280 #include "rte_pci_dev_ids.h"
 281 { .vendor_id = 0, /* sentinel */ },
 282
 283 };
 284
 285 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 286         .dev_configure        = ixgbe_dev_configure,
 287         .dev_start            = ixgbe_dev_start,
 288         .dev_stop             = ixgbe_dev_stop,
 289         .dev_set_link_up    = ixgbe_dev_set_link_up,
 290         .dev_set_link_down  = ixgbe_dev_set_link_down,
 291         .dev_close            = ixgbe_dev_close,
 292         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 293         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 294         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 295         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 296         .link_update          = ixgbe_dev_link_update,
 297         .stats_get            = ixgbe_dev_stats_get,
 298         .stats_reset          = ixgbe_dev_stats_reset,
 299         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 300         .dev_infos_get        = ixgbe_dev_info_get,
 301         .mtu_set              = ixgbe_dev_mtu_set,
 302         .vlan_filter_set      = ixgbe_vlan_filter_set,
 303         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 304         .vlan_offload_set     = ixgbe_vlan_offload_set,
 305         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 306         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 307         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 308         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 309         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 310         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 311         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 312         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 313         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 314         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 315         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 316         .dev_led_on           = ixgbe_dev_led_on,
 317         .dev_led_off          = ixgbe_dev_led_off,
 318         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 319         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 320         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 321         .mac_addr_add         = ixgbe_add_rar,
 322         .mac_addr_remove      = ixgbe_remove_rar,
 323         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 324         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 325         .mirror_rule_set      = ixgbe_mirror_rule_set,
 326         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 327         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 328         .set_vf_rx            = ixgbe_set_pool_rx,
 329         .set_vf_tx            = ixgbe_set_pool_tx,
 330         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 331         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 332         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 333         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 334         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 335         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 336         .fdir_infos_get               = ixgbe_fdir_info_get,
 337         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 338         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 339         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 340         .fdir_set_masks               = ixgbe_fdir_set_masks,
 341         .reta_update          = ixgbe_dev_rss_reta_update,
 342         .reta_query           = ixgbe_dev_rss_reta_query,
 343 #ifdef RTE_NIC_BYPASS
 344         .bypass_init          = ixgbe_bypass_init,
 345         .bypass_state_set     = ixgbe_bypass_state_store,
 346         .bypass_state_show    = ixgbe_bypass_state_show,
 347         .bypass_event_set     = ixgbe_bypass_event_store,
 348         .bypass_event_show    = ixgbe_bypass_event_show,
 349         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 350         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 351         .bypass_ver_show      = ixgbe_bypass_ver_show,
 352         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 353 #endif /* RTE_NIC_BYPASS */
 354         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 355         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 356         .add_syn_filter          = ixgbe_add_syn_filter,
 357         .remove_syn_filter       = ixgbe_remove_syn_filter,
 358         .get_syn_filter          = ixgbe_get_syn_filter,
 359         .add_ethertype_filter    = ixgbe_add_ethertype_filter,
 360         .remove_ethertype_filter = ixgbe_remove_ethertype_filter,
 361         .get_ethertype_filter    = ixgbe_get_ethertype_filter,
 362         .add_5tuple_filter       = ixgbe_add_5tuple_filter,
 363         .remove_5tuple_filter    = ixgbe_remove_5tuple_filter,
 364         .get_5tuple_filter       = ixgbe_get_5tuple_filter,
 365 };
 366
 367 /*
 368  * dev_ops for virtual function, bare necessities for basic vf
 369  * operation have been implemented
 370  */
 371 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 372
 373         .dev_configure        = ixgbevf_dev_configure,
 374         .dev_start            = ixgbevf_dev_start,
 375         .dev_stop             = ixgbevf_dev_stop,
 376         .link_update          = ixgbe_dev_link_update,
 377         .stats_get            = ixgbevf_dev_stats_get,
 378         .stats_reset          = ixgbevf_dev_stats_reset,
 379         .dev_close            = ixgbevf_dev_close,
 380         .dev_infos_get        = ixgbe_dev_info_get,
 381         .mtu_set              = ixgbevf_dev_set_mtu,
 382         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 383         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 384         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 385         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 386         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 387         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 388         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 389         .mac_addr_add         = ixgbevf_add_mac_addr,
 390         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 391 };
 392
 393 /**
 394  * Atomically reads the link status information from global
 395  * structure rte_eth_dev.
 396  *
 397  * @param dev
 398  *   - Pointer to the structure rte_eth_dev to read from.
 399  *   - Pointer to the buffer to be saved with the link status.
 400  *
 401  * @return
 402  *   - On success, zero.
 403  *   - On failure, negative value.
 404  */
 405 static inline int
 406 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 407                                 struct rte_eth_link *link)
 408 {
 409         struct rte_eth_link *dst = link;
 410         struct rte_eth_link *src = &(dev->data->dev_link);
 411
 412         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 413                                         *(uint64_t *)src) == 0)
 414                 return -1;
 415
 416         return 0;
 417 }
 418
 419 /**
 420  * Atomically writes the link status information into global
 421  * structure rte_eth_dev.
 422  *
 423  * @param dev
 424  *   - Pointer to the structure rte_eth_dev to read from.
 425  *   - Pointer to the buffer to be saved with the link status.
 426  *
 427  * @return
 428  *   - On success, zero.
 429  *   - On failure, negative value.
 430  */
 431 static inline int
 432 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 433                                 struct rte_eth_link *link)
 434 {
 435         struct rte_eth_link *dst = &(dev->data->dev_link);
 436         struct rte_eth_link *src = link;
 437
 438         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 439                                         *(uint64_t *)src) == 0)
 440                 return -1;
 441
 442         return 0;
 443 }
 444
 445 /*
 446  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 447  */
 448 static inline int
 449 ixgbe_is_sfp(struct ixgbe_hw *hw)
 450 {
 451         switch (hw->phy.type) {
 452         case ixgbe_phy_sfp_avago:
 453         case ixgbe_phy_sfp_ftl:
 454         case ixgbe_phy_sfp_intel:
 455         case ixgbe_phy_sfp_unknown:
 456         case ixgbe_phy_sfp_passive_tyco:
 457         case ixgbe_phy_sfp_passive_unknown:
 458                 return 1;
 459         default:
 460                 return 0;
 461         }
 462 }
 463
 464 static inline int32_t
 465 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 466 {
 467         uint32_t ctrl_ext;
 468         int32_t status;
 469
 470         status = ixgbe_reset_hw(hw);
 471
 472         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 473         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 474         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 475         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 476         IXGBE_WRITE_FLUSH(hw);
 477
 478         return status;
 479 }
 480
 481 static inline void
 482 ixgbe_enable_intr(struct rte_eth_dev *dev)
 483 {
 484         struct ixgbe_interrupt *intr =
 485                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 486         struct ixgbe_hw *hw =
 487                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 488
 489         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 490         IXGBE_WRITE_FLUSH(hw);
 491 }
 492
 493 /*
 494  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 495  */
 496 static void
 497 ixgbe_disable_intr(struct ixgbe_hw *hw)
 498 {
 499         PMD_INIT_FUNC_TRACE();
 500
 501         if (hw->mac.type == ixgbe_mac_82598EB) {
 502                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 503         } else {
 504                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 505                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 506                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 507         }
 508         IXGBE_WRITE_FLUSH(hw);
 509 }
 510
 511 /*
 512  * This function resets queue statistics mapping registers.
 513  * From Niantic datasheet, Initialization of Statistics section:
 514  * "...if software requires the queue counters, the RQSMR and TQSM registers
 515  * must be re-programmed following a device reset.
 516  */
 517 static void
 518 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 519 {
 520         uint32_t i;
 521
 522         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 523                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 524                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 525         }
 526 }
 527
 528
 529 static int
 530 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 531                                   uint16_t queue_id,
 532                                   uint8_t stat_idx,
 533                                   uint8_t is_rx)
 534 {
 535 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 536 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 537 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 538
 539         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 540         struct ixgbe_stat_mapping_registers *stat_mappings =
 541                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 542         uint32_t qsmr_mask = 0;
 543         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 544         uint32_t q_map;
 545         uint8_t n, offset;
 546
 547         if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
 548                 return -ENOSYS;
 549
 550         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
 551                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 552                      queue_id, stat_idx);
 553
 554         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 555         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 556                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
 557                 return -EIO;
 558         }
 559         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 560
 561         /* Now clear any previous stat_idx set */
 562         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 563         if (!is_rx)
 564                 stat_mappings->tqsm[n] &= ~clearing_mask;
 565         else
 566                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 567
 568         q_map = (uint32_t)stat_idx;
 569         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 570         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 571         if (!is_rx)
 572                 stat_mappings->tqsm[n] |= qsmr_mask;
 573         else
 574                 stat_mappings->rqsmr[n] |= qsmr_mask;
 575
 576         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
 577                      "%s[%d] = 0x%08x\n",
 578                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 579                      queue_id, stat_idx, is_rx ? "RQSMR" : "TQSM", n,
 580                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 581
 582         /* Now write the mapping in the appropriate register */
 583         if (is_rx) {
 584                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
 585                              stat_mappings->rqsmr[n], n);
 586                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 587         }
 588         else {
 589                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
 590                              stat_mappings->tqsm[n], n);
 591                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 592         }
 593         return 0;
 594 }
 595
 596 static void
 597 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 598 {
 599         struct ixgbe_stat_mapping_registers *stat_mappings =
 600                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 601         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 602         int i;
 603
 604         /* write whatever was in stat mapping table to the NIC */
 605         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 606                 /* rx */
 607                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 608
 609                 /* tx */
 610                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 611         }
 612 }
 613
 614 static void
 615 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 616 {
 617         uint8_t i;
 618         struct ixgbe_dcb_tc_config *tc;
 619         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 620
 621         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 622         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 623         for (i = 0; i < dcb_max_tc; i++) {
 624                 tc = &dcb_config->tc_config[i];
 625                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 626                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 627                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 628                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 629                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 630                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 631                 tc->pfc = ixgbe_dcb_pfc_disabled;
 632         }
 633
 634         /* Initialize default user to priority mapping, UPx->TC0 */
 635         tc = &dcb_config->tc_config[0];
 636         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 637         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 638         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 639                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 640                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 641         }
 642         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 643         dcb_config->pfc_mode_enable = false;
 644         dcb_config->vt_mode = true;
 645         dcb_config->round_robin_enable = false;
 646         /* support all DCB capabilities in 82599 */
 647         dcb_config->support.capabilities = 0xFF;
 648
 649         /*we only support 4 Tcs for X540*/
 650         if (hw->mac.type == ixgbe_mac_X540) {
 651                 dcb_config->num_tcs.pg_tcs = 4;
 652                 dcb_config->num_tcs.pfc_tcs = 4;
 653         }
 654 }
 655
 656 /*
 657  * Ensure that all locks are released before first NVM or PHY access
 658  */
 659 static void
 660 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 661 {
 662         uint16_t mask;
 663
 664         /*
 665          * Phy lock should not fail in this early stage. If this is the case,
 666          * it is due to an improper exit of the application.
 667          * So force the release of the faulty lock. Release of common lock
 668          * is done automatically by swfw_sync function.
 669          */
 670         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 671         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 672                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 673         }
 674         ixgbe_release_swfw_semaphore(hw, mask);
 675
 676         /*
 677          * These ones are more tricky since they are common to all ports; but
 678          * swfw_sync retries last long enough (1s) to be almost sure that if
 679          * lock can not be taken it is due to an improper lock of the
 680          * semaphore.
 681          */
 682         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 683         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 684                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 685         }
 686         ixgbe_release_swfw_semaphore(hw, mask);
 687 }
 688
 689 /*
 690  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 691  * It returns 0 on success.
 692  */
 693 static int
 694 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 695                      struct rte_eth_dev *eth_dev)
 696 {
 697         struct rte_pci_device *pci_dev;
 698         struct ixgbe_hw *hw =
 699                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 700         struct ixgbe_vfta * shadow_vfta =
 701                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 702         struct ixgbe_hwstrip *hwstrip =
 703                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 704         struct ixgbe_dcb_config *dcb_config =
 705                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 706         uint32_t ctrl_ext;
 707         uint16_t csum;
 708         int diag, i;
 709
 710         PMD_INIT_FUNC_TRACE();
 711
 712         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 713         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 714         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 715
 716         /* for secondary processes, we don't initialise any further as primary
 717          * has already done this work. Only check we don't need a different
 718          * RX function */
 719         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 720                 if (eth_dev->data->scattered_rx)
 721                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 722                 return 0;
 723         }
 724         pci_dev = eth_dev->pci_dev;
 725
 726         /* Vendor and Device ID need to be set before init of shared code */
 727         hw->device_id = pci_dev->id.device_id;
 728         hw->vendor_id = pci_dev->id.vendor_id;
 729         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 730 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
 731         hw->allow_unsupported_sfp = 1;
 732 #endif
 733
 734         /* Initialize the shared code (base driver) */
 735 #ifdef RTE_NIC_BYPASS
 736         diag = ixgbe_bypass_init_shared_code(hw);
 737 #else
 738         diag = ixgbe_init_shared_code(hw);
 739 #endif /* RTE_NIC_BYPASS */
 740
 741         if (diag != IXGBE_SUCCESS) {
 742                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 743                 return -EIO;
 744         }
 745
 746         /* pick up the PCI bus settings for reporting later */
 747         ixgbe_get_bus_info(hw);
 748
 749         /* Unlock any pending hardware semaphore */
 750         ixgbe_swfw_lock_reset(hw);
 751
 752         /* Initialize DCB configuration*/
 753         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 754         ixgbe_dcb_init(hw,dcb_config);
 755         /* Get Hardware Flow Control setting */
 756         hw->fc.requested_mode = ixgbe_fc_full;
 757         hw->fc.current_mode = ixgbe_fc_full;
 758         hw->fc.pause_time = IXGBE_FC_PAUSE;
 759         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 760                 hw->fc.low_water[i] = IXGBE_FC_LO;
 761                 hw->fc.high_water[i] = IXGBE_FC_HI;
 762         }
 763         hw->fc.send_xon = 1;
 764
 765         /* Make sure we have a good EEPROM before we read from it */
 766         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 767         if (diag != IXGBE_SUCCESS) {
 768                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 769                 return -EIO;
 770         }
 771
 772 #ifdef RTE_NIC_BYPASS
 773         diag = ixgbe_bypass_init_hw(hw);
 774 #else
 775         diag = ixgbe_init_hw(hw);
 776 #endif /* RTE_NIC_BYPASS */
 777
 778         /*
 779          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 780          * is called too soon after the kernel driver unbinding/binding occurs.
 781          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 782          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 783          * also called. See ixgbe_identify_phy_82599(). The reason for the
 784          * failure is not known, and only occuts when virtualisation features
 785          * are disabled in the bios. A delay of 100ms  was found to be enough by
 786          * trial-and-error, and is doubled to be safe.
 787          */
 788         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 789                 rte_delay_ms(200);
 790                 diag = ixgbe_init_hw(hw);
 791         }
 792
 793         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 794                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 795                     "LOM.  Please be aware there may be issues associated "
 796                     "with your hardware.\n If you are experiencing problems "
 797                     "please contact your Intel or hardware representative "
 798                     "who provided you with this hardware.\n");
 799         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 800                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
 801         if (diag) {
 802                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 803                 return -EIO;
 804         }
 805
 806         /* disable interrupt */
 807         ixgbe_disable_intr(hw);
 808
 809         /* reset mappings for queue statistics hw counters*/
 810         ixgbe_reset_qstat_mappings(hw);
 811
 812         /* Allocate memory for storing MAC addresses */
 813         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 814                         hw->mac.num_rar_entries, 0);
 815         if (eth_dev->data->mac_addrs == NULL) {
 816                 PMD_INIT_LOG(ERR,
 817                         "Failed to allocate %u bytes needed to store "
 818                         "MAC addresses",
 819                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 820                 return -ENOMEM;
 821         }
 822         /* Copy the permanent MAC address */
 823         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 824                         &eth_dev->data->mac_addrs[0]);
 825
 826         /* Allocate memory for storing hash filter MAC addresses */
 827         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 828                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 829         if (eth_dev->data->hash_mac_addrs == NULL) {
 830                 PMD_INIT_LOG(ERR,
 831                         "Failed to allocate %d bytes needed to store MAC addresses",
 832                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 833                 return -ENOMEM;
 834         }
 835
 836         /* initialize the vfta */
 837         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 838
 839         /* initialize the hw strip bitmap*/
 840         memset(hwstrip, 0, sizeof(*hwstrip));
 841
 842         /* initialize PF if max_vfs not zero */
 843         ixgbe_pf_host_init(eth_dev);
 844
 845         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 846         /* let hardware know driver is loaded */
 847         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 848         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 849         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 850         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 851         IXGBE_WRITE_FLUSH(hw);
 852
 853         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 854                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d<n",
 855                              (int) hw->mac.type, (int) hw->phy.type,
 856                              (int) hw->phy.sfp_type);
 857         else
 858                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
 859                              (int) hw->mac.type, (int) hw->phy.type);
 860
 861         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 862                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 863                         pci_dev->id.device_id);
 864
 865         rte_intr_callback_register(&(pci_dev->intr_handle),
 866                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 867
 868         /* enable uio intr after callback register */
 869         rte_intr_enable(&(pci_dev->intr_handle));
 870
 871         /* enable support intr */
 872         ixgbe_enable_intr(eth_dev);
 873
 874         return 0;
 875 }
 876
 877
 878 /*
 879  * Negotiate mailbox API version with the PF.
 880  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 881  * Then we try to negotiate starting with the most recent one.
 882  * If all negotiation attempts fail, then we will proceed with
 883  * the default one (ixgbe_mbox_api_10).
 884  */
 885 static void
 886 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 887 {
 888         int32_t i;
 889
 890         /* start with highest supported, proceed down */
 891         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 892                 ixgbe_mbox_api_11,
 893                 ixgbe_mbox_api_10,
 894         };
 895
 896         for (i = 0;
 897                         i != RTE_DIM(sup_ver) &&
 898                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 899                         i++)
 900                 ;
 901 }
 902
 903 static void
 904 generate_random_mac_addr(struct ether_addr *mac_addr)
 905 {
 906         uint64_t random;
 907
 908         /* Set Organizationally Unique Identifier (OUI) prefix. */
 909         mac_addr->addr_bytes[0] = 0x00;
 910         mac_addr->addr_bytes[1] = 0x09;
 911         mac_addr->addr_bytes[2] = 0xC0;
 912         /* Force indication of locally assigned MAC address. */
 913         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 914         /* Generate the last 3 bytes of the MAC address with a random number. */
 915         random = rte_rand();
 916         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 917 }
 918
 919 /*
 920  * Virtual Function device init
 921  */
 922 static int
 923 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 924                      struct rte_eth_dev *eth_dev)
 925 {
 926         int diag;
 927         uint32_t tc, tcs;
 928         struct rte_pci_device *pci_dev;
 929         struct ixgbe_hw *hw =
 930                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 931         struct ixgbe_vfta * shadow_vfta =
 932                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 933         struct ixgbe_hwstrip *hwstrip =
 934                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 935         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 936
 937         PMD_INIT_FUNC_TRACE();
 938
 939         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 940         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 941         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 942
 943         /* for secondary processes, we don't initialise any further as primary
 944          * has already done this work. Only check we don't need a different
 945          * RX function */
 946         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 947                 if (eth_dev->data->scattered_rx)
 948                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 949                 return 0;
 950         }
 951
 952         pci_dev = eth_dev->pci_dev;
 953
 954         hw->device_id = pci_dev->id.device_id;
 955         hw->vendor_id = pci_dev->id.vendor_id;
 956         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 957
 958         /* initialize the vfta */
 959         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 960
 961         /* initialize the hw strip bitmap*/
 962         memset(hwstrip, 0, sizeof(*hwstrip));
 963
 964         /* Initialize the shared code (base driver) */
 965         diag = ixgbe_init_shared_code(hw);
 966         if (diag != IXGBE_SUCCESS) {
 967                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 968                 return -EIO;
 969         }
 970
 971         /* init_mailbox_params */
 972         hw->mbx.ops.init_params(hw);
 973
 974         /* Disable the interrupts for VF */
 975         ixgbevf_intr_disable(hw);
 976
 977         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
 978         diag = hw->mac.ops.reset_hw(hw);
 979
 980         /*
 981          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
 982          * the underlying PF driver has not assigned a MAC address to the VF.
 983          * In this case, assign a random MAC address.
 984          */
 985         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
 986                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 987                 return (diag);
 988         }
 989
 990         /* negotiate mailbox API version to use with the PF. */
 991         ixgbevf_negotiate_api(hw);
 992
 993         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
 994         ixgbevf_get_queues(hw, &tcs, &tc);
 995
 996         /* Allocate memory for storing MAC addresses */
 997         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
 998                         hw->mac.num_rar_entries, 0);
 999         if (eth_dev->data->mac_addrs == NULL) {
1000                 PMD_INIT_LOG(ERR,
1001                         "Failed to allocate %u bytes needed to store "
1002                         "MAC addresses",
1003                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1004                 return -ENOMEM;
1005         }
1006
1007         /* Generate a random MAC address, if none was assigned by PF. */
1008         if (is_zero_ether_addr(perm_addr)) {
1009                 generate_random_mac_addr(perm_addr);
1010                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1011                 if (diag) {
1012                         rte_free(eth_dev->data->mac_addrs);
1013                         eth_dev->data->mac_addrs = NULL;
1014                         return diag;
1015                 }
1016                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1017                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1018                              "%02x:%02x:%02x:%02x:%02x:%02x",
1019                              perm_addr->addr_bytes[0],
1020                              perm_addr->addr_bytes[1],
1021                              perm_addr->addr_bytes[2],
1022                              perm_addr->addr_bytes[3],
1023                              perm_addr->addr_bytes[4],
1024                              perm_addr->addr_bytes[5]);
1025         }
1026
1027         /* Copy the permanent MAC address */
1028         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1029
1030         /* reset the hardware with the new settings */
1031         diag = hw->mac.ops.start_hw(hw);
1032         switch (diag) {
1033                 case  0:
1034                         break;
1035
1036                 default:
1037                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1038                         return (-EIO);
1039         }
1040
1041         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
1042                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1043                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1044
1045         return 0;
1046 }
1047
1048 static struct eth_driver rte_ixgbe_pmd = {
1049         {
1050                 .name = "rte_ixgbe_pmd",
1051                 .id_table = pci_id_ixgbe_map,
1052                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1053         },
1054         .eth_dev_init = eth_ixgbe_dev_init,
1055         .dev_private_size = sizeof(struct ixgbe_adapter),
1056 };
1057
1058 /*
1059  * virtual function driver struct
1060  */
1061 static struct eth_driver rte_ixgbevf_pmd = {
1062         {
1063                 .name = "rte_ixgbevf_pmd",
1064                 .id_table = pci_id_ixgbevf_map,
1065                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1066         },
1067         .eth_dev_init = eth_ixgbevf_dev_init,
1068         .dev_private_size = sizeof(struct ixgbe_adapter),
1069 };
1070
1071 /*
1072  * Driver initialization routine.
1073  * Invoked once at EAL init time.
1074  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1075  */
1076 static int
1077 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1078 {
1079         PMD_INIT_FUNC_TRACE();
1080
1081         rte_eth_driver_register(&rte_ixgbe_pmd);
1082         return 0;
1083 }
1084
1085 /*
1086  * VF Driver initialization routine.
1087  * Invoked one at EAL init time.
1088  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1089  */
1090 static int
1091 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1092 {
1093         PMD_INIT_FUNC_TRACE();
1094
1095         rte_eth_driver_register(&rte_ixgbevf_pmd);
1096         return (0);
1097 }
1098
1099 static int
1100 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1101 {
1102         struct ixgbe_hw *hw =
1103                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1104         struct ixgbe_vfta * shadow_vfta =
1105                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1106         uint32_t vfta;
1107         uint32_t vid_idx;
1108         uint32_t vid_bit;
1109
1110         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1111         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1112         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1113         if (on)
1114                 vfta |= vid_bit;
1115         else
1116                 vfta &= ~vid_bit;
1117         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1118
1119         /* update local VFTA copy */
1120         shadow_vfta->vfta[vid_idx] = vfta;
1121
1122         return 0;
1123 }
1124
1125 static void
1126 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1127 {
1128         if (on)
1129                 ixgbe_vlan_hw_strip_enable(dev, queue);
1130         else
1131                 ixgbe_vlan_hw_strip_disable(dev, queue);
1132 }
1133
1134 static void
1135 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1136 {
1137         struct ixgbe_hw *hw =
1138                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1139
1140         /* Only the high 16-bits is valid */
1141         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1142 }
1143
1144 void
1145 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1146 {
1147         struct ixgbe_hw *hw =
1148                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1149         uint32_t vlnctrl;
1150
1151         PMD_INIT_FUNC_TRACE();
1152
1153         /* Filter Table Disable */
1154         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1155         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1156
1157         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1158 }
1159
1160 void
1161 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1162 {
1163         struct ixgbe_hw *hw =
1164                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1165         struct ixgbe_vfta * shadow_vfta =
1166                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1167         uint32_t vlnctrl;
1168         uint16_t i;
1169
1170         PMD_INIT_FUNC_TRACE();
1171
1172         /* Filter Table Enable */
1173         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1174         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1175         vlnctrl |= IXGBE_VLNCTRL_VFE;
1176
1177         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1178
1179         /* write whatever is in local vfta copy */
1180         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1181                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1182 }
1183
1184 static void
1185 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1186 {
1187         struct ixgbe_hwstrip *hwstrip =
1188                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1189
1190         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1191                 return;
1192
1193         if (on)
1194                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1195         else
1196                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1197 }
1198
1199 static void
1200 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1201 {
1202         struct ixgbe_hw *hw =
1203                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1204         uint32_t ctrl;
1205
1206         PMD_INIT_FUNC_TRACE();
1207
1208         if (hw->mac.type == ixgbe_mac_82598EB) {
1209                 /* No queue level support */
1210                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1211                 return;
1212         }
1213         else {
1214                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1215                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1216                 ctrl &= ~IXGBE_RXDCTL_VME;
1217                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1218         }
1219         /* record those setting for HW strip per queue */
1220         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1221 }
1222
1223 static void
1224 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1225 {
1226         struct ixgbe_hw *hw =
1227                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1228         uint32_t ctrl;
1229
1230         PMD_INIT_FUNC_TRACE();
1231
1232         if (hw->mac.type == ixgbe_mac_82598EB) {
1233                 /* No queue level supported */
1234                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1235                 return;
1236         }
1237         else {
1238                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1239                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1240                 ctrl |= IXGBE_RXDCTL_VME;
1241                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1242         }
1243         /* record those setting for HW strip per queue */
1244         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1245 }
1246
1247 void
1248 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1249 {
1250         struct ixgbe_hw *hw =
1251                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1252         uint32_t ctrl;
1253         uint16_t i;
1254
1255         PMD_INIT_FUNC_TRACE();
1256
1257         if (hw->mac.type == ixgbe_mac_82598EB) {
1258                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1259                 ctrl &= ~IXGBE_VLNCTRL_VME;
1260                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1261         }
1262         else {
1263                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1264                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1265                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1266                         ctrl &= ~IXGBE_RXDCTL_VME;
1267                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1268
1269                         /* record those setting for HW strip per queue */
1270                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1271                 }
1272         }
1273 }
1274
1275 void
1276 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1277 {
1278         struct ixgbe_hw *hw =
1279                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1280         uint32_t ctrl;
1281         uint16_t i;
1282
1283         PMD_INIT_FUNC_TRACE();
1284
1285         if (hw->mac.type == ixgbe_mac_82598EB) {
1286                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1287                 ctrl |= IXGBE_VLNCTRL_VME;
1288                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1289         }
1290         else {
1291                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1292                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1293                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1294                         ctrl |= IXGBE_RXDCTL_VME;
1295                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1296
1297                         /* record those setting for HW strip per queue */
1298                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1299                 }
1300         }
1301 }
1302
1303 static void
1304 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1305 {
1306         struct ixgbe_hw *hw =
1307                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1308         uint32_t ctrl;
1309
1310         PMD_INIT_FUNC_TRACE();
1311
1312         /* DMATXCTRL: Geric Double VLAN Disable */
1313         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1314         ctrl &= ~IXGBE_DMATXCTL_GDV;
1315         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1316
1317         /* CTRL_EXT: Global Double VLAN Disable */
1318         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1319         ctrl &= ~IXGBE_EXTENDED_VLAN;
1320         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1321
1322 }
1323
1324 static void
1325 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1326 {
1327         struct ixgbe_hw *hw =
1328                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1329         uint32_t ctrl;
1330
1331         PMD_INIT_FUNC_TRACE();
1332
1333         /* DMATXCTRL: Geric Double VLAN Enable */
1334         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1335         ctrl |= IXGBE_DMATXCTL_GDV;
1336         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1337
1338         /* CTRL_EXT: Global Double VLAN Enable */
1339         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1340         ctrl |= IXGBE_EXTENDED_VLAN;
1341         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1342
1343         /*
1344          * VET EXT field in the EXVET register = 0x8100 by default
1345          * So no need to change. Same to VT field of DMATXCTL register
1346          */
1347 }
1348
1349 static void
1350 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1351 {
1352         if(mask & ETH_VLAN_STRIP_MASK){
1353                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1354                         ixgbe_vlan_hw_strip_enable_all(dev);
1355                 else
1356                         ixgbe_vlan_hw_strip_disable_all(dev);
1357         }
1358
1359         if(mask & ETH_VLAN_FILTER_MASK){
1360                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1361                         ixgbe_vlan_hw_filter_enable(dev);
1362                 else
1363                         ixgbe_vlan_hw_filter_disable(dev);
1364         }
1365
1366         if(mask & ETH_VLAN_EXTEND_MASK){
1367                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1368                         ixgbe_vlan_hw_extend_enable(dev);
1369                 else
1370                         ixgbe_vlan_hw_extend_disable(dev);
1371         }
1372 }
1373
1374 static void
1375 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1376 {
1377         struct ixgbe_hw *hw =
1378                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1379         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1380         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1381         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1382         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1383 }
1384
1385 static int
1386 ixgbe_dev_configure(struct rte_eth_dev *dev)
1387 {
1388         struct ixgbe_interrupt *intr =
1389                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1390
1391         PMD_INIT_FUNC_TRACE();
1392
1393         /* set flag to update link status after init */
1394         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1395
1396         return 0;
1397 }
1398
1399 /*
1400  * Configure device link speed and setup link.
1401  * It returns 0 on success.
1402  */
1403 static int
1404 ixgbe_dev_start(struct rte_eth_dev *dev)
1405 {
1406         struct ixgbe_hw *hw =
1407                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1408         struct ixgbe_vf_info *vfinfo =
1409                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1410         int err, link_up = 0, negotiate = 0;
1411         uint32_t speed = 0;
1412         int mask = 0;
1413         int status;
1414         uint16_t vf, idx;
1415
1416         PMD_INIT_FUNC_TRACE();
1417
1418         /* IXGBE devices don't support half duplex */
1419         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1420                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1421                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1422                              dev->data->dev_conf.link_duplex,
1423                              dev->data->port_id);
1424                 return -EINVAL;
1425         }
1426
1427         /* stop adapter */
1428         hw->adapter_stopped = FALSE;
1429         ixgbe_stop_adapter(hw);
1430
1431         /* reinitialize adapter
1432          * this calls reset and start */
1433         status = ixgbe_pf_reset_hw(hw);
1434         if (status != 0)
1435                 return -1;
1436         hw->mac.ops.start_hw(hw);
1437
1438         /* configure PF module if SRIOV enabled */
1439         ixgbe_pf_host_configure(dev);
1440
1441         /* initialize transmission unit */
1442         ixgbe_dev_tx_init(dev);
1443
1444         /* This can fail when allocating mbufs for descriptor rings */
1445         err = ixgbe_dev_rx_init(dev);
1446         if (err) {
1447                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1448                 goto error;
1449         }
1450
1451         ixgbe_dev_rxtx_start(dev);
1452
1453         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1454                 err = hw->mac.ops.setup_sfp(hw);
1455                 if (err)
1456                         goto error;
1457         }
1458
1459         /* Turn on the laser */
1460         ixgbe_enable_tx_laser(hw);
1461
1462         /* Skip link setup if loopback mode is enabled for 82599. */
1463         if (hw->mac.type == ixgbe_mac_82599EB &&
1464                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1465                 goto skip_link_setup;
1466
1467         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1468         if (err)
1469                 goto error;
1470         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1471         if (err)
1472                 goto error;
1473
1474         switch(dev->data->dev_conf.link_speed) {
1475         case ETH_LINK_SPEED_AUTONEG:
1476                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1477                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1478                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1479                 break;
1480         case ETH_LINK_SPEED_100:
1481                 /*
1482                  * Invalid for 82598 but error will be detected by
1483                  * ixgbe_setup_link()
1484                  */
1485                 speed = IXGBE_LINK_SPEED_100_FULL;
1486                 break;
1487         case ETH_LINK_SPEED_1000:
1488                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1489                 break;
1490         case ETH_LINK_SPEED_10000:
1491                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1492                 break;
1493         default:
1494                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1495                              dev->data->dev_conf.link_speed,
1496                              dev->data->port_id);
1497                 goto error;
1498         }
1499
1500         err = ixgbe_setup_link(hw, speed, link_up);
1501         if (err)
1502                 goto error;
1503
1504 skip_link_setup:
1505
1506         /* check if lsc interrupt is enabled */
1507         if (dev->data->dev_conf.intr_conf.lsc != 0)
1508                 ixgbe_dev_lsc_interrupt_setup(dev);
1509
1510         /* resume enabled intr since hw reset */
1511         ixgbe_enable_intr(dev);
1512
1513         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1514                 ETH_VLAN_EXTEND_MASK;
1515         ixgbe_vlan_offload_set(dev, mask);
1516
1517         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1518                 /* Enable vlan filtering for VMDq */
1519                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1520         }
1521
1522         /* Configure DCB hw */
1523         ixgbe_configure_dcb(dev);
1524
1525         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1526                 err = ixgbe_fdir_configure(dev);
1527                 if (err)
1528                         goto error;
1529         }
1530
1531         /* Restore vf rate limit */
1532         if (vfinfo != NULL) {
1533                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1534                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1535                                 if (vfinfo[vf].tx_rate[idx] != 0)
1536                                         ixgbe_set_vf_rate_limit(dev, vf,
1537                                                 vfinfo[vf].tx_rate[idx],
1538                                                 1 << idx);
1539         }
1540
1541         ixgbe_restore_statistics_mapping(dev);
1542
1543         return (0);
1544
1545 error:
1546         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1547         ixgbe_dev_clear_queues(dev);
1548         return -EIO;
1549 }
1550
1551 /*
1552  * Stop device: disable rx and tx functions to allow for reconfiguring.
1553  */
1554 static void
1555 ixgbe_dev_stop(struct rte_eth_dev *dev)
1556 {
1557         struct rte_eth_link link;
1558         struct ixgbe_hw *hw =
1559                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1560         struct ixgbe_vf_info *vfinfo =
1561                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1562         int vf;
1563
1564         PMD_INIT_FUNC_TRACE();
1565
1566         /* disable interrupts */
1567         ixgbe_disable_intr(hw);
1568
1569         /* reset the NIC */
1570         ixgbe_pf_reset_hw(hw);
1571         hw->adapter_stopped = FALSE;
1572
1573         /* stop adapter */
1574         ixgbe_stop_adapter(hw);
1575
1576         for (vf = 0; vfinfo != NULL &&
1577                      vf < dev->pci_dev->max_vfs; vf++)
1578                 vfinfo[vf].clear_to_send = false;
1579
1580         /* Turn off the laser */
1581         ixgbe_disable_tx_laser(hw);
1582
1583         ixgbe_dev_clear_queues(dev);
1584
1585         /* Clear recorded link status */
1586         memset(&link, 0, sizeof(link));
1587         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1588 }
1589
1590 /*
1591  * Set device link up: enable tx laser.
1592  */
1593 static int
1594 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1595 {
1596         struct ixgbe_hw *hw =
1597                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598         if (hw->mac.type == ixgbe_mac_82599EB) {
1599 #ifdef RTE_NIC_BYPASS
1600                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1601                         /* Not suported in bypass mode */
1602                         PMD_INIT_LOG(ERR, "\nSet link up is not supported "
1603                                      "by device id 0x%x\n", hw->device_id);
1604                         return -ENOTSUP;
1605                 }
1606 #endif
1607                 /* Turn on the laser */
1608                 ixgbe_enable_tx_laser(hw);
1609                 return 0;
1610         }
1611
1612         PMD_INIT_LOG(ERR, "\nSet link up is not supported by device id 0x%x\n",
1613                      hw->device_id);
1614         return -ENOTSUP;
1615 }
1616
1617 /*
1618  * Set device link down: disable tx laser.
1619  */
1620 static int
1621 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1622 {
1623         struct ixgbe_hw *hw =
1624                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1625         if (hw->mac.type == ixgbe_mac_82599EB) {
1626 #ifdef RTE_NIC_BYPASS
1627                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1628                         /* Not suported in bypass mode */
1629                         PMD_INIT_LOG(ERR, "\nSet link down is not supported "
1630                                      "by device id 0x%x\n", hw->device_id);
1631                         return -ENOTSUP;
1632                 }
1633 #endif
1634                 /* Turn off the laser */
1635                 ixgbe_disable_tx_laser(hw);
1636                 return 0;
1637         }
1638
1639         PMD_INIT_LOG(ERR, "\nSet link down is not supported by device id 0x%x\n",
1640                      hw->device_id);
1641         return -ENOTSUP;
1642 }
1643
1644 /*
1645  * Reest and stop device.
1646  */
1647 static void
1648 ixgbe_dev_close(struct rte_eth_dev *dev)
1649 {
1650         struct ixgbe_hw *hw =
1651                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1652
1653         PMD_INIT_FUNC_TRACE();
1654
1655         ixgbe_pf_reset_hw(hw);
1656
1657         ixgbe_dev_stop(dev);
1658         hw->adapter_stopped = 1;
1659
1660         ixgbe_disable_pcie_master(hw);
1661
1662         /* reprogram the RAR[0] in case user changed it. */
1663         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1664 }
1665
1666 /*
1667  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1668  */
1669 static void
1670 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1671 {
1672         struct ixgbe_hw *hw =
1673                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674         struct ixgbe_hw_stats *hw_stats =
1675                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1676         uint32_t bprc, lxon, lxoff, total;
1677         uint64_t total_missed_rx, total_qbrc, total_qprc;
1678         unsigned i;
1679
1680         total_missed_rx = 0;
1681         total_qbrc = 0;
1682         total_qprc = 0;
1683
1684         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1685         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1686         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1687         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1688
1689         for (i = 0; i < 8; i++) {
1690                 uint32_t mp;
1691                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1692                 /* global total per queue */
1693                 hw_stats->mpc[i] += mp;
1694                 /* Running comprehensive total for stats display */
1695                 total_missed_rx += hw_stats->mpc[i];
1696                 if (hw->mac.type == ixgbe_mac_82598EB)
1697                         hw_stats->rnbc[i] +=
1698                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1699                 hw_stats->pxontxc[i] +=
1700                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1701                 hw_stats->pxonrxc[i] +=
1702                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1703                 hw_stats->pxofftxc[i] +=
1704                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1705                 hw_stats->pxoffrxc[i] +=
1706                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1707                 hw_stats->pxon2offc[i] +=
1708                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1709         }
1710         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1711                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1712                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1713                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1714                 hw_stats->qbrc[i] +=
1715                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1716                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1717                 hw_stats->qbtc[i] +=
1718                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1719                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1720
1721                 total_qprc += hw_stats->qprc[i];
1722                 total_qbrc += hw_stats->qbrc[i];
1723         }
1724         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1725         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1726         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1727
1728         /* Note that gprc counts missed packets */
1729         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1730
1731         if (hw->mac.type != ixgbe_mac_82598EB) {
1732                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1733                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1734                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1735                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1736                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1737                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1738                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1739                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1740         } else {
1741                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1742                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1743                 /* 82598 only has a counter in the high register */
1744                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1745                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1746                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1747         }
1748
1749         /*
1750          * Workaround: mprc hardware is incorrectly counting
1751          * broadcasts, so for now we subtract those.
1752          */
1753         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1754         hw_stats->bprc += bprc;
1755         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1756         if (hw->mac.type == ixgbe_mac_82598EB)
1757                 hw_stats->mprc -= bprc;
1758
1759         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1760         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1761         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1762         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1763         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1764         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1765
1766         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1767         hw_stats->lxontxc += lxon;
1768         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1769         hw_stats->lxofftxc += lxoff;
1770         total = lxon + lxoff;
1771
1772         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1773         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1774         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1775         hw_stats->gptc -= total;
1776         hw_stats->mptc -= total;
1777         hw_stats->ptc64 -= total;
1778         hw_stats->gotc -= total * ETHER_MIN_LEN;
1779
1780         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1781         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1782         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1783         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1784         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1785         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1786         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1787         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1788         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1789         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1790         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1791         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1792         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1793         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1794         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1795         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1796         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1797         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1798         /* Only read FCOE on 82599 */
1799         if (hw->mac.type != ixgbe_mac_82598EB) {
1800                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1801                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1802                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1803                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1804                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1805         }
1806
1807         if (stats == NULL)
1808                 return;
1809
1810         /* Fill out the rte_eth_stats statistics structure */
1811         stats->ipackets = total_qprc;
1812         stats->ibytes = total_qbrc;
1813         stats->opackets = hw_stats->gptc;
1814         stats->obytes = hw_stats->gotc;
1815         stats->imcasts = hw_stats->mprc;
1816
1817         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1818                 stats->q_ipackets[i] = hw_stats->qprc[i];
1819                 stats->q_opackets[i] = hw_stats->qptc[i];
1820                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1821                 stats->q_obytes[i] = hw_stats->qbtc[i];
1822                 stats->q_errors[i] = hw_stats->qprdc[i];
1823         }
1824
1825         /* Rx Errors */
1826         stats->ibadcrc  = hw_stats->crcerrs;
1827         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1828         stats->imissed  = total_missed_rx;
1829         stats->ierrors  = stats->ibadcrc +
1830                           stats->ibadlen +
1831                           stats->imissed +
1832                           hw_stats->illerrc + hw_stats->errbc;
1833
1834         /* Tx Errors */
1835         stats->oerrors  = 0;
1836
1837         /* XON/XOFF pause frames */
1838         stats->tx_pause_xon  = hw_stats->lxontxc;
1839         stats->rx_pause_xon  = hw_stats->lxonrxc;
1840         stats->tx_pause_xoff = hw_stats->lxofftxc;
1841         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1842
1843         /* Flow Director Stats registers */
1844         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1845         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1846         stats->fdirmatch = hw_stats->fdirmatch;
1847         stats->fdirmiss = hw_stats->fdirmiss;
1848 }
1849
1850 static void
1851 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1852 {
1853         struct ixgbe_hw_stats *stats =
1854                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1855
1856         /* HW registers are cleared on read */
1857         ixgbe_dev_stats_get(dev, NULL);
1858
1859         /* Reset software totals */
1860         memset(stats, 0, sizeof(*stats));
1861 }
1862
1863 static void
1864 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1865 {
1866         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1867         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1868                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1869
1870         /* Good Rx packet, include VF loopback */
1871         UPDATE_VF_STAT(IXGBE_VFGPRC,
1872             hw_stats->last_vfgprc, hw_stats->vfgprc);
1873
1874         /* Good Rx octets, include VF loopback */
1875         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1876             hw_stats->last_vfgorc, hw_stats->vfgorc);
1877
1878         /* Good Tx packet, include VF loopback */
1879         UPDATE_VF_STAT(IXGBE_VFGPTC,
1880             hw_stats->last_vfgptc, hw_stats->vfgptc);
1881
1882         /* Good Tx octets, include VF loopback */
1883         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1884             hw_stats->last_vfgotc, hw_stats->vfgotc);
1885
1886         /* Rx Multicst Packet */
1887         UPDATE_VF_STAT(IXGBE_VFMPRC,
1888             hw_stats->last_vfmprc, hw_stats->vfmprc);
1889
1890         if (stats == NULL)
1891                 return;
1892
1893         memset(stats, 0, sizeof(*stats));
1894         stats->ipackets = hw_stats->vfgprc;
1895         stats->ibytes = hw_stats->vfgorc;
1896         stats->opackets = hw_stats->vfgptc;
1897         stats->obytes = hw_stats->vfgotc;
1898         stats->imcasts = hw_stats->vfmprc;
1899 }
1900
1901 static void
1902 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1903 {
1904         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1905                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1906
1907         /* Sync HW register to the last stats */
1908         ixgbevf_dev_stats_get(dev, NULL);
1909
1910         /* reset HW current stats*/
1911         hw_stats->vfgprc = 0;
1912         hw_stats->vfgorc = 0;
1913         hw_stats->vfgptc = 0;
1914         hw_stats->vfgotc = 0;
1915         hw_stats->vfmprc = 0;
1916
1917 }
1918
1919 static void
1920 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1921 {
1922         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1923
1924         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1925         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1926         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1927         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1928         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1929         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1930         dev_info->max_vfs = dev->pci_dev->max_vfs;
1931         if (hw->mac.type == ixgbe_mac_82598EB)
1932                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1933         else
1934                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1935         dev_info->rx_offload_capa =
1936                 DEV_RX_OFFLOAD_VLAN_STRIP |
1937                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1938                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1939                 DEV_RX_OFFLOAD_TCP_CKSUM;
1940         dev_info->tx_offload_capa =
1941                 DEV_TX_OFFLOAD_VLAN_INSERT |
1942                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1943                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1944                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1945                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1946 }
1947
1948 /* return 0 means link status changed, -1 means not changed */
1949 static int
1950 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1951 {
1952         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953         struct rte_eth_link link, old;
1954         ixgbe_link_speed link_speed;
1955         int link_up;
1956         int diag;
1957
1958         link.link_status = 0;
1959         link.link_speed = 0;
1960         link.link_duplex = 0;
1961         memset(&old, 0, sizeof(old));
1962         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1963
1964         /* check if it needs to wait to complete, if lsc interrupt is enabled */
1965         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1966                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1967         else
1968                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1969         if (diag != 0) {
1970                 link.link_speed = ETH_LINK_SPEED_100;
1971                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1972                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1973                 if (link.link_status == old.link_status)
1974                         return -1;
1975                 return 0;
1976         }
1977
1978         if (link_up == 0) {
1979                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1980                 if (link.link_status == old.link_status)
1981                         return -1;
1982                 return 0;
1983         }
1984         link.link_status = 1;
1985         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1986
1987         switch (link_speed) {
1988         default:
1989         case IXGBE_LINK_SPEED_UNKNOWN:
1990                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1991                 link.link_speed = ETH_LINK_SPEED_100;
1992                 break;
1993
1994         case IXGBE_LINK_SPEED_100_FULL:
1995                 link.link_speed = ETH_LINK_SPEED_100;
1996                 break;
1997
1998         case IXGBE_LINK_SPEED_1GB_FULL:
1999                 link.link_speed = ETH_LINK_SPEED_1000;
2000                 break;
2001
2002         case IXGBE_LINK_SPEED_10GB_FULL:
2003                 link.link_speed = ETH_LINK_SPEED_10000;
2004                 break;
2005         }
2006         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2007
2008         if (link.link_status == old.link_status)
2009                 return -1;
2010
2011         return 0;
2012 }
2013
2014 static void
2015 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2016 {
2017         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2018         uint32_t fctrl;
2019
2020         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2021         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2022         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2023 }
2024
2025 static void
2026 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2027 {
2028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029         uint32_t fctrl;
2030
2031         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2032         fctrl &= (~IXGBE_FCTRL_UPE);
2033         if (dev->data->all_multicast == 1)
2034                 fctrl |= IXGBE_FCTRL_MPE;
2035         else
2036                 fctrl &= (~IXGBE_FCTRL_MPE);
2037         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2038 }
2039
2040 static void
2041 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2042 {
2043         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2044         uint32_t fctrl;
2045
2046         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2047         fctrl |= IXGBE_FCTRL_MPE;
2048         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2049 }
2050
2051 static void
2052 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2053 {
2054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055         uint32_t fctrl;
2056
2057         if (dev->data->promiscuous == 1)
2058                 return; /* must remain in all_multicast mode */
2059
2060         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2061         fctrl &= (~IXGBE_FCTRL_MPE);
2062         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2063 }
2064
2065 /**
2066  * It clears the interrupt causes and enables the interrupt.
2067  * It will be called once only during nic initialized.
2068  *
2069  * @param dev
2070  *  Pointer to struct rte_eth_dev.
2071  *
2072  * @return
2073  *  - On success, zero.
2074  *  - On failure, a negative value.
2075  */
2076 static int
2077 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2078 {
2079         struct ixgbe_interrupt *intr =
2080                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2081
2082         ixgbe_dev_link_status_print(dev);
2083         intr->mask |= IXGBE_EICR_LSC;
2084
2085         return 0;
2086 }
2087
2088 /*
2089  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2090  *
2091  * @param dev
2092  *  Pointer to struct rte_eth_dev.
2093  *
2094  * @return
2095  *  - On success, zero.
2096  *  - On failure, a negative value.
2097  */
2098 static int
2099 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2100 {
2101         uint32_t eicr;
2102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103         struct ixgbe_interrupt *intr =
2104                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2105
2106         /* clear all cause mask */
2107         ixgbe_disable_intr(hw);
2108
2109         /* read-on-clear nic registers here */
2110         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2111         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2112
2113         intr->flags = 0;
2114         if (eicr & IXGBE_EICR_LSC) {
2115                 /* set flag for async link update */
2116                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2117         }
2118
2119         if (eicr & IXGBE_EICR_MAILBOX)
2120                 intr->flags |= IXGBE_FLAG_MAILBOX;
2121
2122         return 0;
2123 }
2124
2125 /**
2126  * It gets and then prints the link status.
2127  *
2128  * @param dev
2129  *  Pointer to struct rte_eth_dev.
2130  *
2131  * @return
2132  *  - On success, zero.
2133  *  - On failure, a negative value.
2134  */
2135 static void
2136 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2137 {
2138         struct rte_eth_link link;
2139
2140         memset(&link, 0, sizeof(link));
2141         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2142         if (link.link_status) {
2143                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2144                                         (int)(dev->data->port_id),
2145                                         (unsigned)link.link_speed,
2146                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2147                                         "full-duplex" : "half-duplex");
2148         } else {
2149                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2150                                 (int)(dev->data->port_id));
2151         }
2152         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2153                                 dev->pci_dev->addr.domain,
2154                                 dev->pci_dev->addr.bus,
2155                                 dev->pci_dev->addr.devid,
2156                                 dev->pci_dev->addr.function);
2157 }
2158
2159 /*
2160  * It executes link_update after knowing an interrupt occurred.
2161  *
2162  * @param dev
2163  *  Pointer to struct rte_eth_dev.
2164  *
2165  * @return
2166  *  - On success, zero.
2167  *  - On failure, a negative value.
2168  */
2169 static int
2170 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2171 {
2172         struct ixgbe_interrupt *intr =
2173                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2174         int64_t timeout;
2175         struct rte_eth_link link;
2176         int intr_enable_delay = false;
2177
2178         PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
2179
2180         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2181                 ixgbe_pf_mbx_process(dev);
2182                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2183         }
2184
2185         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2186                 /* get the link status before link update, for predicting later */
2187                 memset(&link, 0, sizeof(link));
2188                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2189
2190                 ixgbe_dev_link_update(dev, 0);
2191
2192                 /* likely to up */
2193                 if (!link.link_status)
2194                         /* handle it 1 sec later, wait it being stable */
2195                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2196                 /* likely to down */
2197                 else
2198                         /* handle it 4 sec later, wait it being stable */
2199                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2200
2201                 ixgbe_dev_link_status_print(dev);
2202
2203                 intr_enable_delay = true;
2204         }
2205
2206         if (intr_enable_delay) {
2207                 if (rte_eal_alarm_set(timeout * 1000,
2208                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2209                         PMD_DRV_LOG(ERR, "Error setting alarm");
2210         } else {
2211                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2212                 ixgbe_enable_intr(dev);
2213                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2214         }
2215
2216
2217         return 0;
2218 }
2219
2220 /**
2221  * Interrupt handler which shall be registered for alarm callback for delayed
2222  * handling specific interrupt to wait for the stable nic state. As the
2223  * NIC interrupt state is not stable for ixgbe after link is just down,
2224  * it needs to wait 4 seconds to get the stable status.
2225  *
2226  * @param handle
2227  *  Pointer to interrupt handle.
2228  * @param param
2229  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2230  *
2231  * @return
2232  *  void
2233  */
2234 static void
2235 ixgbe_dev_interrupt_delayed_handler(void *param)
2236 {
2237         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2238         struct ixgbe_interrupt *intr =
2239                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2240         struct ixgbe_hw *hw =
2241                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242         uint32_t eicr;
2243
2244         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2245         if (eicr & IXGBE_EICR_MAILBOX)
2246                 ixgbe_pf_mbx_process(dev);
2247
2248         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2249                 ixgbe_dev_link_update(dev, 0);
2250                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2251                 ixgbe_dev_link_status_print(dev);
2252                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2253         }
2254
2255         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
2256         ixgbe_enable_intr(dev);
2257         rte_intr_enable(&(dev->pci_dev->intr_handle));
2258 }
2259
2260 /**
2261  * Interrupt handler triggered by NIC  for handling
2262  * specific interrupt.
2263  *
2264  * @param handle
2265  *  Pointer to interrupt handle.
2266  * @param param
2267  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2268  *
2269  * @return
2270  *  void
2271  */
2272 static void
2273 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2274                                                         void *param)
2275 {
2276         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2277         ixgbe_dev_interrupt_get_status(dev);
2278         ixgbe_dev_interrupt_action(dev);
2279 }
2280
2281 static int
2282 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2283 {
2284         struct ixgbe_hw *hw;
2285
2286         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2288 }
2289
2290 static int
2291 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2292 {
2293         struct ixgbe_hw *hw;
2294
2295         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2297 }
2298
2299 static int
2300 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2301 {
2302         struct ixgbe_hw *hw;
2303         uint32_t mflcn_reg;
2304         uint32_t fccfg_reg;
2305         int rx_pause;
2306         int tx_pause;
2307
2308         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2309
2310         fc_conf->pause_time = hw->fc.pause_time;
2311         fc_conf->high_water = hw->fc.high_water[0];
2312         fc_conf->low_water = hw->fc.low_water[0];
2313         fc_conf->send_xon = hw->fc.send_xon;
2314         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2315
2316         /*
2317          * Return rx_pause status according to actual setting of
2318          * MFLCN register.
2319          */
2320         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2321         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2322                 rx_pause = 1;
2323         else
2324                 rx_pause = 0;
2325
2326         /*
2327          * Return tx_pause status according to actual setting of
2328          * FCCFG register.
2329          */
2330         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2331         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2332                 tx_pause = 1;
2333         else
2334                 tx_pause = 0;
2335
2336         if (rx_pause && tx_pause)
2337                 fc_conf->mode = RTE_FC_FULL;
2338         else if (rx_pause)
2339                 fc_conf->mode = RTE_FC_RX_PAUSE;
2340         else if (tx_pause)
2341                 fc_conf->mode = RTE_FC_TX_PAUSE;
2342         else
2343                 fc_conf->mode = RTE_FC_NONE;
2344
2345         return 0;
2346 }
2347
2348 static int
2349 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2350 {
2351         struct ixgbe_hw *hw;
2352         int err;
2353         uint32_t rx_buf_size;
2354         uint32_t max_high_water;
2355         uint32_t mflcn;
2356         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2357                 ixgbe_fc_none,
2358                 ixgbe_fc_rx_pause,
2359                 ixgbe_fc_tx_pause,
2360                 ixgbe_fc_full
2361         };
2362
2363         PMD_INIT_FUNC_TRACE();
2364
2365         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2366         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2367                 return -ENOTSUP;
2368         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2369         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2370
2371         /*
2372          * At least reserve one Ethernet frame for watermark
2373          * high_water/low_water in kilo bytes for ixgbe
2374          */
2375         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2376         if ((fc_conf->high_water > max_high_water) ||
2377                 (fc_conf->high_water < fc_conf->low_water)) {
2378                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2379                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2380                 return (-EINVAL);
2381         }
2382
2383         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2384         hw->fc.pause_time     = fc_conf->pause_time;
2385         hw->fc.high_water[0]  = fc_conf->high_water;
2386         hw->fc.low_water[0]   = fc_conf->low_water;
2387         hw->fc.send_xon       = fc_conf->send_xon;
2388
2389         err = ixgbe_fc_enable(hw);
2390
2391         /* Not negotiated is not an error case */
2392         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2393
2394                 /* check if we want to forward MAC frames - driver doesn't have native
2395                  * capability to do that, so we'll write the registers ourselves */
2396
2397                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2398
2399                 /* set or clear MFLCN.PMCF bit depending on configuration */
2400                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2401                         mflcn |= IXGBE_MFLCN_PMCF;
2402                 else
2403                         mflcn &= ~IXGBE_MFLCN_PMCF;
2404
2405                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2406                 IXGBE_WRITE_FLUSH(hw);
2407
2408                 return 0;
2409         }
2410
2411         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2412         return -EIO;
2413 }
2414
2415 /**
2416  *  ixgbe_pfc_enable_generic - Enable flow control
2417  *  @hw: pointer to hardware structure
2418  *  @tc_num: traffic class number
2419  *  Enable flow control according to the current settings.
2420  */
2421 static int
2422 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2423 {
2424         int ret_val = 0;
2425         uint32_t mflcn_reg, fccfg_reg;
2426         uint32_t reg;
2427         uint32_t fcrtl, fcrth;
2428         uint8_t i;
2429         uint8_t nb_rx_en;
2430
2431         /* Validate the water mark configuration */
2432         if (!hw->fc.pause_time) {
2433                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2434                 goto out;
2435         }
2436
2437         /* Low water mark of zero causes XOFF floods */
2438         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2439                  /* High/Low water can not be 0 */
2440                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2441                         PMD_INIT_LOG(ERR, "Invalid water mark configuration\n");
2442                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2443                         goto out;
2444                 }
2445
2446                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2447                         PMD_INIT_LOG(ERR, "Invalid water mark configuration\n");
2448                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2449                         goto out;
2450                 }
2451         }
2452         /* Negotiate the fc mode to use */
2453         ixgbe_fc_autoneg(hw);
2454
2455         /* Disable any previous flow control settings */
2456         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2457         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2458
2459         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2460         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2461
2462         switch (hw->fc.current_mode) {
2463         case ixgbe_fc_none:
2464                 /*
2465                  * If the count of enabled RX Priority Flow control >1,
2466                  * and the TX pause can not be disabled
2467                  */
2468                 nb_rx_en = 0;
2469                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2470                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2471                         if (reg & IXGBE_FCRTH_FCEN)
2472                                 nb_rx_en++;
2473                 }
2474                 if (nb_rx_en > 1)
2475                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2476                 break;
2477         case ixgbe_fc_rx_pause:
2478                 /*
2479                  * Rx Flow control is enabled and Tx Flow control is
2480                  * disabled by software override. Since there really
2481                  * isn't a way to advertise that we are capable of RX
2482                  * Pause ONLY, we will advertise that we support both
2483                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2484                  * disable the adapter's ability to send PAUSE frames.
2485                  */
2486                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2487                 /*
2488                  * If the count of enabled RX Priority Flow control >1,
2489                  * and the TX pause can not be disabled
2490                  */
2491                 nb_rx_en = 0;
2492                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2493                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2494                         if (reg & IXGBE_FCRTH_FCEN)
2495                                 nb_rx_en++;
2496                 }
2497                 if (nb_rx_en > 1)
2498                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2499                 break;
2500         case ixgbe_fc_tx_pause:
2501                 /*
2502                  * Tx Flow control is enabled, and Rx Flow control is
2503                  * disabled by software override.
2504                  */
2505                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2506                 break;
2507         case ixgbe_fc_full:
2508                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2509                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2510                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2511                 break;
2512         default:
2513                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2514                 ret_val = IXGBE_ERR_CONFIG;
2515                 goto out;
2516                 break;
2517         }
2518
2519         /* Set 802.3x based flow control settings. */
2520         mflcn_reg |= IXGBE_MFLCN_DPF;
2521         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2522         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2523
2524         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2525         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2526                 hw->fc.high_water[tc_num]) {
2527                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2528                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2529                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2530         } else {
2531                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2532                 /*
2533                  * In order to prevent Tx hangs when the internal Tx
2534                  * switch is enabled we must set the high water mark
2535                  * to the maximum FCRTH value.  This allows the Tx
2536                  * switch to function even under heavy Rx workloads.
2537                  */
2538                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2539         }
2540         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2541
2542         /* Configure pause time (2 TCs per register) */
2543         reg = hw->fc.pause_time * 0x00010001;
2544         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2545                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2546
2547         /* Configure flow control refresh threshold value */
2548         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2549
2550 out:
2551         return ret_val;
2552 }
2553
2554 static int
2555 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2556 {
2557         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2558         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2559
2560         if(hw->mac.type != ixgbe_mac_82598EB) {
2561                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2562         }
2563         return ret_val;
2564 }
2565
2566 static int
2567 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2568 {
2569         int err;
2570         uint32_t rx_buf_size;
2571         uint32_t max_high_water;
2572         uint8_t tc_num;
2573         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2574         struct ixgbe_hw *hw =
2575                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2576         struct ixgbe_dcb_config *dcb_config =
2577                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2578
2579         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2580                 ixgbe_fc_none,
2581                 ixgbe_fc_rx_pause,
2582                 ixgbe_fc_tx_pause,
2583                 ixgbe_fc_full
2584         };
2585
2586         PMD_INIT_FUNC_TRACE();
2587
2588         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2589         tc_num = map[pfc_conf->priority];
2590         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2591         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2592         /*
2593          * At least reserve one Ethernet frame for watermark
2594          * high_water/low_water in kilo bytes for ixgbe
2595          */
2596         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2597         if ((pfc_conf->fc.high_water > max_high_water) ||
2598             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2599                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2600                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2601                 return (-EINVAL);
2602         }
2603
2604         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2605         hw->fc.pause_time = pfc_conf->fc.pause_time;
2606         hw->fc.send_xon = pfc_conf->fc.send_xon;
2607         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2608         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2609
2610         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2611
2612         /* Not negotiated is not an error case */
2613         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2614                 return 0;
2615
2616         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2617         return -EIO;
2618 }
2619
2620 static int
2621 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2622                                 struct rte_eth_rss_reta *reta_conf)
2623 {
2624         uint8_t i,j,mask;
2625         uint32_t reta;
2626         struct ixgbe_hw *hw =
2627                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2628
2629         PMD_INIT_FUNC_TRACE();
2630         /*
2631         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2632         * 128-entries in 32 registers
2633          */
2634         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2635                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2636                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2637                 else
2638                         mask = (uint8_t)((reta_conf->mask_hi >>
2639                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2640                 if (mask != 0) {
2641                         reta = 0;
2642                         if (mask != 0xF)
2643                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2644
2645                         for (j = 0; j < 4; j++) {
2646                                 if (mask & (0x1 << j)) {
2647                                         if (mask != 0xF)
2648                                                 reta &= ~(0xFF << 8 * j);
2649                                         reta |= reta_conf->reta[i + j] << 8*j;
2650                                 }
2651                         }
2652                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2653                 }
2654         }
2655
2656         return 0;
2657 }
2658
2659 static int
2660 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2661                                 struct rte_eth_rss_reta *reta_conf)
2662 {
2663         uint8_t i,j,mask;
2664         uint32_t reta;
2665         struct ixgbe_hw *hw =
2666                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2667
2668         PMD_INIT_FUNC_TRACE();
2669         /*
2670          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2671          * 128-entries in 32 registers
2672          */
2673         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2674                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2675                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2676                 else
2677                         mask = (uint8_t)((reta_conf->mask_hi >>
2678                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2679
2680                 if (mask != 0) {
2681                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2682                         for (j = 0; j < 4; j++) {
2683                                 if (mask & (0x1 << j))
2684                                         reta_conf->reta[i + j] =
2685                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2686                         }
2687                 }
2688         }
2689
2690         return 0;
2691 }
2692
2693 static void
2694 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2695                                 uint32_t index, uint32_t pool)
2696 {
2697         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2698         uint32_t enable_addr = 1;
2699
2700         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2701 }
2702
2703 static void
2704 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2705 {
2706         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2707
2708         ixgbe_clear_rar(hw, index);
2709 }
2710
2711 static int
2712 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2713 {
2714         uint32_t hlreg0;
2715         uint32_t maxfrs;
2716         struct ixgbe_hw *hw;
2717         struct rte_eth_dev_info dev_info;
2718         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2719
2720         ixgbe_dev_info_get(dev, &dev_info);
2721
2722         /* check that mtu is within the allowed range */
2723         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2724                 return -EINVAL;
2725
2726         /* refuse mtu that requires the support of scattered packets when this
2727          * feature has not been enabled before. */
2728         if (!dev->data->scattered_rx &&
2729             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2730              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2731                 return -EINVAL;
2732
2733         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2734         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2735
2736         /* switch to jumbo mode if needed */
2737         if (frame_size > ETHER_MAX_LEN) {
2738                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2739                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2740         } else {
2741                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2742                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2743         }
2744         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2745
2746         /* update max frame size */
2747         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2748
2749         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2750         maxfrs &= 0x0000FFFF;
2751         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2752         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2753
2754         return 0;
2755 }
2756
2757 /*
2758  * Virtual Function operations
2759  */
2760 static void
2761 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2762 {
2763         PMD_INIT_FUNC_TRACE();
2764
2765         /* Clear interrupt mask to stop from interrupts being generated */
2766         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2767
2768         IXGBE_WRITE_FLUSH(hw);
2769 }
2770
2771 static int
2772 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2773 {
2774         struct rte_eth_conf* conf = &dev->data->dev_conf;
2775
2776         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2777                      dev->data->port_id);
2778
2779         /*
2780          * VF has no ability to enable/disable HW CRC
2781          * Keep the persistent behavior the same as Host PF
2782          */
2783 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2784         if (!conf->rxmode.hw_strip_crc) {
2785                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2786                 conf->rxmode.hw_strip_crc = 1;
2787         }
2788 #else
2789         if (conf->rxmode.hw_strip_crc) {
2790                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2791                 conf->rxmode.hw_strip_crc = 0;
2792         }
2793 #endif
2794
2795         return 0;
2796 }
2797
2798 static int
2799 ixgbevf_dev_start(struct rte_eth_dev *dev)
2800 {
2801         struct ixgbe_hw *hw =
2802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2803         int err, mask = 0;
2804
2805         PMD_INIT_FUNC_TRACE();
2806
2807         hw->mac.ops.reset_hw(hw);
2808
2809         /* negotiate mailbox API version to use with the PF. */
2810         ixgbevf_negotiate_api(hw);
2811
2812         ixgbevf_dev_tx_init(dev);
2813
2814         /* This can fail when allocating mbufs for descriptor rings */
2815         err = ixgbevf_dev_rx_init(dev);
2816         if (err) {
2817                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n",
2818                              err);
2819                 ixgbe_dev_clear_queues(dev);
2820                 return err;
2821         }
2822
2823         /* Set vfta */
2824         ixgbevf_set_vfta_all(dev,1);
2825
2826         /* Set HW strip */
2827         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2828                 ETH_VLAN_EXTEND_MASK;
2829         ixgbevf_vlan_offload_set(dev, mask);
2830
2831         ixgbevf_dev_rxtx_start(dev);
2832
2833         return 0;
2834 }
2835
2836 static void
2837 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2838 {
2839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2840
2841         PMD_INIT_FUNC_TRACE();
2842
2843         hw->adapter_stopped = TRUE;
2844         ixgbe_stop_adapter(hw);
2845
2846         /*
2847           * Clear what we set, but we still keep shadow_vfta to
2848           * restore after device starts
2849           */
2850         ixgbevf_set_vfta_all(dev,0);
2851
2852         ixgbe_dev_clear_queues(dev);
2853 }
2854
2855 static void
2856 ixgbevf_dev_close(struct rte_eth_dev *dev)
2857 {
2858         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2859
2860         PMD_INIT_FUNC_TRACE();
2861
2862         ixgbe_reset_hw(hw);
2863
2864         ixgbevf_dev_stop(dev);
2865
2866         /* reprogram the RAR[0] in case user changed it. */
2867         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2868 }
2869
2870 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2871 {
2872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2873         struct ixgbe_vfta * shadow_vfta =
2874                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2875         int i = 0, j = 0, vfta = 0, mask = 1;
2876
2877         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2878                 vfta = shadow_vfta->vfta[i];
2879                 if(vfta){
2880                         mask = 1;
2881                         for (j = 0; j < 32; j++){
2882                                 if(vfta & mask)
2883                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2884                                 mask<<=1;
2885                         }
2886                 }
2887         }
2888
2889 }
2890
2891 static int
2892 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2893 {
2894         struct ixgbe_hw *hw =
2895                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896         struct ixgbe_vfta * shadow_vfta =
2897                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2898         uint32_t vid_idx = 0;
2899         uint32_t vid_bit = 0;
2900         int ret = 0;
2901
2902         PMD_INIT_FUNC_TRACE();
2903
2904         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2905         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2906         if(ret){
2907                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2908                 return ret;
2909         }
2910         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2911         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2912
2913         /* Save what we set and retore it after device reset */
2914         if (on)
2915                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2916         else
2917                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2918
2919         return 0;
2920 }
2921
2922 static void
2923 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2924 {
2925         struct ixgbe_hw *hw =
2926                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2927         uint32_t ctrl;
2928
2929         PMD_INIT_FUNC_TRACE();
2930
2931         if(queue >= hw->mac.max_rx_queues)
2932                 return;
2933
2934         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2935         if(on)
2936                 ctrl |= IXGBE_RXDCTL_VME;
2937         else
2938                 ctrl &= ~IXGBE_RXDCTL_VME;
2939         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2940
2941         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2942 }
2943
2944 static void
2945 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2946 {
2947         struct ixgbe_hw *hw =
2948                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2949         uint16_t i;
2950         int on = 0;
2951
2952         /* VF function only support hw strip feature, others are not support */
2953         if(mask & ETH_VLAN_STRIP_MASK){
2954                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2955
2956                 for(i=0; i < hw->mac.max_rx_queues; i++)
2957                         ixgbevf_vlan_strip_queue_set(dev,i,on);
2958         }
2959 }
2960
2961 static int
2962 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2963 {
2964         uint32_t reg_val;
2965
2966         /* we only need to do this if VMDq is enabled */
2967         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2968         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2969                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2970                 return (-1);
2971         }
2972
2973         return 0;
2974 }
2975
2976 static uint32_t
2977 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2978 {
2979         uint32_t vector = 0;
2980         switch (hw->mac.mc_filter_type) {
2981         case 0:   /* use bits [47:36] of the address */
2982                 vector = ((uc_addr->addr_bytes[4] >> 4) |
2983                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2984                 break;
2985         case 1:   /* use bits [46:35] of the address */
2986                 vector = ((uc_addr->addr_bytes[4] >> 3) |
2987                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2988                 break;
2989         case 2:   /* use bits [45:34] of the address */
2990                 vector = ((uc_addr->addr_bytes[4] >> 2) |
2991                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2992                 break;
2993         case 3:   /* use bits [43:32] of the address */
2994                 vector = ((uc_addr->addr_bytes[4]) |
2995                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2996                 break;
2997         default:  /* Invalid mc_filter_type */
2998                 break;
2999         }
3000
3001         /* vector can only be 12-bits or boundary will be exceeded */
3002         vector &= 0xFFF;
3003         return vector;
3004 }
3005
3006 static int
3007 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3008                                uint8_t on)
3009 {
3010         uint32_t vector;
3011         uint32_t uta_idx;
3012         uint32_t reg_val;
3013         uint32_t uta_shift;
3014         uint32_t rc;
3015         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3016         const uint32_t ixgbe_uta_bit_shift = 5;
3017         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3018         const uint32_t bit1 = 0x1;
3019
3020         struct ixgbe_hw *hw =
3021                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3022         struct ixgbe_uta_info *uta_info =
3023                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3024
3025         /* The UTA table only exists on 82599 hardware and newer */
3026         if (hw->mac.type < ixgbe_mac_82599EB)
3027                 return (-ENOTSUP);
3028
3029         vector = ixgbe_uta_vector(hw,mac_addr);
3030         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3031         uta_shift = vector & ixgbe_uta_bit_mask;
3032
3033         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3034         if(rc == on)
3035                 return 0;
3036
3037         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3038         if (on) {
3039                 uta_info->uta_in_use++;
3040                 reg_val |= (bit1 << uta_shift);
3041                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3042         } else {
3043                 uta_info->uta_in_use--;
3044                 reg_val &= ~(bit1 << uta_shift);
3045                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3046         }
3047
3048         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3049
3050         if (uta_info->uta_in_use > 0)
3051                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3052                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3053         else
3054                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3055
3056         return 0;
3057 }
3058
3059 static int
3060 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3061 {
3062         int i;
3063         struct ixgbe_hw *hw =
3064                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3065         struct ixgbe_uta_info *uta_info =
3066                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3067
3068         /* The UTA table only exists on 82599 hardware and newer */
3069         if (hw->mac.type < ixgbe_mac_82599EB)
3070                 return (-ENOTSUP);
3071
3072         if(on) {
3073                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3074                         uta_info->uta_shadow[i] = ~0;
3075                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3076                 }
3077         } else {
3078                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3079                         uta_info->uta_shadow[i] = 0;
3080                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3081                 }
3082         }
3083         return 0;
3084
3085 }
3086 static int
3087 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3088                                uint16_t rx_mask, uint8_t on)
3089 {
3090         int val = 0;
3091
3092         struct ixgbe_hw *hw =
3093                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3094         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3095
3096         if (hw->mac.type == ixgbe_mac_82598EB) {
3097                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3098                              " on 82599 hardware and newer\n");
3099                 return (-ENOTSUP);
3100         }
3101         if (ixgbe_vmdq_mode_check(hw) < 0)
3102                 return (-ENOTSUP);
3103
3104         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
3105                 val |= IXGBE_VMOLR_AUPE;
3106         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
3107                 val |= IXGBE_VMOLR_ROMPE;
3108         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3109                 val |= IXGBE_VMOLR_ROPE;
3110         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3111                 val |= IXGBE_VMOLR_BAM;
3112         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3113                 val |= IXGBE_VMOLR_MPE;
3114
3115         if (on)
3116                 vmolr |= val;
3117         else
3118                 vmolr &= ~val;
3119
3120         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3121
3122         return 0;
3123 }
3124
3125 static int
3126 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3127 {
3128         uint32_t reg,addr;
3129         uint32_t val;
3130         const uint8_t bit1 = 0x1;
3131
3132         struct ixgbe_hw *hw =
3133                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3134
3135         if (ixgbe_vmdq_mode_check(hw) < 0)
3136                 return (-ENOTSUP);
3137
3138         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3139         reg = IXGBE_READ_REG(hw, addr);
3140         val = bit1 << pool;
3141
3142         if (on)
3143                 reg |= val;
3144         else
3145                 reg &= ~val;
3146
3147         IXGBE_WRITE_REG(hw, addr,reg);
3148
3149         return 0;
3150 }
3151
3152 static int
3153 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3154 {
3155         uint32_t reg,addr;
3156         uint32_t val;
3157         const uint8_t bit1 = 0x1;
3158
3159         struct ixgbe_hw *hw =
3160                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3161
3162         if (ixgbe_vmdq_mode_check(hw) < 0)
3163                 return (-ENOTSUP);
3164
3165         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3166         reg = IXGBE_READ_REG(hw, addr);
3167         val = bit1 << pool;
3168
3169         if (on)
3170                 reg |= val;
3171         else
3172                 reg &= ~val;
3173
3174         IXGBE_WRITE_REG(hw, addr,reg);
3175
3176         return 0;
3177 }
3178
3179 static int
3180 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3181                         uint64_t pool_mask, uint8_t vlan_on)
3182 {
3183         int ret = 0;
3184         uint16_t pool_idx;
3185         struct ixgbe_hw *hw =
3186                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3187
3188         if (ixgbe_vmdq_mode_check(hw) < 0)
3189                 return (-ENOTSUP);
3190         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3191                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3192                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3193                         if (ret < 0)
3194                                 return ret;
3195         }
3196
3197         return ret;
3198 }
3199
3200 static int
3201 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3202                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3203                         uint8_t rule_id, uint8_t on)
3204 {
3205         uint32_t mr_ctl,vlvf;
3206         uint32_t mp_lsb = 0;
3207         uint32_t mv_msb = 0;
3208         uint32_t mv_lsb = 0;
3209         uint32_t mp_msb = 0;
3210         uint8_t i = 0;
3211         int reg_index = 0;
3212         uint64_t vlan_mask = 0;
3213
3214         const uint8_t pool_mask_offset = 32;
3215         const uint8_t vlan_mask_offset = 32;
3216         const uint8_t dst_pool_offset = 8;
3217         const uint8_t rule_mr_offset  = 4;
3218         const uint8_t mirror_rule_mask= 0x0F;
3219
3220         struct ixgbe_mirror_info *mr_info =
3221                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3222         struct ixgbe_hw *hw =
3223                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3224
3225         if (ixgbe_vmdq_mode_check(hw) < 0)
3226                 return (-ENOTSUP);
3227
3228         /* Check if vlan mask is valid */
3229         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3230                 if (mirror_conf->vlan.vlan_mask == 0)
3231                         return (-EINVAL);
3232         }
3233
3234         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3235         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3236                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3237                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3238                                 /* search vlan id related pool vlan filter index */
3239                                 reg_index = ixgbe_find_vlvf_slot(hw,
3240                                                 mirror_conf->vlan.vlan_id[i]);
3241                                 if(reg_index < 0)
3242                                         return (-EINVAL);
3243                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3244                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3245                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3246                                                 == mirror_conf->vlan.vlan_id[i]))
3247                                         vlan_mask |= (1ULL << reg_index);
3248                                 else
3249                                         return (-EINVAL);
3250                         }
3251                 }
3252
3253                 if (on) {
3254                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3255                         mv_msb = vlan_mask >> vlan_mask_offset;
3256
3257                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3258                                                 mirror_conf->vlan.vlan_mask;
3259                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3260                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3261                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3262                                                 mirror_conf->vlan.vlan_id[i];
3263                         }
3264                 } else {
3265                         mv_lsb = 0;
3266                         mv_msb = 0;
3267                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3268                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3269                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3270                 }
3271         }
3272
3273         /*
3274          * if enable pool mirror, write related pool mask register,if disable
3275          * pool mirror, clear PFMRVM register
3276          */
3277         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3278                 if (on) {
3279                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3280                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3281                         mr_info->mr_conf[rule_id].pool_mask =
3282                                         mirror_conf->pool_mask;
3283
3284                 } else {
3285                         mp_lsb = 0;
3286                         mp_msb = 0;
3287                         mr_info->mr_conf[rule_id].pool_mask = 0;
3288                 }
3289         }
3290
3291         /* read  mirror control register and recalculate it */
3292         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3293
3294         if (on) {
3295                 mr_ctl |= mirror_conf->rule_type_mask;
3296                 mr_ctl &= mirror_rule_mask;
3297                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3298         } else
3299                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3300
3301         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3302         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3303
3304         /* write mirrror control  register */
3305         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3306
3307         /* write pool mirrror control  register */
3308         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3309                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3310                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3311                                 mp_msb);
3312         }
3313         /* write VLAN mirrror control  register */
3314         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3315                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3316                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3317                                 mv_msb);
3318         }
3319
3320         return 0;
3321 }
3322
3323 static int
3324 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3325 {
3326         int mr_ctl = 0;
3327         uint32_t lsb_val = 0;
3328         uint32_t msb_val = 0;
3329         const uint8_t rule_mr_offset = 4;
3330
3331         struct ixgbe_hw *hw =
3332                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3333         struct ixgbe_mirror_info *mr_info =
3334                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3335
3336         if (ixgbe_vmdq_mode_check(hw) < 0)
3337                 return (-ENOTSUP);
3338
3339         memset(&mr_info->mr_conf[rule_id], 0,
3340                 sizeof(struct rte_eth_vmdq_mirror_conf));
3341
3342         /* clear PFVMCTL register */
3343         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3344
3345         /* clear pool mask register */
3346         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3347         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3348
3349         /* clear vlan mask register */
3350         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3351         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3352
3353         return 0;
3354 }
3355
3356 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3357         uint16_t queue_idx, uint16_t tx_rate)
3358 {
3359         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360         uint32_t rf_dec, rf_int;
3361         uint32_t bcnrc_val;
3362         uint16_t link_speed = dev->data->dev_link.link_speed;
3363
3364         if (queue_idx >= hw->mac.max_tx_queues)
3365                 return -EINVAL;
3366
3367         if (tx_rate != 0) {
3368                 /* Calculate the rate factor values to set */
3369                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3370                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3371                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3372
3373                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3374                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3375                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3376                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3377         } else {
3378                 bcnrc_val = 0;
3379         }
3380
3381         /*
3382          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3383          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3384          * set as 0x4.
3385          */
3386         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3387                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3388                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3389                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3390                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3391         else
3392                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3393                         IXGBE_MMW_SIZE_DEFAULT);
3394
3395         /* Set RTTBCNRC of queue X */
3396         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3397         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3398         IXGBE_WRITE_FLUSH(hw);
3399
3400         return 0;
3401 }
3402
3403 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3404         uint16_t tx_rate, uint64_t q_msk)
3405 {
3406         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3407         struct ixgbe_vf_info *vfinfo =
3408                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3409         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3410         uint32_t queue_stride =
3411                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3412         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3413         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3414         uint16_t total_rate = 0;
3415
3416         if (queue_end >= hw->mac.max_tx_queues)
3417                 return -EINVAL;
3418
3419         if (vfinfo != NULL) {
3420                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3421                         if (vf_idx == vf)
3422                                 continue;
3423                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3424                                 idx++)
3425                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3426                 }
3427         } else
3428                 return -EINVAL;
3429
3430         /* Store tx_rate for this vf. */
3431         for (idx = 0; idx < nb_q_per_pool; idx++) {
3432                 if (((uint64_t)0x1 << idx) & q_msk) {
3433                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3434                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3435                         total_rate += tx_rate;
3436                 }
3437         }
3438
3439         if (total_rate > dev->data->dev_link.link_speed) {
3440                 /*
3441                  * Reset stored TX rate of the VF if it causes exceed
3442                  * link speed.
3443                  */
3444                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3445                 return -EINVAL;
3446         }
3447
3448         /* Set RTTBCNRC of each queue/pool for vf X  */
3449         for (; queue_idx <= queue_end; queue_idx++) {
3450                 if (0x1 & q_msk)
3451                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3452                 q_msk = q_msk >> 1;
3453         }
3454
3455         return 0;
3456 }
3457
3458 static void
3459 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3460                      __attribute__((unused)) uint32_t index,
3461                      __attribute__((unused)) uint32_t pool)
3462 {
3463         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3464         int diag;
3465
3466         /*
3467          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3468          * operation. Trap this case to avoid exhausting the [very limited]
3469          * set of PF resources used to store VF MAC addresses.
3470          */
3471         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3472                 return;
3473         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3474         if (diag == 0)
3475                 return;
3476         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3477 }
3478
3479 static void
3480 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3481 {
3482         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3483         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3484         struct ether_addr *mac_addr;
3485         uint32_t i;
3486         int diag;
3487
3488         /*
3489          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3490          * not support the deletion of a given MAC address.
3491          * Instead, it imposes to delete all MAC addresses, then to add again
3492          * all MAC addresses with the exception of the one to be deleted.
3493          */
3494         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3495
3496         /*
3497          * Add again all MAC addresses, with the exception of the deleted one
3498          * and of the permanent MAC address.
3499          */
3500         for (i = 0, mac_addr = dev->data->mac_addrs;
3501              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3502                 /* Skip the deleted MAC address */
3503                 if (i == index)
3504                         continue;
3505                 /* Skip NULL MAC addresses */
3506                 if (is_zero_ether_addr(mac_addr))
3507                         continue;
3508                 /* Skip the permanent MAC address */
3509                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3510                         continue;
3511                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3512                 if (diag != 0)
3513                         PMD_DRV_LOG(ERR,
3514                                     "Adding again MAC address "
3515                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3516                                     "diag=%d",
3517                                     mac_addr->addr_bytes[0],
3518                                     mac_addr->addr_bytes[1],
3519                                     mac_addr->addr_bytes[2],
3520                                     mac_addr->addr_bytes[3],
3521                                     mac_addr->addr_bytes[4],
3522                                     mac_addr->addr_bytes[5],
3523                                     diag);
3524         }
3525 }
3526
3527 /*
3528  * add syn filter
3529  *
3530  * @param
3531  * dev: Pointer to struct rte_eth_dev.
3532  * filter: ponter to the filter that will be added.
3533  * rx_queue: the queue id the filter assigned to.
3534  *
3535  * @return
3536  *    - On success, zero.
3537  *    - On failure, a negative value.
3538  */
3539 static int
3540 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3541                         struct rte_syn_filter *filter, uint16_t rx_queue)
3542 {
3543         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3544         uint32_t synqf;
3545
3546         if (hw->mac.type != ixgbe_mac_82599EB)
3547                 return -ENOSYS;
3548
3549         if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3550                 return -EINVAL;
3551
3552         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3553
3554         if (synqf & IXGBE_SYN_FILTER_ENABLE)
3555                 return -EINVAL;
3556
3557         synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3558                 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3559
3560         if (filter->hig_pri)
3561                 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3562         else
3563                 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3564
3565         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3566         return 0;
3567 }
3568
3569 /*
3570  * remove syn filter
3571  *
3572  * @param
3573  * dev: Pointer to struct rte_eth_dev.
3574  *
3575  * @return
3576  *    - On success, zero.
3577  *    - On failure, a negative value.
3578  */
3579 static int
3580 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3581 {
3582         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3583         uint32_t synqf;
3584
3585         if (hw->mac.type != ixgbe_mac_82599EB)
3586                 return -ENOSYS;
3587
3588         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3589
3590         synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3591
3592         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3593         return 0;
3594 }
3595
3596 /*
3597  * get the syn filter's info
3598  *
3599  * @param
3600  * dev: Pointer to struct rte_eth_dev.
3601  * filter: ponter to the filter that returns.
3602  * *rx_queue: pointer to the queue id the filter assigned to.
3603  *
3604  * @return
3605  *    - On success, zero.
3606  *    - On failure, a negative value.
3607  */
3608 static int
3609 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3610                         struct rte_syn_filter *filter, uint16_t *rx_queue)
3611
3612 {
3613         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3614         uint32_t synqf;
3615
3616         if (hw->mac.type != ixgbe_mac_82599EB)
3617                 return -ENOSYS;
3618
3619         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3620         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3621                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3622                 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3623                 return 0;
3624         }
3625         return -ENOENT;
3626 }
3627
3628 /*
3629  * add an ethertype filter
3630  *
3631  * @param
3632  * dev: Pointer to struct rte_eth_dev.
3633  * index: the index the filter allocates.
3634  * filter: ponter to the filter that will be added.
3635  * rx_queue: the queue id the filter assigned to.
3636  *
3637  * @return
3638  *    - On success, zero.
3639  *    - On failure, a negative value.
3640  */
3641 static int
3642 ixgbe_add_ethertype_filter(struct rte_eth_dev *dev,
3643                         uint16_t index, struct rte_ethertype_filter *filter,
3644                         uint16_t rx_queue)
3645 {
3646         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3647         uint32_t etqf, etqs = 0;
3648
3649         if (hw->mac.type != ixgbe_mac_82599EB)
3650                 return -ENOSYS;
3651
3652         if (index >= IXGBE_MAX_ETQF_FILTERS ||
3653                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3654                 return -EINVAL;
3655
3656         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3657         if (etqf & IXGBE_ETQF_FILTER_EN)
3658                 return -EINVAL;  /* filter index is in use. */
3659
3660         etqf = 0;
3661         etqf |= IXGBE_ETQF_FILTER_EN;
3662         etqf |= (uint32_t)filter->ethertype;
3663
3664         if (filter->priority_en) {
3665                 if (filter->priority > IXGBE_ETQF_MAX_PRI)
3666                         return -EINVAL;
3667                 etqf |= (uint32_t)((filter->priority << IXGBE_ETQF_SHIFT) & IXGBE_ETQF_UP);
3668                 etqf |= IXGBE_ETQF_UP_EN;
3669         }
3670         etqs |= (uint32_t)((rx_queue << IXGBE_ETQS_RX_QUEUE_SHIFT) & IXGBE_ETQS_RX_QUEUE);
3671         etqs |= IXGBE_ETQS_QUEUE_EN;
3672
3673         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), etqf);
3674         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), etqs);
3675         return 0;
3676 }
3677
3678 /*
3679  * remove an ethertype filter
3680  *
3681  * @param
3682  * dev: Pointer to struct rte_eth_dev.
3683  * index: the index the filter allocates.
3684  *
3685  * @return
3686  *    - On success, zero.
3687  *    - On failure, a negative value.
3688  */
3689 static int
3690 ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
3691                         uint16_t index)
3692 {
3693         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3694
3695         if (hw->mac.type != ixgbe_mac_82599EB)
3696                 return -ENOSYS;
3697
3698         if (index >= IXGBE_MAX_ETQF_FILTERS)
3699                 return -EINVAL;
3700
3701         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), 0);
3702         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), 0);
3703
3704         return 0;
3705 }
3706
3707 /*
3708  * get an ethertype filter
3709  *
3710  * @param
3711  * dev: Pointer to struct rte_eth_dev.
3712  * index: the index the filter allocates.
3713  * filter: ponter to the filter that will be gotten.
3714  * *rx_queue: the ponited of the queue id the filter assigned to.
3715  *
3716  * @return
3717  *    - On success, zero.
3718  *    - On failure, a negative value.
3719  */
3720 static int
3721 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
3722                         uint16_t index, struct rte_ethertype_filter *filter,
3723                         uint16_t *rx_queue)
3724 {
3725         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3726         uint32_t etqf, etqs;
3727
3728         if (hw->mac.type != ixgbe_mac_82599EB)
3729                 return -ENOSYS;
3730
3731         if (index >= IXGBE_MAX_ETQF_FILTERS)
3732                 return -EINVAL;
3733
3734         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3735         etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(index));
3736         if (etqf & IXGBE_ETQF_FILTER_EN) {
3737                 filter->ethertype = etqf & IXGBE_ETQF_ETHERTYPE;
3738                 filter->priority_en = (etqf & IXGBE_ETQF_UP_EN) ? 1 : 0;
3739                 if (filter->priority_en)
3740                         filter->priority = (etqf & IXGBE_ETQF_UP) >> 16;
3741                 *rx_queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> IXGBE_ETQS_RX_QUEUE_SHIFT;
3742                 return 0;
3743         }
3744         return -ENOENT;
3745 }
3746
3747 static inline enum ixgbe_5tuple_protocol
3748 convert_protocol_type(uint8_t protocol_value)
3749 {
3750         if (protocol_value == IPPROTO_TCP)
3751                 return IXGBE_FILTER_PROTOCOL_TCP;
3752         else if (protocol_value == IPPROTO_UDP)
3753                 return IXGBE_FILTER_PROTOCOL_UDP;
3754         else if (protocol_value == IPPROTO_SCTP)
3755                 return IXGBE_FILTER_PROTOCOL_SCTP;
3756         else
3757                 return IXGBE_FILTER_PROTOCOL_NONE;
3758 }
3759
3760 static inline uint8_t
3761 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3762 {
3763         if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3764                 return IPPROTO_TCP;
3765         else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3766                 return IPPROTO_UDP;
3767         else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3768                 return IPPROTO_SCTP;
3769         else
3770                 return 0;
3771 }
3772
3773 /*
3774  * add a 5tuple filter
3775  *
3776  * @param
3777  * dev: Pointer to struct rte_eth_dev.
3778  * index: the index the filter allocates.
3779  * filter: ponter to the filter that will be added.
3780  * rx_queue: the queue id the filter assigned to.
3781  *
3782  * @return
3783  *    - On success, zero.
3784  *    - On failure, a negative value.
3785  */
3786 static int
3787 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3788                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
3789 {
3790         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3791         uint32_t ftqf, sdpqf = 0;
3792         uint32_t l34timir = 0;
3793         uint8_t mask = 0xff;
3794
3795         if (hw->mac.type != ixgbe_mac_82599EB)
3796                 return -ENOSYS;
3797
3798         if (index >= IXGBE_MAX_FTQF_FILTERS ||
3799                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3800                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3801                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3802                 return -EINVAL;  /* filter index is out of range. */
3803
3804         if (filter->tcp_flags) {
3805                 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3806                 return -EINVAL;
3807         }
3808
3809         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3810         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3811                 return -EINVAL;  /* filter index is in use. */
3812
3813         ftqf = 0;
3814         sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3815         sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3816
3817         ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3818                 IXGBE_FTQF_PROTOCOL_MASK);
3819         ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3820                 IXGBE_FTQF_PRIORITY_SHIFT);
3821         if (filter->src_ip_mask == 0) /* 0 means compare. */
3822                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3823         if (filter->dst_ip_mask == 0)
3824                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3825         if (filter->src_port_mask == 0)
3826                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3827         if (filter->dst_port_mask == 0)
3828                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3829         if (filter->protocol_mask == 0)
3830                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3831         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3832         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3833         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3834
3835         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3836         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3837         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3838         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3839
3840         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3841         l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3842         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3843         return 0;
3844 }
3845
3846 /*
3847  * remove a 5tuple filter
3848  *
3849  * @param
3850  * dev: Pointer to struct rte_eth_dev.
3851  * index: the index the filter allocates.
3852  *
3853  * @return
3854  *    - On success, zero.
3855  *    - On failure, a negative value.
3856  */
3857 static int
3858 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3859                         uint16_t index)
3860 {
3861         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3862
3863         if (hw->mac.type != ixgbe_mac_82599EB)
3864                 return -ENOSYS;
3865
3866         if (index >= IXGBE_MAX_FTQF_FILTERS)
3867                 return -EINVAL;  /* filter index is out of range. */
3868
3869         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3870         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3871         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3872         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3873         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3874         return 0;
3875 }
3876
3877 /*
3878  * get a 5tuple filter
3879  *
3880  * @param
3881  * dev: Pointer to struct rte_eth_dev.
3882  * index: the index the filter allocates
3883  * filter: ponter to the filter that returns.
3884  * *rx_queue: pointer of the queue id the filter assigned to.
3885  *
3886  * @return
3887  *    - On success, zero.
3888  *    - On failure, a negative value.
3889  */
3890 static int
3891 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3892                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3893 {
3894         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3895         uint32_t sdpqf, ftqf, l34timir;
3896         uint8_t mask;
3897         enum ixgbe_5tuple_protocol proto;
3898
3899         if (hw->mac.type != ixgbe_mac_82599EB)
3900                 return -ENOSYS;
3901
3902         if (index >= IXGBE_MAX_FTQF_FILTERS)
3903                 return -EINVAL;  /* filter index is out of range. */
3904
3905         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3906         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3907                 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3908                 filter->protocol = revert_protocol_type(proto);
3909                 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3910                                         IXGBE_FTQF_PRIORITY_MASK;
3911                 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3912                                         IXGBE_FTQF_5TUPLE_MASK_MASK);
3913                 filter->src_ip_mask =
3914                         (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3915                 filter->dst_ip_mask =
3916                         (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3917                 filter->src_port_mask =
3918                         (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3919                 filter->dst_port_mask =
3920                         (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3921                 filter->protocol_mask =
3922                         (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3923
3924                 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3925                 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3926                                         IXGBE_SDPQF_DSTPORT_SHIFT;
3927                 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3928                 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3929                 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3930
3931                 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3932                 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3933                                         IXGBE_L34T_IMIR_QUEUE_SHIFT;
3934                 return 0;
3935         }
3936         return -ENOENT;
3937 }
3938
3939 static int
3940 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3941 {
3942         struct ixgbe_hw *hw;
3943         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3944
3945         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3946
3947         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3948                 return -EINVAL;
3949
3950         /* refuse mtu that requires the support of scattered packets when this
3951          * feature has not been enabled before. */
3952         if (!dev->data->scattered_rx &&
3953             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3954              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3955                 return -EINVAL;
3956
3957         /*
3958          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3959          * request of the version 2.0 of the mailbox API.
3960          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3961          * of the mailbox API.
3962          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3963          * prior to 3.11.33 which contains the following change:
3964          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3965          */
3966         ixgbevf_rlpml_set_vf(hw, max_frame);
3967
3968         /* update max frame size */
3969         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
3970         return 0;
3971 }
3972
3973 static struct rte_driver rte_ixgbe_driver = {
3974         .type = PMD_PDEV,
3975         .init = rte_ixgbe_pmd_init,
3976 };
3977
3978 static struct rte_driver rte_ixgbevf_driver = {
3979         .type = PMD_PDEV,
3980         .init = rte_ixgbevf_pmd_init,
3981 };
3982
3983 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
3984 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);