lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72
  73 /*
  74  * High threshold controlling when to start sending XOFF frames. Must be at
  75  * least 8 bytes less than receive packet buffer size. This value is in units
  76  * of 1024 bytes.
  77  */
  78 #define IXGBE_FC_HI    0x80
  79
  80 /*
  81  * Low threshold controlling when to start sending XON frames. This value is
  82  * in units of 1024 bytes.
  83  */
  84 #define IXGBE_FC_LO    0x40
  85
  86 /* Timer value included in XOFF frames. */
  87 #define IXGBE_FC_PAUSE 0x680
  88
  89 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  90 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  91 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  92
  93 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  94 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  95
  96 /*
  97  *  Default values for RX/TX configuration
  98  */
  99 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 100 #define IXGBE_DEFAULT_RX_PTHRESH      8
 101 #define IXGBE_DEFAULT_RX_HTHRESH      8
 102 #define IXGBE_DEFAULT_RX_WTHRESH      0
 103
 104 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 105 #define IXGBE_DEFAULT_TX_PTHRESH      32
 106 #define IXGBE_DEFAULT_TX_HTHRESH      0
 107 #define IXGBE_DEFAULT_TX_WTHRESH      0
 108 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 109
 110 /* Bit shift and mask */
 111 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 112 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 113 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 114 #define IXGBE_8_BIT_MASK   UINT8_MAX
 115
 116 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 117
 118 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 119
 120 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 121                 struct rte_eth_dev *eth_dev);
 122 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 123 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 124 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 125 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 126 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 127 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 128 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 129 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 130 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 131 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 132 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 133                                 int wait_to_complete);
 134 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 135                                 struct rte_eth_stats *stats);
 136 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 137 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 138                                              uint16_t queue_id,
 139                                              uint8_t stat_idx,
 140                                              uint8_t is_rx);
 141 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 142                                struct rte_eth_dev_info *dev_info);
 143 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 144                                  struct rte_eth_dev_info *dev_info);
 145 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 146
 147 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 148                 uint16_t vlan_id, int on);
 149 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 150 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 151                 uint16_t queue, bool on);
 152 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 153                 int on);
 154 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 155 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 156 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 157 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 158 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 159
 160 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 161 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 162 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 163                                struct rte_eth_fc_conf *fc_conf);
 164 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 165                                struct rte_eth_fc_conf *fc_conf);
 166 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 167                 struct rte_eth_pfc_conf *pfc_conf);
 168 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 169                         struct rte_eth_rss_reta_entry64 *reta_conf,
 170                         uint16_t reta_size);
 171 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 172                         struct rte_eth_rss_reta_entry64 *reta_conf,
 173                         uint16_t reta_size);
 174 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 178 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 179                 void *param);
 180 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 181 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 182                 uint32_t index, uint32_t pool);
 183 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 184 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 185
 186 /* For Virtual Function support */
 187 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 188                 struct rte_eth_dev *eth_dev);
 189 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 190 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 191 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 192 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 193 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 194 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 195                 struct rte_eth_stats *stats);
 196 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 197 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 198                 uint16_t vlan_id, int on);
 199 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 200                 uint16_t queue, int on);
 201 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 202 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203
 204 /* For Eth VMDQ APIs support */
 205 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 206                 ether_addr* mac_addr,uint8_t on);
 207 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 208 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 209                 uint16_t rx_mask, uint8_t on);
 210 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 211 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 212 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 213                 uint64_t pool_mask,uint8_t vlan_on);
 214 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 215                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 216                 uint8_t rule_id, uint8_t on);
 217 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 218                 uint8_t rule_id);
 219
 220 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 221                 uint16_t queue_idx, uint16_t tx_rate);
 222 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 223                 uint16_t tx_rate, uint64_t q_msk);
 224
 225 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 226                                  struct ether_addr *mac_addr,
 227                                  uint32_t index, uint32_t pool);
 228 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 229 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 230                         struct rte_eth_syn_filter *filter,
 231                         bool add);
 232 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 233                         struct rte_eth_syn_filter *filter);
 234 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 235                         enum rte_filter_op filter_op,
 236                         void *arg);
 237 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 238                         struct ixgbe_5tuple_filter *filter);
 239 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 240                         struct ixgbe_5tuple_filter *filter);
 241 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 242                         struct rte_eth_ntuple_filter *filter,
 243                         bool add);
 244 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 245                                 enum rte_filter_op filter_op,
 246                                 void *arg);
 247 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 248                         struct rte_eth_ntuple_filter *filter);
 249 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 250                         struct rte_eth_ethertype_filter *filter,
 251                         bool add);
 252 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 253                                 enum rte_filter_op filter_op,
 254                                 void *arg);
 255 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 256                         struct rte_eth_ethertype_filter *filter);
 257 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 258                      enum rte_filter_type filter_type,
 259                      enum rte_filter_op filter_op,
 260                      void *arg);
 261 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 262
 263 /*
 264  * Define VF Stats MACRO for Non "cleared on read" register
 265  */
 266 #define UPDATE_VF_STAT(reg, last, cur)                          \
 267 {                                                               \
 268         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 269         cur += latest - last;                                   \
 270         last = latest;                                          \
 271 }
 272
 273 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 274 {                                                                \
 275         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 276         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 277         u64 latest = ((new_msb << 32) | new_lsb);                \
 278         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 279         last = latest;                                           \
 280 }
 281
 282 #define IXGBE_SET_HWSTRIP(h, q) do{\
 283                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 284                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 285                 (h)->bitmap[idx] |= 1 << bit;\
 286         }while(0)
 287
 288 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 289                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 290                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 291                 (h)->bitmap[idx] &= ~(1 << bit);\
 292         }while(0)
 293
 294 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 295                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 296                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 297                 (r) = (h)->bitmap[idx] >> bit & 1;\
 298         }while(0)
 299
 300 /*
 301  * The set of PCI devices this driver supports
 302  */
 303 static struct rte_pci_id pci_id_ixgbe_map[] = {
 304
 305 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 306 #include "rte_pci_dev_ids.h"
 307
 308 { .vendor_id = 0, /* sentinel */ },
 309 };
 310
 311
 312 /*
 313  * The set of PCI devices this driver supports (for 82599 VF)
 314  */
 315 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 316
 317 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 318 #include "rte_pci_dev_ids.h"
 319 { .vendor_id = 0, /* sentinel */ },
 320
 321 };
 322
 323 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 324         .dev_configure        = ixgbe_dev_configure,
 325         .dev_start            = ixgbe_dev_start,
 326         .dev_stop             = ixgbe_dev_stop,
 327         .dev_set_link_up    = ixgbe_dev_set_link_up,
 328         .dev_set_link_down  = ixgbe_dev_set_link_down,
 329         .dev_close            = ixgbe_dev_close,
 330         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 331         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 332         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 333         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 334         .link_update          = ixgbe_dev_link_update,
 335         .stats_get            = ixgbe_dev_stats_get,
 336         .stats_reset          = ixgbe_dev_stats_reset,
 337         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 338         .dev_infos_get        = ixgbe_dev_info_get,
 339         .mtu_set              = ixgbe_dev_mtu_set,
 340         .vlan_filter_set      = ixgbe_vlan_filter_set,
 341         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 342         .vlan_offload_set     = ixgbe_vlan_offload_set,
 343         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 344         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 345         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 346         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 347         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 348         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 349         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 350         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 351         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 352         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 353         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 354         .dev_led_on           = ixgbe_dev_led_on,
 355         .dev_led_off          = ixgbe_dev_led_off,
 356         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 357         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 358         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 359         .mac_addr_add         = ixgbe_add_rar,
 360         .mac_addr_remove      = ixgbe_remove_rar,
 361         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 362         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 363         .mirror_rule_set      = ixgbe_mirror_rule_set,
 364         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 365         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 366         .set_vf_rx            = ixgbe_set_pool_rx,
 367         .set_vf_tx            = ixgbe_set_pool_tx,
 368         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 369         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 370         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 371         .reta_update          = ixgbe_dev_rss_reta_update,
 372         .reta_query           = ixgbe_dev_rss_reta_query,
 373 #ifdef RTE_NIC_BYPASS
 374         .bypass_init          = ixgbe_bypass_init,
 375         .bypass_state_set     = ixgbe_bypass_state_store,
 376         .bypass_state_show    = ixgbe_bypass_state_show,
 377         .bypass_event_set     = ixgbe_bypass_event_store,
 378         .bypass_event_show    = ixgbe_bypass_event_show,
 379         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 380         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 381         .bypass_ver_show      = ixgbe_bypass_ver_show,
 382         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 383 #endif /* RTE_NIC_BYPASS */
 384         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 385         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 386         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 387 };
 388
 389 /*
 390  * dev_ops for virtual function, bare necessities for basic vf
 391  * operation have been implemented
 392  */
 393 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 394
 395         .dev_configure        = ixgbevf_dev_configure,
 396         .dev_start            = ixgbevf_dev_start,
 397         .dev_stop             = ixgbevf_dev_stop,
 398         .link_update          = ixgbe_dev_link_update,
 399         .stats_get            = ixgbevf_dev_stats_get,
 400         .stats_reset          = ixgbevf_dev_stats_reset,
 401         .dev_close            = ixgbevf_dev_close,
 402         .dev_infos_get        = ixgbevf_dev_info_get,
 403         .mtu_set              = ixgbevf_dev_set_mtu,
 404         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 405         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 406         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 407         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 408         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 409         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 410         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 411         .mac_addr_add         = ixgbevf_add_mac_addr,
 412         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 413 };
 414
 415 /**
 416  * Atomically reads the link status information from global
 417  * structure rte_eth_dev.
 418  *
 419  * @param dev
 420  *   - Pointer to the structure rte_eth_dev to read from.
 421  *   - Pointer to the buffer to be saved with the link status.
 422  *
 423  * @return
 424  *   - On success, zero.
 425  *   - On failure, negative value.
 426  */
 427 static inline int
 428 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 429                                 struct rte_eth_link *link)
 430 {
 431         struct rte_eth_link *dst = link;
 432         struct rte_eth_link *src = &(dev->data->dev_link);
 433
 434         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 435                                         *(uint64_t *)src) == 0)
 436                 return -1;
 437
 438         return 0;
 439 }
 440
 441 /**
 442  * Atomically writes the link status information into global
 443  * structure rte_eth_dev.
 444  *
 445  * @param dev
 446  *   - Pointer to the structure rte_eth_dev to read from.
 447  *   - Pointer to the buffer to be saved with the link status.
 448  *
 449  * @return
 450  *   - On success, zero.
 451  *   - On failure, negative value.
 452  */
 453 static inline int
 454 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 455                                 struct rte_eth_link *link)
 456 {
 457         struct rte_eth_link *dst = &(dev->data->dev_link);
 458         struct rte_eth_link *src = link;
 459
 460         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 461                                         *(uint64_t *)src) == 0)
 462                 return -1;
 463
 464         return 0;
 465 }
 466
 467 /*
 468  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 469  */
 470 static inline int
 471 ixgbe_is_sfp(struct ixgbe_hw *hw)
 472 {
 473         switch (hw->phy.type) {
 474         case ixgbe_phy_sfp_avago:
 475         case ixgbe_phy_sfp_ftl:
 476         case ixgbe_phy_sfp_intel:
 477         case ixgbe_phy_sfp_unknown:
 478         case ixgbe_phy_sfp_passive_tyco:
 479         case ixgbe_phy_sfp_passive_unknown:
 480                 return 1;
 481         default:
 482                 return 0;
 483         }
 484 }
 485
 486 static inline int32_t
 487 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 488 {
 489         uint32_t ctrl_ext;
 490         int32_t status;
 491
 492         status = ixgbe_reset_hw(hw);
 493
 494         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 495         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 496         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 497         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 498         IXGBE_WRITE_FLUSH(hw);
 499
 500         return status;
 501 }
 502
 503 static inline void
 504 ixgbe_enable_intr(struct rte_eth_dev *dev)
 505 {
 506         struct ixgbe_interrupt *intr =
 507                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 508         struct ixgbe_hw *hw =
 509                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 510
 511         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 512         IXGBE_WRITE_FLUSH(hw);
 513 }
 514
 515 /*
 516  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 517  */
 518 static void
 519 ixgbe_disable_intr(struct ixgbe_hw *hw)
 520 {
 521         PMD_INIT_FUNC_TRACE();
 522
 523         if (hw->mac.type == ixgbe_mac_82598EB) {
 524                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 525         } else {
 526                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 527                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 528                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 529         }
 530         IXGBE_WRITE_FLUSH(hw);
 531 }
 532
 533 /*
 534  * This function resets queue statistics mapping registers.
 535  * From Niantic datasheet, Initialization of Statistics section:
 536  * "...if software requires the queue counters, the RQSMR and TQSM registers
 537  * must be re-programmed following a device reset.
 538  */
 539 static void
 540 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 541 {
 542         uint32_t i;
 543
 544         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 545                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 546                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 547         }
 548 }
 549
 550
 551 static int
 552 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 553                                   uint16_t queue_id,
 554                                   uint8_t stat_idx,
 555                                   uint8_t is_rx)
 556 {
 557 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 558 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 559 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 560
 561         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 562         struct ixgbe_stat_mapping_registers *stat_mappings =
 563                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 564         uint32_t qsmr_mask = 0;
 565         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 566         uint32_t q_map;
 567         uint8_t n, offset;
 568
 569         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 570                 (hw->mac.type != ixgbe_mac_X540) &&
 571                 (hw->mac.type != ixgbe_mac_X550) &&
 572                 (hw->mac.type != ixgbe_mac_X550EM_x))
 573                 return -ENOSYS;
 574
 575         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 576                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 577                      queue_id, stat_idx);
 578
 579         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 580         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 581                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 582                 return -EIO;
 583         }
 584         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 585
 586         /* Now clear any previous stat_idx set */
 587         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 588         if (!is_rx)
 589                 stat_mappings->tqsm[n] &= ~clearing_mask;
 590         else
 591                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 592
 593         q_map = (uint32_t)stat_idx;
 594         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 595         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 596         if (!is_rx)
 597                 stat_mappings->tqsm[n] |= qsmr_mask;
 598         else
 599                 stat_mappings->rqsmr[n] |= qsmr_mask;
 600
 601         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 602                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 603                      queue_id, stat_idx);
 604         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 605                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 606
 607         /* Now write the mapping in the appropriate register */
 608         if (is_rx) {
 609                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 610                              stat_mappings->rqsmr[n], n);
 611                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 612         }
 613         else {
 614                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 615                              stat_mappings->tqsm[n], n);
 616                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 617         }
 618         return 0;
 619 }
 620
 621 static void
 622 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 623 {
 624         struct ixgbe_stat_mapping_registers *stat_mappings =
 625                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 626         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 627         int i;
 628
 629         /* write whatever was in stat mapping table to the NIC */
 630         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 631                 /* rx */
 632                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 633
 634                 /* tx */
 635                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 636         }
 637 }
 638
 639 static void
 640 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 641 {
 642         uint8_t i;
 643         struct ixgbe_dcb_tc_config *tc;
 644         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 645
 646         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 647         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 648         for (i = 0; i < dcb_max_tc; i++) {
 649                 tc = &dcb_config->tc_config[i];
 650                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 651                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 652                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 653                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 654                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 655                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 656                 tc->pfc = ixgbe_dcb_pfc_disabled;
 657         }
 658
 659         /* Initialize default user to priority mapping, UPx->TC0 */
 660         tc = &dcb_config->tc_config[0];
 661         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 662         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 663         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 664                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 665                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 666         }
 667         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 668         dcb_config->pfc_mode_enable = false;
 669         dcb_config->vt_mode = true;
 670         dcb_config->round_robin_enable = false;
 671         /* support all DCB capabilities in 82599 */
 672         dcb_config->support.capabilities = 0xFF;
 673
 674         /*we only support 4 Tcs for X540, X550 */
 675         if (hw->mac.type == ixgbe_mac_X540 ||
 676                 hw->mac.type == ixgbe_mac_X550 ||
 677                 hw->mac.type == ixgbe_mac_X550EM_x) {
 678                 dcb_config->num_tcs.pg_tcs = 4;
 679                 dcb_config->num_tcs.pfc_tcs = 4;
 680         }
 681 }
 682
 683 /*
 684  * Ensure that all locks are released before first NVM or PHY access
 685  */
 686 static void
 687 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 688 {
 689         uint16_t mask;
 690
 691         /*
 692          * Phy lock should not fail in this early stage. If this is the case,
 693          * it is due to an improper exit of the application.
 694          * So force the release of the faulty lock. Release of common lock
 695          * is done automatically by swfw_sync function.
 696          */
 697         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 698         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 699                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 700         }
 701         ixgbe_release_swfw_semaphore(hw, mask);
 702
 703         /*
 704          * These ones are more tricky since they are common to all ports; but
 705          * swfw_sync retries last long enough (1s) to be almost sure that if
 706          * lock can not be taken it is due to an improper lock of the
 707          * semaphore.
 708          */
 709         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 710         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 711                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 712         }
 713         ixgbe_release_swfw_semaphore(hw, mask);
 714 }
 715
 716 /*
 717  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 718  * It returns 0 on success.
 719  */
 720 static int
 721 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 722                      struct rte_eth_dev *eth_dev)
 723 {
 724         struct rte_pci_device *pci_dev;
 725         struct ixgbe_hw *hw =
 726                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 727         struct ixgbe_vfta * shadow_vfta =
 728                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 729         struct ixgbe_hwstrip *hwstrip =
 730                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 731         struct ixgbe_dcb_config *dcb_config =
 732                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 733         struct ixgbe_filter_info *filter_info =
 734                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 735         uint32_t ctrl_ext;
 736         uint16_t csum;
 737         int diag, i;
 738
 739         PMD_INIT_FUNC_TRACE();
 740
 741         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 742         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 743         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 744
 745         /*
 746          * For secondary processes, we don't initialise any further as primary
 747          * has already done this work. Only check we don't need a different
 748          * RX and TX function.
 749          */
 750         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 751                 struct igb_tx_queue *txq;
 752                 /* TX queue function in primary, set by last queue initialized
 753                  * Tx queue may not initialized by primary process */
 754                 if (eth_dev->data->tx_queues) {
 755                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 756                         set_tx_function(eth_dev, txq);
 757                 } else {
 758                         /* Use default TX function if we get here */
 759                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 760                                            "Using default TX function.");
 761                 }
 762
 763                 if (eth_dev->data->scattered_rx)
 764                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 765                 return 0;
 766         }
 767         pci_dev = eth_dev->pci_dev;
 768
 769         /* Vendor and Device ID need to be set before init of shared code */
 770         hw->device_id = pci_dev->id.device_id;
 771         hw->vendor_id = pci_dev->id.vendor_id;
 772         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 773         hw->allow_unsupported_sfp = 1;
 774
 775         /* Initialize the shared code (base driver) */
 776 #ifdef RTE_NIC_BYPASS
 777         diag = ixgbe_bypass_init_shared_code(hw);
 778 #else
 779         diag = ixgbe_init_shared_code(hw);
 780 #endif /* RTE_NIC_BYPASS */
 781
 782         if (diag != IXGBE_SUCCESS) {
 783                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 784                 return -EIO;
 785         }
 786
 787         /* pick up the PCI bus settings for reporting later */
 788         ixgbe_get_bus_info(hw);
 789
 790         /* Unlock any pending hardware semaphore */
 791         ixgbe_swfw_lock_reset(hw);
 792
 793         /* Initialize DCB configuration*/
 794         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 795         ixgbe_dcb_init(hw,dcb_config);
 796         /* Get Hardware Flow Control setting */
 797         hw->fc.requested_mode = ixgbe_fc_full;
 798         hw->fc.current_mode = ixgbe_fc_full;
 799         hw->fc.pause_time = IXGBE_FC_PAUSE;
 800         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 801                 hw->fc.low_water[i] = IXGBE_FC_LO;
 802                 hw->fc.high_water[i] = IXGBE_FC_HI;
 803         }
 804         hw->fc.send_xon = 1;
 805
 806         /* Make sure we have a good EEPROM before we read from it */
 807         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 808         if (diag != IXGBE_SUCCESS) {
 809                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 810                 return -EIO;
 811         }
 812
 813 #ifdef RTE_NIC_BYPASS
 814         diag = ixgbe_bypass_init_hw(hw);
 815 #else
 816         diag = ixgbe_init_hw(hw);
 817 #endif /* RTE_NIC_BYPASS */
 818
 819         /*
 820          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 821          * is called too soon after the kernel driver unbinding/binding occurs.
 822          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 823          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 824          * also called. See ixgbe_identify_phy_82599(). The reason for the
 825          * failure is not known, and only occuts when virtualisation features
 826          * are disabled in the bios. A delay of 100ms  was found to be enough by
 827          * trial-and-error, and is doubled to be safe.
 828          */
 829         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 830                 rte_delay_ms(200);
 831                 diag = ixgbe_init_hw(hw);
 832         }
 833
 834         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 835                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 836                     "LOM.  Please be aware there may be issues associated "
 837                     "with your hardware.");
 838                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 839                     "please contact your Intel or hardware representative "
 840                     "who provided you with this hardware.");
 841         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 842                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 843         if (diag) {
 844                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 845                 return -EIO;
 846         }
 847
 848         /* disable interrupt */
 849         ixgbe_disable_intr(hw);
 850
 851         /* reset mappings for queue statistics hw counters*/
 852         ixgbe_reset_qstat_mappings(hw);
 853
 854         /* Allocate memory for storing MAC addresses */
 855         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 856                         hw->mac.num_rar_entries, 0);
 857         if (eth_dev->data->mac_addrs == NULL) {
 858                 PMD_INIT_LOG(ERR,
 859                         "Failed to allocate %u bytes needed to store "
 860                         "MAC addresses",
 861                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 862                 return -ENOMEM;
 863         }
 864         /* Copy the permanent MAC address */
 865         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 866                         &eth_dev->data->mac_addrs[0]);
 867
 868         /* Allocate memory for storing hash filter MAC addresses */
 869         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 870                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 871         if (eth_dev->data->hash_mac_addrs == NULL) {
 872                 PMD_INIT_LOG(ERR,
 873                         "Failed to allocate %d bytes needed to store MAC addresses",
 874                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 875                 return -ENOMEM;
 876         }
 877
 878         /* initialize the vfta */
 879         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 880
 881         /* initialize the hw strip bitmap*/
 882         memset(hwstrip, 0, sizeof(*hwstrip));
 883
 884         /* initialize PF if max_vfs not zero */
 885         ixgbe_pf_host_init(eth_dev);
 886
 887         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 888         /* let hardware know driver is loaded */
 889         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 890         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 891         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 892         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 893         IXGBE_WRITE_FLUSH(hw);
 894
 895         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 896                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 897                              (int) hw->mac.type, (int) hw->phy.type,
 898                              (int) hw->phy.sfp_type);
 899         else
 900                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 901                              (int) hw->mac.type, (int) hw->phy.type);
 902
 903         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 904                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 905                         pci_dev->id.device_id);
 906
 907         rte_intr_callback_register(&(pci_dev->intr_handle),
 908                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 909
 910         /* enable uio intr after callback register */
 911         rte_intr_enable(&(pci_dev->intr_handle));
 912
 913         /* enable support intr */
 914         ixgbe_enable_intr(eth_dev);
 915
 916         /* initialize 5tuple filter list */
 917         TAILQ_INIT(&filter_info->fivetuple_list);
 918         memset(filter_info->fivetuple_mask, 0,
 919                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
 920
 921         return 0;
 922 }
 923
 924
 925 /*
 926  * Negotiate mailbox API version with the PF.
 927  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 928  * Then we try to negotiate starting with the most recent one.
 929  * If all negotiation attempts fail, then we will proceed with
 930  * the default one (ixgbe_mbox_api_10).
 931  */
 932 static void
 933 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 934 {
 935         int32_t i;
 936
 937         /* start with highest supported, proceed down */
 938         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 939                 ixgbe_mbox_api_11,
 940                 ixgbe_mbox_api_10,
 941         };
 942
 943         for (i = 0;
 944                         i != RTE_DIM(sup_ver) &&
 945                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 946                         i++)
 947                 ;
 948 }
 949
 950 static void
 951 generate_random_mac_addr(struct ether_addr *mac_addr)
 952 {
 953         uint64_t random;
 954
 955         /* Set Organizationally Unique Identifier (OUI) prefix. */
 956         mac_addr->addr_bytes[0] = 0x00;
 957         mac_addr->addr_bytes[1] = 0x09;
 958         mac_addr->addr_bytes[2] = 0xC0;
 959         /* Force indication of locally assigned MAC address. */
 960         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 961         /* Generate the last 3 bytes of the MAC address with a random number. */
 962         random = rte_rand();
 963         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 964 }
 965
 966 /*
 967  * Virtual Function device init
 968  */
 969 static int
 970 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 971                      struct rte_eth_dev *eth_dev)
 972 {
 973         int diag;
 974         uint32_t tc, tcs;
 975         struct rte_pci_device *pci_dev;
 976         struct ixgbe_hw *hw =
 977                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 978         struct ixgbe_vfta * shadow_vfta =
 979                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 980         struct ixgbe_hwstrip *hwstrip =
 981                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 982         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 983
 984         PMD_INIT_FUNC_TRACE();
 985
 986         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 987         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 988         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 989
 990         /* for secondary processes, we don't initialise any further as primary
 991          * has already done this work. Only check we don't need a different
 992          * RX function */
 993         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 994                 if (eth_dev->data->scattered_rx)
 995                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 996                 return 0;
 997         }
 998
 999         pci_dev = eth_dev->pci_dev;
1000
1001         hw->device_id = pci_dev->id.device_id;
1002         hw->vendor_id = pci_dev->id.vendor_id;
1003         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1004
1005         /* initialize the vfta */
1006         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1007
1008         /* initialize the hw strip bitmap*/
1009         memset(hwstrip, 0, sizeof(*hwstrip));
1010
1011         /* Initialize the shared code (base driver) */
1012         diag = ixgbe_init_shared_code(hw);
1013         if (diag != IXGBE_SUCCESS) {
1014                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1015                 return -EIO;
1016         }
1017
1018         /* init_mailbox_params */
1019         hw->mbx.ops.init_params(hw);
1020
1021         /* Disable the interrupts for VF */
1022         ixgbevf_intr_disable(hw);
1023
1024         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1025         diag = hw->mac.ops.reset_hw(hw);
1026
1027         /*
1028          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1029          * the underlying PF driver has not assigned a MAC address to the VF.
1030          * In this case, assign a random MAC address.
1031          */
1032         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1033                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1034                 return (diag);
1035         }
1036
1037         /* negotiate mailbox API version to use with the PF. */
1038         ixgbevf_negotiate_api(hw);
1039
1040         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1041         ixgbevf_get_queues(hw, &tcs, &tc);
1042
1043         /* Allocate memory for storing MAC addresses */
1044         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1045                         hw->mac.num_rar_entries, 0);
1046         if (eth_dev->data->mac_addrs == NULL) {
1047                 PMD_INIT_LOG(ERR,
1048                         "Failed to allocate %u bytes needed to store "
1049                         "MAC addresses",
1050                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1051                 return -ENOMEM;
1052         }
1053
1054         /* Generate a random MAC address, if none was assigned by PF. */
1055         if (is_zero_ether_addr(perm_addr)) {
1056                 generate_random_mac_addr(perm_addr);
1057                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1058                 if (diag) {
1059                         rte_free(eth_dev->data->mac_addrs);
1060                         eth_dev->data->mac_addrs = NULL;
1061                         return diag;
1062                 }
1063                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1064                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1065                              "%02x:%02x:%02x:%02x:%02x:%02x",
1066                              perm_addr->addr_bytes[0],
1067                              perm_addr->addr_bytes[1],
1068                              perm_addr->addr_bytes[2],
1069                              perm_addr->addr_bytes[3],
1070                              perm_addr->addr_bytes[4],
1071                              perm_addr->addr_bytes[5]);
1072         }
1073
1074         /* Copy the permanent MAC address */
1075         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1076
1077         /* reset the hardware with the new settings */
1078         diag = hw->mac.ops.start_hw(hw);
1079         switch (diag) {
1080                 case  0:
1081                         break;
1082
1083                 default:
1084                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1085                         return (-EIO);
1086         }
1087
1088         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1089                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1090                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1091
1092         return 0;
1093 }
1094
1095 static struct eth_driver rte_ixgbe_pmd = {
1096         {
1097                 .name = "rte_ixgbe_pmd",
1098                 .id_table = pci_id_ixgbe_map,
1099                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1100         },
1101         .eth_dev_init = eth_ixgbe_dev_init,
1102         .dev_private_size = sizeof(struct ixgbe_adapter),
1103 };
1104
1105 /*
1106  * virtual function driver struct
1107  */
1108 static struct eth_driver rte_ixgbevf_pmd = {
1109         {
1110                 .name = "rte_ixgbevf_pmd",
1111                 .id_table = pci_id_ixgbevf_map,
1112                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1113         },
1114         .eth_dev_init = eth_ixgbevf_dev_init,
1115         .dev_private_size = sizeof(struct ixgbe_adapter),
1116 };
1117
1118 /*
1119  * Driver initialization routine.
1120  * Invoked once at EAL init time.
1121  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1122  */
1123 static int
1124 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1125 {
1126         PMD_INIT_FUNC_TRACE();
1127
1128         rte_eth_driver_register(&rte_ixgbe_pmd);
1129         return 0;
1130 }
1131
1132 /*
1133  * VF Driver initialization routine.
1134  * Invoked one at EAL init time.
1135  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1136  */
1137 static int
1138 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1139 {
1140         PMD_INIT_FUNC_TRACE();
1141
1142         rte_eth_driver_register(&rte_ixgbevf_pmd);
1143         return (0);
1144 }
1145
1146 static int
1147 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1148 {
1149         struct ixgbe_hw *hw =
1150                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1151         struct ixgbe_vfta * shadow_vfta =
1152                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1153         uint32_t vfta;
1154         uint32_t vid_idx;
1155         uint32_t vid_bit;
1156
1157         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1158         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1159         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1160         if (on)
1161                 vfta |= vid_bit;
1162         else
1163                 vfta &= ~vid_bit;
1164         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1165
1166         /* update local VFTA copy */
1167         shadow_vfta->vfta[vid_idx] = vfta;
1168
1169         return 0;
1170 }
1171
1172 static void
1173 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1174 {
1175         if (on)
1176                 ixgbe_vlan_hw_strip_enable(dev, queue);
1177         else
1178                 ixgbe_vlan_hw_strip_disable(dev, queue);
1179 }
1180
1181 static void
1182 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1183 {
1184         struct ixgbe_hw *hw =
1185                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1186
1187         /* Only the high 16-bits is valid */
1188         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1189 }
1190
1191 void
1192 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1193 {
1194         struct ixgbe_hw *hw =
1195                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1196         uint32_t vlnctrl;
1197
1198         PMD_INIT_FUNC_TRACE();
1199
1200         /* Filter Table Disable */
1201         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1202         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1203
1204         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1205 }
1206
1207 void
1208 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1209 {
1210         struct ixgbe_hw *hw =
1211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1212         struct ixgbe_vfta * shadow_vfta =
1213                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1214         uint32_t vlnctrl;
1215         uint16_t i;
1216
1217         PMD_INIT_FUNC_TRACE();
1218
1219         /* Filter Table Enable */
1220         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1221         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1222         vlnctrl |= IXGBE_VLNCTRL_VFE;
1223
1224         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1225
1226         /* write whatever is in local vfta copy */
1227         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1228                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1229 }
1230
1231 static void
1232 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1233 {
1234         struct ixgbe_hwstrip *hwstrip =
1235                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1236
1237         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1238                 return;
1239
1240         if (on)
1241                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1242         else
1243                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1244 }
1245
1246 static void
1247 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1248 {
1249         struct ixgbe_hw *hw =
1250                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1251         uint32_t ctrl;
1252
1253         PMD_INIT_FUNC_TRACE();
1254
1255         if (hw->mac.type == ixgbe_mac_82598EB) {
1256                 /* No queue level support */
1257                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1258                 return;
1259         }
1260         else {
1261                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1262                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1263                 ctrl &= ~IXGBE_RXDCTL_VME;
1264                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1265         }
1266         /* record those setting for HW strip per queue */
1267         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1268 }
1269
1270 static void
1271 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1272 {
1273         struct ixgbe_hw *hw =
1274                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1275         uint32_t ctrl;
1276
1277         PMD_INIT_FUNC_TRACE();
1278
1279         if (hw->mac.type == ixgbe_mac_82598EB) {
1280                 /* No queue level supported */
1281                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1282                 return;
1283         }
1284         else {
1285                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1286                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1287                 ctrl |= IXGBE_RXDCTL_VME;
1288                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1289         }
1290         /* record those setting for HW strip per queue */
1291         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1292 }
1293
1294 void
1295 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1296 {
1297         struct ixgbe_hw *hw =
1298                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1299         uint32_t ctrl;
1300         uint16_t i;
1301
1302         PMD_INIT_FUNC_TRACE();
1303
1304         if (hw->mac.type == ixgbe_mac_82598EB) {
1305                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1306                 ctrl &= ~IXGBE_VLNCTRL_VME;
1307                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1308         }
1309         else {
1310                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1311                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1312                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1313                         ctrl &= ~IXGBE_RXDCTL_VME;
1314                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1315
1316                         /* record those setting for HW strip per queue */
1317                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1318                 }
1319         }
1320 }
1321
1322 void
1323 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1324 {
1325         struct ixgbe_hw *hw =
1326                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1327         uint32_t ctrl;
1328         uint16_t i;
1329
1330         PMD_INIT_FUNC_TRACE();
1331
1332         if (hw->mac.type == ixgbe_mac_82598EB) {
1333                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1334                 ctrl |= IXGBE_VLNCTRL_VME;
1335                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1336         }
1337         else {
1338                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1339                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1340                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1341                         ctrl |= IXGBE_RXDCTL_VME;
1342                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1343
1344                         /* record those setting for HW strip per queue */
1345                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1346                 }
1347         }
1348 }
1349
1350 static void
1351 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1352 {
1353         struct ixgbe_hw *hw =
1354                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1355         uint32_t ctrl;
1356
1357         PMD_INIT_FUNC_TRACE();
1358
1359         /* DMATXCTRL: Geric Double VLAN Disable */
1360         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1361         ctrl &= ~IXGBE_DMATXCTL_GDV;
1362         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1363
1364         /* CTRL_EXT: Global Double VLAN Disable */
1365         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1366         ctrl &= ~IXGBE_EXTENDED_VLAN;
1367         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1368
1369 }
1370
1371 static void
1372 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1373 {
1374         struct ixgbe_hw *hw =
1375                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1376         uint32_t ctrl;
1377
1378         PMD_INIT_FUNC_TRACE();
1379
1380         /* DMATXCTRL: Geric Double VLAN Enable */
1381         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1382         ctrl |= IXGBE_DMATXCTL_GDV;
1383         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1384
1385         /* CTRL_EXT: Global Double VLAN Enable */
1386         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1387         ctrl |= IXGBE_EXTENDED_VLAN;
1388         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1389
1390         /*
1391          * VET EXT field in the EXVET register = 0x8100 by default
1392          * So no need to change. Same to VT field of DMATXCTL register
1393          */
1394 }
1395
1396 static void
1397 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1398 {
1399         if(mask & ETH_VLAN_STRIP_MASK){
1400                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1401                         ixgbe_vlan_hw_strip_enable_all(dev);
1402                 else
1403                         ixgbe_vlan_hw_strip_disable_all(dev);
1404         }
1405
1406         if(mask & ETH_VLAN_FILTER_MASK){
1407                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1408                         ixgbe_vlan_hw_filter_enable(dev);
1409                 else
1410                         ixgbe_vlan_hw_filter_disable(dev);
1411         }
1412
1413         if(mask & ETH_VLAN_EXTEND_MASK){
1414                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1415                         ixgbe_vlan_hw_extend_enable(dev);
1416                 else
1417                         ixgbe_vlan_hw_extend_disable(dev);
1418         }
1419 }
1420
1421 static void
1422 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1423 {
1424         struct ixgbe_hw *hw =
1425                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1427         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1428         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1429         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1430 }
1431
1432 static int
1433 ixgbe_dev_configure(struct rte_eth_dev *dev)
1434 {
1435         struct ixgbe_interrupt *intr =
1436                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1437
1438         PMD_INIT_FUNC_TRACE();
1439
1440         /* set flag to update link status after init */
1441         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1442
1443         return 0;
1444 }
1445
1446 /*
1447  * Configure device link speed and setup link.
1448  * It returns 0 on success.
1449  */
1450 static int
1451 ixgbe_dev_start(struct rte_eth_dev *dev)
1452 {
1453         struct ixgbe_hw *hw =
1454                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1455         struct ixgbe_vf_info *vfinfo =
1456                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1457         int err, link_up = 0, negotiate = 0;
1458         uint32_t speed = 0;
1459         int mask = 0;
1460         int status;
1461         uint16_t vf, idx;
1462
1463         PMD_INIT_FUNC_TRACE();
1464
1465         /* IXGBE devices don't support half duplex */
1466         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1467                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1468                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1469                              dev->data->dev_conf.link_duplex,
1470                              dev->data->port_id);
1471                 return -EINVAL;
1472         }
1473
1474         /* stop adapter */
1475         hw->adapter_stopped = FALSE;
1476         ixgbe_stop_adapter(hw);
1477
1478         /* reinitialize adapter
1479          * this calls reset and start */
1480         status = ixgbe_pf_reset_hw(hw);
1481         if (status != 0)
1482                 return -1;
1483         hw->mac.ops.start_hw(hw);
1484         hw->mac.get_link_status = true;
1485
1486         /* configure PF module if SRIOV enabled */
1487         ixgbe_pf_host_configure(dev);
1488
1489         /* initialize transmission unit */
1490         ixgbe_dev_tx_init(dev);
1491
1492         /* This can fail when allocating mbufs for descriptor rings */
1493         err = ixgbe_dev_rx_init(dev);
1494         if (err) {
1495                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1496                 goto error;
1497         }
1498
1499         err = ixgbe_dev_rxtx_start(dev);
1500         if (err < 0) {
1501                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1502                 goto error;
1503         }
1504
1505         /* Skip link setup if loopback mode is enabled for 82599. */
1506         if (hw->mac.type == ixgbe_mac_82599EB &&
1507                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1508                 goto skip_link_setup;
1509
1510         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1511                 err = hw->mac.ops.setup_sfp(hw);
1512                 if (err)
1513                         goto error;
1514         }
1515
1516         /* Turn on the laser */
1517         ixgbe_enable_tx_laser(hw);
1518
1519         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1520         if (err)
1521                 goto error;
1522         dev->data->dev_link.link_status = link_up;
1523
1524         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1525         if (err)
1526                 goto error;
1527
1528         switch(dev->data->dev_conf.link_speed) {
1529         case ETH_LINK_SPEED_AUTONEG:
1530                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1531                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1532                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1533                 break;
1534         case ETH_LINK_SPEED_100:
1535                 /*
1536                  * Invalid for 82598 but error will be detected by
1537                  * ixgbe_setup_link()
1538                  */
1539                 speed = IXGBE_LINK_SPEED_100_FULL;
1540                 break;
1541         case ETH_LINK_SPEED_1000:
1542                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1543                 break;
1544         case ETH_LINK_SPEED_10000:
1545                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1546                 break;
1547         default:
1548                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1549                              dev->data->dev_conf.link_speed,
1550                              dev->data->port_id);
1551                 goto error;
1552         }
1553
1554         err = ixgbe_setup_link(hw, speed, link_up);
1555         if (err)
1556                 goto error;
1557
1558 skip_link_setup:
1559
1560         /* check if lsc interrupt is enabled */
1561         if (dev->data->dev_conf.intr_conf.lsc != 0)
1562                 ixgbe_dev_lsc_interrupt_setup(dev);
1563
1564         /* resume enabled intr since hw reset */
1565         ixgbe_enable_intr(dev);
1566
1567         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1568                 ETH_VLAN_EXTEND_MASK;
1569         ixgbe_vlan_offload_set(dev, mask);
1570
1571         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1572                 /* Enable vlan filtering for VMDq */
1573                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1574         }
1575
1576         /* Configure DCB hw */
1577         ixgbe_configure_dcb(dev);
1578
1579         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1580                 err = ixgbe_fdir_configure(dev);
1581                 if (err)
1582                         goto error;
1583         }
1584
1585         /* Restore vf rate limit */
1586         if (vfinfo != NULL) {
1587                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1588                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1589                                 if (vfinfo[vf].tx_rate[idx] != 0)
1590                                         ixgbe_set_vf_rate_limit(dev, vf,
1591                                                 vfinfo[vf].tx_rate[idx],
1592                                                 1 << idx);
1593         }
1594
1595         ixgbe_restore_statistics_mapping(dev);
1596
1597         return (0);
1598
1599 error:
1600         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1601         ixgbe_dev_clear_queues(dev);
1602         return -EIO;
1603 }
1604
1605 /*
1606  * Stop device: disable rx and tx functions to allow for reconfiguring.
1607  */
1608 static void
1609 ixgbe_dev_stop(struct rte_eth_dev *dev)
1610 {
1611         struct rte_eth_link link;
1612         struct ixgbe_hw *hw =
1613                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614         struct ixgbe_vf_info *vfinfo =
1615                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1616         struct ixgbe_filter_info *filter_info =
1617                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1618         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1619         int vf;
1620
1621         PMD_INIT_FUNC_TRACE();
1622
1623         /* disable interrupts */
1624         ixgbe_disable_intr(hw);
1625
1626         /* reset the NIC */
1627         ixgbe_pf_reset_hw(hw);
1628         hw->adapter_stopped = FALSE;
1629
1630         /* stop adapter */
1631         ixgbe_stop_adapter(hw);
1632
1633         for (vf = 0; vfinfo != NULL &&
1634                      vf < dev->pci_dev->max_vfs; vf++)
1635                 vfinfo[vf].clear_to_send = false;
1636
1637         /* Turn off the laser */
1638         ixgbe_disable_tx_laser(hw);
1639
1640         ixgbe_dev_clear_queues(dev);
1641
1642         /* Clear stored conf */
1643         dev->data->scattered_rx = 0;
1644
1645         /* Clear recorded link status */
1646         memset(&link, 0, sizeof(link));
1647         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1648
1649         /* Remove all ntuple filters of the device */
1650         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1651              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1652                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1653                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1654                              p_5tuple, entries);
1655                 rte_free(p_5tuple);
1656         }
1657         memset(filter_info->fivetuple_mask, 0,
1658                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1659
1660 }
1661
1662 /*
1663  * Set device link up: enable tx laser.
1664  */
1665 static int
1666 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1667 {
1668         struct ixgbe_hw *hw =
1669                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1670         if (hw->mac.type == ixgbe_mac_82599EB) {
1671 #ifdef RTE_NIC_BYPASS
1672                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1673                         /* Not suported in bypass mode */
1674                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1675                                      "by device id 0x%x", hw->device_id);
1676                         return -ENOTSUP;
1677                 }
1678 #endif
1679                 /* Turn on the laser */
1680                 ixgbe_enable_tx_laser(hw);
1681                 return 0;
1682         }
1683
1684         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1685                      hw->device_id);
1686         return -ENOTSUP;
1687 }
1688
1689 /*
1690  * Set device link down: disable tx laser.
1691  */
1692 static int
1693 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1694 {
1695         struct ixgbe_hw *hw =
1696                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1697         if (hw->mac.type == ixgbe_mac_82599EB) {
1698 #ifdef RTE_NIC_BYPASS
1699                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1700                         /* Not suported in bypass mode */
1701                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1702                                      "by device id 0x%x", hw->device_id);
1703                         return -ENOTSUP;
1704                 }
1705 #endif
1706                 /* Turn off the laser */
1707                 ixgbe_disable_tx_laser(hw);
1708                 return 0;
1709         }
1710
1711         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1712                      hw->device_id);
1713         return -ENOTSUP;
1714 }
1715
1716 /*
1717  * Reest and stop device.
1718  */
1719 static void
1720 ixgbe_dev_close(struct rte_eth_dev *dev)
1721 {
1722         struct ixgbe_hw *hw =
1723                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1724
1725         PMD_INIT_FUNC_TRACE();
1726
1727         ixgbe_pf_reset_hw(hw);
1728
1729         ixgbe_dev_stop(dev);
1730         hw->adapter_stopped = 1;
1731
1732         ixgbe_disable_pcie_master(hw);
1733
1734         /* reprogram the RAR[0] in case user changed it. */
1735         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1736 }
1737
1738 /*
1739  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1740  */
1741 static void
1742 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1743 {
1744         struct ixgbe_hw *hw =
1745                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1746         struct ixgbe_hw_stats *hw_stats =
1747                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1748         uint32_t bprc, lxon, lxoff, total;
1749         uint64_t total_missed_rx, total_qbrc, total_qprc;
1750         unsigned i;
1751
1752         total_missed_rx = 0;
1753         total_qbrc = 0;
1754         total_qprc = 0;
1755
1756         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1757         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1758         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1759         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1760
1761         for (i = 0; i < 8; i++) {
1762                 uint32_t mp;
1763                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1764                 /* global total per queue */
1765                 hw_stats->mpc[i] += mp;
1766                 /* Running comprehensive total for stats display */
1767                 total_missed_rx += hw_stats->mpc[i];
1768                 if (hw->mac.type == ixgbe_mac_82598EB)
1769                         hw_stats->rnbc[i] +=
1770                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1771                 hw_stats->pxontxc[i] +=
1772                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1773                 hw_stats->pxonrxc[i] +=
1774                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1775                 hw_stats->pxofftxc[i] +=
1776                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1777                 hw_stats->pxoffrxc[i] +=
1778                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1779                 hw_stats->pxon2offc[i] +=
1780                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1781         }
1782         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1783                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1784                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1785                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1786                 hw_stats->qbrc[i] +=
1787                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1788                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1789                 hw_stats->qbtc[i] +=
1790                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1791                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1792
1793                 total_qprc += hw_stats->qprc[i];
1794                 total_qbrc += hw_stats->qbrc[i];
1795         }
1796         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1797         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1798         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1799
1800         /* Note that gprc counts missed packets */
1801         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1802
1803         if (hw->mac.type != ixgbe_mac_82598EB) {
1804                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1805                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1806                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1807                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1808                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1809                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1810                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1811                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1812         } else {
1813                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1814                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1815                 /* 82598 only has a counter in the high register */
1816                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1817                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1818                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1819         }
1820
1821         /*
1822          * Workaround: mprc hardware is incorrectly counting
1823          * broadcasts, so for now we subtract those.
1824          */
1825         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1826         hw_stats->bprc += bprc;
1827         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1828         if (hw->mac.type == ixgbe_mac_82598EB)
1829                 hw_stats->mprc -= bprc;
1830
1831         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1832         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1833         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1834         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1835         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1836         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1837
1838         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1839         hw_stats->lxontxc += lxon;
1840         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1841         hw_stats->lxofftxc += lxoff;
1842         total = lxon + lxoff;
1843
1844         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1845         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1846         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1847         hw_stats->gptc -= total;
1848         hw_stats->mptc -= total;
1849         hw_stats->ptc64 -= total;
1850         hw_stats->gotc -= total * ETHER_MIN_LEN;
1851
1852         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1853         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1854         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1855         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1856         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1857         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1858         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1859         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1860         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1861         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1862         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1863         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1864         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1865         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1866         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1867         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1868         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1869         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1870         /* Only read FCOE on 82599 */
1871         if (hw->mac.type != ixgbe_mac_82598EB) {
1872                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1873                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1874                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1875                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1876                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1877         }
1878
1879         if (stats == NULL)
1880                 return;
1881
1882         /* Fill out the rte_eth_stats statistics structure */
1883         stats->ipackets = total_qprc;
1884         stats->ibytes = total_qbrc;
1885         stats->opackets = hw_stats->gptc;
1886         stats->obytes = hw_stats->gotc;
1887         stats->imcasts = hw_stats->mprc;
1888
1889         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1890                 stats->q_ipackets[i] = hw_stats->qprc[i];
1891                 stats->q_opackets[i] = hw_stats->qptc[i];
1892                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1893                 stats->q_obytes[i] = hw_stats->qbtc[i];
1894                 stats->q_errors[i] = hw_stats->qprdc[i];
1895         }
1896
1897         /* Rx Errors */
1898         stats->ibadcrc  = hw_stats->crcerrs;
1899         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1900         stats->imissed  = total_missed_rx;
1901         stats->ierrors  = stats->ibadcrc +
1902                           stats->ibadlen +
1903                           stats->imissed +
1904                           hw_stats->illerrc + hw_stats->errbc;
1905
1906         /* Tx Errors */
1907         stats->oerrors  = 0;
1908
1909         /* XON/XOFF pause frames */
1910         stats->tx_pause_xon  = hw_stats->lxontxc;
1911         stats->rx_pause_xon  = hw_stats->lxonrxc;
1912         stats->tx_pause_xoff = hw_stats->lxofftxc;
1913         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1914
1915         /* Flow Director Stats registers */
1916         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1917         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1918         stats->fdirmatch = hw_stats->fdirmatch;
1919         stats->fdirmiss = hw_stats->fdirmiss;
1920 }
1921
1922 static void
1923 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1924 {
1925         struct ixgbe_hw_stats *stats =
1926                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1927
1928         /* HW registers are cleared on read */
1929         ixgbe_dev_stats_get(dev, NULL);
1930
1931         /* Reset software totals */
1932         memset(stats, 0, sizeof(*stats));
1933 }
1934
1935 static void
1936 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1937 {
1938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1940                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1941
1942         /* Good Rx packet, include VF loopback */
1943         UPDATE_VF_STAT(IXGBE_VFGPRC,
1944             hw_stats->last_vfgprc, hw_stats->vfgprc);
1945
1946         /* Good Rx octets, include VF loopback */
1947         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1948             hw_stats->last_vfgorc, hw_stats->vfgorc);
1949
1950         /* Good Tx packet, include VF loopback */
1951         UPDATE_VF_STAT(IXGBE_VFGPTC,
1952             hw_stats->last_vfgptc, hw_stats->vfgptc);
1953
1954         /* Good Tx octets, include VF loopback */
1955         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1956             hw_stats->last_vfgotc, hw_stats->vfgotc);
1957
1958         /* Rx Multicst Packet */
1959         UPDATE_VF_STAT(IXGBE_VFMPRC,
1960             hw_stats->last_vfmprc, hw_stats->vfmprc);
1961
1962         if (stats == NULL)
1963                 return;
1964
1965         stats->ipackets = hw_stats->vfgprc;
1966         stats->ibytes = hw_stats->vfgorc;
1967         stats->opackets = hw_stats->vfgptc;
1968         stats->obytes = hw_stats->vfgotc;
1969         stats->imcasts = hw_stats->vfmprc;
1970 }
1971
1972 static void
1973 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1974 {
1975         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1976                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1977
1978         /* Sync HW register to the last stats */
1979         ixgbevf_dev_stats_get(dev, NULL);
1980
1981         /* reset HW current stats*/
1982         hw_stats->vfgprc = 0;
1983         hw_stats->vfgorc = 0;
1984         hw_stats->vfgptc = 0;
1985         hw_stats->vfgotc = 0;
1986         hw_stats->vfmprc = 0;
1987
1988 }
1989
1990 static void
1991 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1992 {
1993         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1994
1995         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1996         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1997         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1998         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1999         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2000         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2001         dev_info->max_vfs = dev->pci_dev->max_vfs;
2002         if (hw->mac.type == ixgbe_mac_82598EB)
2003                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2004         else
2005                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2006         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2007         dev_info->rx_offload_capa =
2008                 DEV_RX_OFFLOAD_VLAN_STRIP |
2009                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2010                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2011                 DEV_RX_OFFLOAD_TCP_CKSUM;
2012         dev_info->tx_offload_capa =
2013                 DEV_TX_OFFLOAD_VLAN_INSERT |
2014                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2015                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2016                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2017                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2018                 DEV_TX_OFFLOAD_TCP_TSO;
2019
2020         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2021                 .rx_thresh = {
2022                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2023                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2024                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2025                 },
2026                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2027                 .rx_drop_en = 0,
2028         };
2029
2030         dev_info->default_txconf = (struct rte_eth_txconf) {
2031                 .tx_thresh = {
2032                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2033                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2034                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2035                 },
2036                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2037                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2038                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2039                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2040         };
2041         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2042         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2043 }
2044
2045 static void
2046 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2047                      struct rte_eth_dev_info *dev_info)
2048 {
2049         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2050
2051         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2052         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2053         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2054         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2055         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2056         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2057         dev_info->max_vfs = dev->pci_dev->max_vfs;
2058         if (hw->mac.type == ixgbe_mac_82598EB)
2059                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2060         else
2061                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2062         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2063                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2064                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2065                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2066         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2067                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2068                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2069                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2070                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2071
2072         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2073                 .rx_thresh = {
2074                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2075                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2076                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2077                 },
2078                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2079                 .rx_drop_en = 0,
2080         };
2081
2082         dev_info->default_txconf = (struct rte_eth_txconf) {
2083                 .tx_thresh = {
2084                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2085                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2086                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2087                 },
2088                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2089                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2090                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2091                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2092         };
2093 }
2094
2095 /* return 0 means link status changed, -1 means not changed */
2096 static int
2097 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2098 {
2099         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100         struct rte_eth_link link, old;
2101         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2102         int link_up;
2103         int diag;
2104
2105         link.link_status = 0;
2106         link.link_speed = 0;
2107         link.link_duplex = 0;
2108         memset(&old, 0, sizeof(old));
2109         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2110
2111         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2112         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2113                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2114         else
2115                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2116         if (diag != 0) {
2117                 link.link_speed = ETH_LINK_SPEED_100;
2118                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2119                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2120                 if (link.link_status == old.link_status)
2121                         return -1;
2122                 return 0;
2123         }
2124
2125         if (link_speed == IXGBE_LINK_SPEED_UNKNOWN &&
2126             !hw->mac.get_link_status) {
2127                 memcpy(&link, &old, sizeof(link));
2128                 return -1;
2129         }
2130
2131         if (link_up == 0) {
2132                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2133                 if (link.link_status == old.link_status)
2134                         return -1;
2135                 return 0;
2136         }
2137         link.link_status = 1;
2138         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2139
2140         switch (link_speed) {
2141         default:
2142         case IXGBE_LINK_SPEED_UNKNOWN:
2143                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2144                 link.link_speed = ETH_LINK_SPEED_100;
2145                 break;
2146
2147         case IXGBE_LINK_SPEED_100_FULL:
2148                 link.link_speed = ETH_LINK_SPEED_100;
2149                 break;
2150
2151         case IXGBE_LINK_SPEED_1GB_FULL:
2152                 link.link_speed = ETH_LINK_SPEED_1000;
2153                 break;
2154
2155         case IXGBE_LINK_SPEED_10GB_FULL:
2156                 link.link_speed = ETH_LINK_SPEED_10000;
2157                 break;
2158         }
2159         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2160
2161         if (link.link_status == old.link_status)
2162                 return -1;
2163
2164         return 0;
2165 }
2166
2167 static void
2168 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2169 {
2170         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2171         uint32_t fctrl;
2172
2173         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2174         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2175         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2176 }
2177
2178 static void
2179 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2180 {
2181         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182         uint32_t fctrl;
2183
2184         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2185         fctrl &= (~IXGBE_FCTRL_UPE);
2186         if (dev->data->all_multicast == 1)
2187                 fctrl |= IXGBE_FCTRL_MPE;
2188         else
2189                 fctrl &= (~IXGBE_FCTRL_MPE);
2190         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2191 }
2192
2193 static void
2194 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2195 {
2196         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2197         uint32_t fctrl;
2198
2199         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2200         fctrl |= IXGBE_FCTRL_MPE;
2201         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2202 }
2203
2204 static void
2205 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2206 {
2207         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2208         uint32_t fctrl;
2209
2210         if (dev->data->promiscuous == 1)
2211                 return; /* must remain in all_multicast mode */
2212
2213         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2214         fctrl &= (~IXGBE_FCTRL_MPE);
2215         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2216 }
2217
2218 /**
2219  * It clears the interrupt causes and enables the interrupt.
2220  * It will be called once only during nic initialized.
2221  *
2222  * @param dev
2223  *  Pointer to struct rte_eth_dev.
2224  *
2225  * @return
2226  *  - On success, zero.
2227  *  - On failure, a negative value.
2228  */
2229 static int
2230 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2231 {
2232         struct ixgbe_interrupt *intr =
2233                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2234
2235         ixgbe_dev_link_status_print(dev);
2236         intr->mask |= IXGBE_EICR_LSC;
2237
2238         return 0;
2239 }
2240
2241 /*
2242  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2243  *
2244  * @param dev
2245  *  Pointer to struct rte_eth_dev.
2246  *
2247  * @return
2248  *  - On success, zero.
2249  *  - On failure, a negative value.
2250  */
2251 static int
2252 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2253 {
2254         uint32_t eicr;
2255         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2256         struct ixgbe_interrupt *intr =
2257                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2258
2259         /* clear all cause mask */
2260         ixgbe_disable_intr(hw);
2261
2262         /* read-on-clear nic registers here */
2263         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2264         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2265
2266         intr->flags = 0;
2267         if (eicr & IXGBE_EICR_LSC) {
2268                 /* set flag for async link update */
2269                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2270         }
2271
2272         if (eicr & IXGBE_EICR_MAILBOX)
2273                 intr->flags |= IXGBE_FLAG_MAILBOX;
2274
2275         return 0;
2276 }
2277
2278 /**
2279  * It gets and then prints the link status.
2280  *
2281  * @param dev
2282  *  Pointer to struct rte_eth_dev.
2283  *
2284  * @return
2285  *  - On success, zero.
2286  *  - On failure, a negative value.
2287  */
2288 static void
2289 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2290 {
2291         struct rte_eth_link link;
2292
2293         memset(&link, 0, sizeof(link));
2294         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2295         if (link.link_status) {
2296                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2297                                         (int)(dev->data->port_id),
2298                                         (unsigned)link.link_speed,
2299                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2300                                         "full-duplex" : "half-duplex");
2301         } else {
2302                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2303                                 (int)(dev->data->port_id));
2304         }
2305         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2306                                 dev->pci_dev->addr.domain,
2307                                 dev->pci_dev->addr.bus,
2308                                 dev->pci_dev->addr.devid,
2309                                 dev->pci_dev->addr.function);
2310 }
2311
2312 /*
2313  * It executes link_update after knowing an interrupt occurred.
2314  *
2315  * @param dev
2316  *  Pointer to struct rte_eth_dev.
2317  *
2318  * @return
2319  *  - On success, zero.
2320  *  - On failure, a negative value.
2321  */
2322 static int
2323 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2324 {
2325         struct ixgbe_interrupt *intr =
2326                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2327         int64_t timeout;
2328         struct rte_eth_link link;
2329         int intr_enable_delay = false;
2330
2331         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2332
2333         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2334                 ixgbe_pf_mbx_process(dev);
2335                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2336         }
2337
2338         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2339                 /* get the link status before link update, for predicting later */
2340                 memset(&link, 0, sizeof(link));
2341                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2342
2343                 ixgbe_dev_link_update(dev, 0);
2344
2345                 /* likely to up */
2346                 if (!link.link_status)
2347                         /* handle it 1 sec later, wait it being stable */
2348                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2349                 /* likely to down */
2350                 else
2351                         /* handle it 4 sec later, wait it being stable */
2352                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2353
2354                 ixgbe_dev_link_status_print(dev);
2355
2356                 intr_enable_delay = true;
2357         }
2358
2359         if (intr_enable_delay) {
2360                 if (rte_eal_alarm_set(timeout * 1000,
2361                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2362                         PMD_DRV_LOG(ERR, "Error setting alarm");
2363         } else {
2364                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2365                 ixgbe_enable_intr(dev);
2366                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2367         }
2368
2369
2370         return 0;
2371 }
2372
2373 /**
2374  * Interrupt handler which shall be registered for alarm callback for delayed
2375  * handling specific interrupt to wait for the stable nic state. As the
2376  * NIC interrupt state is not stable for ixgbe after link is just down,
2377  * it needs to wait 4 seconds to get the stable status.
2378  *
2379  * @param handle
2380  *  Pointer to interrupt handle.
2381  * @param param
2382  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2383  *
2384  * @return
2385  *  void
2386  */
2387 static void
2388 ixgbe_dev_interrupt_delayed_handler(void *param)
2389 {
2390         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2391         struct ixgbe_interrupt *intr =
2392                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2393         struct ixgbe_hw *hw =
2394                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2395         uint32_t eicr;
2396
2397         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2398         if (eicr & IXGBE_EICR_MAILBOX)
2399                 ixgbe_pf_mbx_process(dev);
2400
2401         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2402                 ixgbe_dev_link_update(dev, 0);
2403                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2404                 ixgbe_dev_link_status_print(dev);
2405                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2406         }
2407
2408         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2409         ixgbe_enable_intr(dev);
2410         rte_intr_enable(&(dev->pci_dev->intr_handle));
2411 }
2412
2413 /**
2414  * Interrupt handler triggered by NIC  for handling
2415  * specific interrupt.
2416  *
2417  * @param handle
2418  *  Pointer to interrupt handle.
2419  * @param param
2420  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2421  *
2422  * @return
2423  *  void
2424  */
2425 static void
2426 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2427                                                         void *param)
2428 {
2429         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2430         ixgbe_dev_interrupt_get_status(dev);
2431         ixgbe_dev_interrupt_action(dev);
2432 }
2433
2434 static int
2435 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2436 {
2437         struct ixgbe_hw *hw;
2438
2439         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2440         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2441 }
2442
2443 static int
2444 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2445 {
2446         struct ixgbe_hw *hw;
2447
2448         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2449         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2450 }
2451
2452 static int
2453 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2454 {
2455         struct ixgbe_hw *hw;
2456         uint32_t mflcn_reg;
2457         uint32_t fccfg_reg;
2458         int rx_pause;
2459         int tx_pause;
2460
2461         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2462
2463         fc_conf->pause_time = hw->fc.pause_time;
2464         fc_conf->high_water = hw->fc.high_water[0];
2465         fc_conf->low_water = hw->fc.low_water[0];
2466         fc_conf->send_xon = hw->fc.send_xon;
2467         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2468
2469         /*
2470          * Return rx_pause status according to actual setting of
2471          * MFLCN register.
2472          */
2473         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2474         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2475                 rx_pause = 1;
2476         else
2477                 rx_pause = 0;
2478
2479         /*
2480          * Return tx_pause status according to actual setting of
2481          * FCCFG register.
2482          */
2483         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2484         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2485                 tx_pause = 1;
2486         else
2487                 tx_pause = 0;
2488
2489         if (rx_pause && tx_pause)
2490                 fc_conf->mode = RTE_FC_FULL;
2491         else if (rx_pause)
2492                 fc_conf->mode = RTE_FC_RX_PAUSE;
2493         else if (tx_pause)
2494                 fc_conf->mode = RTE_FC_TX_PAUSE;
2495         else
2496                 fc_conf->mode = RTE_FC_NONE;
2497
2498         return 0;
2499 }
2500
2501 static int
2502 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2503 {
2504         struct ixgbe_hw *hw;
2505         int err;
2506         uint32_t rx_buf_size;
2507         uint32_t max_high_water;
2508         uint32_t mflcn;
2509         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2510                 ixgbe_fc_none,
2511                 ixgbe_fc_rx_pause,
2512                 ixgbe_fc_tx_pause,
2513                 ixgbe_fc_full
2514         };
2515
2516         PMD_INIT_FUNC_TRACE();
2517
2518         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2519         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2520                 return -ENOTSUP;
2521         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2522         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2523
2524         /*
2525          * At least reserve one Ethernet frame for watermark
2526          * high_water/low_water in kilo bytes for ixgbe
2527          */
2528         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2529         if ((fc_conf->high_water > max_high_water) ||
2530                 (fc_conf->high_water < fc_conf->low_water)) {
2531                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2532                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2533                 return (-EINVAL);
2534         }
2535
2536         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2537         hw->fc.pause_time     = fc_conf->pause_time;
2538         hw->fc.high_water[0]  = fc_conf->high_water;
2539         hw->fc.low_water[0]   = fc_conf->low_water;
2540         hw->fc.send_xon       = fc_conf->send_xon;
2541
2542         err = ixgbe_fc_enable(hw);
2543
2544         /* Not negotiated is not an error case */
2545         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2546
2547                 /* check if we want to forward MAC frames - driver doesn't have native
2548                  * capability to do that, so we'll write the registers ourselves */
2549
2550                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2551
2552                 /* set or clear MFLCN.PMCF bit depending on configuration */
2553                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2554                         mflcn |= IXGBE_MFLCN_PMCF;
2555                 else
2556                         mflcn &= ~IXGBE_MFLCN_PMCF;
2557
2558                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2559                 IXGBE_WRITE_FLUSH(hw);
2560
2561                 return 0;
2562         }
2563
2564         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2565         return -EIO;
2566 }
2567
2568 /**
2569  *  ixgbe_pfc_enable_generic - Enable flow control
2570  *  @hw: pointer to hardware structure
2571  *  @tc_num: traffic class number
2572  *  Enable flow control according to the current settings.
2573  */
2574 static int
2575 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2576 {
2577         int ret_val = 0;
2578         uint32_t mflcn_reg, fccfg_reg;
2579         uint32_t reg;
2580         uint32_t fcrtl, fcrth;
2581         uint8_t i;
2582         uint8_t nb_rx_en;
2583
2584         /* Validate the water mark configuration */
2585         if (!hw->fc.pause_time) {
2586                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2587                 goto out;
2588         }
2589
2590         /* Low water mark of zero causes XOFF floods */
2591         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2592                  /* High/Low water can not be 0 */
2593                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2594                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2595                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2596                         goto out;
2597                 }
2598
2599                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2600                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2601                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2602                         goto out;
2603                 }
2604         }
2605         /* Negotiate the fc mode to use */
2606         ixgbe_fc_autoneg(hw);
2607
2608         /* Disable any previous flow control settings */
2609         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2610         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2611
2612         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2613         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2614
2615         switch (hw->fc.current_mode) {
2616         case ixgbe_fc_none:
2617                 /*
2618                  * If the count of enabled RX Priority Flow control >1,
2619                  * and the TX pause can not be disabled
2620                  */
2621                 nb_rx_en = 0;
2622                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2623                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2624                         if (reg & IXGBE_FCRTH_FCEN)
2625                                 nb_rx_en++;
2626                 }
2627                 if (nb_rx_en > 1)
2628                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2629                 break;
2630         case ixgbe_fc_rx_pause:
2631                 /*
2632                  * Rx Flow control is enabled and Tx Flow control is
2633                  * disabled by software override. Since there really
2634                  * isn't a way to advertise that we are capable of RX
2635                  * Pause ONLY, we will advertise that we support both
2636                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2637                  * disable the adapter's ability to send PAUSE frames.
2638                  */
2639                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2640                 /*
2641                  * If the count of enabled RX Priority Flow control >1,
2642                  * and the TX pause can not be disabled
2643                  */
2644                 nb_rx_en = 0;
2645                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2646                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2647                         if (reg & IXGBE_FCRTH_FCEN)
2648                                 nb_rx_en++;
2649                 }
2650                 if (nb_rx_en > 1)
2651                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2652                 break;
2653         case ixgbe_fc_tx_pause:
2654                 /*
2655                  * Tx Flow control is enabled, and Rx Flow control is
2656                  * disabled by software override.
2657                  */
2658                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2659                 break;
2660         case ixgbe_fc_full:
2661                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2662                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2663                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2664                 break;
2665         default:
2666                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2667                 ret_val = IXGBE_ERR_CONFIG;
2668                 goto out;
2669                 break;
2670         }
2671
2672         /* Set 802.3x based flow control settings. */
2673         mflcn_reg |= IXGBE_MFLCN_DPF;
2674         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2675         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2676
2677         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2678         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2679                 hw->fc.high_water[tc_num]) {
2680                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2681                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2682                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2683         } else {
2684                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2685                 /*
2686                  * In order to prevent Tx hangs when the internal Tx
2687                  * switch is enabled we must set the high water mark
2688                  * to the maximum FCRTH value.  This allows the Tx
2689                  * switch to function even under heavy Rx workloads.
2690                  */
2691                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2692         }
2693         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2694
2695         /* Configure pause time (2 TCs per register) */
2696         reg = hw->fc.pause_time * 0x00010001;
2697         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2698                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2699
2700         /* Configure flow control refresh threshold value */
2701         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2702
2703 out:
2704         return ret_val;
2705 }
2706
2707 static int
2708 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2709 {
2710         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2711         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2712
2713         if(hw->mac.type != ixgbe_mac_82598EB) {
2714                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2715         }
2716         return ret_val;
2717 }
2718
2719 static int
2720 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2721 {
2722         int err;
2723         uint32_t rx_buf_size;
2724         uint32_t max_high_water;
2725         uint8_t tc_num;
2726         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2727         struct ixgbe_hw *hw =
2728                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2729         struct ixgbe_dcb_config *dcb_config =
2730                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2731
2732         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2733                 ixgbe_fc_none,
2734                 ixgbe_fc_rx_pause,
2735                 ixgbe_fc_tx_pause,
2736                 ixgbe_fc_full
2737         };
2738
2739         PMD_INIT_FUNC_TRACE();
2740
2741         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2742         tc_num = map[pfc_conf->priority];
2743         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2744         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2745         /*
2746          * At least reserve one Ethernet frame for watermark
2747          * high_water/low_water in kilo bytes for ixgbe
2748          */
2749         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2750         if ((pfc_conf->fc.high_water > max_high_water) ||
2751             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2752                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2753                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2754                 return (-EINVAL);
2755         }
2756
2757         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2758         hw->fc.pause_time = pfc_conf->fc.pause_time;
2759         hw->fc.send_xon = pfc_conf->fc.send_xon;
2760         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2761         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2762
2763         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2764
2765         /* Not negotiated is not an error case */
2766         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2767                 return 0;
2768
2769         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2770         return -EIO;
2771 }
2772
2773 static int
2774 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2775                           struct rte_eth_rss_reta_entry64 *reta_conf,
2776                           uint16_t reta_size)
2777 {
2778         uint8_t i, j, mask;
2779         uint32_t reta, r;
2780         uint16_t idx, shift;
2781         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782
2783         PMD_INIT_FUNC_TRACE();
2784         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2785                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2786                         "(%d) doesn't match the number hardware can supported "
2787                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2788                 return -EINVAL;
2789         }
2790
2791         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2792                 idx = i / RTE_RETA_GROUP_SIZE;
2793                 shift = i % RTE_RETA_GROUP_SIZE;
2794                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2795                                                 IXGBE_4_BIT_MASK);
2796                 if (!mask)
2797                         continue;
2798                 if (mask == IXGBE_4_BIT_MASK)
2799                         r = 0;
2800                 else
2801                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2802                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2803                         if (mask & (0x1 << j))
2804                                 reta |= reta_conf[idx].reta[shift + j] <<
2805                                                         (CHAR_BIT * j);
2806                         else
2807                                 reta |= r & (IXGBE_8_BIT_MASK <<
2808                                                 (CHAR_BIT * j));
2809                 }
2810                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2811         }
2812
2813         return 0;
2814 }
2815
2816 static int
2817 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2818                          struct rte_eth_rss_reta_entry64 *reta_conf,
2819                          uint16_t reta_size)
2820 {
2821         uint8_t i, j, mask;
2822         uint32_t reta;
2823         uint16_t idx, shift;
2824         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2825
2826         PMD_INIT_FUNC_TRACE();
2827         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2828                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2829                         "(%d) doesn't match the number hardware can supported "
2830                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2831                 return -EINVAL;
2832         }
2833
2834         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2835                 idx = i / RTE_RETA_GROUP_SIZE;
2836                 shift = i % RTE_RETA_GROUP_SIZE;
2837                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2838                                                 IXGBE_4_BIT_MASK);
2839                 if (!mask)
2840                         continue;
2841
2842                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2843                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2844                         if (mask & (0x1 << j))
2845                                 reta_conf[idx].reta[shift + j] =
2846                                         ((reta >> (CHAR_BIT * j)) &
2847                                                 IXGBE_8_BIT_MASK);
2848                 }
2849         }
2850
2851         return 0;
2852 }
2853
2854 static void
2855 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2856                                 uint32_t index, uint32_t pool)
2857 {
2858         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2859         uint32_t enable_addr = 1;
2860
2861         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2862 }
2863
2864 static void
2865 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2866 {
2867         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2868
2869         ixgbe_clear_rar(hw, index);
2870 }
2871
2872 static int
2873 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2874 {
2875         uint32_t hlreg0;
2876         uint32_t maxfrs;
2877         struct ixgbe_hw *hw;
2878         struct rte_eth_dev_info dev_info;
2879         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2880
2881         ixgbe_dev_info_get(dev, &dev_info);
2882
2883         /* check that mtu is within the allowed range */
2884         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2885                 return -EINVAL;
2886
2887         /* refuse mtu that requires the support of scattered packets when this
2888          * feature has not been enabled before. */
2889         if (!dev->data->scattered_rx &&
2890             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2891              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2892                 return -EINVAL;
2893
2894         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2895         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2896
2897         /* switch to jumbo mode if needed */
2898         if (frame_size > ETHER_MAX_LEN) {
2899                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2900                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2901         } else {
2902                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2903                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2904         }
2905         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2906
2907         /* update max frame size */
2908         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2909
2910         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2911         maxfrs &= 0x0000FFFF;
2912         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2913         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2914
2915         return 0;
2916 }
2917
2918 /*
2919  * Virtual Function operations
2920  */
2921 static void
2922 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2923 {
2924         PMD_INIT_FUNC_TRACE();
2925
2926         /* Clear interrupt mask to stop from interrupts being generated */
2927         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2928
2929         IXGBE_WRITE_FLUSH(hw);
2930 }
2931
2932 static int
2933 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2934 {
2935         struct rte_eth_conf* conf = &dev->data->dev_conf;
2936
2937         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2938                      dev->data->port_id);
2939
2940         /*
2941          * VF has no ability to enable/disable HW CRC
2942          * Keep the persistent behavior the same as Host PF
2943          */
2944 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2945         if (!conf->rxmode.hw_strip_crc) {
2946                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2947                 conf->rxmode.hw_strip_crc = 1;
2948         }
2949 #else
2950         if (conf->rxmode.hw_strip_crc) {
2951                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2952                 conf->rxmode.hw_strip_crc = 0;
2953         }
2954 #endif
2955
2956         return 0;
2957 }
2958
2959 static int
2960 ixgbevf_dev_start(struct rte_eth_dev *dev)
2961 {
2962         struct ixgbe_hw *hw =
2963                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2964         int err, mask = 0;
2965
2966         PMD_INIT_FUNC_TRACE();
2967
2968         hw->mac.ops.reset_hw(hw);
2969         hw->mac.get_link_status = true;
2970
2971         /* negotiate mailbox API version to use with the PF. */
2972         ixgbevf_negotiate_api(hw);
2973
2974         ixgbevf_dev_tx_init(dev);
2975
2976         /* This can fail when allocating mbufs for descriptor rings */
2977         err = ixgbevf_dev_rx_init(dev);
2978         if (err) {
2979                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2980                 ixgbe_dev_clear_queues(dev);
2981                 return err;
2982         }
2983
2984         /* Set vfta */
2985         ixgbevf_set_vfta_all(dev,1);
2986
2987         /* Set HW strip */
2988         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2989                 ETH_VLAN_EXTEND_MASK;
2990         ixgbevf_vlan_offload_set(dev, mask);
2991
2992         ixgbevf_dev_rxtx_start(dev);
2993
2994         return 0;
2995 }
2996
2997 static void
2998 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2999 {
3000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3001
3002         PMD_INIT_FUNC_TRACE();
3003
3004         hw->adapter_stopped = TRUE;
3005         ixgbe_stop_adapter(hw);
3006
3007         /*
3008           * Clear what we set, but we still keep shadow_vfta to
3009           * restore after device starts
3010           */
3011         ixgbevf_set_vfta_all(dev,0);
3012
3013         /* Clear stored conf */
3014         dev->data->scattered_rx = 0;
3015
3016         ixgbe_dev_clear_queues(dev);
3017 }
3018
3019 static void
3020 ixgbevf_dev_close(struct rte_eth_dev *dev)
3021 {
3022         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3023
3024         PMD_INIT_FUNC_TRACE();
3025
3026         ixgbe_reset_hw(hw);
3027
3028         ixgbevf_dev_stop(dev);
3029
3030         /* reprogram the RAR[0] in case user changed it. */
3031         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3032 }
3033
3034 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3035 {
3036         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3037         struct ixgbe_vfta * shadow_vfta =
3038                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3039         int i = 0, j = 0, vfta = 0, mask = 1;
3040
3041         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3042                 vfta = shadow_vfta->vfta[i];
3043                 if(vfta){
3044                         mask = 1;
3045                         for (j = 0; j < 32; j++){
3046                                 if(vfta & mask)
3047                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3048                                 mask<<=1;
3049                         }
3050                 }
3051         }
3052
3053 }
3054
3055 static int
3056 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3057 {
3058         struct ixgbe_hw *hw =
3059                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3060         struct ixgbe_vfta * shadow_vfta =
3061                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3062         uint32_t vid_idx = 0;
3063         uint32_t vid_bit = 0;
3064         int ret = 0;
3065
3066         PMD_INIT_FUNC_TRACE();
3067
3068         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3069         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3070         if(ret){
3071                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3072                 return ret;
3073         }
3074         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3075         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3076
3077         /* Save what we set and retore it after device reset */
3078         if (on)
3079                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3080         else
3081                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3082
3083         return 0;
3084 }
3085
3086 static void
3087 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3088 {
3089         struct ixgbe_hw *hw =
3090                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3091         uint32_t ctrl;
3092
3093         PMD_INIT_FUNC_TRACE();
3094
3095         if(queue >= hw->mac.max_rx_queues)
3096                 return;
3097
3098         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3099         if(on)
3100                 ctrl |= IXGBE_RXDCTL_VME;
3101         else
3102                 ctrl &= ~IXGBE_RXDCTL_VME;
3103         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3104
3105         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3106 }
3107
3108 static void
3109 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3110 {
3111         struct ixgbe_hw *hw =
3112                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3113         uint16_t i;
3114         int on = 0;
3115
3116         /* VF function only support hw strip feature, others are not support */
3117         if(mask & ETH_VLAN_STRIP_MASK){
3118                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3119
3120                 for(i=0; i < hw->mac.max_rx_queues; i++)
3121                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3122         }
3123 }
3124
3125 static int
3126 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3127 {
3128         uint32_t reg_val;
3129
3130         /* we only need to do this if VMDq is enabled */
3131         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3132         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3133                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3134                 return (-1);
3135         }
3136
3137         return 0;
3138 }
3139
3140 static uint32_t
3141 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3142 {
3143         uint32_t vector = 0;
3144         switch (hw->mac.mc_filter_type) {
3145         case 0:   /* use bits [47:36] of the address */
3146                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3147                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3148                 break;
3149         case 1:   /* use bits [46:35] of the address */
3150                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3151                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3152                 break;
3153         case 2:   /* use bits [45:34] of the address */
3154                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3155                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3156                 break;
3157         case 3:   /* use bits [43:32] of the address */
3158                 vector = ((uc_addr->addr_bytes[4]) |
3159                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3160                 break;
3161         default:  /* Invalid mc_filter_type */
3162                 break;
3163         }
3164
3165         /* vector can only be 12-bits or boundary will be exceeded */
3166         vector &= 0xFFF;
3167         return vector;
3168 }
3169
3170 static int
3171 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3172                                uint8_t on)
3173 {
3174         uint32_t vector;
3175         uint32_t uta_idx;
3176         uint32_t reg_val;
3177         uint32_t uta_shift;
3178         uint32_t rc;
3179         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3180         const uint32_t ixgbe_uta_bit_shift = 5;
3181         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3182         const uint32_t bit1 = 0x1;
3183
3184         struct ixgbe_hw *hw =
3185                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3186         struct ixgbe_uta_info *uta_info =
3187                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3188
3189         /* The UTA table only exists on 82599 hardware and newer */
3190         if (hw->mac.type < ixgbe_mac_82599EB)
3191                 return (-ENOTSUP);
3192
3193         vector = ixgbe_uta_vector(hw,mac_addr);
3194         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3195         uta_shift = vector & ixgbe_uta_bit_mask;
3196
3197         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3198         if(rc == on)
3199                 return 0;
3200
3201         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3202         if (on) {
3203                 uta_info->uta_in_use++;
3204                 reg_val |= (bit1 << uta_shift);
3205                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3206         } else {
3207                 uta_info->uta_in_use--;
3208                 reg_val &= ~(bit1 << uta_shift);
3209                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3210         }
3211
3212         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3213
3214         if (uta_info->uta_in_use > 0)
3215                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3216                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3217         else
3218                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3219
3220         return 0;
3221 }
3222
3223 static int
3224 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3225 {
3226         int i;
3227         struct ixgbe_hw *hw =
3228                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3229         struct ixgbe_uta_info *uta_info =
3230                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3231
3232         /* The UTA table only exists on 82599 hardware and newer */
3233         if (hw->mac.type < ixgbe_mac_82599EB)
3234                 return (-ENOTSUP);
3235
3236         if(on) {
3237                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3238                         uta_info->uta_shadow[i] = ~0;
3239                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3240                 }
3241         } else {
3242                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3243                         uta_info->uta_shadow[i] = 0;
3244                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3245                 }
3246         }
3247         return 0;
3248
3249 }
3250
3251 uint32_t
3252 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3253 {
3254         uint32_t new_val = orig_val;
3255
3256         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3257                 new_val |= IXGBE_VMOLR_AUPE;
3258         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3259                 new_val |= IXGBE_VMOLR_ROMPE;
3260         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3261                 new_val |= IXGBE_VMOLR_ROPE;
3262         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3263                 new_val |= IXGBE_VMOLR_BAM;
3264         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3265                 new_val |= IXGBE_VMOLR_MPE;
3266
3267         return new_val;
3268 }
3269
3270 static int
3271 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3272                                uint16_t rx_mask, uint8_t on)
3273 {
3274         int val = 0;
3275
3276         struct ixgbe_hw *hw =
3277                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3278         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3279
3280         if (hw->mac.type == ixgbe_mac_82598EB) {
3281                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3282                              " on 82599 hardware and newer");
3283                 return (-ENOTSUP);
3284         }
3285         if (ixgbe_vmdq_mode_check(hw) < 0)
3286                 return (-ENOTSUP);
3287
3288         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3289
3290         if (on)
3291                 vmolr |= val;
3292         else
3293                 vmolr &= ~val;
3294
3295         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3296
3297         return 0;
3298 }
3299
3300 static int
3301 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3302 {
3303         uint32_t reg,addr;
3304         uint32_t val;
3305         const uint8_t bit1 = 0x1;
3306
3307         struct ixgbe_hw *hw =
3308                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3309
3310         if (ixgbe_vmdq_mode_check(hw) < 0)
3311                 return (-ENOTSUP);
3312
3313         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3314         reg = IXGBE_READ_REG(hw, addr);
3315         val = bit1 << pool;
3316
3317         if (on)
3318                 reg |= val;
3319         else
3320                 reg &= ~val;
3321
3322         IXGBE_WRITE_REG(hw, addr,reg);
3323
3324         return 0;
3325 }
3326
3327 static int
3328 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3329 {
3330         uint32_t reg,addr;
3331         uint32_t val;
3332         const uint8_t bit1 = 0x1;
3333
3334         struct ixgbe_hw *hw =
3335                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3336
3337         if (ixgbe_vmdq_mode_check(hw) < 0)
3338                 return (-ENOTSUP);
3339
3340         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3341         reg = IXGBE_READ_REG(hw, addr);
3342         val = bit1 << pool;
3343
3344         if (on)
3345                 reg |= val;
3346         else
3347                 reg &= ~val;
3348
3349         IXGBE_WRITE_REG(hw, addr,reg);
3350
3351         return 0;
3352 }
3353
3354 static int
3355 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3356                         uint64_t pool_mask, uint8_t vlan_on)
3357 {
3358         int ret = 0;
3359         uint16_t pool_idx;
3360         struct ixgbe_hw *hw =
3361                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3362
3363         if (ixgbe_vmdq_mode_check(hw) < 0)
3364                 return (-ENOTSUP);
3365         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3366                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3367                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3368                         if (ret < 0)
3369                                 return ret;
3370         }
3371
3372         return ret;
3373 }
3374
3375 static int
3376 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3377                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3378                         uint8_t rule_id, uint8_t on)
3379 {
3380         uint32_t mr_ctl,vlvf;
3381         uint32_t mp_lsb = 0;
3382         uint32_t mv_msb = 0;
3383         uint32_t mv_lsb = 0;
3384         uint32_t mp_msb = 0;
3385         uint8_t i = 0;
3386         int reg_index = 0;
3387         uint64_t vlan_mask = 0;
3388
3389         const uint8_t pool_mask_offset = 32;
3390         const uint8_t vlan_mask_offset = 32;
3391         const uint8_t dst_pool_offset = 8;
3392         const uint8_t rule_mr_offset  = 4;
3393         const uint8_t mirror_rule_mask= 0x0F;
3394
3395         struct ixgbe_mirror_info *mr_info =
3396                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3397         struct ixgbe_hw *hw =
3398                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3399
3400         if (ixgbe_vmdq_mode_check(hw) < 0)
3401                 return (-ENOTSUP);
3402
3403         /* Check if vlan mask is valid */
3404         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3405                 if (mirror_conf->vlan.vlan_mask == 0)
3406                         return (-EINVAL);
3407         }
3408
3409         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3410         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3411                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3412                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3413                                 /* search vlan id related pool vlan filter index */
3414                                 reg_index = ixgbe_find_vlvf_slot(hw,
3415                                                 mirror_conf->vlan.vlan_id[i]);
3416                                 if(reg_index < 0)
3417                                         return (-EINVAL);
3418                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3419                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3420                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3421                                                 == mirror_conf->vlan.vlan_id[i]))
3422                                         vlan_mask |= (1ULL << reg_index);
3423                                 else
3424                                         return (-EINVAL);
3425                         }
3426                 }
3427
3428                 if (on) {
3429                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3430                         mv_msb = vlan_mask >> vlan_mask_offset;
3431
3432                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3433                                                 mirror_conf->vlan.vlan_mask;
3434                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3435                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3436                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3437                                                 mirror_conf->vlan.vlan_id[i];
3438                         }
3439                 } else {
3440                         mv_lsb = 0;
3441                         mv_msb = 0;
3442                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3443                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3444                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3445                 }
3446         }
3447
3448         /*
3449          * if enable pool mirror, write related pool mask register,if disable
3450          * pool mirror, clear PFMRVM register
3451          */
3452         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3453                 if (on) {
3454                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3455                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3456                         mr_info->mr_conf[rule_id].pool_mask =
3457                                         mirror_conf->pool_mask;
3458
3459                 } else {
3460                         mp_lsb = 0;
3461                         mp_msb = 0;
3462                         mr_info->mr_conf[rule_id].pool_mask = 0;
3463                 }
3464         }
3465
3466         /* read  mirror control register and recalculate it */
3467         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3468
3469         if (on) {
3470                 mr_ctl |= mirror_conf->rule_type_mask;
3471                 mr_ctl &= mirror_rule_mask;
3472                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3473         } else
3474                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3475
3476         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3477         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3478
3479         /* write mirrror control  register */
3480         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3481
3482         /* write pool mirrror control  register */
3483         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3484                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3485                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3486                                 mp_msb);
3487         }
3488         /* write VLAN mirrror control  register */
3489         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3490                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3491                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3492                                 mv_msb);
3493         }
3494
3495         return 0;
3496 }
3497
3498 static int
3499 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3500 {
3501         int mr_ctl = 0;
3502         uint32_t lsb_val = 0;
3503         uint32_t msb_val = 0;
3504         const uint8_t rule_mr_offset = 4;
3505
3506         struct ixgbe_hw *hw =
3507                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3508         struct ixgbe_mirror_info *mr_info =
3509                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3510
3511         if (ixgbe_vmdq_mode_check(hw) < 0)
3512                 return (-ENOTSUP);
3513
3514         memset(&mr_info->mr_conf[rule_id], 0,
3515                 sizeof(struct rte_eth_vmdq_mirror_conf));
3516
3517         /* clear PFVMCTL register */
3518         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3519
3520         /* clear pool mask register */
3521         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3522         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3523
3524         /* clear vlan mask register */
3525         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3526         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3527
3528         return 0;
3529 }
3530
3531 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3532         uint16_t queue_idx, uint16_t tx_rate)
3533 {
3534         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3535         uint32_t rf_dec, rf_int;
3536         uint32_t bcnrc_val;
3537         uint16_t link_speed = dev->data->dev_link.link_speed;
3538
3539         if (queue_idx >= hw->mac.max_tx_queues)
3540                 return -EINVAL;
3541
3542         if (tx_rate != 0) {
3543                 /* Calculate the rate factor values to set */
3544                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3545                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3546                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3547
3548                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3549                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3550                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3551                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3552         } else {
3553                 bcnrc_val = 0;
3554         }
3555
3556         /*
3557          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3558          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3559          * set as 0x4.
3560          */
3561         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3562                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3563                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3564                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3565                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3566         else
3567                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3568                         IXGBE_MMW_SIZE_DEFAULT);
3569
3570         /* Set RTTBCNRC of queue X */
3571         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3572         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3573         IXGBE_WRITE_FLUSH(hw);
3574
3575         return 0;
3576 }
3577
3578 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3579         uint16_t tx_rate, uint64_t q_msk)
3580 {
3581         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3582         struct ixgbe_vf_info *vfinfo =
3583                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3584         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3585         uint32_t queue_stride =
3586                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3587         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3588         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3589         uint16_t total_rate = 0;
3590
3591         if (queue_end >= hw->mac.max_tx_queues)
3592                 return -EINVAL;
3593
3594         if (vfinfo != NULL) {
3595                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3596                         if (vf_idx == vf)
3597                                 continue;
3598                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3599                                 idx++)
3600                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3601                 }
3602         } else
3603                 return -EINVAL;
3604
3605         /* Store tx_rate for this vf. */
3606         for (idx = 0; idx < nb_q_per_pool; idx++) {
3607                 if (((uint64_t)0x1 << idx) & q_msk) {
3608                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3609                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3610                         total_rate += tx_rate;
3611                 }
3612         }
3613
3614         if (total_rate > dev->data->dev_link.link_speed) {
3615                 /*
3616                  * Reset stored TX rate of the VF if it causes exceed
3617                  * link speed.
3618                  */
3619                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3620                 return -EINVAL;
3621         }
3622
3623         /* Set RTTBCNRC of each queue/pool for vf X  */
3624         for (; queue_idx <= queue_end; queue_idx++) {
3625                 if (0x1 & q_msk)
3626                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3627                 q_msk = q_msk >> 1;
3628         }
3629
3630         return 0;
3631 }
3632
3633 static void
3634 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3635                      __attribute__((unused)) uint32_t index,
3636                      __attribute__((unused)) uint32_t pool)
3637 {
3638         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3639         int diag;
3640
3641         /*
3642          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3643          * operation. Trap this case to avoid exhausting the [very limited]
3644          * set of PF resources used to store VF MAC addresses.
3645          */
3646         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3647                 return;
3648         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3649         if (diag == 0)
3650                 return;
3651         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3652 }
3653
3654 static void
3655 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3656 {
3657         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3658         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3659         struct ether_addr *mac_addr;
3660         uint32_t i;
3661         int diag;
3662
3663         /*
3664          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3665          * not support the deletion of a given MAC address.
3666          * Instead, it imposes to delete all MAC addresses, then to add again
3667          * all MAC addresses with the exception of the one to be deleted.
3668          */
3669         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3670
3671         /*
3672          * Add again all MAC addresses, with the exception of the deleted one
3673          * and of the permanent MAC address.
3674          */
3675         for (i = 0, mac_addr = dev->data->mac_addrs;
3676              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3677                 /* Skip the deleted MAC address */
3678                 if (i == index)
3679                         continue;
3680                 /* Skip NULL MAC addresses */
3681                 if (is_zero_ether_addr(mac_addr))
3682                         continue;
3683                 /* Skip the permanent MAC address */
3684                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3685                         continue;
3686                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3687                 if (diag != 0)
3688                         PMD_DRV_LOG(ERR,
3689                                     "Adding again MAC address "
3690                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3691                                     "diag=%d",
3692                                     mac_addr->addr_bytes[0],
3693                                     mac_addr->addr_bytes[1],
3694                                     mac_addr->addr_bytes[2],
3695                                     mac_addr->addr_bytes[3],
3696                                     mac_addr->addr_bytes[4],
3697                                     mac_addr->addr_bytes[5],
3698                                     diag);
3699         }
3700 }
3701
3702 #define MAC_TYPE_FILTER_SUP(type)    do {\
3703         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
3704                 (type) != ixgbe_mac_X550)\
3705                 return -ENOTSUP;\
3706 } while (0)
3707
3708 static int
3709 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
3710                         struct rte_eth_syn_filter *filter,
3711                         bool add)
3712 {
3713         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3714         uint32_t synqf;
3715
3716         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
3717                 return -EINVAL;
3718
3719         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3720
3721         if (add) {
3722                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3723                         return -EINVAL;
3724                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3725                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3726
3727                 if (filter->hig_pri)
3728                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
3729                 else
3730                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3731         } else {
3732                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
3733                         return -ENOENT;
3734                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3735         }
3736         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3737         IXGBE_WRITE_FLUSH(hw);
3738         return 0;
3739 }
3740
3741 static int
3742 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
3743                         struct rte_eth_syn_filter *filter)
3744 {
3745         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3746         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3747
3748         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3749                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3750                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3751                 return 0;
3752         }
3753         return -ENOENT;
3754 }
3755
3756 static int
3757 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
3758                         enum rte_filter_op filter_op,
3759                         void *arg)
3760 {
3761         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3762         int ret;
3763
3764         MAC_TYPE_FILTER_SUP(hw->mac.type);
3765
3766         if (filter_op == RTE_ETH_FILTER_NOP)
3767                 return 0;
3768
3769         if (arg == NULL) {
3770                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3771                             filter_op);
3772                 return -EINVAL;
3773         }
3774
3775         switch (filter_op) {
3776         case RTE_ETH_FILTER_ADD:
3777                 ret = ixgbe_syn_filter_set(dev,
3778                                 (struct rte_eth_syn_filter *)arg,
3779                                 TRUE);
3780                 break;
3781         case RTE_ETH_FILTER_DELETE:
3782                 ret = ixgbe_syn_filter_set(dev,
3783                                 (struct rte_eth_syn_filter *)arg,
3784                                 FALSE);
3785                 break;
3786         case RTE_ETH_FILTER_GET:
3787                 ret = ixgbe_syn_filter_get(dev,
3788                                 (struct rte_eth_syn_filter *)arg);
3789                 break;
3790         default:
3791                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3792                 ret = -EINVAL;
3793                 break;
3794         }
3795
3796         return ret;
3797 }
3798
3799
3800 static inline enum ixgbe_5tuple_protocol
3801 convert_protocol_type(uint8_t protocol_value)
3802 {
3803         if (protocol_value == IPPROTO_TCP)
3804                 return IXGBE_FILTER_PROTOCOL_TCP;
3805         else if (protocol_value == IPPROTO_UDP)
3806                 return IXGBE_FILTER_PROTOCOL_UDP;
3807         else if (protocol_value == IPPROTO_SCTP)
3808                 return IXGBE_FILTER_PROTOCOL_SCTP;
3809         else
3810                 return IXGBE_FILTER_PROTOCOL_NONE;
3811 }
3812
3813 /*
3814  * add a 5tuple filter
3815  *
3816  * @param
3817  * dev: Pointer to struct rte_eth_dev.
3818  * index: the index the filter allocates.
3819  * filter: ponter to the filter that will be added.
3820  * rx_queue: the queue id the filter assigned to.
3821  *
3822  * @return
3823  *    - On success, zero.
3824  *    - On failure, a negative value.
3825  */
3826 static int
3827 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3828                         struct ixgbe_5tuple_filter *filter)
3829 {
3830         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3831         struct ixgbe_filter_info *filter_info =
3832                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3833         int i, idx, shift;
3834         uint32_t ftqf, sdpqf;
3835         uint32_t l34timir = 0;
3836         uint8_t mask = 0xff;
3837
3838         /*
3839          * look for an unused 5tuple filter index,
3840          * and insert the filter to list.
3841          */
3842         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
3843                 idx = i / (sizeof(uint32_t) * NBBY);
3844                 shift = i % (sizeof(uint32_t) * NBBY);
3845                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3846                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3847                         filter->index = i;
3848                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3849                                           filter,
3850                                           entries);
3851                         break;
3852                 }
3853         }
3854         if (i >= IXGBE_MAX_FTQF_FILTERS) {
3855                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3856                 return -ENOSYS;
3857         }
3858
3859         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
3860                                 IXGBE_SDPQF_DSTPORT_SHIFT);
3861         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
3862
3863         ftqf = (uint32_t)(filter->filter_info.proto &
3864                 IXGBE_FTQF_PROTOCOL_MASK);
3865         ftqf |= (uint32_t)((filter->filter_info.priority &
3866                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
3867         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3868                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3869         if (filter->filter_info.dst_ip_mask == 0)
3870                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3871         if (filter->filter_info.src_port_mask == 0)
3872                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3873         if (filter->filter_info.dst_port_mask == 0)
3874                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3875         if (filter->filter_info.proto_mask == 0)
3876                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3877         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3878         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3879         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3880
3881         IXGBE_WRITE_REG(hw, IXGBE_DAQF(idx), filter->filter_info.dst_ip);
3882         IXGBE_WRITE_REG(hw, IXGBE_SAQF(idx), filter->filter_info.src_ip);
3883         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(idx), sdpqf);
3884         IXGBE_WRITE_REG(hw, IXGBE_FTQF(idx), ftqf);
3885
3886         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3887         l34timir |= (uint32_t)(filter->queue <<
3888                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
3889         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
3890         return 0;
3891 }
3892
3893 /*
3894  * remove a 5tuple filter
3895  *
3896  * @param
3897  * dev: Pointer to struct rte_eth_dev.
3898  * filter: the pointer of the filter will be removed.
3899  */
3900 static void
3901 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3902                         struct ixgbe_5tuple_filter *filter)
3903 {
3904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3905         struct ixgbe_filter_info *filter_info =
3906                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3907         uint16_t index = filter->index;
3908
3909         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3910                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3911         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3912         rte_free(filter);
3913
3914         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3915         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3916         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3917         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3918         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3919 }
3920
3921 static int
3922 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3923 {
3924         struct ixgbe_hw *hw;
3925         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3926
3927         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3928
3929         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3930                 return -EINVAL;
3931
3932         /* refuse mtu that requires the support of scattered packets when this
3933          * feature has not been enabled before. */
3934         if (!dev->data->scattered_rx &&
3935             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3936              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3937                 return -EINVAL;
3938
3939         /*
3940          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3941          * request of the version 2.0 of the mailbox API.
3942          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3943          * of the mailbox API.
3944          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3945          * prior to 3.11.33 which contains the following change:
3946          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3947          */
3948         ixgbevf_rlpml_set_vf(hw, max_frame);
3949
3950         /* update max frame size */
3951         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
3952         return 0;
3953 }
3954
3955 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3956         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
3957                 return -ENOTSUP;\
3958 } while (0)
3959
3960 static inline struct ixgbe_5tuple_filter *
3961 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
3962                         struct ixgbe_5tuple_filter_info *key)
3963 {
3964         struct ixgbe_5tuple_filter *it;
3965
3966         TAILQ_FOREACH(it, filter_list, entries) {
3967                 if (memcmp(key, &it->filter_info,
3968                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
3969                         return it;
3970                 }
3971         }
3972         return NULL;
3973 }
3974
3975 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
3976 static inline int
3977 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3978                         struct ixgbe_5tuple_filter_info *filter_info)
3979 {
3980         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3981                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3982                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3983                 return -EINVAL;
3984
3985         switch (filter->dst_ip_mask) {
3986         case UINT32_MAX:
3987                 filter_info->dst_ip_mask = 0;
3988                 filter_info->dst_ip = filter->dst_ip;
3989                 break;
3990         case 0:
3991                 filter_info->dst_ip_mask = 1;
3992                 break;
3993         default:
3994                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3995                 return -EINVAL;
3996         }
3997
3998         switch (filter->src_ip_mask) {
3999         case UINT32_MAX:
4000                 filter_info->src_ip_mask = 0;
4001                 filter_info->src_ip = filter->src_ip;
4002                 break;
4003         case 0:
4004                 filter_info->src_ip_mask = 1;
4005                 break;
4006         default:
4007                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4008                 return -EINVAL;
4009         }
4010
4011         switch (filter->dst_port_mask) {
4012         case UINT16_MAX:
4013                 filter_info->dst_port_mask = 0;
4014                 filter_info->dst_port = filter->dst_port;
4015                 break;
4016         case 0:
4017                 filter_info->dst_port_mask = 1;
4018                 break;
4019         default:
4020                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4021                 return -EINVAL;
4022         }
4023
4024         switch (filter->src_port_mask) {
4025         case UINT16_MAX:
4026                 filter_info->src_port_mask = 0;
4027                 filter_info->src_port = filter->src_port;
4028                 break;
4029         case 0:
4030                 filter_info->src_port_mask = 1;
4031                 break;
4032         default:
4033                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4034                 return -EINVAL;
4035         }
4036
4037         switch (filter->proto_mask) {
4038         case UINT8_MAX:
4039                 filter_info->proto_mask = 0;
4040                 filter_info->proto =
4041                         convert_protocol_type(filter->proto);
4042                 break;
4043         case 0:
4044                 filter_info->proto_mask = 1;
4045                 break;
4046         default:
4047                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4048                 return -EINVAL;
4049         }
4050
4051         filter_info->priority = (uint8_t)filter->priority;
4052         return 0;
4053 }
4054
4055 /*
4056  * add or delete a ntuple filter
4057  *
4058  * @param
4059  * dev: Pointer to struct rte_eth_dev.
4060  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4061  * add: if true, add filter, if false, remove filter
4062  *
4063  * @return
4064  *    - On success, zero.
4065  *    - On failure, a negative value.
4066  */
4067 static int
4068 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4069                         struct rte_eth_ntuple_filter *ntuple_filter,
4070                         bool add)
4071 {
4072         struct ixgbe_filter_info *filter_info =
4073                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4074         struct ixgbe_5tuple_filter_info filter_5tuple;
4075         struct ixgbe_5tuple_filter *filter;
4076         int ret;
4077
4078         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4079                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4080                 return -EINVAL;
4081         }
4082
4083         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4084         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4085         if (ret < 0)
4086                 return ret;
4087
4088         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4089                                          &filter_5tuple);
4090         if (filter != NULL && add) {
4091                 PMD_DRV_LOG(ERR, "filter exists.");
4092                 return -EEXIST;
4093         }
4094         if (filter == NULL && !add) {
4095                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4096                 return -ENOENT;
4097         }
4098
4099         if (add) {
4100                 filter = rte_zmalloc("ixgbe_5tuple_filter",
4101                                 sizeof(struct ixgbe_5tuple_filter), 0);
4102                 if (filter == NULL)
4103                         return -ENOMEM;
4104                 (void)rte_memcpy(&filter->filter_info,
4105                                  &filter_5tuple,
4106                                  sizeof(struct ixgbe_5tuple_filter_info));
4107                 filter->queue = ntuple_filter->queue;
4108                 ret = ixgbe_add_5tuple_filter(dev, filter);
4109                 if (ret < 0) {
4110                         rte_free(filter);
4111                         return ret;
4112                 }
4113         } else
4114                 ixgbe_remove_5tuple_filter(dev, filter);
4115
4116         return 0;
4117 }
4118
4119 /*
4120  * get a ntuple filter
4121  *
4122  * @param
4123  * dev: Pointer to struct rte_eth_dev.
4124  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4125  *
4126  * @return
4127  *    - On success, zero.
4128  *    - On failure, a negative value.
4129  */
4130 static int
4131 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4132                         struct rte_eth_ntuple_filter *ntuple_filter)
4133 {
4134         struct ixgbe_filter_info *filter_info =
4135                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4136         struct ixgbe_5tuple_filter_info filter_5tuple;
4137         struct ixgbe_5tuple_filter *filter;
4138         int ret;
4139
4140         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4141                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4142                 return -EINVAL;
4143         }
4144
4145         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4146         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4147         if (ret < 0)
4148                 return ret;
4149
4150         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4151                                          &filter_5tuple);
4152         if (filter == NULL) {
4153                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4154                 return -ENOENT;
4155         }
4156         ntuple_filter->queue = filter->queue;
4157         return 0;
4158 }
4159
4160 /*
4161  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4162  * @dev: pointer to rte_eth_dev structure
4163  * @filter_op:operation will be taken.
4164  * @arg: a pointer to specific structure corresponding to the filter_op
4165  *
4166  * @return
4167  *    - On success, zero.
4168  *    - On failure, a negative value.
4169  */
4170 static int
4171 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4172                                 enum rte_filter_op filter_op,
4173                                 void *arg)
4174 {
4175         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4176         int ret;
4177
4178         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4179
4180         if (filter_op == RTE_ETH_FILTER_NOP)
4181                 return 0;
4182
4183         if (arg == NULL) {
4184                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4185                             filter_op);
4186                 return -EINVAL;
4187         }
4188
4189         switch (filter_op) {
4190         case RTE_ETH_FILTER_ADD:
4191                 ret = ixgbe_add_del_ntuple_filter(dev,
4192                         (struct rte_eth_ntuple_filter *)arg,
4193                         TRUE);
4194                 break;
4195         case RTE_ETH_FILTER_DELETE:
4196                 ret = ixgbe_add_del_ntuple_filter(dev,
4197                         (struct rte_eth_ntuple_filter *)arg,
4198                         FALSE);
4199                 break;
4200         case RTE_ETH_FILTER_GET:
4201                 ret = ixgbe_get_ntuple_filter(dev,
4202                         (struct rte_eth_ntuple_filter *)arg);
4203                 break;
4204         default:
4205                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4206                 ret = -EINVAL;
4207                 break;
4208         }
4209         return ret;
4210 }
4211
4212 static inline int
4213 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4214                         uint16_t ethertype)
4215 {
4216         int i;
4217
4218         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4219                 if (filter_info->ethertype_filters[i] == ethertype &&
4220                     (filter_info->ethertype_mask & (1 << i)))
4221                         return i;
4222         }
4223         return -1;
4224 }
4225
4226 static inline int
4227 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4228                         uint16_t ethertype)
4229 {
4230         int i;
4231
4232         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4233                 if (!(filter_info->ethertype_mask & (1 << i))) {
4234                         filter_info->ethertype_mask |= 1 << i;
4235                         filter_info->ethertype_filters[i] = ethertype;
4236                         return i;
4237                 }
4238         }
4239         return -1;
4240 }
4241
4242 static inline int
4243 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4244                         uint8_t idx)
4245 {
4246         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4247                 return -1;
4248         filter_info->ethertype_mask &= ~(1 << idx);
4249         filter_info->ethertype_filters[idx] = 0;
4250         return idx;
4251 }
4252
4253 static int
4254 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4255                         struct rte_eth_ethertype_filter *filter,
4256                         bool add)
4257 {
4258         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4259         struct ixgbe_filter_info *filter_info =
4260                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4261         uint32_t etqf = 0;
4262         uint32_t etqs = 0;
4263         int ret;
4264
4265         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4266                 return -EINVAL;
4267
4268         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4269                 filter->ether_type == ETHER_TYPE_IPv6) {
4270                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4271                         " ethertype filter.", filter->ether_type);
4272                 return -EINVAL;
4273         }
4274
4275         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4276                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4277                 return -EINVAL;
4278         }
4279         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4280                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4281                 return -EINVAL;
4282         }
4283
4284         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4285         if (ret >= 0 && add) {
4286                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4287                             filter->ether_type);
4288                 return -EEXIST;
4289         }
4290         if (ret < 0 && !add) {
4291                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4292                             filter->ether_type);
4293                 return -ENOENT;
4294         }
4295
4296         if (add) {
4297                 ret = ixgbe_ethertype_filter_insert(filter_info,
4298                         filter->ether_type);
4299                 if (ret < 0) {
4300                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4301                         return -ENOSYS;
4302                 }
4303                 etqf = IXGBE_ETQF_FILTER_EN;
4304                 etqf |= (uint32_t)filter->ether_type;
4305                 etqs |= (uint32_t)((filter->queue <<
4306                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4307                                     IXGBE_ETQS_RX_QUEUE);
4308                 etqs |= IXGBE_ETQS_QUEUE_EN;
4309         } else {
4310                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4311                 if (ret < 0)
4312                         return -ENOSYS;
4313         }
4314         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4315         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4316         IXGBE_WRITE_FLUSH(hw);
4317
4318         return 0;
4319 }
4320
4321 static int
4322 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4323                         struct rte_eth_ethertype_filter *filter)
4324 {
4325         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4326         struct ixgbe_filter_info *filter_info =
4327                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4328         uint32_t etqf, etqs;
4329         int ret;
4330
4331         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4332         if (ret < 0) {
4333                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4334                             filter->ether_type);
4335                 return -ENOENT;
4336         }
4337
4338         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4339         if (etqf & IXGBE_ETQF_FILTER_EN) {
4340                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4341                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4342                 filter->flags = 0;
4343                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4344                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4345                 return 0;
4346         }
4347         return -ENOENT;
4348 }
4349
4350 /*
4351  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4352  * @dev: pointer to rte_eth_dev structure
4353  * @filter_op:operation will be taken.
4354  * @arg: a pointer to specific structure corresponding to the filter_op
4355  */
4356 static int
4357 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4358                                 enum rte_filter_op filter_op,
4359                                 void *arg)
4360 {
4361         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4362         int ret;
4363
4364         MAC_TYPE_FILTER_SUP(hw->mac.type);
4365
4366         if (filter_op == RTE_ETH_FILTER_NOP)
4367                 return 0;
4368
4369         if (arg == NULL) {
4370                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4371                             filter_op);
4372                 return -EINVAL;
4373         }
4374
4375         switch (filter_op) {
4376         case RTE_ETH_FILTER_ADD:
4377                 ret = ixgbe_add_del_ethertype_filter(dev,
4378                         (struct rte_eth_ethertype_filter *)arg,
4379                         TRUE);
4380                 break;
4381         case RTE_ETH_FILTER_DELETE:
4382                 ret = ixgbe_add_del_ethertype_filter(dev,
4383                         (struct rte_eth_ethertype_filter *)arg,
4384                         FALSE);
4385                 break;
4386         case RTE_ETH_FILTER_GET:
4387                 ret = ixgbe_get_ethertype_filter(dev,
4388                         (struct rte_eth_ethertype_filter *)arg);
4389                 break;
4390         default:
4391                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4392                 ret = -EINVAL;
4393                 break;
4394         }
4395         return ret;
4396 }
4397
4398 static int
4399 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4400                      enum rte_filter_type filter_type,
4401                      enum rte_filter_op filter_op,
4402                      void *arg)
4403 {
4404         int ret = -EINVAL;
4405
4406         switch (filter_type) {
4407         case RTE_ETH_FILTER_NTUPLE:
4408                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4409                 break;
4410         case RTE_ETH_FILTER_ETHERTYPE:
4411                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4412                 break;
4413         case RTE_ETH_FILTER_SYN:
4414                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4415                 break;
4416         case RTE_ETH_FILTER_FDIR:
4417                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4418                 break;
4419         default:
4420                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4421                                                         filter_type);
4422                 break;
4423         }
4424
4425         return ret;
4426 }
4427
4428 static struct rte_driver rte_ixgbe_driver = {
4429         .type = PMD_PDEV,
4430         .init = rte_ixgbe_pmd_init,
4431 };
4432
4433 static struct rte_driver rte_ixgbevf_driver = {
4434         .type = PMD_PDEV,
4435         .init = rte_ixgbevf_pmd_init,
4436 };
4437
4438 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4439 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);