lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72
  73 /*
  74  * High threshold controlling when to start sending XOFF frames. Must be at
  75  * least 8 bytes less than receive packet buffer size. This value is in units
  76  * of 1024 bytes.
  77  */
  78 #define IXGBE_FC_HI    0x80
  79
  80 /*
  81  * Low threshold controlling when to start sending XON frames. This value is
  82  * in units of 1024 bytes.
  83  */
  84 #define IXGBE_FC_LO    0x40
  85
  86 /* Timer value included in XOFF frames. */
  87 #define IXGBE_FC_PAUSE 0x680
  88
  89 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  90 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  91 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  92
  93 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  94 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  95
  96 /*
  97  *  Default values for RX/TX configuration
  98  */
  99 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 100 #define IXGBE_DEFAULT_RX_PTHRESH      8
 101 #define IXGBE_DEFAULT_RX_HTHRESH      8
 102 #define IXGBE_DEFAULT_RX_WTHRESH      0
 103
 104 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 105 #define IXGBE_DEFAULT_TX_PTHRESH      32
 106 #define IXGBE_DEFAULT_TX_HTHRESH      0
 107 #define IXGBE_DEFAULT_TX_WTHRESH      0
 108 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 109
 110 /* Bit shift and mask */
 111 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 112 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 113 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 114 #define IXGBE_8_BIT_MASK   UINT8_MAX
 115
 116 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 117
 118 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 119
 120 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 121                 struct rte_eth_dev *eth_dev);
 122 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 123 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 124 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 125 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 126 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 127 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 128 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 129 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 130 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 131 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 132 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 133                                 int wait_to_complete);
 134 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 135                                 struct rte_eth_stats *stats);
 136 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 137 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 138                                              uint16_t queue_id,
 139                                              uint8_t stat_idx,
 140                                              uint8_t is_rx);
 141 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 142                                struct rte_eth_dev_info *dev_info);
 143 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 144                                  struct rte_eth_dev_info *dev_info);
 145 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 146
 147 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 148                 uint16_t vlan_id, int on);
 149 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 150 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 151                 uint16_t queue, bool on);
 152 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 153                 int on);
 154 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 155 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 156 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 157 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 158 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 159
 160 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 161 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 162 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 163                                struct rte_eth_fc_conf *fc_conf);
 164 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 165                                struct rte_eth_fc_conf *fc_conf);
 166 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 167                 struct rte_eth_pfc_conf *pfc_conf);
 168 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 169                         struct rte_eth_rss_reta_entry64 *reta_conf,
 170                         uint16_t reta_size);
 171 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 172                         struct rte_eth_rss_reta_entry64 *reta_conf,
 173                         uint16_t reta_size);
 174 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 178 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 179                 void *param);
 180 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 181 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 182                 uint32_t index, uint32_t pool);
 183 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 184 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 185
 186 /* For Virtual Function support */
 187 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 188                 struct rte_eth_dev *eth_dev);
 189 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 190 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 191 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 192 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 193 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 194 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 195                 struct rte_eth_stats *stats);
 196 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 197 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 198                 uint16_t vlan_id, int on);
 199 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 200                 uint16_t queue, int on);
 201 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 202 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203
 204 /* For Eth VMDQ APIs support */
 205 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 206                 ether_addr* mac_addr,uint8_t on);
 207 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 208 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 209                 uint16_t rx_mask, uint8_t on);
 210 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 211 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 212 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 213                 uint64_t pool_mask,uint8_t vlan_on);
 214 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 215                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 216                 uint8_t rule_id, uint8_t on);
 217 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 218                 uint8_t rule_id);
 219
 220 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 221                 uint16_t queue_idx, uint16_t tx_rate);
 222 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 223                 uint16_t tx_rate, uint64_t q_msk);
 224
 225 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 226                                  struct ether_addr *mac_addr,
 227                                  uint32_t index, uint32_t pool);
 228 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 229 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
 230                         struct rte_syn_filter *filter, uint16_t rx_queue);
 231 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
 232 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
 233                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 234 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 235                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 236 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 237                         uint16_t index);
 238 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 239                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 240
 241 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 242 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 243                         struct rte_eth_ethertype_filter *filter,
 244                         bool add);
 245 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 246                                 enum rte_filter_op filter_op,
 247                                 void *arg);
 248 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 249                         struct rte_eth_ethertype_filter *filter);
 250 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 251                      enum rte_filter_type filter_type,
 252                      enum rte_filter_op filter_op,
 253                      void *arg);
 254
 255 /*
 256  * Define VF Stats MACRO for Non "cleared on read" register
 257  */
 258 #define UPDATE_VF_STAT(reg, last, cur)                          \
 259 {                                                               \
 260         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 261         cur += latest - last;                                   \
 262         last = latest;                                          \
 263 }
 264
 265 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 266 {                                                                \
 267         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 268         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 269         u64 latest = ((new_msb << 32) | new_lsb);                \
 270         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 271         last = latest;                                           \
 272 }
 273
 274 #define IXGBE_SET_HWSTRIP(h, q) do{\
 275                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 276                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 277                 (h)->bitmap[idx] |= 1 << bit;\
 278         }while(0)
 279
 280 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 281                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 282                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 283                 (h)->bitmap[idx] &= ~(1 << bit);\
 284         }while(0)
 285
 286 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 287                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 288                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 289                 (r) = (h)->bitmap[idx] >> bit & 1;\
 290         }while(0)
 291
 292 /*
 293  * The set of PCI devices this driver supports
 294  */
 295 static struct rte_pci_id pci_id_ixgbe_map[] = {
 296
 297 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 298 #include "rte_pci_dev_ids.h"
 299
 300 { .vendor_id = 0, /* sentinel */ },
 301 };
 302
 303
 304 /*
 305  * The set of PCI devices this driver supports (for 82599 VF)
 306  */
 307 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 308
 309 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 310 #include "rte_pci_dev_ids.h"
 311 { .vendor_id = 0, /* sentinel */ },
 312
 313 };
 314
 315 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 316         .dev_configure        = ixgbe_dev_configure,
 317         .dev_start            = ixgbe_dev_start,
 318         .dev_stop             = ixgbe_dev_stop,
 319         .dev_set_link_up    = ixgbe_dev_set_link_up,
 320         .dev_set_link_down  = ixgbe_dev_set_link_down,
 321         .dev_close            = ixgbe_dev_close,
 322         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 323         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 324         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 325         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 326         .link_update          = ixgbe_dev_link_update,
 327         .stats_get            = ixgbe_dev_stats_get,
 328         .stats_reset          = ixgbe_dev_stats_reset,
 329         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 330         .dev_infos_get        = ixgbe_dev_info_get,
 331         .mtu_set              = ixgbe_dev_mtu_set,
 332         .vlan_filter_set      = ixgbe_vlan_filter_set,
 333         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 334         .vlan_offload_set     = ixgbe_vlan_offload_set,
 335         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 336         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 337         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 338         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 339         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 340         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 341         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 342         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 343         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 344         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 345         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 346         .dev_led_on           = ixgbe_dev_led_on,
 347         .dev_led_off          = ixgbe_dev_led_off,
 348         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 349         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 350         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 351         .mac_addr_add         = ixgbe_add_rar,
 352         .mac_addr_remove      = ixgbe_remove_rar,
 353         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 354         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 355         .mirror_rule_set      = ixgbe_mirror_rule_set,
 356         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 357         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 358         .set_vf_rx            = ixgbe_set_pool_rx,
 359         .set_vf_tx            = ixgbe_set_pool_tx,
 360         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 361         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 362         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 363         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 364         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 365         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 366         .fdir_infos_get               = ixgbe_fdir_info_get,
 367         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 368         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 369         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 370         .fdir_set_masks               = ixgbe_fdir_set_masks,
 371         .reta_update          = ixgbe_dev_rss_reta_update,
 372         .reta_query           = ixgbe_dev_rss_reta_query,
 373 #ifdef RTE_NIC_BYPASS
 374         .bypass_init          = ixgbe_bypass_init,
 375         .bypass_state_set     = ixgbe_bypass_state_store,
 376         .bypass_state_show    = ixgbe_bypass_state_show,
 377         .bypass_event_set     = ixgbe_bypass_event_store,
 378         .bypass_event_show    = ixgbe_bypass_event_show,
 379         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 380         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 381         .bypass_ver_show      = ixgbe_bypass_ver_show,
 382         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 383 #endif /* RTE_NIC_BYPASS */
 384         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 385         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 386         .add_syn_filter          = ixgbe_add_syn_filter,
 387         .remove_syn_filter       = ixgbe_remove_syn_filter,
 388         .get_syn_filter          = ixgbe_get_syn_filter,
 389         .add_5tuple_filter       = ixgbe_add_5tuple_filter,
 390         .remove_5tuple_filter    = ixgbe_remove_5tuple_filter,
 391         .get_5tuple_filter       = ixgbe_get_5tuple_filter,
 392         .filter_ctrl             = ixgbe_dev_filter_ctrl,
 393 };
 394
 395 /*
 396  * dev_ops for virtual function, bare necessities for basic vf
 397  * operation have been implemented
 398  */
 399 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 400
 401         .dev_configure        = ixgbevf_dev_configure,
 402         .dev_start            = ixgbevf_dev_start,
 403         .dev_stop             = ixgbevf_dev_stop,
 404         .link_update          = ixgbe_dev_link_update,
 405         .stats_get            = ixgbevf_dev_stats_get,
 406         .stats_reset          = ixgbevf_dev_stats_reset,
 407         .dev_close            = ixgbevf_dev_close,
 408         .dev_infos_get        = ixgbevf_dev_info_get,
 409         .mtu_set              = ixgbevf_dev_set_mtu,
 410         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 411         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 412         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 413         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 414         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 415         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 416         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 417         .mac_addr_add         = ixgbevf_add_mac_addr,
 418         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 419 };
 420
 421 /**
 422  * Atomically reads the link status information from global
 423  * structure rte_eth_dev.
 424  *
 425  * @param dev
 426  *   - Pointer to the structure rte_eth_dev to read from.
 427  *   - Pointer to the buffer to be saved with the link status.
 428  *
 429  * @return
 430  *   - On success, zero.
 431  *   - On failure, negative value.
 432  */
 433 static inline int
 434 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 435                                 struct rte_eth_link *link)
 436 {
 437         struct rte_eth_link *dst = link;
 438         struct rte_eth_link *src = &(dev->data->dev_link);
 439
 440         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 441                                         *(uint64_t *)src) == 0)
 442                 return -1;
 443
 444         return 0;
 445 }
 446
 447 /**
 448  * Atomically writes the link status information into global
 449  * structure rte_eth_dev.
 450  *
 451  * @param dev
 452  *   - Pointer to the structure rte_eth_dev to read from.
 453  *   - Pointer to the buffer to be saved with the link status.
 454  *
 455  * @return
 456  *   - On success, zero.
 457  *   - On failure, negative value.
 458  */
 459 static inline int
 460 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 461                                 struct rte_eth_link *link)
 462 {
 463         struct rte_eth_link *dst = &(dev->data->dev_link);
 464         struct rte_eth_link *src = link;
 465
 466         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 467                                         *(uint64_t *)src) == 0)
 468                 return -1;
 469
 470         return 0;
 471 }
 472
 473 /*
 474  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 475  */
 476 static inline int
 477 ixgbe_is_sfp(struct ixgbe_hw *hw)
 478 {
 479         switch (hw->phy.type) {
 480         case ixgbe_phy_sfp_avago:
 481         case ixgbe_phy_sfp_ftl:
 482         case ixgbe_phy_sfp_intel:
 483         case ixgbe_phy_sfp_unknown:
 484         case ixgbe_phy_sfp_passive_tyco:
 485         case ixgbe_phy_sfp_passive_unknown:
 486                 return 1;
 487         default:
 488                 return 0;
 489         }
 490 }
 491
 492 static inline int32_t
 493 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 494 {
 495         uint32_t ctrl_ext;
 496         int32_t status;
 497
 498         status = ixgbe_reset_hw(hw);
 499
 500         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 501         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 502         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 503         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 504         IXGBE_WRITE_FLUSH(hw);
 505
 506         return status;
 507 }
 508
 509 static inline void
 510 ixgbe_enable_intr(struct rte_eth_dev *dev)
 511 {
 512         struct ixgbe_interrupt *intr =
 513                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 514         struct ixgbe_hw *hw =
 515                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 516
 517         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 518         IXGBE_WRITE_FLUSH(hw);
 519 }
 520
 521 /*
 522  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 523  */
 524 static void
 525 ixgbe_disable_intr(struct ixgbe_hw *hw)
 526 {
 527         PMD_INIT_FUNC_TRACE();
 528
 529         if (hw->mac.type == ixgbe_mac_82598EB) {
 530                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 531         } else {
 532                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 533                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 534                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 535         }
 536         IXGBE_WRITE_FLUSH(hw);
 537 }
 538
 539 /*
 540  * This function resets queue statistics mapping registers.
 541  * From Niantic datasheet, Initialization of Statistics section:
 542  * "...if software requires the queue counters, the RQSMR and TQSM registers
 543  * must be re-programmed following a device reset.
 544  */
 545 static void
 546 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 547 {
 548         uint32_t i;
 549
 550         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 551                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 552                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 553         }
 554 }
 555
 556
 557 static int
 558 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 559                                   uint16_t queue_id,
 560                                   uint8_t stat_idx,
 561                                   uint8_t is_rx)
 562 {
 563 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 564 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 565 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 566
 567         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 568         struct ixgbe_stat_mapping_registers *stat_mappings =
 569                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 570         uint32_t qsmr_mask = 0;
 571         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 572         uint32_t q_map;
 573         uint8_t n, offset;
 574
 575         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 576                 (hw->mac.type != ixgbe_mac_X540) &&
 577                 (hw->mac.type != ixgbe_mac_X550) &&
 578                 (hw->mac.type != ixgbe_mac_X550EM_x))
 579                 return -ENOSYS;
 580
 581         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 582                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 583                      queue_id, stat_idx);
 584
 585         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 586         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 587                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 588                 return -EIO;
 589         }
 590         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 591
 592         /* Now clear any previous stat_idx set */
 593         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 594         if (!is_rx)
 595                 stat_mappings->tqsm[n] &= ~clearing_mask;
 596         else
 597                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 598
 599         q_map = (uint32_t)stat_idx;
 600         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 601         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 602         if (!is_rx)
 603                 stat_mappings->tqsm[n] |= qsmr_mask;
 604         else
 605                 stat_mappings->rqsmr[n] |= qsmr_mask;
 606
 607         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 608                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 609                      queue_id, stat_idx);
 610         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 611                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 612
 613         /* Now write the mapping in the appropriate register */
 614         if (is_rx) {
 615                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 616                              stat_mappings->rqsmr[n], n);
 617                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 618         }
 619         else {
 620                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 621                              stat_mappings->tqsm[n], n);
 622                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 623         }
 624         return 0;
 625 }
 626
 627 static void
 628 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 629 {
 630         struct ixgbe_stat_mapping_registers *stat_mappings =
 631                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 632         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 633         int i;
 634
 635         /* write whatever was in stat mapping table to the NIC */
 636         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 637                 /* rx */
 638                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 639
 640                 /* tx */
 641                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 642         }
 643 }
 644
 645 static void
 646 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 647 {
 648         uint8_t i;
 649         struct ixgbe_dcb_tc_config *tc;
 650         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 651
 652         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 653         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 654         for (i = 0; i < dcb_max_tc; i++) {
 655                 tc = &dcb_config->tc_config[i];
 656                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 657                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 658                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 659                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 660                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 661                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 662                 tc->pfc = ixgbe_dcb_pfc_disabled;
 663         }
 664
 665         /* Initialize default user to priority mapping, UPx->TC0 */
 666         tc = &dcb_config->tc_config[0];
 667         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 668         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 669         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 670                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 671                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 672         }
 673         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 674         dcb_config->pfc_mode_enable = false;
 675         dcb_config->vt_mode = true;
 676         dcb_config->round_robin_enable = false;
 677         /* support all DCB capabilities in 82599 */
 678         dcb_config->support.capabilities = 0xFF;
 679
 680         /*we only support 4 Tcs for X540, X550 */
 681         if (hw->mac.type == ixgbe_mac_X540 ||
 682                 hw->mac.type == ixgbe_mac_X550 ||
 683                 hw->mac.type == ixgbe_mac_X550EM_x) {
 684                 dcb_config->num_tcs.pg_tcs = 4;
 685                 dcb_config->num_tcs.pfc_tcs = 4;
 686         }
 687 }
 688
 689 /*
 690  * Ensure that all locks are released before first NVM or PHY access
 691  */
 692 static void
 693 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 694 {
 695         uint16_t mask;
 696
 697         /*
 698          * Phy lock should not fail in this early stage. If this is the case,
 699          * it is due to an improper exit of the application.
 700          * So force the release of the faulty lock. Release of common lock
 701          * is done automatically by swfw_sync function.
 702          */
 703         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 704         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 705                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 706         }
 707         ixgbe_release_swfw_semaphore(hw, mask);
 708
 709         /*
 710          * These ones are more tricky since they are common to all ports; but
 711          * swfw_sync retries last long enough (1s) to be almost sure that if
 712          * lock can not be taken it is due to an improper lock of the
 713          * semaphore.
 714          */
 715         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 716         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 717                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 718         }
 719         ixgbe_release_swfw_semaphore(hw, mask);
 720 }
 721
 722 /*
 723  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 724  * It returns 0 on success.
 725  */
 726 static int
 727 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 728                      struct rte_eth_dev *eth_dev)
 729 {
 730         struct rte_pci_device *pci_dev;
 731         struct ixgbe_hw *hw =
 732                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 733         struct ixgbe_vfta * shadow_vfta =
 734                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 735         struct ixgbe_hwstrip *hwstrip =
 736                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 737         struct ixgbe_dcb_config *dcb_config =
 738                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 739         uint32_t ctrl_ext;
 740         uint16_t csum;
 741         int diag, i;
 742
 743         PMD_INIT_FUNC_TRACE();
 744
 745         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 746         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 747         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 748
 749         /*
 750          * For secondary processes, we don't initialise any further as primary
 751          * has already done this work. Only check we don't need a different
 752          * RX and TX function.
 753          */
 754         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 755                 struct igb_tx_queue *txq;
 756                 /* TX queue function in primary, set by last queue initialized
 757                  * Tx queue may not initialized by primary process */
 758                 if (eth_dev->data->tx_queues) {
 759                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 760                         set_tx_function(eth_dev, txq);
 761                 } else {
 762                         /* Use default TX function if we get here */
 763                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 764                                            "Using default TX function.");
 765                 }
 766
 767                 if (eth_dev->data->scattered_rx)
 768                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 769                 return 0;
 770         }
 771         pci_dev = eth_dev->pci_dev;
 772
 773         /* Vendor and Device ID need to be set before init of shared code */
 774         hw->device_id = pci_dev->id.device_id;
 775         hw->vendor_id = pci_dev->id.vendor_id;
 776         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 777         hw->allow_unsupported_sfp = 1;
 778
 779         /* Initialize the shared code (base driver) */
 780 #ifdef RTE_NIC_BYPASS
 781         diag = ixgbe_bypass_init_shared_code(hw);
 782 #else
 783         diag = ixgbe_init_shared_code(hw);
 784 #endif /* RTE_NIC_BYPASS */
 785
 786         if (diag != IXGBE_SUCCESS) {
 787                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 788                 return -EIO;
 789         }
 790
 791         /* pick up the PCI bus settings for reporting later */
 792         ixgbe_get_bus_info(hw);
 793
 794         /* Unlock any pending hardware semaphore */
 795         ixgbe_swfw_lock_reset(hw);
 796
 797         /* Initialize DCB configuration*/
 798         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 799         ixgbe_dcb_init(hw,dcb_config);
 800         /* Get Hardware Flow Control setting */
 801         hw->fc.requested_mode = ixgbe_fc_full;
 802         hw->fc.current_mode = ixgbe_fc_full;
 803         hw->fc.pause_time = IXGBE_FC_PAUSE;
 804         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 805                 hw->fc.low_water[i] = IXGBE_FC_LO;
 806                 hw->fc.high_water[i] = IXGBE_FC_HI;
 807         }
 808         hw->fc.send_xon = 1;
 809
 810         /* Make sure we have a good EEPROM before we read from it */
 811         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 812         if (diag != IXGBE_SUCCESS) {
 813                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 814                 return -EIO;
 815         }
 816
 817 #ifdef RTE_NIC_BYPASS
 818         diag = ixgbe_bypass_init_hw(hw);
 819 #else
 820         diag = ixgbe_init_hw(hw);
 821 #endif /* RTE_NIC_BYPASS */
 822
 823         /*
 824          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 825          * is called too soon after the kernel driver unbinding/binding occurs.
 826          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 827          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 828          * also called. See ixgbe_identify_phy_82599(). The reason for the
 829          * failure is not known, and only occuts when virtualisation features
 830          * are disabled in the bios. A delay of 100ms  was found to be enough by
 831          * trial-and-error, and is doubled to be safe.
 832          */
 833         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 834                 rte_delay_ms(200);
 835                 diag = ixgbe_init_hw(hw);
 836         }
 837
 838         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 839                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 840                     "LOM.  Please be aware there may be issues associated "
 841                     "with your hardware.");
 842                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 843                     "please contact your Intel or hardware representative "
 844                     "who provided you with this hardware.");
 845         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 846                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 847         if (diag) {
 848                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 849                 return -EIO;
 850         }
 851
 852         /* disable interrupt */
 853         ixgbe_disable_intr(hw);
 854
 855         /* reset mappings for queue statistics hw counters*/
 856         ixgbe_reset_qstat_mappings(hw);
 857
 858         /* Allocate memory for storing MAC addresses */
 859         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 860                         hw->mac.num_rar_entries, 0);
 861         if (eth_dev->data->mac_addrs == NULL) {
 862                 PMD_INIT_LOG(ERR,
 863                         "Failed to allocate %u bytes needed to store "
 864                         "MAC addresses",
 865                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 866                 return -ENOMEM;
 867         }
 868         /* Copy the permanent MAC address */
 869         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 870                         &eth_dev->data->mac_addrs[0]);
 871
 872         /* Allocate memory for storing hash filter MAC addresses */
 873         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 874                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 875         if (eth_dev->data->hash_mac_addrs == NULL) {
 876                 PMD_INIT_LOG(ERR,
 877                         "Failed to allocate %d bytes needed to store MAC addresses",
 878                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 879                 return -ENOMEM;
 880         }
 881
 882         /* initialize the vfta */
 883         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 884
 885         /* initialize the hw strip bitmap*/
 886         memset(hwstrip, 0, sizeof(*hwstrip));
 887
 888         /* initialize PF if max_vfs not zero */
 889         ixgbe_pf_host_init(eth_dev);
 890
 891         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 892         /* let hardware know driver is loaded */
 893         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 894         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 895         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 896         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 897         IXGBE_WRITE_FLUSH(hw);
 898
 899         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 900                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 901                              (int) hw->mac.type, (int) hw->phy.type,
 902                              (int) hw->phy.sfp_type);
 903         else
 904                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 905                              (int) hw->mac.type, (int) hw->phy.type);
 906
 907         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 908                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 909                         pci_dev->id.device_id);
 910
 911         rte_intr_callback_register(&(pci_dev->intr_handle),
 912                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 913
 914         /* enable uio intr after callback register */
 915         rte_intr_enable(&(pci_dev->intr_handle));
 916
 917         /* enable support intr */
 918         ixgbe_enable_intr(eth_dev);
 919
 920         return 0;
 921 }
 922
 923
 924 /*
 925  * Negotiate mailbox API version with the PF.
 926  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 927  * Then we try to negotiate starting with the most recent one.
 928  * If all negotiation attempts fail, then we will proceed with
 929  * the default one (ixgbe_mbox_api_10).
 930  */
 931 static void
 932 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 933 {
 934         int32_t i;
 935
 936         /* start with highest supported, proceed down */
 937         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 938                 ixgbe_mbox_api_11,
 939                 ixgbe_mbox_api_10,
 940         };
 941
 942         for (i = 0;
 943                         i != RTE_DIM(sup_ver) &&
 944                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 945                         i++)
 946                 ;
 947 }
 948
 949 static void
 950 generate_random_mac_addr(struct ether_addr *mac_addr)
 951 {
 952         uint64_t random;
 953
 954         /* Set Organizationally Unique Identifier (OUI) prefix. */
 955         mac_addr->addr_bytes[0] = 0x00;
 956         mac_addr->addr_bytes[1] = 0x09;
 957         mac_addr->addr_bytes[2] = 0xC0;
 958         /* Force indication of locally assigned MAC address. */
 959         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 960         /* Generate the last 3 bytes of the MAC address with a random number. */
 961         random = rte_rand();
 962         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 963 }
 964
 965 /*
 966  * Virtual Function device init
 967  */
 968 static int
 969 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 970                      struct rte_eth_dev *eth_dev)
 971 {
 972         int diag;
 973         uint32_t tc, tcs;
 974         struct rte_pci_device *pci_dev;
 975         struct ixgbe_hw *hw =
 976                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 977         struct ixgbe_vfta * shadow_vfta =
 978                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 979         struct ixgbe_hwstrip *hwstrip =
 980                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 981         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 982
 983         PMD_INIT_FUNC_TRACE();
 984
 985         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 986         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 987         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 988
 989         /* for secondary processes, we don't initialise any further as primary
 990          * has already done this work. Only check we don't need a different
 991          * RX function */
 992         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 993                 if (eth_dev->data->scattered_rx)
 994                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 995                 return 0;
 996         }
 997
 998         pci_dev = eth_dev->pci_dev;
 999
1000         hw->device_id = pci_dev->id.device_id;
1001         hw->vendor_id = pci_dev->id.vendor_id;
1002         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1003
1004         /* initialize the vfta */
1005         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1006
1007         /* initialize the hw strip bitmap*/
1008         memset(hwstrip, 0, sizeof(*hwstrip));
1009
1010         /* Initialize the shared code (base driver) */
1011         diag = ixgbe_init_shared_code(hw);
1012         if (diag != IXGBE_SUCCESS) {
1013                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1014                 return -EIO;
1015         }
1016
1017         /* init_mailbox_params */
1018         hw->mbx.ops.init_params(hw);
1019
1020         /* Disable the interrupts for VF */
1021         ixgbevf_intr_disable(hw);
1022
1023         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1024         diag = hw->mac.ops.reset_hw(hw);
1025
1026         /*
1027          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1028          * the underlying PF driver has not assigned a MAC address to the VF.
1029          * In this case, assign a random MAC address.
1030          */
1031         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1032                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1033                 return (diag);
1034         }
1035
1036         /* negotiate mailbox API version to use with the PF. */
1037         ixgbevf_negotiate_api(hw);
1038
1039         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1040         ixgbevf_get_queues(hw, &tcs, &tc);
1041
1042         /* Allocate memory for storing MAC addresses */
1043         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1044                         hw->mac.num_rar_entries, 0);
1045         if (eth_dev->data->mac_addrs == NULL) {
1046                 PMD_INIT_LOG(ERR,
1047                         "Failed to allocate %u bytes needed to store "
1048                         "MAC addresses",
1049                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1050                 return -ENOMEM;
1051         }
1052
1053         /* Generate a random MAC address, if none was assigned by PF. */
1054         if (is_zero_ether_addr(perm_addr)) {
1055                 generate_random_mac_addr(perm_addr);
1056                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1057                 if (diag) {
1058                         rte_free(eth_dev->data->mac_addrs);
1059                         eth_dev->data->mac_addrs = NULL;
1060                         return diag;
1061                 }
1062                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1063                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1064                              "%02x:%02x:%02x:%02x:%02x:%02x",
1065                              perm_addr->addr_bytes[0],
1066                              perm_addr->addr_bytes[1],
1067                              perm_addr->addr_bytes[2],
1068                              perm_addr->addr_bytes[3],
1069                              perm_addr->addr_bytes[4],
1070                              perm_addr->addr_bytes[5]);
1071         }
1072
1073         /* Copy the permanent MAC address */
1074         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1075
1076         /* reset the hardware with the new settings */
1077         diag = hw->mac.ops.start_hw(hw);
1078         switch (diag) {
1079                 case  0:
1080                         break;
1081
1082                 default:
1083                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1084                         return (-EIO);
1085         }
1086
1087         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1088                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1089                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1090
1091         return 0;
1092 }
1093
1094 static struct eth_driver rte_ixgbe_pmd = {
1095         {
1096                 .name = "rte_ixgbe_pmd",
1097                 .id_table = pci_id_ixgbe_map,
1098                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1099         },
1100         .eth_dev_init = eth_ixgbe_dev_init,
1101         .dev_private_size = sizeof(struct ixgbe_adapter),
1102 };
1103
1104 /*
1105  * virtual function driver struct
1106  */
1107 static struct eth_driver rte_ixgbevf_pmd = {
1108         {
1109                 .name = "rte_ixgbevf_pmd",
1110                 .id_table = pci_id_ixgbevf_map,
1111                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1112         },
1113         .eth_dev_init = eth_ixgbevf_dev_init,
1114         .dev_private_size = sizeof(struct ixgbe_adapter),
1115 };
1116
1117 /*
1118  * Driver initialization routine.
1119  * Invoked once at EAL init time.
1120  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1121  */
1122 static int
1123 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1124 {
1125         PMD_INIT_FUNC_TRACE();
1126
1127         rte_eth_driver_register(&rte_ixgbe_pmd);
1128         return 0;
1129 }
1130
1131 /*
1132  * VF Driver initialization routine.
1133  * Invoked one at EAL init time.
1134  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1135  */
1136 static int
1137 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1138 {
1139         PMD_INIT_FUNC_TRACE();
1140
1141         rte_eth_driver_register(&rte_ixgbevf_pmd);
1142         return (0);
1143 }
1144
1145 static int
1146 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1147 {
1148         struct ixgbe_hw *hw =
1149                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1150         struct ixgbe_vfta * shadow_vfta =
1151                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1152         uint32_t vfta;
1153         uint32_t vid_idx;
1154         uint32_t vid_bit;
1155
1156         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1157         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1158         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1159         if (on)
1160                 vfta |= vid_bit;
1161         else
1162                 vfta &= ~vid_bit;
1163         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1164
1165         /* update local VFTA copy */
1166         shadow_vfta->vfta[vid_idx] = vfta;
1167
1168         return 0;
1169 }
1170
1171 static void
1172 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1173 {
1174         if (on)
1175                 ixgbe_vlan_hw_strip_enable(dev, queue);
1176         else
1177                 ixgbe_vlan_hw_strip_disable(dev, queue);
1178 }
1179
1180 static void
1181 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1182 {
1183         struct ixgbe_hw *hw =
1184                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1185
1186         /* Only the high 16-bits is valid */
1187         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1188 }
1189
1190 void
1191 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1192 {
1193         struct ixgbe_hw *hw =
1194                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1195         uint32_t vlnctrl;
1196
1197         PMD_INIT_FUNC_TRACE();
1198
1199         /* Filter Table Disable */
1200         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1201         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1202
1203         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1204 }
1205
1206 void
1207 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1208 {
1209         struct ixgbe_hw *hw =
1210                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1211         struct ixgbe_vfta * shadow_vfta =
1212                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1213         uint32_t vlnctrl;
1214         uint16_t i;
1215
1216         PMD_INIT_FUNC_TRACE();
1217
1218         /* Filter Table Enable */
1219         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1220         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1221         vlnctrl |= IXGBE_VLNCTRL_VFE;
1222
1223         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1224
1225         /* write whatever is in local vfta copy */
1226         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1227                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1228 }
1229
1230 static void
1231 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1232 {
1233         struct ixgbe_hwstrip *hwstrip =
1234                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1235
1236         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1237                 return;
1238
1239         if (on)
1240                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1241         else
1242                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1243 }
1244
1245 static void
1246 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1247 {
1248         struct ixgbe_hw *hw =
1249                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1250         uint32_t ctrl;
1251
1252         PMD_INIT_FUNC_TRACE();
1253
1254         if (hw->mac.type == ixgbe_mac_82598EB) {
1255                 /* No queue level support */
1256                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1257                 return;
1258         }
1259         else {
1260                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1261                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1262                 ctrl &= ~IXGBE_RXDCTL_VME;
1263                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1264         }
1265         /* record those setting for HW strip per queue */
1266         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1267 }
1268
1269 static void
1270 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1271 {
1272         struct ixgbe_hw *hw =
1273                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274         uint32_t ctrl;
1275
1276         PMD_INIT_FUNC_TRACE();
1277
1278         if (hw->mac.type == ixgbe_mac_82598EB) {
1279                 /* No queue level supported */
1280                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1281                 return;
1282         }
1283         else {
1284                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1285                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1286                 ctrl |= IXGBE_RXDCTL_VME;
1287                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1288         }
1289         /* record those setting for HW strip per queue */
1290         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1291 }
1292
1293 void
1294 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1295 {
1296         struct ixgbe_hw *hw =
1297                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1298         uint32_t ctrl;
1299         uint16_t i;
1300
1301         PMD_INIT_FUNC_TRACE();
1302
1303         if (hw->mac.type == ixgbe_mac_82598EB) {
1304                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1305                 ctrl &= ~IXGBE_VLNCTRL_VME;
1306                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1307         }
1308         else {
1309                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1310                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1311                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1312                         ctrl &= ~IXGBE_RXDCTL_VME;
1313                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1314
1315                         /* record those setting for HW strip per queue */
1316                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1317                 }
1318         }
1319 }
1320
1321 void
1322 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1323 {
1324         struct ixgbe_hw *hw =
1325                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1326         uint32_t ctrl;
1327         uint16_t i;
1328
1329         PMD_INIT_FUNC_TRACE();
1330
1331         if (hw->mac.type == ixgbe_mac_82598EB) {
1332                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1333                 ctrl |= IXGBE_VLNCTRL_VME;
1334                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1335         }
1336         else {
1337                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1338                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1339                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1340                         ctrl |= IXGBE_RXDCTL_VME;
1341                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1342
1343                         /* record those setting for HW strip per queue */
1344                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1345                 }
1346         }
1347 }
1348
1349 static void
1350 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1351 {
1352         struct ixgbe_hw *hw =
1353                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1354         uint32_t ctrl;
1355
1356         PMD_INIT_FUNC_TRACE();
1357
1358         /* DMATXCTRL: Geric Double VLAN Disable */
1359         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1360         ctrl &= ~IXGBE_DMATXCTL_GDV;
1361         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1362
1363         /* CTRL_EXT: Global Double VLAN Disable */
1364         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1365         ctrl &= ~IXGBE_EXTENDED_VLAN;
1366         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1367
1368 }
1369
1370 static void
1371 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1372 {
1373         struct ixgbe_hw *hw =
1374                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1375         uint32_t ctrl;
1376
1377         PMD_INIT_FUNC_TRACE();
1378
1379         /* DMATXCTRL: Geric Double VLAN Enable */
1380         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1381         ctrl |= IXGBE_DMATXCTL_GDV;
1382         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1383
1384         /* CTRL_EXT: Global Double VLAN Enable */
1385         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1386         ctrl |= IXGBE_EXTENDED_VLAN;
1387         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1388
1389         /*
1390          * VET EXT field in the EXVET register = 0x8100 by default
1391          * So no need to change. Same to VT field of DMATXCTL register
1392          */
1393 }
1394
1395 static void
1396 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1397 {
1398         if(mask & ETH_VLAN_STRIP_MASK){
1399                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1400                         ixgbe_vlan_hw_strip_enable_all(dev);
1401                 else
1402                         ixgbe_vlan_hw_strip_disable_all(dev);
1403         }
1404
1405         if(mask & ETH_VLAN_FILTER_MASK){
1406                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1407                         ixgbe_vlan_hw_filter_enable(dev);
1408                 else
1409                         ixgbe_vlan_hw_filter_disable(dev);
1410         }
1411
1412         if(mask & ETH_VLAN_EXTEND_MASK){
1413                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1414                         ixgbe_vlan_hw_extend_enable(dev);
1415                 else
1416                         ixgbe_vlan_hw_extend_disable(dev);
1417         }
1418 }
1419
1420 static void
1421 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1422 {
1423         struct ixgbe_hw *hw =
1424                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1425         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1426         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1427         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1428         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1429 }
1430
1431 static int
1432 ixgbe_dev_configure(struct rte_eth_dev *dev)
1433 {
1434         struct ixgbe_interrupt *intr =
1435                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1436
1437         PMD_INIT_FUNC_TRACE();
1438
1439         /* set flag to update link status after init */
1440         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1441
1442         return 0;
1443 }
1444
1445 /*
1446  * Configure device link speed and setup link.
1447  * It returns 0 on success.
1448  */
1449 static int
1450 ixgbe_dev_start(struct rte_eth_dev *dev)
1451 {
1452         struct ixgbe_hw *hw =
1453                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1454         struct ixgbe_vf_info *vfinfo =
1455                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1456         int err, link_up = 0, negotiate = 0;
1457         uint32_t speed = 0;
1458         int mask = 0;
1459         int status;
1460         uint16_t vf, idx;
1461
1462         PMD_INIT_FUNC_TRACE();
1463
1464         /* IXGBE devices don't support half duplex */
1465         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1466                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1467                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1468                              dev->data->dev_conf.link_duplex,
1469                              dev->data->port_id);
1470                 return -EINVAL;
1471         }
1472
1473         /* stop adapter */
1474         hw->adapter_stopped = FALSE;
1475         ixgbe_stop_adapter(hw);
1476
1477         /* reinitialize adapter
1478          * this calls reset and start */
1479         status = ixgbe_pf_reset_hw(hw);
1480         if (status != 0)
1481                 return -1;
1482         hw->mac.ops.start_hw(hw);
1483         hw->mac.get_link_status = true;
1484
1485         /* configure PF module if SRIOV enabled */
1486         ixgbe_pf_host_configure(dev);
1487
1488         /* initialize transmission unit */
1489         ixgbe_dev_tx_init(dev);
1490
1491         /* This can fail when allocating mbufs for descriptor rings */
1492         err = ixgbe_dev_rx_init(dev);
1493         if (err) {
1494                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1495                 goto error;
1496         }
1497
1498         err = ixgbe_dev_rxtx_start(dev);
1499         if (err < 0) {
1500                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1501                 goto error;
1502         }
1503
1504         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1505                 err = hw->mac.ops.setup_sfp(hw);
1506                 if (err)
1507                         goto error;
1508         }
1509
1510         /* Turn on the laser */
1511         ixgbe_enable_tx_laser(hw);
1512
1513         /* Skip link setup if loopback mode is enabled for 82599. */
1514         if (hw->mac.type == ixgbe_mac_82599EB &&
1515                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1516                 goto skip_link_setup;
1517
1518         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1519         if (err)
1520                 goto error;
1521         dev->data->dev_link.link_status = link_up;
1522
1523         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1524         if (err)
1525                 goto error;
1526
1527         switch(dev->data->dev_conf.link_speed) {
1528         case ETH_LINK_SPEED_AUTONEG:
1529                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1530                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1531                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1532                 break;
1533         case ETH_LINK_SPEED_100:
1534                 /*
1535                  * Invalid for 82598 but error will be detected by
1536                  * ixgbe_setup_link()
1537                  */
1538                 speed = IXGBE_LINK_SPEED_100_FULL;
1539                 break;
1540         case ETH_LINK_SPEED_1000:
1541                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1542                 break;
1543         case ETH_LINK_SPEED_10000:
1544                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1545                 break;
1546         default:
1547                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1548                              dev->data->dev_conf.link_speed,
1549                              dev->data->port_id);
1550                 goto error;
1551         }
1552
1553         err = ixgbe_setup_link(hw, speed, link_up);
1554         if (err)
1555                 goto error;
1556
1557 skip_link_setup:
1558
1559         /* check if lsc interrupt is enabled */
1560         if (dev->data->dev_conf.intr_conf.lsc != 0)
1561                 ixgbe_dev_lsc_interrupt_setup(dev);
1562
1563         /* resume enabled intr since hw reset */
1564         ixgbe_enable_intr(dev);
1565
1566         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1567                 ETH_VLAN_EXTEND_MASK;
1568         ixgbe_vlan_offload_set(dev, mask);
1569
1570         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1571                 /* Enable vlan filtering for VMDq */
1572                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1573         }
1574
1575         /* Configure DCB hw */
1576         ixgbe_configure_dcb(dev);
1577
1578         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1579                 err = ixgbe_fdir_configure(dev);
1580                 if (err)
1581                         goto error;
1582         }
1583
1584         /* Restore vf rate limit */
1585         if (vfinfo != NULL) {
1586                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1587                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1588                                 if (vfinfo[vf].tx_rate[idx] != 0)
1589                                         ixgbe_set_vf_rate_limit(dev, vf,
1590                                                 vfinfo[vf].tx_rate[idx],
1591                                                 1 << idx);
1592         }
1593
1594         ixgbe_restore_statistics_mapping(dev);
1595
1596         return (0);
1597
1598 error:
1599         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1600         ixgbe_dev_clear_queues(dev);
1601         return -EIO;
1602 }
1603
1604 /*
1605  * Stop device: disable rx and tx functions to allow for reconfiguring.
1606  */
1607 static void
1608 ixgbe_dev_stop(struct rte_eth_dev *dev)
1609 {
1610         struct rte_eth_link link;
1611         struct ixgbe_hw *hw =
1612                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613         struct ixgbe_vf_info *vfinfo =
1614                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1615         int vf;
1616
1617         PMD_INIT_FUNC_TRACE();
1618
1619         /* disable interrupts */
1620         ixgbe_disable_intr(hw);
1621
1622         /* reset the NIC */
1623         ixgbe_pf_reset_hw(hw);
1624         hw->adapter_stopped = FALSE;
1625
1626         /* stop adapter */
1627         ixgbe_stop_adapter(hw);
1628
1629         for (vf = 0; vfinfo != NULL &&
1630                      vf < dev->pci_dev->max_vfs; vf++)
1631                 vfinfo[vf].clear_to_send = false;
1632
1633         /* Turn off the laser */
1634         ixgbe_disable_tx_laser(hw);
1635
1636         ixgbe_dev_clear_queues(dev);
1637
1638         /* Clear stored conf */
1639         dev->data->scattered_rx = 0;
1640
1641         /* Clear recorded link status */
1642         memset(&link, 0, sizeof(link));
1643         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1644 }
1645
1646 /*
1647  * Set device link up: enable tx laser.
1648  */
1649 static int
1650 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1651 {
1652         struct ixgbe_hw *hw =
1653                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654         if (hw->mac.type == ixgbe_mac_82599EB) {
1655 #ifdef RTE_NIC_BYPASS
1656                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1657                         /* Not suported in bypass mode */
1658                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1659                                      "by device id 0x%x", hw->device_id);
1660                         return -ENOTSUP;
1661                 }
1662 #endif
1663                 /* Turn on the laser */
1664                 ixgbe_enable_tx_laser(hw);
1665                 return 0;
1666         }
1667
1668         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1669                      hw->device_id);
1670         return -ENOTSUP;
1671 }
1672
1673 /*
1674  * Set device link down: disable tx laser.
1675  */
1676 static int
1677 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1678 {
1679         struct ixgbe_hw *hw =
1680                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1681         if (hw->mac.type == ixgbe_mac_82599EB) {
1682 #ifdef RTE_NIC_BYPASS
1683                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1684                         /* Not suported in bypass mode */
1685                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1686                                      "by device id 0x%x", hw->device_id);
1687                         return -ENOTSUP;
1688                 }
1689 #endif
1690                 /* Turn off the laser */
1691                 ixgbe_disable_tx_laser(hw);
1692                 return 0;
1693         }
1694
1695         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1696                      hw->device_id);
1697         return -ENOTSUP;
1698 }
1699
1700 /*
1701  * Reest and stop device.
1702  */
1703 static void
1704 ixgbe_dev_close(struct rte_eth_dev *dev)
1705 {
1706         struct ixgbe_hw *hw =
1707                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1708
1709         PMD_INIT_FUNC_TRACE();
1710
1711         ixgbe_pf_reset_hw(hw);
1712
1713         ixgbe_dev_stop(dev);
1714         hw->adapter_stopped = 1;
1715
1716         ixgbe_disable_pcie_master(hw);
1717
1718         /* reprogram the RAR[0] in case user changed it. */
1719         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1720 }
1721
1722 /*
1723  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1724  */
1725 static void
1726 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1727 {
1728         struct ixgbe_hw *hw =
1729                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1730         struct ixgbe_hw_stats *hw_stats =
1731                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1732         uint32_t bprc, lxon, lxoff, total;
1733         uint64_t total_missed_rx, total_qbrc, total_qprc;
1734         unsigned i;
1735
1736         total_missed_rx = 0;
1737         total_qbrc = 0;
1738         total_qprc = 0;
1739
1740         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1741         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1742         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1743         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1744
1745         for (i = 0; i < 8; i++) {
1746                 uint32_t mp;
1747                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1748                 /* global total per queue */
1749                 hw_stats->mpc[i] += mp;
1750                 /* Running comprehensive total for stats display */
1751                 total_missed_rx += hw_stats->mpc[i];
1752                 if (hw->mac.type == ixgbe_mac_82598EB)
1753                         hw_stats->rnbc[i] +=
1754                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1755                 hw_stats->pxontxc[i] +=
1756                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1757                 hw_stats->pxonrxc[i] +=
1758                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1759                 hw_stats->pxofftxc[i] +=
1760                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1761                 hw_stats->pxoffrxc[i] +=
1762                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1763                 hw_stats->pxon2offc[i] +=
1764                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1765         }
1766         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1767                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1768                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1769                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1770                 hw_stats->qbrc[i] +=
1771                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1772                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1773                 hw_stats->qbtc[i] +=
1774                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1775                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1776
1777                 total_qprc += hw_stats->qprc[i];
1778                 total_qbrc += hw_stats->qbrc[i];
1779         }
1780         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1781         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1782         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1783
1784         /* Note that gprc counts missed packets */
1785         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1786
1787         if (hw->mac.type != ixgbe_mac_82598EB) {
1788                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1789                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1790                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1791                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1792                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1793                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1794                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1795                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1796         } else {
1797                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1798                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1799                 /* 82598 only has a counter in the high register */
1800                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1801                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1802                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1803         }
1804
1805         /*
1806          * Workaround: mprc hardware is incorrectly counting
1807          * broadcasts, so for now we subtract those.
1808          */
1809         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1810         hw_stats->bprc += bprc;
1811         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1812         if (hw->mac.type == ixgbe_mac_82598EB)
1813                 hw_stats->mprc -= bprc;
1814
1815         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1816         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1817         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1818         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1819         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1820         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1821
1822         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1823         hw_stats->lxontxc += lxon;
1824         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1825         hw_stats->lxofftxc += lxoff;
1826         total = lxon + lxoff;
1827
1828         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1829         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1830         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1831         hw_stats->gptc -= total;
1832         hw_stats->mptc -= total;
1833         hw_stats->ptc64 -= total;
1834         hw_stats->gotc -= total * ETHER_MIN_LEN;
1835
1836         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1837         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1838         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1839         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1840         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1841         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1842         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1843         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1844         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1845         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1846         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1847         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1848         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1849         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1850         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1851         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1852         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1853         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1854         /* Only read FCOE on 82599 */
1855         if (hw->mac.type != ixgbe_mac_82598EB) {
1856                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1857                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1858                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1859                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1860                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1861         }
1862
1863         if (stats == NULL)
1864                 return;
1865
1866         /* Fill out the rte_eth_stats statistics structure */
1867         stats->ipackets = total_qprc;
1868         stats->ibytes = total_qbrc;
1869         stats->opackets = hw_stats->gptc;
1870         stats->obytes = hw_stats->gotc;
1871         stats->imcasts = hw_stats->mprc;
1872
1873         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1874                 stats->q_ipackets[i] = hw_stats->qprc[i];
1875                 stats->q_opackets[i] = hw_stats->qptc[i];
1876                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1877                 stats->q_obytes[i] = hw_stats->qbtc[i];
1878                 stats->q_errors[i] = hw_stats->qprdc[i];
1879         }
1880
1881         /* Rx Errors */
1882         stats->ibadcrc  = hw_stats->crcerrs;
1883         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1884         stats->imissed  = total_missed_rx;
1885         stats->ierrors  = stats->ibadcrc +
1886                           stats->ibadlen +
1887                           stats->imissed +
1888                           hw_stats->illerrc + hw_stats->errbc;
1889
1890         /* Tx Errors */
1891         stats->oerrors  = 0;
1892
1893         /* XON/XOFF pause frames */
1894         stats->tx_pause_xon  = hw_stats->lxontxc;
1895         stats->rx_pause_xon  = hw_stats->lxonrxc;
1896         stats->tx_pause_xoff = hw_stats->lxofftxc;
1897         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1898
1899         /* Flow Director Stats registers */
1900         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1901         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1902         stats->fdirmatch = hw_stats->fdirmatch;
1903         stats->fdirmiss = hw_stats->fdirmiss;
1904 }
1905
1906 static void
1907 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1908 {
1909         struct ixgbe_hw_stats *stats =
1910                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1911
1912         /* HW registers are cleared on read */
1913         ixgbe_dev_stats_get(dev, NULL);
1914
1915         /* Reset software totals */
1916         memset(stats, 0, sizeof(*stats));
1917 }
1918
1919 static void
1920 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1921 {
1922         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1923         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1924                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1925
1926         /* Good Rx packet, include VF loopback */
1927         UPDATE_VF_STAT(IXGBE_VFGPRC,
1928             hw_stats->last_vfgprc, hw_stats->vfgprc);
1929
1930         /* Good Rx octets, include VF loopback */
1931         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1932             hw_stats->last_vfgorc, hw_stats->vfgorc);
1933
1934         /* Good Tx packet, include VF loopback */
1935         UPDATE_VF_STAT(IXGBE_VFGPTC,
1936             hw_stats->last_vfgptc, hw_stats->vfgptc);
1937
1938         /* Good Tx octets, include VF loopback */
1939         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1940             hw_stats->last_vfgotc, hw_stats->vfgotc);
1941
1942         /* Rx Multicst Packet */
1943         UPDATE_VF_STAT(IXGBE_VFMPRC,
1944             hw_stats->last_vfmprc, hw_stats->vfmprc);
1945
1946         if (stats == NULL)
1947                 return;
1948
1949         stats->ipackets = hw_stats->vfgprc;
1950         stats->ibytes = hw_stats->vfgorc;
1951         stats->opackets = hw_stats->vfgptc;
1952         stats->obytes = hw_stats->vfgotc;
1953         stats->imcasts = hw_stats->vfmprc;
1954 }
1955
1956 static void
1957 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1958 {
1959         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1960                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1961
1962         /* Sync HW register to the last stats */
1963         ixgbevf_dev_stats_get(dev, NULL);
1964
1965         /* reset HW current stats*/
1966         hw_stats->vfgprc = 0;
1967         hw_stats->vfgorc = 0;
1968         hw_stats->vfgptc = 0;
1969         hw_stats->vfgotc = 0;
1970         hw_stats->vfmprc = 0;
1971
1972 }
1973
1974 static void
1975 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1976 {
1977         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1978
1979         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1980         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1981         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1982         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1983         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1984         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1985         dev_info->max_vfs = dev->pci_dev->max_vfs;
1986         if (hw->mac.type == ixgbe_mac_82598EB)
1987                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1988         else
1989                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1990         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
1991         dev_info->rx_offload_capa =
1992                 DEV_RX_OFFLOAD_VLAN_STRIP |
1993                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1994                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1995                 DEV_RX_OFFLOAD_TCP_CKSUM;
1996         dev_info->tx_offload_capa =
1997                 DEV_TX_OFFLOAD_VLAN_INSERT |
1998                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1999                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2000                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2001                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2002                 DEV_TX_OFFLOAD_TCP_TSO;
2003
2004         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2005                 .rx_thresh = {
2006                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2007                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2008                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2009                 },
2010                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2011                 .rx_drop_en = 0,
2012         };
2013
2014         dev_info->default_txconf = (struct rte_eth_txconf) {
2015                 .tx_thresh = {
2016                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2017                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2018                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2019                 },
2020                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2021                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2022                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2023                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2024         };
2025         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2026 }
2027
2028 static void
2029 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2030                      struct rte_eth_dev_info *dev_info)
2031 {
2032         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2033
2034         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2035         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2036         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2037         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2038         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2039         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2040         dev_info->max_vfs = dev->pci_dev->max_vfs;
2041         if (hw->mac.type == ixgbe_mac_82598EB)
2042                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2043         else
2044                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2045         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2046                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2047                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2048                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2049         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2050                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2051                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2052                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2053                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2054
2055         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2056                 .rx_thresh = {
2057                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2058                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2059                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2060                 },
2061                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2062                 .rx_drop_en = 0,
2063         };
2064
2065         dev_info->default_txconf = (struct rte_eth_txconf) {
2066                 .tx_thresh = {
2067                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2068                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2069                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2070                 },
2071                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2072                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2073                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2074                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2075         };
2076 }
2077
2078 /* return 0 means link status changed, -1 means not changed */
2079 static int
2080 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2081 {
2082         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083         struct rte_eth_link link, old;
2084         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2085         int link_up;
2086         int diag;
2087
2088         link.link_status = 0;
2089         link.link_speed = 0;
2090         link.link_duplex = 0;
2091         memset(&old, 0, sizeof(old));
2092         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2093
2094         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2095         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2096                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2097         else
2098                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2099         if (diag != 0) {
2100                 link.link_speed = ETH_LINK_SPEED_100;
2101                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2102                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2103                 if (link.link_status == old.link_status)
2104                         return -1;
2105                 return 0;
2106         }
2107
2108         if (link_speed == IXGBE_LINK_SPEED_UNKNOWN &&
2109             !hw->mac.get_link_status) {
2110                 memcpy(&link, &old, sizeof(link));
2111                 return -1;
2112         }
2113
2114         if (link_up == 0) {
2115                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2116                 if (link.link_status == old.link_status)
2117                         return -1;
2118                 return 0;
2119         }
2120         link.link_status = 1;
2121         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2122
2123         switch (link_speed) {
2124         default:
2125         case IXGBE_LINK_SPEED_UNKNOWN:
2126                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2127                 link.link_speed = ETH_LINK_SPEED_100;
2128                 break;
2129
2130         case IXGBE_LINK_SPEED_100_FULL:
2131                 link.link_speed = ETH_LINK_SPEED_100;
2132                 break;
2133
2134         case IXGBE_LINK_SPEED_1GB_FULL:
2135                 link.link_speed = ETH_LINK_SPEED_1000;
2136                 break;
2137
2138         case IXGBE_LINK_SPEED_10GB_FULL:
2139                 link.link_speed = ETH_LINK_SPEED_10000;
2140                 break;
2141         }
2142         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2143
2144         if (link.link_status == old.link_status)
2145                 return -1;
2146
2147         return 0;
2148 }
2149
2150 static void
2151 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2152 {
2153         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2154         uint32_t fctrl;
2155
2156         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2157         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2158         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2159 }
2160
2161 static void
2162 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2163 {
2164         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2165         uint32_t fctrl;
2166
2167         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2168         fctrl &= (~IXGBE_FCTRL_UPE);
2169         if (dev->data->all_multicast == 1)
2170                 fctrl |= IXGBE_FCTRL_MPE;
2171         else
2172                 fctrl &= (~IXGBE_FCTRL_MPE);
2173         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2174 }
2175
2176 static void
2177 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2178 {
2179         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2180         uint32_t fctrl;
2181
2182         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2183         fctrl |= IXGBE_FCTRL_MPE;
2184         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2185 }
2186
2187 static void
2188 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2189 {
2190         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2191         uint32_t fctrl;
2192
2193         if (dev->data->promiscuous == 1)
2194                 return; /* must remain in all_multicast mode */
2195
2196         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2197         fctrl &= (~IXGBE_FCTRL_MPE);
2198         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2199 }
2200
2201 /**
2202  * It clears the interrupt causes and enables the interrupt.
2203  * It will be called once only during nic initialized.
2204  *
2205  * @param dev
2206  *  Pointer to struct rte_eth_dev.
2207  *
2208  * @return
2209  *  - On success, zero.
2210  *  - On failure, a negative value.
2211  */
2212 static int
2213 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2214 {
2215         struct ixgbe_interrupt *intr =
2216                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2217
2218         ixgbe_dev_link_status_print(dev);
2219         intr->mask |= IXGBE_EICR_LSC;
2220
2221         return 0;
2222 }
2223
2224 /*
2225  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2226  *
2227  * @param dev
2228  *  Pointer to struct rte_eth_dev.
2229  *
2230  * @return
2231  *  - On success, zero.
2232  *  - On failure, a negative value.
2233  */
2234 static int
2235 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2236 {
2237         uint32_t eicr;
2238         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239         struct ixgbe_interrupt *intr =
2240                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2241
2242         /* clear all cause mask */
2243         ixgbe_disable_intr(hw);
2244
2245         /* read-on-clear nic registers here */
2246         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2247         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2248
2249         intr->flags = 0;
2250         if (eicr & IXGBE_EICR_LSC) {
2251                 /* set flag for async link update */
2252                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2253         }
2254
2255         if (eicr & IXGBE_EICR_MAILBOX)
2256                 intr->flags |= IXGBE_FLAG_MAILBOX;
2257
2258         return 0;
2259 }
2260
2261 /**
2262  * It gets and then prints the link status.
2263  *
2264  * @param dev
2265  *  Pointer to struct rte_eth_dev.
2266  *
2267  * @return
2268  *  - On success, zero.
2269  *  - On failure, a negative value.
2270  */
2271 static void
2272 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2273 {
2274         struct rte_eth_link link;
2275
2276         memset(&link, 0, sizeof(link));
2277         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2278         if (link.link_status) {
2279                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2280                                         (int)(dev->data->port_id),
2281                                         (unsigned)link.link_speed,
2282                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2283                                         "full-duplex" : "half-duplex");
2284         } else {
2285                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2286                                 (int)(dev->data->port_id));
2287         }
2288         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2289                                 dev->pci_dev->addr.domain,
2290                                 dev->pci_dev->addr.bus,
2291                                 dev->pci_dev->addr.devid,
2292                                 dev->pci_dev->addr.function);
2293 }
2294
2295 /*
2296  * It executes link_update after knowing an interrupt occurred.
2297  *
2298  * @param dev
2299  *  Pointer to struct rte_eth_dev.
2300  *
2301  * @return
2302  *  - On success, zero.
2303  *  - On failure, a negative value.
2304  */
2305 static int
2306 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2307 {
2308         struct ixgbe_interrupt *intr =
2309                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2310         int64_t timeout;
2311         struct rte_eth_link link;
2312         int intr_enable_delay = false;
2313
2314         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2315
2316         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2317                 ixgbe_pf_mbx_process(dev);
2318                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2319         }
2320
2321         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2322                 /* get the link status before link update, for predicting later */
2323                 memset(&link, 0, sizeof(link));
2324                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2325
2326                 ixgbe_dev_link_update(dev, 0);
2327
2328                 /* likely to up */
2329                 if (!link.link_status)
2330                         /* handle it 1 sec later, wait it being stable */
2331                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2332                 /* likely to down */
2333                 else
2334                         /* handle it 4 sec later, wait it being stable */
2335                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2336
2337                 ixgbe_dev_link_status_print(dev);
2338
2339                 intr_enable_delay = true;
2340         }
2341
2342         if (intr_enable_delay) {
2343                 if (rte_eal_alarm_set(timeout * 1000,
2344                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2345                         PMD_DRV_LOG(ERR, "Error setting alarm");
2346         } else {
2347                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2348                 ixgbe_enable_intr(dev);
2349                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2350         }
2351
2352
2353         return 0;
2354 }
2355
2356 /**
2357  * Interrupt handler which shall be registered for alarm callback for delayed
2358  * handling specific interrupt to wait for the stable nic state. As the
2359  * NIC interrupt state is not stable for ixgbe after link is just down,
2360  * it needs to wait 4 seconds to get the stable status.
2361  *
2362  * @param handle
2363  *  Pointer to interrupt handle.
2364  * @param param
2365  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2366  *
2367  * @return
2368  *  void
2369  */
2370 static void
2371 ixgbe_dev_interrupt_delayed_handler(void *param)
2372 {
2373         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2374         struct ixgbe_interrupt *intr =
2375                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2376         struct ixgbe_hw *hw =
2377                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2378         uint32_t eicr;
2379
2380         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2381         if (eicr & IXGBE_EICR_MAILBOX)
2382                 ixgbe_pf_mbx_process(dev);
2383
2384         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2385                 ixgbe_dev_link_update(dev, 0);
2386                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2387                 ixgbe_dev_link_status_print(dev);
2388                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2389         }
2390
2391         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2392         ixgbe_enable_intr(dev);
2393         rte_intr_enable(&(dev->pci_dev->intr_handle));
2394 }
2395
2396 /**
2397  * Interrupt handler triggered by NIC  for handling
2398  * specific interrupt.
2399  *
2400  * @param handle
2401  *  Pointer to interrupt handle.
2402  * @param param
2403  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2404  *
2405  * @return
2406  *  void
2407  */
2408 static void
2409 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2410                                                         void *param)
2411 {
2412         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2413         ixgbe_dev_interrupt_get_status(dev);
2414         ixgbe_dev_interrupt_action(dev);
2415 }
2416
2417 static int
2418 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2419 {
2420         struct ixgbe_hw *hw;
2421
2422         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2424 }
2425
2426 static int
2427 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2428 {
2429         struct ixgbe_hw *hw;
2430
2431         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2432         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2433 }
2434
2435 static int
2436 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2437 {
2438         struct ixgbe_hw *hw;
2439         uint32_t mflcn_reg;
2440         uint32_t fccfg_reg;
2441         int rx_pause;
2442         int tx_pause;
2443
2444         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2445
2446         fc_conf->pause_time = hw->fc.pause_time;
2447         fc_conf->high_water = hw->fc.high_water[0];
2448         fc_conf->low_water = hw->fc.low_water[0];
2449         fc_conf->send_xon = hw->fc.send_xon;
2450         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2451
2452         /*
2453          * Return rx_pause status according to actual setting of
2454          * MFLCN register.
2455          */
2456         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2457         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2458                 rx_pause = 1;
2459         else
2460                 rx_pause = 0;
2461
2462         /*
2463          * Return tx_pause status according to actual setting of
2464          * FCCFG register.
2465          */
2466         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2467         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2468                 tx_pause = 1;
2469         else
2470                 tx_pause = 0;
2471
2472         if (rx_pause && tx_pause)
2473                 fc_conf->mode = RTE_FC_FULL;
2474         else if (rx_pause)
2475                 fc_conf->mode = RTE_FC_RX_PAUSE;
2476         else if (tx_pause)
2477                 fc_conf->mode = RTE_FC_TX_PAUSE;
2478         else
2479                 fc_conf->mode = RTE_FC_NONE;
2480
2481         return 0;
2482 }
2483
2484 static int
2485 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2486 {
2487         struct ixgbe_hw *hw;
2488         int err;
2489         uint32_t rx_buf_size;
2490         uint32_t max_high_water;
2491         uint32_t mflcn;
2492         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2493                 ixgbe_fc_none,
2494                 ixgbe_fc_rx_pause,
2495                 ixgbe_fc_tx_pause,
2496                 ixgbe_fc_full
2497         };
2498
2499         PMD_INIT_FUNC_TRACE();
2500
2501         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2502         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2503                 return -ENOTSUP;
2504         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2505         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2506
2507         /*
2508          * At least reserve one Ethernet frame for watermark
2509          * high_water/low_water in kilo bytes for ixgbe
2510          */
2511         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2512         if ((fc_conf->high_water > max_high_water) ||
2513                 (fc_conf->high_water < fc_conf->low_water)) {
2514                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2515                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2516                 return (-EINVAL);
2517         }
2518
2519         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2520         hw->fc.pause_time     = fc_conf->pause_time;
2521         hw->fc.high_water[0]  = fc_conf->high_water;
2522         hw->fc.low_water[0]   = fc_conf->low_water;
2523         hw->fc.send_xon       = fc_conf->send_xon;
2524
2525         err = ixgbe_fc_enable(hw);
2526
2527         /* Not negotiated is not an error case */
2528         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2529
2530                 /* check if we want to forward MAC frames - driver doesn't have native
2531                  * capability to do that, so we'll write the registers ourselves */
2532
2533                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2534
2535                 /* set or clear MFLCN.PMCF bit depending on configuration */
2536                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2537                         mflcn |= IXGBE_MFLCN_PMCF;
2538                 else
2539                         mflcn &= ~IXGBE_MFLCN_PMCF;
2540
2541                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2542                 IXGBE_WRITE_FLUSH(hw);
2543
2544                 return 0;
2545         }
2546
2547         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2548         return -EIO;
2549 }
2550
2551 /**
2552  *  ixgbe_pfc_enable_generic - Enable flow control
2553  *  @hw: pointer to hardware structure
2554  *  @tc_num: traffic class number
2555  *  Enable flow control according to the current settings.
2556  */
2557 static int
2558 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2559 {
2560         int ret_val = 0;
2561         uint32_t mflcn_reg, fccfg_reg;
2562         uint32_t reg;
2563         uint32_t fcrtl, fcrth;
2564         uint8_t i;
2565         uint8_t nb_rx_en;
2566
2567         /* Validate the water mark configuration */
2568         if (!hw->fc.pause_time) {
2569                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2570                 goto out;
2571         }
2572
2573         /* Low water mark of zero causes XOFF floods */
2574         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2575                  /* High/Low water can not be 0 */
2576                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2577                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2578                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2579                         goto out;
2580                 }
2581
2582                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2583                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2584                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2585                         goto out;
2586                 }
2587         }
2588         /* Negotiate the fc mode to use */
2589         ixgbe_fc_autoneg(hw);
2590
2591         /* Disable any previous flow control settings */
2592         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2593         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2594
2595         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2596         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2597
2598         switch (hw->fc.current_mode) {
2599         case ixgbe_fc_none:
2600                 /*
2601                  * If the count of enabled RX Priority Flow control >1,
2602                  * and the TX pause can not be disabled
2603                  */
2604                 nb_rx_en = 0;
2605                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2606                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2607                         if (reg & IXGBE_FCRTH_FCEN)
2608                                 nb_rx_en++;
2609                 }
2610                 if (nb_rx_en > 1)
2611                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2612                 break;
2613         case ixgbe_fc_rx_pause:
2614                 /*
2615                  * Rx Flow control is enabled and Tx Flow control is
2616                  * disabled by software override. Since there really
2617                  * isn't a way to advertise that we are capable of RX
2618                  * Pause ONLY, we will advertise that we support both
2619                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2620                  * disable the adapter's ability to send PAUSE frames.
2621                  */
2622                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2623                 /*
2624                  * If the count of enabled RX Priority Flow control >1,
2625                  * and the TX pause can not be disabled
2626                  */
2627                 nb_rx_en = 0;
2628                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2629                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2630                         if (reg & IXGBE_FCRTH_FCEN)
2631                                 nb_rx_en++;
2632                 }
2633                 if (nb_rx_en > 1)
2634                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2635                 break;
2636         case ixgbe_fc_tx_pause:
2637                 /*
2638                  * Tx Flow control is enabled, and Rx Flow control is
2639                  * disabled by software override.
2640                  */
2641                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2642                 break;
2643         case ixgbe_fc_full:
2644                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2645                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2646                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2647                 break;
2648         default:
2649                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2650                 ret_val = IXGBE_ERR_CONFIG;
2651                 goto out;
2652                 break;
2653         }
2654
2655         /* Set 802.3x based flow control settings. */
2656         mflcn_reg |= IXGBE_MFLCN_DPF;
2657         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2658         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2659
2660         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2661         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2662                 hw->fc.high_water[tc_num]) {
2663                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2664                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2665                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2666         } else {
2667                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2668                 /*
2669                  * In order to prevent Tx hangs when the internal Tx
2670                  * switch is enabled we must set the high water mark
2671                  * to the maximum FCRTH value.  This allows the Tx
2672                  * switch to function even under heavy Rx workloads.
2673                  */
2674                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2675         }
2676         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2677
2678         /* Configure pause time (2 TCs per register) */
2679         reg = hw->fc.pause_time * 0x00010001;
2680         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2681                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2682
2683         /* Configure flow control refresh threshold value */
2684         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2685
2686 out:
2687         return ret_val;
2688 }
2689
2690 static int
2691 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2692 {
2693         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2694         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2695
2696         if(hw->mac.type != ixgbe_mac_82598EB) {
2697                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2698         }
2699         return ret_val;
2700 }
2701
2702 static int
2703 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2704 {
2705         int err;
2706         uint32_t rx_buf_size;
2707         uint32_t max_high_water;
2708         uint8_t tc_num;
2709         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2710         struct ixgbe_hw *hw =
2711                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2712         struct ixgbe_dcb_config *dcb_config =
2713                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2714
2715         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2716                 ixgbe_fc_none,
2717                 ixgbe_fc_rx_pause,
2718                 ixgbe_fc_tx_pause,
2719                 ixgbe_fc_full
2720         };
2721
2722         PMD_INIT_FUNC_TRACE();
2723
2724         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2725         tc_num = map[pfc_conf->priority];
2726         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2727         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2728         /*
2729          * At least reserve one Ethernet frame for watermark
2730          * high_water/low_water in kilo bytes for ixgbe
2731          */
2732         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2733         if ((pfc_conf->fc.high_water > max_high_water) ||
2734             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2735                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2736                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2737                 return (-EINVAL);
2738         }
2739
2740         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2741         hw->fc.pause_time = pfc_conf->fc.pause_time;
2742         hw->fc.send_xon = pfc_conf->fc.send_xon;
2743         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2744         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2745
2746         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2747
2748         /* Not negotiated is not an error case */
2749         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2750                 return 0;
2751
2752         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2753         return -EIO;
2754 }
2755
2756 static int
2757 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2758                           struct rte_eth_rss_reta_entry64 *reta_conf,
2759                           uint16_t reta_size)
2760 {
2761         uint8_t i, j, mask;
2762         uint32_t reta, r;
2763         uint16_t idx, shift;
2764         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2765
2766         PMD_INIT_FUNC_TRACE();
2767         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2768                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2769                         "(%d) doesn't match the number hardware can supported "
2770                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2771                 return -EINVAL;
2772         }
2773
2774         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2775                 idx = i / RTE_RETA_GROUP_SIZE;
2776                 shift = i % RTE_RETA_GROUP_SIZE;
2777                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2778                                                 IXGBE_4_BIT_MASK);
2779                 if (!mask)
2780                         continue;
2781                 if (mask == IXGBE_4_BIT_MASK)
2782                         r = 0;
2783                 else
2784                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2785                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2786                         if (mask & (0x1 << j))
2787                                 reta |= reta_conf[idx].reta[shift + j] <<
2788                                                         (CHAR_BIT * j);
2789                         else
2790                                 reta |= r & (IXGBE_8_BIT_MASK <<
2791                                                 (CHAR_BIT * j));
2792                 }
2793                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2794         }
2795
2796         return 0;
2797 }
2798
2799 static int
2800 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2801                          struct rte_eth_rss_reta_entry64 *reta_conf,
2802                          uint16_t reta_size)
2803 {
2804         uint8_t i, j, mask;
2805         uint32_t reta;
2806         uint16_t idx, shift;
2807         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808
2809         PMD_INIT_FUNC_TRACE();
2810         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2811                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2812                         "(%d) doesn't match the number hardware can supported "
2813                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2814                 return -EINVAL;
2815         }
2816
2817         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2818                 idx = i / RTE_RETA_GROUP_SIZE;
2819                 shift = i % RTE_RETA_GROUP_SIZE;
2820                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2821                                                 IXGBE_4_BIT_MASK);
2822                 if (!mask)
2823                         continue;
2824
2825                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2826                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2827                         if (mask & (0x1 << j))
2828                                 reta_conf[idx].reta[shift + j] =
2829                                         ((reta >> (CHAR_BIT * j)) &
2830                                                 IXGBE_8_BIT_MASK);
2831                 }
2832         }
2833
2834         return 0;
2835 }
2836
2837 static void
2838 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2839                                 uint32_t index, uint32_t pool)
2840 {
2841         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842         uint32_t enable_addr = 1;
2843
2844         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2845 }
2846
2847 static void
2848 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2849 {
2850         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2851
2852         ixgbe_clear_rar(hw, index);
2853 }
2854
2855 static int
2856 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2857 {
2858         uint32_t hlreg0;
2859         uint32_t maxfrs;
2860         struct ixgbe_hw *hw;
2861         struct rte_eth_dev_info dev_info;
2862         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2863
2864         ixgbe_dev_info_get(dev, &dev_info);
2865
2866         /* check that mtu is within the allowed range */
2867         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2868                 return -EINVAL;
2869
2870         /* refuse mtu that requires the support of scattered packets when this
2871          * feature has not been enabled before. */
2872         if (!dev->data->scattered_rx &&
2873             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2874              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2875                 return -EINVAL;
2876
2877         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2878         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2879
2880         /* switch to jumbo mode if needed */
2881         if (frame_size > ETHER_MAX_LEN) {
2882                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2883                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2884         } else {
2885                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2886                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2887         }
2888         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2889
2890         /* update max frame size */
2891         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2892
2893         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2894         maxfrs &= 0x0000FFFF;
2895         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2896         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2897
2898         return 0;
2899 }
2900
2901 /*
2902  * Virtual Function operations
2903  */
2904 static void
2905 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2906 {
2907         PMD_INIT_FUNC_TRACE();
2908
2909         /* Clear interrupt mask to stop from interrupts being generated */
2910         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2911
2912         IXGBE_WRITE_FLUSH(hw);
2913 }
2914
2915 static int
2916 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2917 {
2918         struct rte_eth_conf* conf = &dev->data->dev_conf;
2919
2920         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2921                      dev->data->port_id);
2922
2923         /*
2924          * VF has no ability to enable/disable HW CRC
2925          * Keep the persistent behavior the same as Host PF
2926          */
2927 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2928         if (!conf->rxmode.hw_strip_crc) {
2929                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2930                 conf->rxmode.hw_strip_crc = 1;
2931         }
2932 #else
2933         if (conf->rxmode.hw_strip_crc) {
2934                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2935                 conf->rxmode.hw_strip_crc = 0;
2936         }
2937 #endif
2938
2939         return 0;
2940 }
2941
2942 static int
2943 ixgbevf_dev_start(struct rte_eth_dev *dev)
2944 {
2945         struct ixgbe_hw *hw =
2946                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2947         int err, mask = 0;
2948
2949         PMD_INIT_FUNC_TRACE();
2950
2951         hw->mac.ops.reset_hw(hw);
2952         hw->mac.get_link_status = true;
2953
2954         /* negotiate mailbox API version to use with the PF. */
2955         ixgbevf_negotiate_api(hw);
2956
2957         ixgbevf_dev_tx_init(dev);
2958
2959         /* This can fail when allocating mbufs for descriptor rings */
2960         err = ixgbevf_dev_rx_init(dev);
2961         if (err) {
2962                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2963                 ixgbe_dev_clear_queues(dev);
2964                 return err;
2965         }
2966
2967         /* Set vfta */
2968         ixgbevf_set_vfta_all(dev,1);
2969
2970         /* Set HW strip */
2971         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2972                 ETH_VLAN_EXTEND_MASK;
2973         ixgbevf_vlan_offload_set(dev, mask);
2974
2975         ixgbevf_dev_rxtx_start(dev);
2976
2977         return 0;
2978 }
2979
2980 static void
2981 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2982 {
2983         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2984
2985         PMD_INIT_FUNC_TRACE();
2986
2987         hw->adapter_stopped = TRUE;
2988         ixgbe_stop_adapter(hw);
2989
2990         /*
2991           * Clear what we set, but we still keep shadow_vfta to
2992           * restore after device starts
2993           */
2994         ixgbevf_set_vfta_all(dev,0);
2995
2996         /* Clear stored conf */
2997         dev->data->scattered_rx = 0;
2998
2999         ixgbe_dev_clear_queues(dev);
3000 }
3001
3002 static void
3003 ixgbevf_dev_close(struct rte_eth_dev *dev)
3004 {
3005         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3006
3007         PMD_INIT_FUNC_TRACE();
3008
3009         ixgbe_reset_hw(hw);
3010
3011         ixgbevf_dev_stop(dev);
3012
3013         /* reprogram the RAR[0] in case user changed it. */
3014         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3015 }
3016
3017 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3018 {
3019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3020         struct ixgbe_vfta * shadow_vfta =
3021                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3022         int i = 0, j = 0, vfta = 0, mask = 1;
3023
3024         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3025                 vfta = shadow_vfta->vfta[i];
3026                 if(vfta){
3027                         mask = 1;
3028                         for (j = 0; j < 32; j++){
3029                                 if(vfta & mask)
3030                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3031                                 mask<<=1;
3032                         }
3033                 }
3034         }
3035
3036 }
3037
3038 static int
3039 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3040 {
3041         struct ixgbe_hw *hw =
3042                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3043         struct ixgbe_vfta * shadow_vfta =
3044                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3045         uint32_t vid_idx = 0;
3046         uint32_t vid_bit = 0;
3047         int ret = 0;
3048
3049         PMD_INIT_FUNC_TRACE();
3050
3051         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3052         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3053         if(ret){
3054                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3055                 return ret;
3056         }
3057         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3058         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3059
3060         /* Save what we set and retore it after device reset */
3061         if (on)
3062                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3063         else
3064                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3065
3066         return 0;
3067 }
3068
3069 static void
3070 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3071 {
3072         struct ixgbe_hw *hw =
3073                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3074         uint32_t ctrl;
3075
3076         PMD_INIT_FUNC_TRACE();
3077
3078         if(queue >= hw->mac.max_rx_queues)
3079                 return;
3080
3081         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3082         if(on)
3083                 ctrl |= IXGBE_RXDCTL_VME;
3084         else
3085                 ctrl &= ~IXGBE_RXDCTL_VME;
3086         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3087
3088         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3089 }
3090
3091 static void
3092 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3093 {
3094         struct ixgbe_hw *hw =
3095                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3096         uint16_t i;
3097         int on = 0;
3098
3099         /* VF function only support hw strip feature, others are not support */
3100         if(mask & ETH_VLAN_STRIP_MASK){
3101                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3102
3103                 for(i=0; i < hw->mac.max_rx_queues; i++)
3104                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3105         }
3106 }
3107
3108 static int
3109 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3110 {
3111         uint32_t reg_val;
3112
3113         /* we only need to do this if VMDq is enabled */
3114         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3115         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3116                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3117                 return (-1);
3118         }
3119
3120         return 0;
3121 }
3122
3123 static uint32_t
3124 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3125 {
3126         uint32_t vector = 0;
3127         switch (hw->mac.mc_filter_type) {
3128         case 0:   /* use bits [47:36] of the address */
3129                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3130                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3131                 break;
3132         case 1:   /* use bits [46:35] of the address */
3133                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3134                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3135                 break;
3136         case 2:   /* use bits [45:34] of the address */
3137                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3138                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3139                 break;
3140         case 3:   /* use bits [43:32] of the address */
3141                 vector = ((uc_addr->addr_bytes[4]) |
3142                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3143                 break;
3144         default:  /* Invalid mc_filter_type */
3145                 break;
3146         }
3147
3148         /* vector can only be 12-bits or boundary will be exceeded */
3149         vector &= 0xFFF;
3150         return vector;
3151 }
3152
3153 static int
3154 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3155                                uint8_t on)
3156 {
3157         uint32_t vector;
3158         uint32_t uta_idx;
3159         uint32_t reg_val;
3160         uint32_t uta_shift;
3161         uint32_t rc;
3162         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3163         const uint32_t ixgbe_uta_bit_shift = 5;
3164         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3165         const uint32_t bit1 = 0x1;
3166
3167         struct ixgbe_hw *hw =
3168                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3169         struct ixgbe_uta_info *uta_info =
3170                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3171
3172         /* The UTA table only exists on 82599 hardware and newer */
3173         if (hw->mac.type < ixgbe_mac_82599EB)
3174                 return (-ENOTSUP);
3175
3176         vector = ixgbe_uta_vector(hw,mac_addr);
3177         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3178         uta_shift = vector & ixgbe_uta_bit_mask;
3179
3180         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3181         if(rc == on)
3182                 return 0;
3183
3184         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3185         if (on) {
3186                 uta_info->uta_in_use++;
3187                 reg_val |= (bit1 << uta_shift);
3188                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3189         } else {
3190                 uta_info->uta_in_use--;
3191                 reg_val &= ~(bit1 << uta_shift);
3192                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3193         }
3194
3195         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3196
3197         if (uta_info->uta_in_use > 0)
3198                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3199                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3200         else
3201                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3202
3203         return 0;
3204 }
3205
3206 static int
3207 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3208 {
3209         int i;
3210         struct ixgbe_hw *hw =
3211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3212         struct ixgbe_uta_info *uta_info =
3213                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3214
3215         /* The UTA table only exists on 82599 hardware and newer */
3216         if (hw->mac.type < ixgbe_mac_82599EB)
3217                 return (-ENOTSUP);
3218
3219         if(on) {
3220                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3221                         uta_info->uta_shadow[i] = ~0;
3222                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3223                 }
3224         } else {
3225                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3226                         uta_info->uta_shadow[i] = 0;
3227                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3228                 }
3229         }
3230         return 0;
3231
3232 }
3233
3234 uint32_t
3235 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3236 {
3237         uint32_t new_val = orig_val;
3238
3239         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3240                 new_val |= IXGBE_VMOLR_AUPE;
3241         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3242                 new_val |= IXGBE_VMOLR_ROMPE;
3243         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3244                 new_val |= IXGBE_VMOLR_ROPE;
3245         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3246                 new_val |= IXGBE_VMOLR_BAM;
3247         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3248                 new_val |= IXGBE_VMOLR_MPE;
3249
3250         return new_val;
3251 }
3252
3253 static int
3254 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3255                                uint16_t rx_mask, uint8_t on)
3256 {
3257         int val = 0;
3258
3259         struct ixgbe_hw *hw =
3260                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3261         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3262
3263         if (hw->mac.type == ixgbe_mac_82598EB) {
3264                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3265                              " on 82599 hardware and newer");
3266                 return (-ENOTSUP);
3267         }
3268         if (ixgbe_vmdq_mode_check(hw) < 0)
3269                 return (-ENOTSUP);
3270
3271         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3272
3273         if (on)
3274                 vmolr |= val;
3275         else
3276                 vmolr &= ~val;
3277
3278         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3279
3280         return 0;
3281 }
3282
3283 static int
3284 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3285 {
3286         uint32_t reg,addr;
3287         uint32_t val;
3288         const uint8_t bit1 = 0x1;
3289
3290         struct ixgbe_hw *hw =
3291                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3292
3293         if (ixgbe_vmdq_mode_check(hw) < 0)
3294                 return (-ENOTSUP);
3295
3296         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3297         reg = IXGBE_READ_REG(hw, addr);
3298         val = bit1 << pool;
3299
3300         if (on)
3301                 reg |= val;
3302         else
3303                 reg &= ~val;
3304
3305         IXGBE_WRITE_REG(hw, addr,reg);
3306
3307         return 0;
3308 }
3309
3310 static int
3311 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3312 {
3313         uint32_t reg,addr;
3314         uint32_t val;
3315         const uint8_t bit1 = 0x1;
3316
3317         struct ixgbe_hw *hw =
3318                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3319
3320         if (ixgbe_vmdq_mode_check(hw) < 0)
3321                 return (-ENOTSUP);
3322
3323         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3324         reg = IXGBE_READ_REG(hw, addr);
3325         val = bit1 << pool;
3326
3327         if (on)
3328                 reg |= val;
3329         else
3330                 reg &= ~val;
3331
3332         IXGBE_WRITE_REG(hw, addr,reg);
3333
3334         return 0;
3335 }
3336
3337 static int
3338 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3339                         uint64_t pool_mask, uint8_t vlan_on)
3340 {
3341         int ret = 0;
3342         uint16_t pool_idx;
3343         struct ixgbe_hw *hw =
3344                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3345
3346         if (ixgbe_vmdq_mode_check(hw) < 0)
3347                 return (-ENOTSUP);
3348         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3349                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3350                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3351                         if (ret < 0)
3352                                 return ret;
3353         }
3354
3355         return ret;
3356 }
3357
3358 static int
3359 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3360                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3361                         uint8_t rule_id, uint8_t on)
3362 {
3363         uint32_t mr_ctl,vlvf;
3364         uint32_t mp_lsb = 0;
3365         uint32_t mv_msb = 0;
3366         uint32_t mv_lsb = 0;
3367         uint32_t mp_msb = 0;
3368         uint8_t i = 0;
3369         int reg_index = 0;
3370         uint64_t vlan_mask = 0;
3371
3372         const uint8_t pool_mask_offset = 32;
3373         const uint8_t vlan_mask_offset = 32;
3374         const uint8_t dst_pool_offset = 8;
3375         const uint8_t rule_mr_offset  = 4;
3376         const uint8_t mirror_rule_mask= 0x0F;
3377
3378         struct ixgbe_mirror_info *mr_info =
3379                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3380         struct ixgbe_hw *hw =
3381                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3382
3383         if (ixgbe_vmdq_mode_check(hw) < 0)
3384                 return (-ENOTSUP);
3385
3386         /* Check if vlan mask is valid */
3387         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3388                 if (mirror_conf->vlan.vlan_mask == 0)
3389                         return (-EINVAL);
3390         }
3391
3392         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3393         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3394                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3395                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3396                                 /* search vlan id related pool vlan filter index */
3397                                 reg_index = ixgbe_find_vlvf_slot(hw,
3398                                                 mirror_conf->vlan.vlan_id[i]);
3399                                 if(reg_index < 0)
3400                                         return (-EINVAL);
3401                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3402                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3403                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3404                                                 == mirror_conf->vlan.vlan_id[i]))
3405                                         vlan_mask |= (1ULL << reg_index);
3406                                 else
3407                                         return (-EINVAL);
3408                         }
3409                 }
3410
3411                 if (on) {
3412                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3413                         mv_msb = vlan_mask >> vlan_mask_offset;
3414
3415                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3416                                                 mirror_conf->vlan.vlan_mask;
3417                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3418                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3419                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3420                                                 mirror_conf->vlan.vlan_id[i];
3421                         }
3422                 } else {
3423                         mv_lsb = 0;
3424                         mv_msb = 0;
3425                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3426                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3427                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3428                 }
3429         }
3430
3431         /*
3432          * if enable pool mirror, write related pool mask register,if disable
3433          * pool mirror, clear PFMRVM register
3434          */
3435         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3436                 if (on) {
3437                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3438                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3439                         mr_info->mr_conf[rule_id].pool_mask =
3440                                         mirror_conf->pool_mask;
3441
3442                 } else {
3443                         mp_lsb = 0;
3444                         mp_msb = 0;
3445                         mr_info->mr_conf[rule_id].pool_mask = 0;
3446                 }
3447         }
3448
3449         /* read  mirror control register and recalculate it */
3450         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3451
3452         if (on) {
3453                 mr_ctl |= mirror_conf->rule_type_mask;
3454                 mr_ctl &= mirror_rule_mask;
3455                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3456         } else
3457                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3458
3459         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3460         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3461
3462         /* write mirrror control  register */
3463         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3464
3465         /* write pool mirrror control  register */
3466         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3467                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3468                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3469                                 mp_msb);
3470         }
3471         /* write VLAN mirrror control  register */
3472         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3473                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3474                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3475                                 mv_msb);
3476         }
3477
3478         return 0;
3479 }
3480
3481 static int
3482 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3483 {
3484         int mr_ctl = 0;
3485         uint32_t lsb_val = 0;
3486         uint32_t msb_val = 0;
3487         const uint8_t rule_mr_offset = 4;
3488
3489         struct ixgbe_hw *hw =
3490                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3491         struct ixgbe_mirror_info *mr_info =
3492                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3493
3494         if (ixgbe_vmdq_mode_check(hw) < 0)
3495                 return (-ENOTSUP);
3496
3497         memset(&mr_info->mr_conf[rule_id], 0,
3498                 sizeof(struct rte_eth_vmdq_mirror_conf));
3499
3500         /* clear PFVMCTL register */
3501         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3502
3503         /* clear pool mask register */
3504         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3505         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3506
3507         /* clear vlan mask register */
3508         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3509         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3510
3511         return 0;
3512 }
3513
3514 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3515         uint16_t queue_idx, uint16_t tx_rate)
3516 {
3517         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3518         uint32_t rf_dec, rf_int;
3519         uint32_t bcnrc_val;
3520         uint16_t link_speed = dev->data->dev_link.link_speed;
3521
3522         if (queue_idx >= hw->mac.max_tx_queues)
3523                 return -EINVAL;
3524
3525         if (tx_rate != 0) {
3526                 /* Calculate the rate factor values to set */
3527                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3528                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3529                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3530
3531                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3532                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3533                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3534                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3535         } else {
3536                 bcnrc_val = 0;
3537         }
3538
3539         /*
3540          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3541          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3542          * set as 0x4.
3543          */
3544         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3545                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3546                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3547                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3548                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3549         else
3550                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3551                         IXGBE_MMW_SIZE_DEFAULT);
3552
3553         /* Set RTTBCNRC of queue X */
3554         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3555         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3556         IXGBE_WRITE_FLUSH(hw);
3557
3558         return 0;
3559 }
3560
3561 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3562         uint16_t tx_rate, uint64_t q_msk)
3563 {
3564         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3565         struct ixgbe_vf_info *vfinfo =
3566                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3567         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3568         uint32_t queue_stride =
3569                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3570         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3571         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3572         uint16_t total_rate = 0;
3573
3574         if (queue_end >= hw->mac.max_tx_queues)
3575                 return -EINVAL;
3576
3577         if (vfinfo != NULL) {
3578                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3579                         if (vf_idx == vf)
3580                                 continue;
3581                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3582                                 idx++)
3583                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3584                 }
3585         } else
3586                 return -EINVAL;
3587
3588         /* Store tx_rate for this vf. */
3589         for (idx = 0; idx < nb_q_per_pool; idx++) {
3590                 if (((uint64_t)0x1 << idx) & q_msk) {
3591                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3592                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3593                         total_rate += tx_rate;
3594                 }
3595         }
3596
3597         if (total_rate > dev->data->dev_link.link_speed) {
3598                 /*
3599                  * Reset stored TX rate of the VF if it causes exceed
3600                  * link speed.
3601                  */
3602                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3603                 return -EINVAL;
3604         }
3605
3606         /* Set RTTBCNRC of each queue/pool for vf X  */
3607         for (; queue_idx <= queue_end; queue_idx++) {
3608                 if (0x1 & q_msk)
3609                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3610                 q_msk = q_msk >> 1;
3611         }
3612
3613         return 0;
3614 }
3615
3616 static void
3617 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3618                      __attribute__((unused)) uint32_t index,
3619                      __attribute__((unused)) uint32_t pool)
3620 {
3621         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3622         int diag;
3623
3624         /*
3625          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3626          * operation. Trap this case to avoid exhausting the [very limited]
3627          * set of PF resources used to store VF MAC addresses.
3628          */
3629         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3630                 return;
3631         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3632         if (diag == 0)
3633                 return;
3634         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3635 }
3636
3637 static void
3638 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3639 {
3640         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3641         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3642         struct ether_addr *mac_addr;
3643         uint32_t i;
3644         int diag;
3645
3646         /*
3647          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3648          * not support the deletion of a given MAC address.
3649          * Instead, it imposes to delete all MAC addresses, then to add again
3650          * all MAC addresses with the exception of the one to be deleted.
3651          */
3652         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3653
3654         /*
3655          * Add again all MAC addresses, with the exception of the deleted one
3656          * and of the permanent MAC address.
3657          */
3658         for (i = 0, mac_addr = dev->data->mac_addrs;
3659              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3660                 /* Skip the deleted MAC address */
3661                 if (i == index)
3662                         continue;
3663                 /* Skip NULL MAC addresses */
3664                 if (is_zero_ether_addr(mac_addr))
3665                         continue;
3666                 /* Skip the permanent MAC address */
3667                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3668                         continue;
3669                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3670                 if (diag != 0)
3671                         PMD_DRV_LOG(ERR,
3672                                     "Adding again MAC address "
3673                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3674                                     "diag=%d",
3675                                     mac_addr->addr_bytes[0],
3676                                     mac_addr->addr_bytes[1],
3677                                     mac_addr->addr_bytes[2],
3678                                     mac_addr->addr_bytes[3],
3679                                     mac_addr->addr_bytes[4],
3680                                     mac_addr->addr_bytes[5],
3681                                     diag);
3682         }
3683 }
3684
3685 /*
3686  * add syn filter
3687  *
3688  * @param
3689  * dev: Pointer to struct rte_eth_dev.
3690  * filter: ponter to the filter that will be added.
3691  * rx_queue: the queue id the filter assigned to.
3692  *
3693  * @return
3694  *    - On success, zero.
3695  *    - On failure, a negative value.
3696  */
3697 static int
3698 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3699                         struct rte_syn_filter *filter, uint16_t rx_queue)
3700 {
3701         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3702         uint32_t synqf;
3703
3704         if (hw->mac.type != ixgbe_mac_82599EB)
3705                 return -ENOSYS;
3706
3707         if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3708                 return -EINVAL;
3709
3710         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3711
3712         if (synqf & IXGBE_SYN_FILTER_ENABLE)
3713                 return -EINVAL;
3714
3715         synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3716                 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3717
3718         if (filter->hig_pri)
3719                 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3720         else
3721                 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3722
3723         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3724         return 0;
3725 }
3726
3727 /*
3728  * remove syn filter
3729  *
3730  * @param
3731  * dev: Pointer to struct rte_eth_dev.
3732  *
3733  * @return
3734  *    - On success, zero.
3735  *    - On failure, a negative value.
3736  */
3737 static int
3738 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3739 {
3740         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3741         uint32_t synqf;
3742
3743         if (hw->mac.type != ixgbe_mac_82599EB)
3744                 return -ENOSYS;
3745
3746         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3747
3748         synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3749
3750         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3751         return 0;
3752 }
3753
3754 /*
3755  * get the syn filter's info
3756  *
3757  * @param
3758  * dev: Pointer to struct rte_eth_dev.
3759  * filter: ponter to the filter that returns.
3760  * *rx_queue: pointer to the queue id the filter assigned to.
3761  *
3762  * @return
3763  *    - On success, zero.
3764  *    - On failure, a negative value.
3765  */
3766 static int
3767 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3768                         struct rte_syn_filter *filter, uint16_t *rx_queue)
3769
3770 {
3771         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3772         uint32_t synqf;
3773
3774         if (hw->mac.type != ixgbe_mac_82599EB)
3775                 return -ENOSYS;
3776
3777         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3778         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3779                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3780                 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3781                 return 0;
3782         }
3783         return -ENOENT;
3784 }
3785
3786 static inline enum ixgbe_5tuple_protocol
3787 convert_protocol_type(uint8_t protocol_value)
3788 {
3789         if (protocol_value == IPPROTO_TCP)
3790                 return IXGBE_FILTER_PROTOCOL_TCP;
3791         else if (protocol_value == IPPROTO_UDP)
3792                 return IXGBE_FILTER_PROTOCOL_UDP;
3793         else if (protocol_value == IPPROTO_SCTP)
3794                 return IXGBE_FILTER_PROTOCOL_SCTP;
3795         else
3796                 return IXGBE_FILTER_PROTOCOL_NONE;
3797 }
3798
3799 static inline uint8_t
3800 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3801 {
3802         if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3803                 return IPPROTO_TCP;
3804         else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3805                 return IPPROTO_UDP;
3806         else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3807                 return IPPROTO_SCTP;
3808         else
3809                 return 0;
3810 }
3811
3812 /*
3813  * add a 5tuple filter
3814  *
3815  * @param
3816  * dev: Pointer to struct rte_eth_dev.
3817  * index: the index the filter allocates.
3818  * filter: ponter to the filter that will be added.
3819  * rx_queue: the queue id the filter assigned to.
3820  *
3821  * @return
3822  *    - On success, zero.
3823  *    - On failure, a negative value.
3824  */
3825 static int
3826 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3827                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
3828 {
3829         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3830         uint32_t ftqf, sdpqf = 0;
3831         uint32_t l34timir = 0;
3832         uint8_t mask = 0xff;
3833
3834         if (hw->mac.type != ixgbe_mac_82599EB)
3835                 return -ENOSYS;
3836
3837         if (index >= IXGBE_MAX_FTQF_FILTERS ||
3838                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3839                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3840                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3841                 return -EINVAL;  /* filter index is out of range. */
3842
3843         if (filter->tcp_flags) {
3844                 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3845                 return -EINVAL;
3846         }
3847
3848         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3849         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3850                 return -EINVAL;  /* filter index is in use. */
3851
3852         ftqf = 0;
3853         sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3854         sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3855
3856         ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3857                 IXGBE_FTQF_PROTOCOL_MASK);
3858         ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3859                 IXGBE_FTQF_PRIORITY_SHIFT);
3860         if (filter->src_ip_mask == 0) /* 0 means compare. */
3861                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3862         if (filter->dst_ip_mask == 0)
3863                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3864         if (filter->src_port_mask == 0)
3865                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3866         if (filter->dst_port_mask == 0)
3867                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3868         if (filter->protocol_mask == 0)
3869                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3870         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3871         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3872         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3873
3874         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3875         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3876         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3877         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3878
3879         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3880         l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3881         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3882         return 0;
3883 }
3884
3885 /*
3886  * remove a 5tuple filter
3887  *
3888  * @param
3889  * dev: Pointer to struct rte_eth_dev.
3890  * index: the index the filter allocates.
3891  *
3892  * @return
3893  *    - On success, zero.
3894  *    - On failure, a negative value.
3895  */
3896 static int
3897 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3898                         uint16_t index)
3899 {
3900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3901
3902         if (hw->mac.type != ixgbe_mac_82599EB)
3903                 return -ENOSYS;
3904
3905         if (index >= IXGBE_MAX_FTQF_FILTERS)
3906                 return -EINVAL;  /* filter index is out of range. */
3907
3908         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3909         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3910         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3911         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3912         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3913         return 0;
3914 }
3915
3916 /*
3917  * get a 5tuple filter
3918  *
3919  * @param
3920  * dev: Pointer to struct rte_eth_dev.
3921  * index: the index the filter allocates
3922  * filter: ponter to the filter that returns.
3923  * *rx_queue: pointer of the queue id the filter assigned to.
3924  *
3925  * @return
3926  *    - On success, zero.
3927  *    - On failure, a negative value.
3928  */
3929 static int
3930 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3931                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3932 {
3933         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3934         uint32_t sdpqf, ftqf, l34timir;
3935         uint8_t mask;
3936         enum ixgbe_5tuple_protocol proto;
3937
3938         if (hw->mac.type != ixgbe_mac_82599EB)
3939                 return -ENOSYS;
3940
3941         if (index >= IXGBE_MAX_FTQF_FILTERS)
3942                 return -EINVAL;  /* filter index is out of range. */
3943
3944         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3945         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3946                 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3947                 filter->protocol = revert_protocol_type(proto);
3948                 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3949                                         IXGBE_FTQF_PRIORITY_MASK;
3950                 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3951                                         IXGBE_FTQF_5TUPLE_MASK_MASK);
3952                 filter->src_ip_mask =
3953                         (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3954                 filter->dst_ip_mask =
3955                         (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3956                 filter->src_port_mask =
3957                         (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3958                 filter->dst_port_mask =
3959                         (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3960                 filter->protocol_mask =
3961                         (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3962
3963                 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3964                 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3965                                         IXGBE_SDPQF_DSTPORT_SHIFT;
3966                 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3967                 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3968                 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3969
3970                 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3971                 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3972                                         IXGBE_L34T_IMIR_QUEUE_SHIFT;
3973                 return 0;
3974         }
3975         return -ENOENT;
3976 }
3977
3978 static int
3979 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3980 {
3981         struct ixgbe_hw *hw;
3982         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3983
3984         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3985
3986         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3987                 return -EINVAL;
3988
3989         /* refuse mtu that requires the support of scattered packets when this
3990          * feature has not been enabled before. */
3991         if (!dev->data->scattered_rx &&
3992             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3993              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3994                 return -EINVAL;
3995
3996         /*
3997          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3998          * request of the version 2.0 of the mailbox API.
3999          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4000          * of the mailbox API.
4001          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4002          * prior to 3.11.33 which contains the following change:
4003          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4004          */
4005         ixgbevf_rlpml_set_vf(hw, max_frame);
4006
4007         /* update max frame size */
4008         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4009         return 0;
4010 }
4011
4012 #define MAC_TYPE_FILTER_SUP(type)    do {\
4013         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4014                 (type) != ixgbe_mac_X550)\
4015                 return -ENOTSUP;\
4016 } while (0)
4017
4018 static inline int
4019 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4020                         uint16_t ethertype)
4021 {
4022         int i;
4023
4024         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4025                 if (filter_info->ethertype_filters[i] == ethertype &&
4026                     (filter_info->ethertype_mask & (1 << i)))
4027                         return i;
4028         }
4029         return -1;
4030 }
4031
4032 static inline int
4033 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4034                         uint16_t ethertype)
4035 {
4036         int i;
4037
4038         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4039                 if (!(filter_info->ethertype_mask & (1 << i))) {
4040                         filter_info->ethertype_mask |= 1 << i;
4041                         filter_info->ethertype_filters[i] = ethertype;
4042                         return i;
4043                 }
4044         }
4045         return -1;
4046 }
4047
4048 static inline int
4049 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4050                         uint8_t idx)
4051 {
4052         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4053                 return -1;
4054         filter_info->ethertype_mask &= ~(1 << idx);
4055         filter_info->ethertype_filters[idx] = 0;
4056         return idx;
4057 }
4058
4059 static int
4060 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4061                         struct rte_eth_ethertype_filter *filter,
4062                         bool add)
4063 {
4064         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4065         struct ixgbe_filter_info *filter_info =
4066                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4067         uint32_t etqf = 0;
4068         uint32_t etqs = 0;
4069         int ret;
4070
4071         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4072                 return -EINVAL;
4073
4074         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4075                 filter->ether_type == ETHER_TYPE_IPv6) {
4076                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4077                         " ethertype filter.", filter->ether_type);
4078                 return -EINVAL;
4079         }
4080
4081         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4082                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4083                 return -EINVAL;
4084         }
4085         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4086                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4087                 return -EINVAL;
4088         }
4089
4090         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4091         if (ret >= 0 && add) {
4092                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4093                             filter->ether_type);
4094                 return -EEXIST;
4095         }
4096         if (ret < 0 && !add) {
4097                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4098                             filter->ether_type);
4099                 return -ENOENT;
4100         }
4101
4102         if (add) {
4103                 ret = ixgbe_ethertype_filter_insert(filter_info,
4104                         filter->ether_type);
4105                 if (ret < 0) {
4106                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4107                         return -ENOSYS;
4108                 }
4109                 etqf = IXGBE_ETQF_FILTER_EN;
4110                 etqf |= (uint32_t)filter->ether_type;
4111                 etqs |= (uint32_t)((filter->queue <<
4112                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4113                                     IXGBE_ETQS_RX_QUEUE);
4114                 etqs |= IXGBE_ETQS_QUEUE_EN;
4115         } else {
4116                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4117                 if (ret < 0)
4118                         return -ENOSYS;
4119         }
4120         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4121         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4122         IXGBE_WRITE_FLUSH(hw);
4123
4124         return 0;
4125 }
4126
4127 static int
4128 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4129                         struct rte_eth_ethertype_filter *filter)
4130 {
4131         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4132         struct ixgbe_filter_info *filter_info =
4133                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4134         uint32_t etqf, etqs;
4135         int ret;
4136
4137         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4138         if (ret < 0) {
4139                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4140                             filter->ether_type);
4141                 return -ENOENT;
4142         }
4143
4144         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4145         if (etqf & IXGBE_ETQF_FILTER_EN) {
4146                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4147                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4148                 filter->flags = 0;
4149                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4150                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4151                 return 0;
4152         }
4153         return -ENOENT;
4154 }
4155
4156 /*
4157  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4158  * @dev: pointer to rte_eth_dev structure
4159  * @filter_op:operation will be taken.
4160  * @arg: a pointer to specific structure corresponding to the filter_op
4161  */
4162 static int
4163 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4164                                 enum rte_filter_op filter_op,
4165                                 void *arg)
4166 {
4167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4168         int ret;
4169
4170         MAC_TYPE_FILTER_SUP(hw->mac.type);
4171
4172         if (filter_op == RTE_ETH_FILTER_NOP)
4173                 return 0;
4174
4175         if (arg == NULL) {
4176                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4177                             filter_op);
4178                 return -EINVAL;
4179         }
4180
4181         switch (filter_op) {
4182         case RTE_ETH_FILTER_ADD:
4183                 ret = ixgbe_add_del_ethertype_filter(dev,
4184                         (struct rte_eth_ethertype_filter *)arg,
4185                         TRUE);
4186                 break;
4187         case RTE_ETH_FILTER_DELETE:
4188                 ret = ixgbe_add_del_ethertype_filter(dev,
4189                         (struct rte_eth_ethertype_filter *)arg,
4190                         FALSE);
4191                 break;
4192         case RTE_ETH_FILTER_GET:
4193                 ret = ixgbe_get_ethertype_filter(dev,
4194                         (struct rte_eth_ethertype_filter *)arg);
4195                 break;
4196         default:
4197                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4198                 ret = -EINVAL;
4199                 break;
4200         }
4201         return ret;
4202 }
4203
4204 static int
4205 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4206                      enum rte_filter_type filter_type,
4207                      enum rte_filter_op filter_op,
4208                      void *arg)
4209 {
4210         int ret = -EINVAL;
4211
4212         switch (filter_type) {
4213         case RTE_ETH_FILTER_ETHERTYPE:
4214                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4215                 break;
4216         default:
4217                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4218                                                         filter_type);
4219                 break;
4220         }
4221
4222         return ret;
4223 }
4224
4225 static struct rte_driver rte_ixgbe_driver = {
4226         .type = PMD_PDEV,
4227         .init = rte_ixgbe_pmd_init,
4228 };
4229
4230 static struct rte_driver rte_ixgbevf_driver = {
4231         .type = PMD_PDEV,
4232         .init = rte_ixgbevf_pmd_init,
4233 };
4234
4235 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4236 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);