lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_tailq.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61
  62 #include "ixgbe_logs.h"
  63 #include "ixgbe/ixgbe_api.h"
  64 #include "ixgbe/ixgbe_vf.h"
  65 #include "ixgbe/ixgbe_common.h"
  66 #include "ixgbe_ethdev.h"
  67 #include "ixgbe_bypass.h"
  68
  69 /*
  70  * High threshold controlling when to start sending XOFF frames. Must be at
  71  * least 8 bytes less than receive packet buffer size. This value is in units
  72  * of 1024 bytes.
  73  */
  74 #define IXGBE_FC_HI    0x80
  75
  76 /*
  77  * Low threshold controlling when to start sending XON frames. This value is
  78  * in units of 1024 bytes.
  79  */
  80 #define IXGBE_FC_LO    0x40
  81
  82 /* Timer value included in XOFF frames. */
  83 #define IXGBE_FC_PAUSE 0x680
  84
  85 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  86 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  87 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  88
  89
  90 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  91
  92 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  93
  94 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
  95                 struct rte_eth_dev *eth_dev);
  96 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
  97 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
  98 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
  99 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 100 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 101 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 102 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 103 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 104 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 105                                 int wait_to_complete);
 106 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 107                                 struct rte_eth_stats *stats);
 108 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 109 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 110                                              uint16_t queue_id,
 111                                              uint8_t stat_idx,
 112                                              uint8_t is_rx);
 113 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 114                                 struct rte_eth_dev_info *dev_info);
 115 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 116                 uint16_t vlan_id, int on);
 117 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 118 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 119                 uint16_t queue, bool on);
 120 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 121                 int on);
 122 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 123 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 124 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 125 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 126 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 127
 128 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 129 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 130 static int  ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 131                 struct rte_eth_fc_conf *fc_conf);
 132 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 133                 struct rte_eth_pfc_conf *pfc_conf);
 134 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 135                 struct rte_eth_rss_reta *reta_conf);
 136 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 137                 struct rte_eth_rss_reta *reta_conf);
 138 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 139 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 140 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 141 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 143                 void *param);
 144 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 145 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 146                 uint32_t index, uint32_t pool);
 147 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 148 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 149
 150 /* For Virtual Function support */
 151 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 152                 struct rte_eth_dev *eth_dev);
 153 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 154 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 155 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 156 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 157 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 158 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 159                 struct rte_eth_stats *stats);
 160 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 161 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 162                 uint16_t vlan_id, int on);
 163 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 164                 uint16_t queue, int on);
 165 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 166 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 167
 168 /* For Eth VMDQ APIs support */
 169 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 170                 ether_addr* mac_addr,uint8_t on);
 171 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 172 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 173                 uint16_t rx_mask, uint8_t on);
 174 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 175 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 176 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 177                 uint64_t pool_mask,uint8_t vlan_on);
 178 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 179                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 180                 uint8_t rule_id, uint8_t on);
 181 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 182                 uint8_t rule_id);
 183
 184 /*
 185  * Define VF Stats MACRO for Non "cleared on read" register
 186  */
 187 #define UPDATE_VF_STAT(reg, last, cur)                          \
 188 {                                                               \
 189         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 190         cur += latest - last;                                   \
 191         last = latest;                                          \
 192 }
 193
 194 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 195 {                                                                \
 196         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 197         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 198         u64 latest = ((new_msb << 32) | new_lsb);                \
 199         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 200         last = latest;                                           \
 201 }
 202
 203 #define IXGBE_SET_HWSTRIP(h, q) do{\
 204                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 205                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 206                 (h)->bitmap[idx] |= 1 << bit;\
 207         }while(0)
 208
 209 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 210                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 211                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 212                 (h)->bitmap[idx] &= ~(1 << bit);\
 213         }while(0)
 214
 215 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 216                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 217                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 218                 (r) = (h)->bitmap[idx] >> bit & 1;\
 219         }while(0)
 220
 221 /*
 222  * The set of PCI devices this driver supports
 223  */
 224 static struct rte_pci_id pci_id_ixgbe_map[] = {
 225
 226 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 227 #include "rte_pci_dev_ids.h"
 228
 229 { .vendor_id = 0, /* sentinel */ },
 230 };
 231
 232
 233 /*
 234  * The set of PCI devices this driver supports (for 82599 VF)
 235  */
 236 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 237
 238 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 239 #include "rte_pci_dev_ids.h"
 240 { .vendor_id = 0, /* sentinel */ },
 241
 242 };
 243
 244 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 245         .dev_configure        = ixgbe_dev_configure,
 246         .dev_start            = ixgbe_dev_start,
 247         .dev_stop             = ixgbe_dev_stop,
 248         .dev_close            = ixgbe_dev_close,
 249         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 250         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 251         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 252         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 253         .link_update          = ixgbe_dev_link_update,
 254         .stats_get            = ixgbe_dev_stats_get,
 255         .stats_reset          = ixgbe_dev_stats_reset,
 256         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 257         .dev_infos_get        = ixgbe_dev_info_get,
 258         .vlan_filter_set      = ixgbe_vlan_filter_set,
 259         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 260         .vlan_offload_set     = ixgbe_vlan_offload_set,
 261         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 262         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 263         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 264         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 265         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 266         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 267         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 268         .dev_led_on           = ixgbe_dev_led_on,
 269         .dev_led_off          = ixgbe_dev_led_off,
 270         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 271         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 272         .mac_addr_add         = ixgbe_add_rar,
 273         .mac_addr_remove      = ixgbe_remove_rar,
 274         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 275         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 276         .mirror_rule_set        = ixgbe_mirror_rule_set,
 277         .mirror_rule_reset      = ixgbe_mirror_rule_reset,
 278         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 279         .set_vf_rx            = ixgbe_set_pool_rx,
 280         .set_vf_tx            = ixgbe_set_pool_tx,
 281         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 282         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 283         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 284         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 285         .fdir_infos_get               = ixgbe_fdir_info_get,
 286         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 287         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 288         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 289         .fdir_set_masks               = ixgbe_fdir_set_masks,
 290         .reta_update          = ixgbe_dev_rss_reta_update,
 291         .reta_query           = ixgbe_dev_rss_reta_query,
 292 #ifdef RTE_NIC_BYPASS
 293         .bypass_init          = ixgbe_bypass_init,
 294         .bypass_state_set     = ixgbe_bypass_state_store,
 295         .bypass_state_show    = ixgbe_bypass_state_show,
 296         .bypass_event_set     = ixgbe_bypass_event_store,
 297         .bypass_event_show    = ixgbe_bypass_event_show,
 298         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 299         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 300         .bypass_ver_show      = ixgbe_bypass_ver_show,
 301         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 302 #endif /* RTE_NIC_BYPASS */
 303 };
 304
 305 /*
 306  * dev_ops for virtual function, bare necessities for basic vf
 307  * operation have been implemented
 308  */
 309 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 310
 311         .dev_configure        = ixgbevf_dev_configure,
 312         .dev_start            = ixgbevf_dev_start,
 313         .dev_stop             = ixgbevf_dev_stop,
 314         .link_update          = ixgbe_dev_link_update,
 315         .stats_get            = ixgbevf_dev_stats_get,
 316         .stats_reset          = ixgbevf_dev_stats_reset,
 317         .dev_close            = ixgbevf_dev_close,
 318         .dev_infos_get        = ixgbe_dev_info_get,
 319         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 320         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 321         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 322         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 323         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 324         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 325         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 326 };
 327
 328 /**
 329  * Atomically reads the link status information from global
 330  * structure rte_eth_dev.
 331  *
 332  * @param dev
 333  *   - Pointer to the structure rte_eth_dev to read from.
 334  *   - Pointer to the buffer to be saved with the link status.
 335  *
 336  * @return
 337  *   - On success, zero.
 338  *   - On failure, negative value.
 339  */
 340 static inline int
 341 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 342                                 struct rte_eth_link *link)
 343 {
 344         struct rte_eth_link *dst = link;
 345         struct rte_eth_link *src = &(dev->data->dev_link);
 346
 347         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 348                                         *(uint64_t *)src) == 0)
 349                 return -1;
 350
 351         return 0;
 352 }
 353
 354 /**
 355  * Atomically writes the link status information into global
 356  * structure rte_eth_dev.
 357  *
 358  * @param dev
 359  *   - Pointer to the structure rte_eth_dev to read from.
 360  *   - Pointer to the buffer to be saved with the link status.
 361  *
 362  * @return
 363  *   - On success, zero.
 364  *   - On failure, negative value.
 365  */
 366 static inline int
 367 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 368                                 struct rte_eth_link *link)
 369 {
 370         struct rte_eth_link *dst = &(dev->data->dev_link);
 371         struct rte_eth_link *src = link;
 372
 373         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 374                                         *(uint64_t *)src) == 0)
 375                 return -1;
 376
 377         return 0;
 378 }
 379
 380 /*
 381  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 382  */
 383 static inline int
 384 ixgbe_is_sfp(struct ixgbe_hw *hw)
 385 {
 386         switch (hw->phy.type) {
 387         case ixgbe_phy_sfp_avago:
 388         case ixgbe_phy_sfp_ftl:
 389         case ixgbe_phy_sfp_intel:
 390         case ixgbe_phy_sfp_unknown:
 391         case ixgbe_phy_sfp_passive_tyco:
 392         case ixgbe_phy_sfp_passive_unknown:
 393                 return 1;
 394         default:
 395                 return 0;
 396         }
 397 }
 398
 399 static inline int32_t
 400 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 401 {
 402         uint32_t ctrl_ext;
 403         int32_t status;
 404
 405         status = ixgbe_reset_hw(hw);
 406
 407         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 408         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 409         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 410         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 411         IXGBE_WRITE_FLUSH(hw);
 412
 413         return status;
 414 }
 415
 416 static inline void
 417 ixgbe_enable_intr(struct rte_eth_dev *dev)
 418 {
 419         struct ixgbe_interrupt *intr =
 420                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 421         struct ixgbe_hw *hw =
 422                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 423
 424         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 425         IXGBE_WRITE_FLUSH(hw);
 426 }
 427
 428 /*
 429  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 430  */
 431 static void
 432 ixgbe_disable_intr(struct ixgbe_hw *hw)
 433 {
 434         PMD_INIT_FUNC_TRACE();
 435
 436         if (hw->mac.type == ixgbe_mac_82598EB) {
 437                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 438         } else {
 439                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 440                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 441                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 442         }
 443         IXGBE_WRITE_FLUSH(hw);
 444 }
 445
 446 /*
 447  * This function resets queue statistics mapping registers.
 448  * From Niantic datasheet, Initialization of Statistics section:
 449  * "...if software requires the queue counters, the RQSMR and TQSM registers
 450  * must be re-programmed following a device reset.
 451  */
 452 static void
 453 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 454 {
 455         uint32_t i;
 456
 457         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 458                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 459                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 460         }
 461 }
 462
 463
 464 static int
 465 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 466                                   uint16_t queue_id,
 467                                   uint8_t stat_idx,
 468                                   uint8_t is_rx)
 469 {
 470 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 471 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 472 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 473
 474         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 475         struct ixgbe_stat_mapping_registers *stat_mappings =
 476                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 477         uint32_t qsmr_mask = 0;
 478         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 479         uint32_t q_map;
 480         uint8_t n, offset;
 481
 482         if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
 483                 return -ENOSYS;
 484
 485         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
 486                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
 487
 488         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 489         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 490                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
 491                 return -EIO;
 492         }
 493         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 494
 495         /* Now clear any previous stat_idx set */
 496         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 497         if (!is_rx)
 498                 stat_mappings->tqsm[n] &= ~clearing_mask;
 499         else
 500                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 501
 502         q_map = (uint32_t)stat_idx;
 503         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 504         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 505         if (!is_rx)
 506                 stat_mappings->tqsm[n] |= qsmr_mask;
 507         else
 508                 stat_mappings->rqsmr[n] |= qsmr_mask;
 509
 510         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
 511                      "%s[%d] = 0x%08x\n",
 512                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
 513                      is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 514
 515         /* Now write the mapping in the appropriate register */
 516         if (is_rx) {
 517                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
 518                              stat_mappings->rqsmr[n], n);
 519                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 520         }
 521         else {
 522                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
 523                              stat_mappings->tqsm[n], n);
 524                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 525         }
 526         return 0;
 527 }
 528
 529 static void
 530 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 531 {
 532         struct ixgbe_stat_mapping_registers *stat_mappings =
 533                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 534         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 535         int i;
 536
 537         /* write whatever was in stat mapping table to the NIC */
 538         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 539                 /* rx */
 540                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 541
 542                 /* tx */
 543                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 544         }
 545 }
 546
 547 static void
 548 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 549 {
 550         uint8_t i;
 551         struct ixgbe_dcb_tc_config *tc;
 552         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 553
 554         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 555         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 556         for (i = 0; i < dcb_max_tc; i++) {
 557                 tc = &dcb_config->tc_config[i];
 558                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 559                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 560                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 561                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 562                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 563                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 564                 tc->pfc = ixgbe_dcb_pfc_disabled;
 565         }
 566
 567         /* Initialize default user to priority mapping, UPx->TC0 */
 568         tc = &dcb_config->tc_config[0];
 569         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 570         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 571         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 572                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 573                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 574         }
 575         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 576         dcb_config->pfc_mode_enable = false;
 577         dcb_config->vt_mode = true;
 578         dcb_config->round_robin_enable = false;
 579         /* support all DCB capabilities in 82599 */
 580         dcb_config->support.capabilities = 0xFF;
 581
 582         /*we only support 4 Tcs for X540*/
 583         if (hw->mac.type == ixgbe_mac_X540) {
 584                 dcb_config->num_tcs.pg_tcs = 4;
 585                 dcb_config->num_tcs.pfc_tcs = 4;
 586         }
 587 }
 588
 589 /*
 590  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 591  * It returns 0 on success.
 592  */
 593 static int
 594 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 595                      struct rte_eth_dev *eth_dev)
 596 {
 597         struct rte_pci_device *pci_dev;
 598         struct ixgbe_hw *hw =
 599                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 600         struct ixgbe_vfta * shadow_vfta =
 601                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 602         struct ixgbe_hwstrip *hwstrip =
 603                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 604         struct ixgbe_dcb_config *dcb_config =
 605                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 606         uint32_t ctrl_ext;
 607         uint16_t csum;
 608         int diag, i;
 609
 610         PMD_INIT_FUNC_TRACE();
 611
 612         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 613         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 614         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 615
 616         /* for secondary processes, we don't initialise any further as primary
 617          * has already done this work. Only check we don't need a different
 618          * RX function */
 619         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 620                 if (eth_dev->data->scattered_rx)
 621                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 622                 return 0;
 623         }
 624         pci_dev = eth_dev->pci_dev;
 625
 626         /* Vendor and Device ID need to be set before init of shared code */
 627         hw->device_id = pci_dev->id.device_id;
 628         hw->vendor_id = pci_dev->id.vendor_id;
 629         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 630 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
 631         hw->allow_unsupported_sfp = 1;
 632 #endif
 633
 634         /* Initialize the shared code */
 635 #ifdef RTE_NIC_BYPASS
 636         diag = ixgbe_bypass_init_shared_code(hw);
 637 #else
 638         diag = ixgbe_init_shared_code(hw);
 639 #endif /* RTE_NIC_BYPASS */
 640
 641         if (diag != IXGBE_SUCCESS) {
 642                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 643                 return -EIO;
 644         }
 645
 646         /* Initialize DCB configuration*/
 647         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 648         ixgbe_dcb_init(hw,dcb_config);
 649         /* Get Hardware Flow Control setting */
 650         hw->fc.requested_mode = ixgbe_fc_full;
 651         hw->fc.current_mode = ixgbe_fc_full;
 652         hw->fc.pause_time = IXGBE_FC_PAUSE;
 653         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 654                 hw->fc.low_water[i] = IXGBE_FC_LO;
 655                 hw->fc.high_water[i] = IXGBE_FC_HI;
 656         }
 657         hw->fc.send_xon = 1;
 658
 659         /* Make sure we have a good EEPROM before we read from it */
 660         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 661         if (diag != IXGBE_SUCCESS) {
 662                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 663                 return -EIO;
 664         }
 665
 666 #ifdef RTE_NIC_BYPASS
 667         diag = ixgbe_bypass_init_hw(hw);
 668 #else
 669         diag = ixgbe_init_hw(hw);
 670 #endif /* RTE_NIC_BYPASS */
 671
 672         /*
 673          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 674          * is called too soon after the kernel driver unbinding/binding occurs.
 675          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 676          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 677          * also called. See ixgbe_identify_phy_82599(). The reason for the
 678          * failure is not known, and only occuts when virtualisation features
 679          * are disabled in the bios. A delay of 100ms  was found to be enough by
 680          * trial-and-error, and is doubled to be safe.
 681          */
 682         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 683                 rte_delay_ms(200);
 684                 diag = ixgbe_init_hw(hw);
 685         }
 686
 687         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 688                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 689                     "LOM.  Please be aware there may be issues associated "
 690                     "with your hardware.\n If you are experiencing problems "
 691                     "please contact your Intel or hardware representative "
 692                     "who provided you with this hardware.\n");
 693         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 694                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
 695         if (diag) {
 696                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 697                 return -EIO;
 698         }
 699
 700         /* disable interrupt */
 701         ixgbe_disable_intr(hw);
 702
 703         /* pick up the PCI bus settings for reporting later */
 704         ixgbe_get_bus_info(hw);
 705
 706         /* reset mappings for queue statistics hw counters*/
 707         ixgbe_reset_qstat_mappings(hw);
 708
 709         /* Allocate memory for storing MAC addresses */
 710         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 711                         hw->mac.num_rar_entries, 0);
 712         if (eth_dev->data->mac_addrs == NULL) {
 713                 PMD_INIT_LOG(ERR,
 714                         "Failed to allocate %u bytes needed to store "
 715                         "MAC addresses",
 716                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 717                 return -ENOMEM;
 718         }
 719         /* Copy the permanent MAC address */
 720         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 721                         &eth_dev->data->mac_addrs[0]);
 722
 723         /* Allocate memory for storing hash filter MAC addresses */
 724         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 725                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 726         if (eth_dev->data->hash_mac_addrs == NULL) {
 727                 PMD_INIT_LOG(ERR,
 728                         "Failed to allocate %d bytes needed to store MAC addresses",
 729                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 730                 return -ENOMEM;
 731         }
 732
 733         /* initialize the vfta */
 734         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 735
 736         /* initialize the hw strip bitmap*/
 737         memset(hwstrip, 0, sizeof(*hwstrip));
 738
 739         /* initialize PF if max_vfs not zero */
 740         ixgbe_pf_host_init(eth_dev);
 741
 742         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 743         /* let hardware know driver is loaded */
 744         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 745         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 746         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 747         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 748         IXGBE_WRITE_FLUSH(hw);
 749
 750         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 751                 PMD_INIT_LOG(DEBUG,
 752                              "MAC: %d, PHY: %d, SFP+: %d<n",
 753                              (int) hw->mac.type, (int) hw->phy.type,
 754                              (int) hw->phy.sfp_type);
 755         else
 756                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
 757                              (int) hw->mac.type, (int) hw->phy.type);
 758
 759         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 760                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 761                         pci_dev->id.device_id);
 762
 763         rte_intr_callback_register(&(pci_dev->intr_handle),
 764                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 765
 766         /* enable uio intr after callback register */
 767         rte_intr_enable(&(pci_dev->intr_handle));
 768
 769         /* enable support intr */
 770         ixgbe_enable_intr(eth_dev);
 771
 772         return 0;
 773 }
 774
 775 /*
 776  * Virtual Function device init
 777  */
 778 static int
 779 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 780                      struct rte_eth_dev *eth_dev)
 781 {
 782         struct rte_pci_device *pci_dev;
 783         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 784         int diag;
 785         struct ixgbe_vfta * shadow_vfta =
 786                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 787         struct ixgbe_hwstrip *hwstrip =
 788                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 789
 790         PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
 791
 792         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 793         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 794         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 795
 796         /* for secondary processes, we don't initialise any further as primary
 797          * has already done this work. Only check we don't need a different
 798          * RX function */
 799         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 800                 if (eth_dev->data->scattered_rx)
 801                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 802                 return 0;
 803         }
 804
 805         pci_dev = eth_dev->pci_dev;
 806
 807         hw->device_id = pci_dev->id.device_id;
 808         hw->vendor_id = pci_dev->id.vendor_id;
 809         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 810
 811         /* initialize the vfta */
 812         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 813
 814         /* initialize the hw strip bitmap*/
 815         memset(hwstrip, 0, sizeof(*hwstrip));
 816
 817         /* Initialize the shared code */
 818         diag = ixgbe_init_shared_code(hw);
 819         if (diag != IXGBE_SUCCESS) {
 820                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 821                 return -EIO;
 822         }
 823
 824         /* init_mailbox_params */
 825         hw->mbx.ops.init_params(hw);
 826
 827         /* Disable the interrupts for VF */
 828         ixgbevf_intr_disable(hw);
 829
 830         hw->mac.num_rar_entries = hw->mac.max_rx_queues;
 831         diag = hw->mac.ops.reset_hw(hw);
 832
 833         if (diag != IXGBE_SUCCESS) {
 834                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 835                         RTE_LOG(ERR, PMD, "\tThe MAC address is not valid.\n"
 836                                         "\tThe most likely cause of this error is that the VM host\n"
 837                                         "\thas not assigned a valid MAC address to this VF device.\n"
 838                                         "\tPlease consult the DPDK Release Notes (FAQ section) for\n"
 839                                         "\ta possible solution to this problem.\n");
 840                 return (diag);
 841         }
 842
 843         /* Allocate memory for storing MAC addresses */
 844         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
 845                         hw->mac.num_rar_entries, 0);
 846         if (eth_dev->data->mac_addrs == NULL) {
 847                 PMD_INIT_LOG(ERR,
 848                         "Failed to allocate %u bytes needed to store "
 849                         "MAC addresses",
 850                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 851                 return -ENOMEM;
 852         }
 853
 854         /* Copy the permanent MAC address */
 855         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 856                         &eth_dev->data->mac_addrs[0]);
 857
 858         /* reset the hardware with the new settings */
 859         diag = hw->mac.ops.start_hw(hw);
 860         switch (diag) {
 861                 case  0:
 862                         break;
 863
 864                 default:
 865                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 866                         return (-EIO);
 867         }
 868
 869         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
 870                          eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
 871                          "ixgbe_mac_82599_vf");
 872
 873         return 0;
 874 }
 875
 876 static struct eth_driver rte_ixgbe_pmd = {
 877         {
 878                 .name = "rte_ixgbe_pmd",
 879                 .id_table = pci_id_ixgbe_map,
 880 #ifdef RTE_EAL_UNBIND_PORTS
 881                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 882 #endif
 883         },
 884         .eth_dev_init = eth_ixgbe_dev_init,
 885         .dev_private_size = sizeof(struct ixgbe_adapter),
 886 };
 887
 888 /*
 889  * virtual function driver struct
 890  */
 891 static struct eth_driver rte_ixgbevf_pmd = {
 892         {
 893                 .name = "rte_ixgbevf_pmd",
 894                 .id_table = pci_id_ixgbevf_map,
 895 #ifdef RTE_EAL_UNBIND_PORTS
 896                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 897 #endif
 898         },
 899         .eth_dev_init = eth_ixgbevf_dev_init,
 900         .dev_private_size = sizeof(struct ixgbe_adapter),
 901 };
 902
 903 /*
 904  * Driver initialization routine.
 905  * Invoked once at EAL init time.
 906  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 907  */
 908 int
 909 rte_ixgbe_pmd_init(void)
 910 {
 911         PMD_INIT_FUNC_TRACE();
 912
 913         rte_eth_driver_register(&rte_ixgbe_pmd);
 914         return 0;
 915 }
 916
 917 /*
 918  * VF Driver initialization routine.
 919  * Invoked one at EAL init time.
 920  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
 921  */
 922 int
 923 rte_ixgbevf_pmd_init(void)
 924 {
 925         DEBUGFUNC("rte_ixgbevf_pmd_init");
 926
 927         rte_eth_driver_register(&rte_ixgbevf_pmd);
 928         return (0);
 929 }
 930
 931 static int
 932 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 933 {
 934         struct ixgbe_hw *hw =
 935                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 936         struct ixgbe_vfta * shadow_vfta =
 937                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
 938         uint32_t vfta;
 939         uint32_t vid_idx;
 940         uint32_t vid_bit;
 941
 942         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
 943         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
 944         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
 945         if (on)
 946                 vfta |= vid_bit;
 947         else
 948                 vfta &= ~vid_bit;
 949         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
 950
 951         /* update local VFTA copy */
 952         shadow_vfta->vfta[vid_idx] = vfta;
 953
 954         return 0;
 955 }
 956
 957 static void
 958 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 959 {
 960         if (on)
 961                 ixgbe_vlan_hw_strip_enable(dev, queue);
 962         else
 963                 ixgbe_vlan_hw_strip_disable(dev, queue);
 964 }
 965
 966 static void
 967 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
 968 {
 969         struct ixgbe_hw *hw =
 970                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 971
 972         /* Only the high 16-bits is valid */
 973         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
 974 }
 975
 976 void
 977 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
 978 {
 979         struct ixgbe_hw *hw =
 980                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 981         uint32_t vlnctrl;
 982
 983         PMD_INIT_FUNC_TRACE();
 984
 985         /* Filter Table Disable */
 986         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 987         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
 988
 989         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
 990 }
 991
 992 void
 993 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 994 {
 995         struct ixgbe_hw *hw =
 996                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 997         struct ixgbe_vfta * shadow_vfta =
 998                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
 999         uint32_t vlnctrl;
1000         uint16_t i;
1001
1002         PMD_INIT_FUNC_TRACE();
1003
1004         /* Filter Table Enable */
1005         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1006         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1007         vlnctrl |= IXGBE_VLNCTRL_VFE;
1008
1009         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1010
1011         /* write whatever is in local vfta copy */
1012         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1013                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1014 }
1015
1016 static void
1017 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1018 {
1019         struct ixgbe_hwstrip *hwstrip =
1020                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1021
1022         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1023                 return;
1024
1025         if (on)
1026                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1027         else
1028                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1029 }
1030
1031 static void
1032 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1033 {
1034         struct ixgbe_hw *hw =
1035                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036         uint32_t ctrl;
1037
1038         PMD_INIT_FUNC_TRACE();
1039
1040         if (hw->mac.type == ixgbe_mac_82598EB) {
1041                 /* No queue level support */
1042                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1043                 return;
1044         }
1045         else {
1046                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1047                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1048                 ctrl &= ~IXGBE_RXDCTL_VME;
1049                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1050         }
1051         /* record those setting for HW strip per queue */
1052         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1053 }
1054
1055 static void
1056 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1057 {
1058         struct ixgbe_hw *hw =
1059                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1060         uint32_t ctrl;
1061
1062         PMD_INIT_FUNC_TRACE();
1063
1064         if (hw->mac.type == ixgbe_mac_82598EB) {
1065                 /* No queue level supported */
1066                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1067                 return;
1068         }
1069         else {
1070                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1071                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1072                 ctrl |= IXGBE_RXDCTL_VME;
1073                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1074         }
1075         /* record those setting for HW strip per queue */
1076         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1077 }
1078
1079 void
1080 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1081 {
1082         struct ixgbe_hw *hw =
1083                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1084         uint32_t ctrl;
1085         uint16_t i;
1086
1087         PMD_INIT_FUNC_TRACE();
1088
1089         if (hw->mac.type == ixgbe_mac_82598EB) {
1090                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1091                 ctrl &= ~IXGBE_VLNCTRL_VME;
1092                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1093         }
1094         else {
1095                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1096                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1097                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1098                         ctrl &= ~IXGBE_RXDCTL_VME;
1099                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1100
1101                         /* record those setting for HW strip per queue */
1102                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1103                 }
1104         }
1105 }
1106
1107 void
1108 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1109 {
1110         struct ixgbe_hw *hw =
1111                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1112         uint32_t ctrl;
1113         uint16_t i;
1114
1115         PMD_INIT_FUNC_TRACE();
1116
1117         if (hw->mac.type == ixgbe_mac_82598EB) {
1118                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1119                 ctrl |= IXGBE_VLNCTRL_VME;
1120                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1121         }
1122         else {
1123                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1124                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1125                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1126                         ctrl |= IXGBE_RXDCTL_VME;
1127                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1128
1129                         /* record those setting for HW strip per queue */
1130                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1131                 }
1132         }
1133 }
1134
1135 static void
1136 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1137 {
1138         struct ixgbe_hw *hw =
1139                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1140         uint32_t ctrl;
1141
1142         PMD_INIT_FUNC_TRACE();
1143
1144         /* DMATXCTRL: Geric Double VLAN Disable */
1145         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1146         ctrl &= ~IXGBE_DMATXCTL_GDV;
1147         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1148
1149         /* CTRL_EXT: Global Double VLAN Disable */
1150         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1151         ctrl &= ~IXGBE_EXTENDED_VLAN;
1152         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1153
1154 }
1155
1156 static void
1157 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1158 {
1159         struct ixgbe_hw *hw =
1160                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1161         uint32_t ctrl;
1162
1163         PMD_INIT_FUNC_TRACE();
1164
1165         /* DMATXCTRL: Geric Double VLAN Enable */
1166         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1167         ctrl |= IXGBE_DMATXCTL_GDV;
1168         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1169
1170         /* CTRL_EXT: Global Double VLAN Enable */
1171         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1172         ctrl |= IXGBE_EXTENDED_VLAN;
1173         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1174
1175         /*
1176          * VET EXT field in the EXVET register = 0x8100 by default
1177          * So no need to change. Same to VT field of DMATXCTL register
1178          */
1179 }
1180
1181 static void
1182 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1183 {
1184         if(mask & ETH_VLAN_STRIP_MASK){
1185                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1186                         ixgbe_vlan_hw_strip_enable_all(dev);
1187                 else
1188                         ixgbe_vlan_hw_strip_disable_all(dev);
1189         }
1190
1191         if(mask & ETH_VLAN_FILTER_MASK){
1192                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1193                         ixgbe_vlan_hw_filter_enable(dev);
1194                 else
1195                         ixgbe_vlan_hw_filter_disable(dev);
1196         }
1197
1198         if(mask & ETH_VLAN_EXTEND_MASK){
1199                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1200                         ixgbe_vlan_hw_extend_enable(dev);
1201                 else
1202                         ixgbe_vlan_hw_extend_disable(dev);
1203         }
1204 }
1205
1206 static void
1207 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1208 {
1209         struct ixgbe_hw *hw =
1210                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1211         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1212         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1213         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1214         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1215 }
1216
1217 static int
1218 ixgbe_dev_configure(struct rte_eth_dev *dev)
1219 {
1220         struct ixgbe_interrupt *intr =
1221                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1222
1223         PMD_INIT_FUNC_TRACE();
1224
1225         /* set flag to update link status after init */
1226         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1227
1228         return 0;
1229 }
1230
1231 /*
1232  * Configure device link speed and setup link.
1233  * It returns 0 on success.
1234  */
1235 static int
1236 ixgbe_dev_start(struct rte_eth_dev *dev)
1237 {
1238         struct ixgbe_hw *hw =
1239                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1240         int err, link_up = 0, negotiate = 0;
1241         uint32_t speed = 0;
1242         int mask = 0;
1243         int status;
1244
1245         PMD_INIT_FUNC_TRACE();
1246
1247         /* IXGBE devices don't support half duplex */
1248         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1249                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1250                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1251                                 dev->data->dev_conf.link_duplex,
1252                                 dev->data->port_id);
1253                 return -EINVAL;
1254         }
1255
1256         /* stop adapter */
1257         hw->adapter_stopped = FALSE;
1258         ixgbe_stop_adapter(hw);
1259
1260         /* reinitialize adapter
1261          * this calls reset and start */
1262         status = ixgbe_pf_reset_hw(hw);
1263         if (status != 0)
1264                 return -1;
1265         hw->mac.ops.start_hw(hw);
1266
1267         /* configure PF module if SRIOV enabled */
1268         ixgbe_pf_host_configure(dev);
1269
1270         /* initialize transmission unit */
1271         ixgbe_dev_tx_init(dev);
1272
1273         /* This can fail when allocating mbufs for descriptor rings */
1274         err = ixgbe_dev_rx_init(dev);
1275         if (err) {
1276                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1277                 goto error;
1278         }
1279
1280         ixgbe_dev_rxtx_start(dev);
1281
1282         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1283                 err = hw->mac.ops.setup_sfp(hw);
1284                 if (err)
1285                         goto error;
1286         }
1287
1288         /* Turn on the laser */
1289         ixgbe_enable_tx_laser(hw);
1290
1291         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1292         if (err)
1293                 goto error;
1294         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1295         if (err)
1296                 goto error;
1297
1298         switch(dev->data->dev_conf.link_speed) {
1299         case ETH_LINK_SPEED_AUTONEG:
1300                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1301                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1302                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1303                 break;
1304         case ETH_LINK_SPEED_100:
1305                 /*
1306                  * Invalid for 82598 but error will be detected by
1307                  * ixgbe_setup_link()
1308                  */
1309                 speed = IXGBE_LINK_SPEED_100_FULL;
1310                 break;
1311         case ETH_LINK_SPEED_1000:
1312                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1313                 break;
1314         case ETH_LINK_SPEED_10000:
1315                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1316                 break;
1317         default:
1318                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1319                                 dev->data->dev_conf.link_speed,
1320                                 dev->data->port_id);
1321                 goto error;
1322         }
1323
1324         err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1325         if (err)
1326                 goto error;
1327
1328         /* check if lsc interrupt is enabled */
1329         if (dev->data->dev_conf.intr_conf.lsc != 0)
1330                 ixgbe_dev_lsc_interrupt_setup(dev);
1331
1332         /* resume enabled intr since hw reset */
1333         ixgbe_enable_intr(dev);
1334
1335         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1336                 ETH_VLAN_EXTEND_MASK;
1337         ixgbe_vlan_offload_set(dev, mask);
1338
1339         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1340                 /* Enable vlan filtering for VMDq */
1341                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1342         }
1343
1344         /* Configure DCB hw */
1345         ixgbe_configure_dcb(dev);
1346
1347         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1348                 err = ixgbe_fdir_configure(dev);
1349                 if (err)
1350                         goto error;
1351         }
1352
1353         ixgbe_restore_statistics_mapping(dev);
1354
1355         return (0);
1356
1357 error:
1358         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1359         ixgbe_dev_clear_queues(dev);
1360         return -EIO;
1361 }
1362
1363 /*
1364  * Stop device: disable rx and tx functions to allow for reconfiguring.
1365  */
1366 static void
1367 ixgbe_dev_stop(struct rte_eth_dev *dev)
1368 {
1369         struct rte_eth_link link;
1370         struct ixgbe_hw *hw =
1371                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1372
1373         PMD_INIT_FUNC_TRACE();
1374
1375         /* disable interrupts */
1376         ixgbe_disable_intr(hw);
1377
1378         /* reset the NIC */
1379         ixgbe_pf_reset_hw(hw);
1380         hw->adapter_stopped = FALSE;
1381
1382         /* stop adapter */
1383         ixgbe_stop_adapter(hw);
1384
1385         /* Turn off the laser */
1386         ixgbe_disable_tx_laser(hw);
1387
1388         ixgbe_dev_clear_queues(dev);
1389
1390         /* Clear recorded link status */
1391         memset(&link, 0, sizeof(link));
1392         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1393 }
1394
1395 /*
1396  * Reest and stop device.
1397  */
1398 static void
1399 ixgbe_dev_close(struct rte_eth_dev *dev)
1400 {
1401         struct ixgbe_hw *hw =
1402                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1403
1404         PMD_INIT_FUNC_TRACE();
1405
1406         ixgbe_pf_reset_hw(hw);
1407
1408         ixgbe_dev_stop(dev);
1409         hw->adapter_stopped = 1;
1410
1411         ixgbe_disable_pcie_master(hw);
1412
1413         /* reprogram the RAR[0] in case user changed it. */
1414         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1415 }
1416
1417 /*
1418  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1419  */
1420 static void
1421 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1422 {
1423         struct ixgbe_hw *hw =
1424                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1425         struct ixgbe_hw_stats *hw_stats =
1426                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1427         uint32_t bprc, lxon, lxoff, total;
1428         uint64_t total_missed_rx, total_qbrc, total_qprc;
1429         unsigned i;
1430
1431         total_missed_rx = 0;
1432         total_qbrc = 0;
1433         total_qprc = 0;
1434
1435         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1436         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1437         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1438         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1439
1440         for (i = 0; i < 8; i++) {
1441                 uint32_t mp;
1442                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1443                 /* global total per queue */
1444                 hw_stats->mpc[i] += mp;
1445                 /* Running comprehensive total for stats display */
1446                 total_missed_rx += hw_stats->mpc[i];
1447                 if (hw->mac.type == ixgbe_mac_82598EB)
1448                         hw_stats->rnbc[i] +=
1449                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1450                 hw_stats->pxontxc[i] +=
1451                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1452                 hw_stats->pxonrxc[i] +=
1453                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1454                 hw_stats->pxofftxc[i] +=
1455                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1456                 hw_stats->pxoffrxc[i] +=
1457                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1458                 hw_stats->pxon2offc[i] +=
1459                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1460         }
1461         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1462                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1463                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1464                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1465                 hw_stats->qbrc[i] +=
1466                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1467                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1468                 hw_stats->qbtc[i] +=
1469                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1470                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1471
1472                 total_qprc += hw_stats->qprc[i];
1473                 total_qbrc += hw_stats->qbrc[i];
1474         }
1475         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1476         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1477         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1478
1479         /* Note that gprc counts missed packets */
1480         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1481
1482         if (hw->mac.type != ixgbe_mac_82598EB) {
1483                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1484                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1485                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1486                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1487                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1488                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1489                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1490                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1491         } else {
1492                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1493                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1494                 /* 82598 only has a counter in the high register */
1495                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1496                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1497                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1498         }
1499
1500         /*
1501          * Workaround: mprc hardware is incorrectly counting
1502          * broadcasts, so for now we subtract those.
1503          */
1504         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1505         hw_stats->bprc += bprc;
1506         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1507         if (hw->mac.type == ixgbe_mac_82598EB)
1508                 hw_stats->mprc -= bprc;
1509
1510         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1511         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1512         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1513         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1514         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1515         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1516
1517         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1518         hw_stats->lxontxc += lxon;
1519         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1520         hw_stats->lxofftxc += lxoff;
1521         total = lxon + lxoff;
1522
1523         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1524         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1525         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1526         hw_stats->gptc -= total;
1527         hw_stats->mptc -= total;
1528         hw_stats->ptc64 -= total;
1529         hw_stats->gotc -= total * ETHER_MIN_LEN;
1530
1531         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1532         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1533         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1534         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1535         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1536         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1537         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1538         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1539         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1540         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1541         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1542         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1543         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1544         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1545         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1546         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1547         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1548         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1549         /* Only read FCOE on 82599 */
1550         if (hw->mac.type != ixgbe_mac_82598EB) {
1551                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1552                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1553                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1554                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1555                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1556         }
1557
1558         if (stats == NULL)
1559                 return;
1560
1561         /* Fill out the rte_eth_stats statistics structure */
1562         stats->ipackets = total_qprc;
1563         stats->ibytes = total_qbrc;
1564         stats->opackets = hw_stats->gptc;
1565         stats->obytes = hw_stats->gotc;
1566         stats->imcasts = hw_stats->mprc;
1567
1568         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1569                 stats->q_ipackets[i] = hw_stats->qprc[i];
1570                 stats->q_opackets[i] = hw_stats->qptc[i];
1571                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1572                 stats->q_obytes[i] = hw_stats->qbtc[i];
1573                 stats->q_errors[i] = hw_stats->qprdc[i];
1574         }
1575
1576         /* Rx Errors */
1577         stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1578                 hw_stats->rlec;
1579
1580         stats->oerrors  = 0;
1581
1582         /* Flow Director Stats registers */
1583         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1584         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1585         stats->fdirmatch = hw_stats->fdirmatch;
1586         stats->fdirmiss = hw_stats->fdirmiss;
1587 }
1588
1589 static void
1590 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1591 {
1592         struct ixgbe_hw_stats *stats =
1593                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1594
1595         /* HW registers are cleared on read */
1596         ixgbe_dev_stats_get(dev, NULL);
1597
1598         /* Reset software totals */
1599         memset(stats, 0, sizeof(*stats));
1600 }
1601
1602 static void
1603 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1604 {
1605         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1607                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1608
1609         /* Good Rx packet, include VF loopback */
1610         UPDATE_VF_STAT(IXGBE_VFGPRC,
1611             hw_stats->last_vfgprc, hw_stats->vfgprc);
1612
1613         /* Good Rx octets, include VF loopback */
1614         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1615             hw_stats->last_vfgorc, hw_stats->vfgorc);
1616
1617         /* Good Tx packet, include VF loopback */
1618         UPDATE_VF_STAT(IXGBE_VFGPTC,
1619             hw_stats->last_vfgptc, hw_stats->vfgptc);
1620
1621         /* Good Tx octets, include VF loopback */
1622         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1623             hw_stats->last_vfgotc, hw_stats->vfgotc);
1624
1625         /* Rx Multicst Packet */
1626         UPDATE_VF_STAT(IXGBE_VFMPRC,
1627             hw_stats->last_vfmprc, hw_stats->vfmprc);
1628
1629         if (stats == NULL)
1630                 return;
1631
1632         memset(stats, 0, sizeof(*stats));
1633         stats->ipackets = hw_stats->vfgprc;
1634         stats->ibytes = hw_stats->vfgorc;
1635         stats->opackets = hw_stats->vfgptc;
1636         stats->obytes = hw_stats->vfgotc;
1637         stats->imcasts = hw_stats->vfmprc;
1638 }
1639
1640 static void
1641 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1642 {
1643         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1644                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1645
1646         /* Sync HW register to the last stats */
1647         ixgbevf_dev_stats_get(dev, NULL);
1648
1649         /* reset HW current stats*/
1650         hw_stats->vfgprc = 0;
1651         hw_stats->vfgorc = 0;
1652         hw_stats->vfgptc = 0;
1653         hw_stats->vfgotc = 0;
1654         hw_stats->vfmprc = 0;
1655
1656 }
1657
1658 static void
1659 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1660 {
1661         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1662
1663         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1664         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1665         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1666         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1667         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1668         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1669         dev_info->max_vfs = dev->pci_dev->max_vfs;
1670         if (hw->mac.type == ixgbe_mac_82598EB)
1671                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1672         else
1673                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1674 }
1675
1676 /* return 0 means link status changed, -1 means not changed */
1677 static int
1678 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1679 {
1680         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1681         struct rte_eth_link link, old;
1682         ixgbe_link_speed link_speed;
1683         int link_up;
1684         int diag;
1685
1686         link.link_status = 0;
1687         link.link_speed = 0;
1688         link.link_duplex = 0;
1689         memset(&old, 0, sizeof(old));
1690         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1691
1692         /* check if it needs to wait to complete, if lsc interrupt is enabled */
1693         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1694                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1695         else
1696                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1697         if (diag != 0) {
1698                 link.link_speed = ETH_LINK_SPEED_100;
1699                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1700                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1701                 if (link.link_status == old.link_status)
1702                         return -1;
1703                 return 0;
1704         }
1705
1706         if (link_up == 0) {
1707                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1708                 if (link.link_status == old.link_status)
1709                         return -1;
1710                 return 0;
1711         }
1712         link.link_status = 1;
1713         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1714
1715         switch (link_speed) {
1716         default:
1717         case IXGBE_LINK_SPEED_UNKNOWN:
1718                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1719                 link.link_speed = ETH_LINK_SPEED_100;
1720                 break;
1721
1722         case IXGBE_LINK_SPEED_100_FULL:
1723                 link.link_speed = ETH_LINK_SPEED_100;
1724                 break;
1725
1726         case IXGBE_LINK_SPEED_1GB_FULL:
1727                 link.link_speed = ETH_LINK_SPEED_1000;
1728                 break;
1729
1730         case IXGBE_LINK_SPEED_10GB_FULL:
1731                 link.link_speed = ETH_LINK_SPEED_10000;
1732                 break;
1733         }
1734         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1735
1736         if (link.link_status == old.link_status)
1737                 return -1;
1738
1739         return 0;
1740 }
1741
1742 static void
1743 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1744 {
1745         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1746         uint32_t fctrl;
1747
1748         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1749         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1750         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1751 }
1752
1753 static void
1754 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1755 {
1756         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757         uint32_t fctrl;
1758
1759         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1760         fctrl &= (~IXGBE_FCTRL_UPE);
1761         if (dev->data->all_multicast == 1)
1762                 fctrl |= IXGBE_FCTRL_MPE;
1763         else
1764                 fctrl &= (~IXGBE_FCTRL_MPE);
1765         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1766 }
1767
1768 static void
1769 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1770 {
1771         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1772         uint32_t fctrl;
1773
1774         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1775         fctrl |= IXGBE_FCTRL_MPE;
1776         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1777 }
1778
1779 static void
1780 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1781 {
1782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1783         uint32_t fctrl;
1784
1785         if (dev->data->promiscuous == 1)
1786                 return; /* must remain in all_multicast mode */
1787
1788         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1789         fctrl &= (~IXGBE_FCTRL_MPE);
1790         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1791 }
1792
1793 /**
1794  * It clears the interrupt causes and enables the interrupt.
1795  * It will be called once only during nic initialized.
1796  *
1797  * @param dev
1798  *  Pointer to struct rte_eth_dev.
1799  *
1800  * @return
1801  *  - On success, zero.
1802  *  - On failure, a negative value.
1803  */
1804 static int
1805 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
1806 {
1807         struct ixgbe_interrupt *intr =
1808                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1809
1810         ixgbe_dev_link_status_print(dev);
1811         intr->mask |= IXGBE_EICR_LSC;
1812
1813         return 0;
1814 }
1815
1816 /*
1817  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1818  *
1819  * @param dev
1820  *  Pointer to struct rte_eth_dev.
1821  *
1822  * @return
1823  *  - On success, zero.
1824  *  - On failure, a negative value.
1825  */
1826 static int
1827 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1828 {
1829         uint32_t eicr;
1830         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1831         struct ixgbe_interrupt *intr =
1832                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1833
1834         /* clear all cause mask */
1835         ixgbe_disable_intr(hw);
1836
1837         /* read-on-clear nic registers here */
1838         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1839         PMD_DRV_LOG(INFO, "eicr %x", eicr);
1840
1841         intr->flags = 0;
1842         if (eicr & IXGBE_EICR_LSC) {
1843                 /* set flag for async link update */
1844                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1845         }
1846
1847         if (eicr & IXGBE_EICR_MAILBOX)
1848                 intr->flags |= IXGBE_FLAG_MAILBOX;
1849
1850         return 0;
1851 }
1852
1853 /**
1854  * It gets and then prints the link status.
1855  *
1856  * @param dev
1857  *  Pointer to struct rte_eth_dev.
1858  *
1859  * @return
1860  *  - On success, zero.
1861  *  - On failure, a negative value.
1862  */
1863 static void
1864 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1865 {
1866         struct rte_eth_link link;
1867
1868         memset(&link, 0, sizeof(link));
1869         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1870         if (link.link_status) {
1871                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1872                                         (int)(dev->data->port_id),
1873                                         (unsigned)link.link_speed,
1874                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1875                                         "full-duplex" : "half-duplex");
1876         } else {
1877                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1878                                 (int)(dev->data->port_id));
1879         }
1880         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1881                                 dev->pci_dev->addr.domain,
1882                                 dev->pci_dev->addr.bus,
1883                                 dev->pci_dev->addr.devid,
1884                                 dev->pci_dev->addr.function);
1885 }
1886
1887 /*
1888  * It executes link_update after knowing an interrupt occured.
1889  *
1890  * @param dev
1891  *  Pointer to struct rte_eth_dev.
1892  *
1893  * @return
1894  *  - On success, zero.
1895  *  - On failure, a negative value.
1896  */
1897 static int
1898 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1899 {
1900         struct ixgbe_interrupt *intr =
1901                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1902         int64_t timeout;
1903         struct rte_eth_link link;
1904         int intr_enable_delay = false;
1905
1906         PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
1907
1908         if (intr->flags & IXGBE_FLAG_MAILBOX) {
1909                 ixgbe_pf_mbx_process(dev);
1910                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
1911         }
1912
1913         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1914                 /* get the link status before link update, for predicting later */
1915                 memset(&link, 0, sizeof(link));
1916                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1917
1918                 ixgbe_dev_link_update(dev, 0);
1919
1920                 /* likely to up */
1921                 if (!link.link_status)
1922                         /* handle it 1 sec later, wait it being stable */
1923                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
1924                 /* likely to down */
1925                 else
1926                         /* handle it 4 sec later, wait it being stable */
1927                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
1928
1929                 ixgbe_dev_link_status_print(dev);
1930
1931                 intr_enable_delay = true;
1932         }
1933
1934         if (intr_enable_delay) {
1935                 if (rte_eal_alarm_set(timeout * 1000,
1936                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
1937                         PMD_DRV_LOG(ERR, "Error setting alarm");
1938         } else {
1939                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
1940                 ixgbe_enable_intr(dev);
1941                 rte_intr_enable(&(dev->pci_dev->intr_handle));
1942         }
1943
1944
1945         return 0;
1946 }
1947
1948 /**
1949  * Interrupt handler which shall be registered for alarm callback for delayed
1950  * handling specific interrupt to wait for the stable nic state. As the
1951  * NIC interrupt state is not stable for ixgbe after link is just down,
1952  * it needs to wait 4 seconds to get the stable status.
1953  *
1954  * @param handle
1955  *  Pointer to interrupt handle.
1956  * @param param
1957  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1958  *
1959  * @return
1960  *  void
1961  */
1962 static void
1963 ixgbe_dev_interrupt_delayed_handler(void *param)
1964 {
1965         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1966         struct ixgbe_interrupt *intr =
1967                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1968         struct ixgbe_hw *hw =
1969                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1970         uint32_t eicr;
1971
1972         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1973         if (eicr & IXGBE_EICR_MAILBOX)
1974                 ixgbe_pf_mbx_process(dev);
1975
1976         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1977                 ixgbe_dev_link_update(dev, 0);
1978                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
1979                 ixgbe_dev_link_status_print(dev);
1980                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1981         }
1982
1983         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
1984         ixgbe_enable_intr(dev);
1985         rte_intr_enable(&(dev->pci_dev->intr_handle));
1986 }
1987
1988 /**
1989  * Interrupt handler triggered by NIC  for handling
1990  * specific interrupt.
1991  *
1992  * @param handle
1993  *  Pointer to interrupt handle.
1994  * @param param
1995  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1996  *
1997  * @return
1998  *  void
1999  */
2000 static void
2001 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2002                                                         void *param)
2003 {
2004         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2005         ixgbe_dev_interrupt_get_status(dev);
2006         ixgbe_dev_interrupt_action(dev);
2007 }
2008
2009 static int
2010 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2011 {
2012         struct ixgbe_hw *hw;
2013
2014         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2015         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2016 }
2017
2018 static int
2019 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2020 {
2021         struct ixgbe_hw *hw;
2022
2023         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2024         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2025 }
2026
2027 static int
2028 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2029 {
2030         struct ixgbe_hw *hw;
2031         int err;
2032         uint32_t rx_buf_size;
2033         uint32_t max_high_water;
2034         uint32_t mflcn;
2035         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2036                 ixgbe_fc_none,
2037                 ixgbe_fc_rx_pause,
2038                 ixgbe_fc_tx_pause,
2039                 ixgbe_fc_full
2040         };
2041
2042         PMD_INIT_FUNC_TRACE();
2043
2044         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2046         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2047
2048         /*
2049          * At least reserve one Ethernet frame for watermark
2050          * high_water/low_water in kilo bytes for ixgbe
2051          */
2052         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2053         if ((fc_conf->high_water > max_high_water) ||
2054                 (fc_conf->high_water < fc_conf->low_water)) {
2055                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2056                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2057                 return (-EINVAL);
2058         }
2059
2060         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2061         hw->fc.pause_time     = fc_conf->pause_time;
2062         hw->fc.high_water[0]  = fc_conf->high_water;
2063         hw->fc.low_water[0]   = fc_conf->low_water;
2064         hw->fc.send_xon       = fc_conf->send_xon;
2065
2066         err = ixgbe_fc_enable(hw);
2067
2068         /* Not negotiated is not an error case */
2069         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2070
2071                 /* check if we want to forward MAC frames - driver doesn't have native
2072                  * capability to do that, so we'll write the registers ourselves */
2073
2074                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2075
2076                 /* set or clear MFLCN.PMCF bit depending on configuration */
2077                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2078                         mflcn |= IXGBE_MFLCN_PMCF;
2079                 else
2080                         mflcn &= ~IXGBE_MFLCN_PMCF;
2081
2082                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2083                 IXGBE_WRITE_FLUSH(hw);
2084
2085                 return 0;
2086         }
2087
2088         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2089         return -EIO;
2090 }
2091
2092 /**
2093  *  ixgbe_pfc_enable_generic - Enable flow control
2094  *  @hw: pointer to hardware structure
2095  *  @tc_num: traffic class number
2096  *  Enable flow control according to the current settings.
2097  */
2098 static int
2099 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2100 {
2101         int ret_val = 0;
2102         uint32_t mflcn_reg, fccfg_reg;
2103         uint32_t reg;
2104         uint32_t fcrtl, fcrth;
2105         uint8_t i;
2106         uint8_t nb_rx_en;
2107
2108         /* Validate the water mark configuration */
2109         if (!hw->fc.pause_time) {
2110                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2111                 goto out;
2112         }
2113
2114         /* Low water mark of zero causes XOFF floods */
2115         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2116                  /* High/Low water can not be 0 */
2117                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2118                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2119                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2120                         goto out;
2121                 }
2122
2123                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2124                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2125                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2126                         goto out;
2127                 }
2128         }
2129         /* Negotiate the fc mode to use */
2130         ixgbe_fc_autoneg(hw);
2131
2132         /* Disable any previous flow control settings */
2133         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2134         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2135
2136         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2137         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2138
2139         switch (hw->fc.current_mode) {
2140         case ixgbe_fc_none:
2141                 /*
2142                  * If the count of enabled RX Priority Flow control >1,
2143                  * and the TX pause can not be disabled
2144                  */
2145                 nb_rx_en = 0;
2146                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2147                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2148                         if (reg & IXGBE_FCRTH_FCEN)
2149                                 nb_rx_en++;
2150                 }
2151                 if (nb_rx_en > 1)
2152                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2153                 break;
2154         case ixgbe_fc_rx_pause:
2155                 /*
2156                  * Rx Flow control is enabled and Tx Flow control is
2157                  * disabled by software override. Since there really
2158                  * isn't a way to advertise that we are capable of RX
2159                  * Pause ONLY, we will advertise that we support both
2160                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2161                  * disable the adapter's ability to send PAUSE frames.
2162                  */
2163                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2164                 /*
2165                  * If the count of enabled RX Priority Flow control >1,
2166                  * and the TX pause can not be disabled
2167                  */
2168                 nb_rx_en = 0;
2169                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2170                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2171                         if (reg & IXGBE_FCRTH_FCEN)
2172                                 nb_rx_en++;
2173                 }
2174                 if (nb_rx_en > 1)
2175                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2176                 break;
2177         case ixgbe_fc_tx_pause:
2178                 /*
2179                  * Tx Flow control is enabled, and Rx Flow control is
2180                  * disabled by software override.
2181                  */
2182                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2183                 break;
2184         case ixgbe_fc_full:
2185                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2186                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2187                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2188                 break;
2189         default:
2190                 DEBUGOUT("Flow control param set incorrectly\n");
2191                 ret_val = IXGBE_ERR_CONFIG;
2192                 goto out;
2193                 break;
2194         }
2195
2196         /* Set 802.3x based flow control settings. */
2197         mflcn_reg |= IXGBE_MFLCN_DPF;
2198         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2199         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2200
2201         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2202         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2203                 hw->fc.high_water[tc_num]) {
2204                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2205                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2206                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2207         } else {
2208                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2209                 /*
2210                  * In order to prevent Tx hangs when the internal Tx
2211                  * switch is enabled we must set the high water mark
2212                  * to the maximum FCRTH value.  This allows the Tx
2213                  * switch to function even under heavy Rx workloads.
2214                  */
2215                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2216         }
2217         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2218
2219         /* Configure pause time (2 TCs per register) */
2220         reg = hw->fc.pause_time * 0x00010001;
2221         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2222                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2223
2224         /* Configure flow control refresh threshold value */
2225         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2226
2227 out:
2228         return ret_val;
2229 }
2230
2231 static int
2232 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2233 {
2234         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2235         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2236
2237         if(hw->mac.type != ixgbe_mac_82598EB) {
2238                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2239         }
2240         return ret_val;
2241 }
2242
2243 static int
2244 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2245 {
2246         int err;
2247         uint32_t rx_buf_size;
2248         uint32_t max_high_water;
2249         uint8_t tc_num;
2250         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2251         struct ixgbe_hw *hw =
2252                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2253         struct ixgbe_dcb_config *dcb_config =
2254                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2255
2256         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2257                 ixgbe_fc_none,
2258                 ixgbe_fc_rx_pause,
2259                 ixgbe_fc_tx_pause,
2260                 ixgbe_fc_full
2261         };
2262
2263         PMD_INIT_FUNC_TRACE();
2264
2265         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2266         tc_num = map[pfc_conf->priority];
2267         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2268         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2269         /*
2270          * At least reserve one Ethernet frame for watermark
2271          * high_water/low_water in kilo bytes for ixgbe
2272          */
2273         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2274         if ((pfc_conf->fc.high_water > max_high_water) ||
2275                 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2276                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2277                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2278                 return (-EINVAL);
2279         }
2280
2281         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2282         hw->fc.pause_time = pfc_conf->fc.pause_time;
2283         hw->fc.send_xon = pfc_conf->fc.send_xon;
2284         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2285         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2286
2287         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2288
2289         /* Not negotiated is not an error case */
2290         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2291                 return 0;
2292
2293         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2294         return -EIO;
2295 }
2296
2297 static int
2298 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2299                                 struct rte_eth_rss_reta *reta_conf)
2300 {
2301         uint8_t i,j,mask;
2302         uint32_t reta;
2303         struct ixgbe_hw *hw =
2304                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2305
2306         PMD_INIT_FUNC_TRACE();
2307         /*
2308         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2309         * 128-entries in 32 registers
2310          */
2311         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2312                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2313                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2314                 else
2315                         mask = (uint8_t)((reta_conf->mask_hi >>
2316                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2317                 if (mask != 0) {
2318                         reta = 0;
2319                         if (mask != 0xF)
2320                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2321
2322                         for (j = 0; j < 4; j++) {
2323                                 if (mask & (0x1 << j)) {
2324                                         if (mask != 0xF)
2325                                                 reta &= ~(0xFF << 8 * j);
2326                                         reta |= reta_conf->reta[i + j] << 8*j;
2327                                 }
2328                         }
2329                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2330                 }
2331         }
2332
2333         return 0;
2334 }
2335
2336 static int
2337 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2338                                 struct rte_eth_rss_reta *reta_conf)
2339 {
2340         uint8_t i,j,mask;
2341         uint32_t reta;
2342         struct ixgbe_hw *hw =
2343                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2344
2345         PMD_INIT_FUNC_TRACE();
2346         /*
2347          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2348          * 128-entries in 32 registers
2349          */
2350         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2351                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2352                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2353                 else
2354                         mask = (uint8_t)((reta_conf->mask_hi >>
2355                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2356
2357                 if (mask != 0) {
2358                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2359                         for (j = 0; j < 4; j++) {
2360                                 if (mask & (0x1 << j))
2361                                         reta_conf->reta[i + j] =
2362                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2363                         }
2364                 }
2365         }
2366
2367         return 0;
2368 }
2369
2370 static void
2371 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2372                                 uint32_t index, uint32_t pool)
2373 {
2374         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2375         uint32_t enable_addr = 1;
2376
2377         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2378 }
2379
2380 static void
2381 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2382 {
2383         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2384
2385         ixgbe_clear_rar(hw, index);
2386 }
2387
2388 /*
2389  * Virtual Function operations
2390  */
2391 static void
2392 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2393 {
2394         PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2395
2396         /* Clear interrupt mask to stop from interrupts being generated */
2397         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2398
2399         IXGBE_WRITE_FLUSH(hw);
2400 }
2401
2402 static int
2403 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2404 {
2405         struct rte_eth_conf* conf = &dev->data->dev_conf;
2406
2407         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2408                 dev->data->port_id);
2409
2410         /*
2411          * VF has no ability to enable/disable HW CRC
2412          * Keep the persistent behavior the same as Host PF
2413          */
2414 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2415         if (!conf->rxmode.hw_strip_crc) {
2416                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2417                 conf->rxmode.hw_strip_crc = 1;
2418         }
2419 #else
2420         if (conf->rxmode.hw_strip_crc) {
2421                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2422                 conf->rxmode.hw_strip_crc = 0;
2423         }
2424 #endif
2425
2426         return 0;
2427 }
2428
2429 static int
2430 ixgbevf_dev_start(struct rte_eth_dev *dev)
2431 {
2432         struct ixgbe_hw *hw =
2433                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2434         int err, mask = 0;
2435
2436         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2437
2438         hw->mac.ops.reset_hw(hw);
2439
2440         ixgbevf_dev_tx_init(dev);
2441
2442         /* This can fail when allocating mbufs for descriptor rings */
2443         err = ixgbevf_dev_rx_init(dev);
2444         if (err) {
2445                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2446                 ixgbe_dev_clear_queues(dev);
2447                 return err;
2448         }
2449
2450         /* Set vfta */
2451         ixgbevf_set_vfta_all(dev,1);
2452
2453         /* Set HW strip */
2454         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2455                 ETH_VLAN_EXTEND_MASK;
2456         ixgbevf_vlan_offload_set(dev, mask);
2457
2458         ixgbevf_dev_rxtx_start(dev);
2459
2460         return 0;
2461 }
2462
2463 static void
2464 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2465 {
2466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2467
2468         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2469
2470         hw->adapter_stopped = TRUE;
2471         ixgbe_stop_adapter(hw);
2472
2473         /*
2474           * Clear what we set, but we still keep shadow_vfta to
2475           * restore after device starts
2476           */
2477         ixgbevf_set_vfta_all(dev,0);
2478
2479         ixgbe_dev_clear_queues(dev);
2480 }
2481
2482 static void
2483 ixgbevf_dev_close(struct rte_eth_dev *dev)
2484 {
2485         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486
2487         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2488
2489         ixgbe_reset_hw(hw);
2490
2491         ixgbevf_dev_stop(dev);
2492
2493         /* reprogram the RAR[0] in case user changed it. */
2494         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2495 }
2496
2497 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2498 {
2499         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2500         struct ixgbe_vfta * shadow_vfta =
2501                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2502         int i = 0, j = 0, vfta = 0, mask = 1;
2503
2504         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2505                 vfta = shadow_vfta->vfta[i];
2506                 if(vfta){
2507                         mask = 1;
2508                         for (j = 0; j < 32; j++){
2509                                 if(vfta & mask)
2510                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2511                                 mask<<=1;
2512                         }
2513                 }
2514         }
2515
2516 }
2517
2518 static int
2519 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2520 {
2521         struct ixgbe_hw *hw =
2522                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         struct ixgbe_vfta * shadow_vfta =
2524                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2525         uint32_t vid_idx = 0;
2526         uint32_t vid_bit = 0;
2527         int ret = 0;
2528
2529         PMD_INIT_FUNC_TRACE();
2530
2531         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2532         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2533         if(ret){
2534                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2535                 return ret;
2536         }
2537         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2538         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2539
2540         /* Save what we set and retore it after device reset */
2541         if (on)
2542                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2543         else
2544                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2545
2546         return 0;
2547 }
2548
2549 static void
2550 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2551 {
2552         struct ixgbe_hw *hw =
2553                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2554         uint32_t ctrl;
2555
2556         PMD_INIT_FUNC_TRACE();
2557
2558         if(queue >= hw->mac.max_rx_queues)
2559                 return;
2560
2561         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2562         if(on)
2563                 ctrl |= IXGBE_RXDCTL_VME;
2564         else
2565                 ctrl &= ~IXGBE_RXDCTL_VME;
2566         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2567
2568         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2569 }
2570
2571 static void
2572 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2573 {
2574         struct ixgbe_hw *hw =
2575                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2576         uint16_t i;
2577         int on = 0;
2578
2579         /* VF function only support hw strip feature, others are not support */
2580         if(mask & ETH_VLAN_STRIP_MASK){
2581                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2582
2583                 for(i=0; i < hw->mac.max_rx_queues; i++)
2584                         ixgbevf_vlan_strip_queue_set(dev,i,on);
2585         }
2586 }
2587
2588 static int
2589 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2590 {
2591         uint32_t reg_val;
2592
2593         /* we only need to do this if VMDq is enabled */
2594         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2595         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2596                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2597                 return (-1);
2598         }
2599
2600         return 0;
2601 }
2602
2603 static uint32_t
2604 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2605 {
2606         uint32_t vector = 0;
2607         switch (hw->mac.mc_filter_type) {
2608         case 0:   /* use bits [47:36] of the address */
2609                 vector = ((uc_addr->addr_bytes[4] >> 4) |
2610                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2611                 break;
2612         case 1:   /* use bits [46:35] of the address */
2613                 vector = ((uc_addr->addr_bytes[4] >> 3) |
2614                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2615                 break;
2616         case 2:   /* use bits [45:34] of the address */
2617                 vector = ((uc_addr->addr_bytes[4] >> 2) |
2618                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2619                 break;
2620         case 3:   /* use bits [43:32] of the address */
2621                 vector = ((uc_addr->addr_bytes[4]) |
2622                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2623                 break;
2624         default:  /* Invalid mc_filter_type */
2625                 break;
2626         }
2627
2628         /* vector can only be 12-bits or boundary will be exceeded */
2629         vector &= 0xFFF;
2630         return vector;
2631 }
2632
2633 static int
2634 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
2635                                uint8_t on)
2636 {
2637         uint32_t vector;
2638         uint32_t uta_idx;
2639         uint32_t reg_val;
2640         uint32_t uta_shift;
2641         uint32_t rc;
2642         const uint32_t ixgbe_uta_idx_mask = 0x7F;
2643         const uint32_t ixgbe_uta_bit_shift = 5;
2644         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
2645         const uint32_t bit1 = 0x1;
2646
2647         struct ixgbe_hw *hw =
2648                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2649         struct ixgbe_uta_info *uta_info =
2650                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2651
2652         /* The UTA table only exists on 82599 hardware and newer */
2653         if (hw->mac.type < ixgbe_mac_82599EB)
2654                 return (-ENOTSUP);
2655
2656         vector = ixgbe_uta_vector(hw,mac_addr);
2657         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
2658         uta_shift = vector & ixgbe_uta_bit_mask;
2659
2660         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
2661         if(rc == on)
2662                 return 0;
2663
2664         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
2665         if (on) {
2666                 uta_info->uta_in_use++;
2667                 reg_val |= (bit1 << uta_shift);
2668                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
2669         } else {
2670                 uta_info->uta_in_use--;
2671                 reg_val &= ~(bit1 << uta_shift);
2672                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
2673         }
2674
2675         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
2676
2677         if (uta_info->uta_in_use > 0)
2678                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2679                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2680         else
2681                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
2682
2683         return 0;
2684 }
2685
2686 static int
2687 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
2688 {
2689         int i;
2690         struct ixgbe_hw *hw =
2691                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2692         struct ixgbe_uta_info *uta_info =
2693                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2694
2695         /* The UTA table only exists on 82599 hardware and newer */
2696         if (hw->mac.type < ixgbe_mac_82599EB)
2697                 return (-ENOTSUP);
2698
2699         if(on) {
2700                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2701                         uta_info->uta_shadow[i] = ~0;
2702                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2703                 }
2704         } else {
2705                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2706                         uta_info->uta_shadow[i] = 0;
2707                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2708                 }
2709         }
2710         return 0;
2711
2712 }
2713 static int
2714 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
2715                                uint16_t rx_mask, uint8_t on)
2716 {
2717         int val = 0;
2718
2719         struct ixgbe_hw *hw =
2720                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2721         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
2722
2723         if (hw->mac.type == ixgbe_mac_82598EB) {
2724                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
2725                         " on 82599 hardware and newer\n");
2726                 return (-ENOTSUP);
2727         }
2728         if (ixgbe_vmdq_mode_check(hw) < 0)
2729                 return (-ENOTSUP);
2730
2731         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
2732                 val |= IXGBE_VMOLR_AUPE;
2733         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
2734                 val |= IXGBE_VMOLR_ROMPE;
2735         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
2736                 val |= IXGBE_VMOLR_ROPE;
2737         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
2738                 val |= IXGBE_VMOLR_BAM;
2739         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
2740                 val |= IXGBE_VMOLR_MPE;
2741
2742         if (on)
2743                 vmolr |= val;
2744         else
2745                 vmolr &= ~val;
2746
2747         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
2748
2749         return 0;
2750 }
2751
2752 static int
2753 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2754 {
2755         uint32_t reg,addr;
2756         uint32_t val;
2757         const uint8_t bit1 = 0x1;
2758
2759         struct ixgbe_hw *hw =
2760                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2761
2762         if (ixgbe_vmdq_mode_check(hw) < 0)
2763                 return (-ENOTSUP);
2764
2765         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
2766         reg = IXGBE_READ_REG(hw, addr);
2767         val = bit1 << pool;
2768
2769         if (on)
2770                 reg |= val;
2771         else
2772                 reg &= ~val;
2773
2774         IXGBE_WRITE_REG(hw, addr,reg);
2775
2776         return 0;
2777 }
2778
2779 static int
2780 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2781 {
2782         uint32_t reg,addr;
2783         uint32_t val;
2784         const uint8_t bit1 = 0x1;
2785
2786         struct ixgbe_hw *hw =
2787                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2788
2789         if (ixgbe_vmdq_mode_check(hw) < 0)
2790                 return (-ENOTSUP);
2791
2792         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
2793         reg = IXGBE_READ_REG(hw, addr);
2794         val = bit1 << pool;
2795
2796         if (on)
2797                 reg |= val;
2798         else
2799                 reg &= ~val;
2800
2801         IXGBE_WRITE_REG(hw, addr,reg);
2802
2803         return 0;
2804 }
2805
2806 static int
2807 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
2808                         uint64_t pool_mask, uint8_t vlan_on)
2809 {
2810         int ret = 0;
2811         uint16_t pool_idx;
2812         struct ixgbe_hw *hw =
2813                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2814
2815         if (ixgbe_vmdq_mode_check(hw) < 0)
2816                 return (-ENOTSUP);
2817         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
2818                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
2819                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
2820                         if (ret < 0)
2821                                 return ret;
2822         }
2823
2824         return ret;
2825 }
2826
2827 static int
2828 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
2829                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
2830                         uint8_t rule_id, uint8_t on)
2831 {
2832         uint32_t mr_ctl,vlvf;
2833         uint32_t mp_lsb = 0;
2834         uint32_t mv_msb = 0;
2835         uint32_t mv_lsb = 0;
2836         uint32_t mp_msb = 0;
2837         uint8_t i = 0;
2838         int reg_index = 0;
2839         uint64_t vlan_mask = 0;
2840
2841         const uint8_t pool_mask_offset = 32;
2842         const uint8_t vlan_mask_offset = 32;
2843         const uint8_t dst_pool_offset = 8;
2844         const uint8_t rule_mr_offset  = 4;
2845         const uint8_t mirror_rule_mask= 0x0F;
2846
2847         struct ixgbe_mirror_info *mr_info =
2848                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
2849         struct ixgbe_hw *hw =
2850                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2851
2852         if (ixgbe_vmdq_mode_check(hw) < 0)
2853                 return (-ENOTSUP);
2854
2855         /* Check if vlan mask is valid */
2856         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
2857                 if (mirror_conf->vlan.vlan_mask == 0)
2858                         return (-EINVAL);
2859         }
2860
2861         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
2862         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2863                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
2864                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
2865                                 /* search vlan id related pool vlan filter index */
2866                                 reg_index = ixgbe_find_vlvf_slot(hw,
2867                                                 mirror_conf->vlan.vlan_id[i]);
2868                                 if(reg_index < 0)
2869                                         return (-EINVAL);
2870                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
2871                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
2872                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
2873                                                 == mirror_conf->vlan.vlan_id[i]))
2874                                         vlan_mask |= (1ULL << reg_index);
2875                                 else
2876                                         return (-EINVAL);
2877                         }
2878                 }
2879
2880                 if (on) {
2881                         mv_lsb = vlan_mask & 0xFFFFFFFF;
2882                         mv_msb = vlan_mask >> vlan_mask_offset;
2883
2884                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
2885                                                 mirror_conf->vlan.vlan_mask;
2886                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
2887                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
2888                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
2889                                                 mirror_conf->vlan.vlan_id[i];
2890                         }
2891                 } else {
2892                         mv_lsb = 0;
2893                         mv_msb = 0;
2894                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
2895                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
2896                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
2897                 }
2898         }
2899
2900         /*
2901          * if enable pool mirror, write related pool mask register,if disable
2902          * pool mirror, clear PFMRVM register
2903          */
2904         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
2905                 if (on) {
2906                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
2907                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
2908                         mr_info->mr_conf[rule_id].pool_mask =
2909                                         mirror_conf->pool_mask;
2910
2911                 } else {
2912                         mp_lsb = 0;
2913                         mp_msb = 0;
2914                         mr_info->mr_conf[rule_id].pool_mask = 0;
2915                 }
2916         }
2917
2918         /* read  mirror control register and recalculate it */
2919         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
2920
2921         if (on) {
2922                 mr_ctl |= mirror_conf->rule_type_mask;
2923                 mr_ctl &= mirror_rule_mask;
2924                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
2925         } else
2926                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
2927
2928         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
2929         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
2930
2931         /* write mirrror control  register */
2932         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
2933
2934         /* write pool mirrror control  register */
2935         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
2936                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
2937                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
2938                                 mp_msb);
2939         }
2940         /* write VLAN mirrror control  register */
2941         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2942                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
2943                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
2944                                 mv_msb);
2945         }
2946
2947         return 0;
2948 }
2949
2950 static int
2951 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
2952 {
2953         int mr_ctl = 0;
2954         uint32_t lsb_val = 0;
2955         uint32_t msb_val = 0;
2956         const uint8_t rule_mr_offset = 4;
2957
2958         struct ixgbe_hw *hw =
2959                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2960         struct ixgbe_mirror_info *mr_info =
2961                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
2962
2963         if (ixgbe_vmdq_mode_check(hw) < 0)
2964                 return (-ENOTSUP);
2965
2966         memset(&mr_info->mr_conf[rule_id], 0,
2967                 sizeof(struct rte_eth_vmdq_mirror_conf));
2968
2969         /* clear PFVMCTL register */
2970         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
2971
2972         /* clear pool mask register */
2973         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
2974         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
2975
2976         /* clear vlan mask register */
2977         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
2978         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
2979
2980         return 0;
2981 }