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43 #include <rte_interrupts.h>
45 #include <rte_debug.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_memcpy.h>
50 #include <rte_malloc.h>
51 #include <rte_random.h>
53 #include "ixgbe/ixgbe_common.h"
54 #include "ixgbe_ethdev.h"
56 #define IXGBE_MAX_VFTA (128)
59 void eth_random_addr(uint8_t *addr)
61 uint64_t rand = rte_rand();
62 uint8_t *p = (uint8_t*)&rand;
64 rte_memcpy(addr, p, ETHER_ADDR_LEN);
65 addr[0] &= 0xfe; /* clear multicast bit */
66 addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
69 static inline uint16_t
70 dev_num_vf(struct rte_eth_dev *eth_dev)
72 return eth_dev->pci_dev->max_vfs;
76 int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
78 unsigned char vf_mac_addr[ETHER_ADDR_LEN];
79 struct ixgbe_vf_info *vfinfo =
80 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
83 for (vfn = 0; vfn < vf_num; vfn++) {
84 eth_random_addr(vf_mac_addr);
85 /* keep the random address as default */
86 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
94 ixgbe_mb_intr_setup(struct rte_eth_dev *dev)
96 struct ixgbe_interrupt *intr =
97 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
99 intr->mask |= IXGBE_EICR_MAILBOX;
104 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)
106 struct ixgbe_vf_info **vfinfo =
107 IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
108 struct ixgbe_hw *hw =
109 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
113 PMD_INIT_FUNC_TRACE();
115 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
116 if (0 == (vf_num = dev_num_vf(eth_dev)))
119 *vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0);
121 rte_panic("Cannot allocate memory for private VF data\n");
123 if (vf_num >= ETH_32_POOLS) {
125 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;
126 } else if (vf_num >= ETH_16_POOLS) {
128 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;
131 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;
134 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
135 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
136 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
138 ixgbe_vf_perm_addr_gen(eth_dev, vf_num);
140 /* init_mailbox_params */
141 hw->mbx.ops.init_params(hw);
143 /* set mb interrupt mask */
144 ixgbe_mb_intr_setup(eth_dev);
149 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)
151 uint32_t vtctl, fcrth;
152 uint32_t vfre_slot, vfre_offset;
154 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
155 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
156 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
157 uint32_t gpie, gcr_ext;
161 if (0 == (vf_num = dev_num_vf(eth_dev)))
164 /* enable VMDq and set the default pool for PF */
165 vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
166 vtctl |= IXGBE_VMD_CTL_VMDQ_EN;
167 vtctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
169 << IXGBE_VT_CTL_POOL_SHIFT;
170 vtctl |= IXGBE_VT_CTL_REPLEN;
171 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
173 vfre_offset = vf_num & VFRE_MASK;
174 vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;
176 /* Enable pools reserved to PF only */
177 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0) << vfre_offset);
178 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);
179 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0) << vfre_offset);
180 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);
182 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
183 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
185 /* clear VMDq map to perment rar 0 */
186 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
188 /* clear VMDq map to scan rar 127 */
189 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);
190 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);
192 /* set VMDq map to default PF pool */
193 hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);
196 * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode
198 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
199 gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
201 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
202 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
203 gpie |= IXGBE_GPIE_MSIX_MODE;
205 switch (RTE_ETH_DEV_SRIOV(eth_dev).active) {
207 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
208 gpie |= IXGBE_GPIE_VTMODE_64;
211 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;
212 gpie |= IXGBE_GPIE_VTMODE_32;
215 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;
216 gpie |= IXGBE_GPIE_VTMODE_16;
220 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
221 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
224 * enable vlan filtering and allow all vlan tags through
226 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
227 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
228 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
230 /* VFTA - enable all vlan filters */
231 for (i = 0; i < IXGBE_MAX_VFTA; i++) {
232 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
235 /* Enable MAC Anti-Spoofing */
236 hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);
238 /* set flow control threshold to max to avoid tx switch hang */
239 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
240 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
241 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
242 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
249 set_rx_mode(struct rte_eth_dev *dev)
251 struct rte_eth_dev_data *dev_data =
252 (struct rte_eth_dev_data*)dev->data->dev_private;
253 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
254 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
255 uint16_t vfn = dev_num_vf(dev);
257 /* Check for Promiscuous and All Multicast modes */
258 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
260 /* set all bits that we expect to always be set */
261 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
262 fctrl |= IXGBE_FCTRL_BAM;
264 /* clear the bits we are changing the status of */
265 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
267 if (dev_data->promiscuous) {
268 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
269 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
270 /* don't hardware filter vlans in promisc mode */
271 ixgbe_vlan_hw_filter_disable(dev);
273 if (dev_data->all_multicast) {
274 fctrl |= IXGBE_FCTRL_MPE;
275 vmolr |= IXGBE_VMOLR_MPE;
277 vmolr |= IXGBE_VMOLR_ROMPE;
279 ixgbe_vlan_hw_filter_enable(dev);
282 if (hw->mac.type != ixgbe_mac_82598EB) {
283 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &
284 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
286 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);
289 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
291 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
292 ixgbe_vlan_hw_strip_enable_all(dev);
294 ixgbe_vlan_hw_strip_disable_all(dev);
298 ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
300 struct ixgbe_hw *hw =
301 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
302 struct ixgbe_vf_info *vfinfo =
303 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
304 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
305 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
307 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE |
308 IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
309 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
311 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);
313 /* reset multicast table array for vf */
314 vfinfo[vf].num_vf_mc_hashes = 0;
319 hw->mac.ops.clear_rar(hw, rar_entry);
323 ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
325 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
327 uint32_t reg_offset, vf_shift;
328 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
329 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
331 vf_shift = vf & VFRE_MASK;
332 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
334 /* enable transmit and receive for vf */
335 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
336 reg |= (reg | (1 << vf_shift));
337 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
339 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
340 reg |= (reg | (1 << vf_shift));
341 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
343 /* Enable counting of spoofed packets in the SSVPC register */
344 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
345 reg |= (1 << vf_shift);
346 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
348 ixgbe_vf_reset_event(dev, vf);
352 ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
354 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
355 struct ixgbe_vf_info *vfinfo =
356 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
357 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
358 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
359 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
361 ixgbe_vf_reset_msg(dev, vf);
363 hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);
365 /* reply to reset with ack and vf mac address */
366 msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
367 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
369 * Piggyback the multicast filter type so VF can compute the
372 msgbuf[3] = hw->mac.mc_filter_type;
373 ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);
379 ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
381 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
382 struct ixgbe_vf_info *vfinfo =
383 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
384 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
385 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
387 if (is_valid_assigned_ether_addr((struct ether_addr*)new_mac)) {
388 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
389 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);
395 ixgbe_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
397 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
398 struct ixgbe_vf_info *vfinfo =
399 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
400 int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
401 IXGBE_VT_MSGINFO_SHIFT;
402 uint16_t *hash_list = (uint16_t *)&msgbuf[1];
405 const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;
406 const uint32_t IXGBE_MTA_BIT_SHIFT = 5;
407 const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
411 /* only so many hash values supported */
412 nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);
414 /* store the mc entries */
415 vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;
416 for (i = 0; i < nb_entries; i++) {
417 vfinfo->vf_mc_hashes[i] = hash_list[i];
420 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
421 mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
422 & IXGBE_MTA_INDEX_MASK;
423 mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;
424 reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));
425 reg_val |= (1 << mta_shift);
426 IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
433 ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
436 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
437 struct ixgbe_vf_info *vfinfo =
438 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
440 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
441 >> IXGBE_VT_MSGINFO_SHIFT;
442 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
445 vfinfo[vf].vlan_count++;
446 else if (vfinfo[vf].vlan_count)
447 vfinfo[vf].vlan_count--;
448 return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add);
452 ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
454 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
455 uint32_t new_mtu = msgbuf[1];
457 int max_frame = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
459 /* Only X540 supports jumbo frames in IOV mode */
460 if (hw->mac.type != ixgbe_mac_X540)
463 if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
466 max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
467 IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
468 if (max_frs < new_mtu) {
469 max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT;
470 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
477 ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
479 uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;
480 uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];
482 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
484 retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
486 RTE_LOG(ERR, PMD, "Error mbx recv msg from VF %d\n", vf);
490 /* do nothing with the message already been processed */
491 if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
494 /* flush the ack before we write any messages back */
495 IXGBE_WRITE_FLUSH(hw);
497 /* perform VF reset */
498 if (msgbuf[0] == IXGBE_VF_RESET) {
499 return ixgbe_vf_reset(dev, vf, msgbuf);
502 /* check & process VF to PF mailbox message */
503 switch ((msgbuf[0] & 0xFFFF)) {
504 case IXGBE_VF_SET_MAC_ADDR:
505 retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);
507 case IXGBE_VF_SET_MULTICAST:
508 retval = ixgbe_vf_set_multicast(dev, vf, msgbuf);
510 case IXGBE_VF_SET_LPE:
511 retval = ixgbe_set_vf_lpe(dev, vf, msgbuf);
513 case IXGBE_VF_SET_VLAN:
514 retval = ixgbe_vf_set_vlan(dev, vf, msgbuf);
517 RTE_LOG(DEBUG, PMD, "Unhandled Msg %8.8x\n", (unsigned) msgbuf[0]);
518 retval = IXGBE_ERR_MBX;
522 /* response the VF according to the message process result */
524 msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
526 msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
528 msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;
530 ixgbe_write_mbx(hw, msgbuf, 1, vf);
536 ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
538 uint32_t msg = IXGBE_VT_MSGTYPE_NACK;
539 struct ixgbe_hw *hw =
540 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
542 ixgbe_write_mbx(hw, &msg, 1, vf);
545 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)
548 struct ixgbe_hw *hw =
549 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
551 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
552 /* check & process vf function level reset */
553 if (!ixgbe_check_for_rst(hw, vf))
554 ixgbe_vf_reset_event(eth_dev, vf);
556 /* check & process vf mailbox messages */
557 if (!ixgbe_check_for_msg(hw, vf))
558 ixgbe_rcv_msg_from_vf(eth_dev, vf);
560 /* check & process acks from vf */
561 if (!ixgbe_check_for_ack(hw, vf))
562 ixgbe_rcv_ack_from_vf(eth_dev, vf);