4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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34 #include <sys/queue.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
47 #include <rte_cycles.h>
49 #include <rte_debug.h>
50 #include <rte_interrupts.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
55 #include <rte_tailq.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
82 #include "ixgbe_rxtx.h"
85 static inline struct rte_mbuf *
86 rte_rxmbuf_alloc(struct rte_mempool *mp)
90 m = __rte_mbuf_raw_alloc(mp);
91 __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
97 #define RTE_PMD_USE_PREFETCH
100 #ifdef RTE_PMD_USE_PREFETCH
102 * Prefetch a cache line into all cache levels.
104 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
106 #define rte_ixgbe_prefetch(p) do {} while(0)
109 /*********************************************************************
113 **********************************************************************/
116 * Check for descriptors with their DD bit set and free mbufs.
117 * Return the total number of buffers freed.
119 static inline int __attribute__((always_inline))
120 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
122 struct igb_tx_entry *txep;
126 /* check DD bit on threshold descriptor */
127 status = txq->tx_ring[txq->tx_next_dd].wb.status;
128 if (! (status & IXGBE_ADVTXD_STAT_DD))
132 * first buffer to free from S/W ring is at index
133 * tx_next_dd - (tx_rs_thresh-1)
135 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
137 /* prefetch the mbufs that are about to be freed */
138 for (i = 0; i < txq->tx_rs_thresh; ++i)
139 rte_prefetch0((txep + i)->mbuf);
141 /* free buffers one at a time */
142 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
143 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
144 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
148 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
149 rte_pktmbuf_free_seg(txep->mbuf);
154 /* buffers were freed, update counters */
155 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
156 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
157 if (txq->tx_next_dd >= txq->nb_tx_desc)
158 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
160 return txq->tx_rs_thresh;
163 /* Populate 4 descriptors with data from 4 mbufs */
165 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
167 uint64_t buf_dma_addr;
171 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
172 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
173 pkt_len = (*pkts)->pkt.data_len;
175 /* write data to descriptor */
176 txdp->read.buffer_addr = buf_dma_addr;
177 txdp->read.cmd_type_len =
178 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
179 txdp->read.olinfo_status =
180 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
184 /* Populate 1 descriptor with data from 1 mbuf */
186 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
188 uint64_t buf_dma_addr;
191 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
192 pkt_len = (*pkts)->pkt.data_len;
194 /* write data to descriptor */
195 txdp->read.buffer_addr = buf_dma_addr;
196 txdp->read.cmd_type_len =
197 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
198 txdp->read.olinfo_status =
199 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
203 * Fill H/W descriptor ring with mbuf data.
204 * Copy mbuf pointers to the S/W ring.
207 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
210 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
211 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
212 const int N_PER_LOOP = 4;
213 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
214 int mainpart, leftover;
218 * Process most of the packets in chunks of N pkts. Any
219 * leftover packets will get processed one at a time.
221 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
222 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
223 for (i = 0; i < mainpart; i += N_PER_LOOP) {
224 /* Copy N mbuf pointers to the S/W ring */
225 for (j = 0; j < N_PER_LOOP; ++j) {
226 (txep + i + j)->mbuf = *(pkts + i + j);
228 tx4(txdp + i, pkts + i);
231 if (unlikely(leftover > 0)) {
232 for (i = 0; i < leftover; ++i) {
233 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
234 tx1(txdp + mainpart + i, pkts + mainpart + i);
239 static inline uint16_t
240 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
243 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
244 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
248 * Begin scanning the H/W ring for done descriptors when the
249 * number of available descriptors drops below tx_free_thresh. For
250 * each done descriptor, free the associated buffer.
252 if (txq->nb_tx_free < txq->tx_free_thresh)
253 ixgbe_tx_free_bufs(txq);
255 /* Only use descriptors that are available */
256 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
257 if (unlikely(nb_pkts == 0))
260 /* Use exactly nb_pkts descriptors */
261 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
264 * At this point, we know there are enough descriptors in the
265 * ring to transmit all the packets. This assumes that each
266 * mbuf contains a single segment, and that no new offloads
267 * are expected, which would require a new context descriptor.
271 * See if we're going to wrap-around. If so, handle the top
272 * of the descriptor ring first, then do the bottom. If not,
273 * the processing looks just like the "bottom" part anyway...
275 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
276 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
277 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
280 * We know that the last descriptor in the ring will need to
281 * have its RS bit set because tx_rs_thresh has to be
282 * a divisor of the ring size
284 tx_r[txq->tx_next_rs].read.cmd_type_len |=
285 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
286 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
291 /* Fill H/W descriptor ring with mbuf data */
292 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
293 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
296 * Determine if RS bit should be set
297 * This is what we actually want:
298 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
299 * but instead of subtracting 1 and doing >=, we can just do
300 * greater than without subtracting.
302 if (txq->tx_tail > txq->tx_next_rs) {
303 tx_r[txq->tx_next_rs].read.cmd_type_len |=
304 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
305 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
307 if (txq->tx_next_rs >= txq->nb_tx_desc)
308 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
312 * Check for wrap-around. This would only happen if we used
313 * up to the last descriptor in the ring, no more, no less.
315 if (txq->tx_tail >= txq->nb_tx_desc)
318 /* update tail pointer */
320 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
326 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
331 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
332 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
333 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
335 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
339 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
340 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
341 nb_tx = (uint16_t)(nb_tx + ret);
342 nb_pkts = (uint16_t)(nb_pkts - ret);
351 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
352 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
353 uint16_t ol_flags, uint32_t vlan_macip_lens)
355 uint32_t type_tucmd_mlhl;
356 uint32_t mss_l4len_idx;
360 ctx_idx = txq->ctx_curr;
364 if (ol_flags & PKT_TX_VLAN_PKT) {
365 cmp_mask |= TX_VLAN_CMP_MASK;
368 if (ol_flags & PKT_TX_IP_CKSUM) {
369 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
370 cmp_mask |= TX_MAC_LEN_CMP_MASK;
373 /* Specify which HW CTX to upload. */
374 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
375 switch (ol_flags & PKT_TX_L4_MASK) {
376 case PKT_TX_UDP_CKSUM:
377 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
378 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
379 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
380 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
382 case PKT_TX_TCP_CKSUM:
383 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
384 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
385 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
386 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
388 case PKT_TX_SCTP_CKSUM:
389 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
390 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
391 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
392 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
395 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
396 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
400 txq->ctx_cache[ctx_idx].flags = ol_flags;
401 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
402 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
403 vlan_macip_lens & cmp_mask;
405 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
406 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
407 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
408 ctx_txd->seqnum_seed = 0;
412 * Check which hardware context can be used. Use the existing match
413 * or create a new context descriptor.
415 static inline uint32_t
416 what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
417 uint32_t vlan_macip_lens)
419 /* If match with the current used context */
420 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
421 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
422 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
423 return txq->ctx_curr;
426 /* What if match with the next context */
428 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
429 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
430 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
431 return txq->ctx_curr;
434 /* Mismatch, use the previous context */
435 return (IXGBE_CTX_NUM);
438 static inline uint32_t
439 tx_desc_cksum_flags_to_olinfo(uint16_t ol_flags)
441 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
442 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
445 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
446 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
450 static inline uint32_t
451 tx_desc_vlan_flags_to_cmdtype(uint16_t ol_flags)
453 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
454 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
457 /* Default RS bit threshold values */
458 #ifndef DEFAULT_TX_RS_THRESH
459 #define DEFAULT_TX_RS_THRESH 32
461 #ifndef DEFAULT_TX_FREE_THRESH
462 #define DEFAULT_TX_FREE_THRESH 32
465 /* Reset transmit descriptors after they have been used */
467 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
469 struct igb_tx_entry *sw_ring = txq->sw_ring;
470 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
471 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
472 uint16_t nb_tx_desc = txq->nb_tx_desc;
473 uint16_t desc_to_clean_to;
474 uint16_t nb_tx_to_clean;
476 /* Determine the last descriptor needing to be cleaned */
477 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
478 if (desc_to_clean_to >= nb_tx_desc)
479 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
481 /* Check to make sure the last descriptor to clean is done */
482 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
483 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
485 PMD_TX_FREE_LOG(DEBUG,
486 "TX descriptor %4u is not done"
487 "(port=%d queue=%d)",
489 txq->port_id, txq->queue_id);
490 /* Failed to clean any descriptors, better luck next time */
494 /* Figure out how many descriptors will be cleaned */
495 if (last_desc_cleaned > desc_to_clean_to)
496 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
499 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
502 PMD_TX_FREE_LOG(DEBUG,
503 "Cleaning %4u TX descriptors: %4u to %4u "
504 "(port=%d queue=%d)",
505 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
506 txq->port_id, txq->queue_id);
509 * The last descriptor to clean is done, so that means all the
510 * descriptors from the last descriptor that was cleaned
511 * up to the last descriptor with the RS bit set
512 * are done. Only reset the threshold descriptor.
514 txr[desc_to_clean_to].wb.status = 0;
516 /* Update the txq to reflect the last descriptor that was cleaned */
517 txq->last_desc_cleaned = desc_to_clean_to;
518 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
525 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
528 struct igb_tx_queue *txq;
529 struct igb_tx_entry *sw_ring;
530 struct igb_tx_entry *txe, *txn;
531 volatile union ixgbe_adv_tx_desc *txr;
532 volatile union ixgbe_adv_tx_desc *txd;
533 struct rte_mbuf *tx_pkt;
534 struct rte_mbuf *m_seg;
535 uint64_t buf_dma_addr;
536 uint32_t olinfo_status;
537 uint32_t cmd_type_len;
546 uint32_t vlan_macip_lens;
551 sw_ring = txq->sw_ring;
553 tx_id = txq->tx_tail;
554 txe = &sw_ring[tx_id];
556 /* Determine if the descriptor ring needs to be cleaned. */
557 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
558 ixgbe_xmit_cleanup(txq);
562 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
565 pkt_len = tx_pkt->pkt.pkt_len;
567 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
570 * Determine how many (if any) context descriptors
571 * are needed for offload functionality.
573 ol_flags = tx_pkt->ol_flags;
574 vlan_macip_lens = tx_pkt->pkt.vlan_macip.data;
576 /* If hardware offload required */
577 tx_ol_req = (uint16_t)(ol_flags & PKT_TX_OFFLOAD_MASK);
579 /* If new context need be built or reuse the exist ctx. */
580 ctx = what_advctx_update(txq, tx_ol_req,
582 /* Only allocate context descriptor if required*/
583 new_ctx = (ctx == IXGBE_CTX_NUM);
588 * Keep track of how many descriptors are used this loop
589 * This will always be the number of segments + the number of
590 * Context descriptors required to transmit the packet
592 nb_used = (uint16_t)(tx_pkt->pkt.nb_segs + new_ctx);
595 * The number of descriptors that must be allocated for a
596 * packet is the number of segments of that packet, plus 1
597 * Context Descriptor for the hardware offload, if any.
598 * Determine the last TX descriptor to allocate in the TX ring
599 * for the packet, starting from the current position (tx_id)
602 tx_last = (uint16_t) (tx_id + nb_used - 1);
605 if (tx_last >= txq->nb_tx_desc)
606 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
608 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
609 " tx_first=%u tx_last=%u\n",
610 (unsigned) txq->port_id,
611 (unsigned) txq->queue_id,
617 * Make sure there are enough TX descriptors available to
618 * transmit the entire packet.
619 * nb_used better be less than or equal to txq->tx_rs_thresh
621 if (nb_used > txq->nb_tx_free) {
622 PMD_TX_FREE_LOG(DEBUG,
623 "Not enough free TX descriptors "
624 "nb_used=%4u nb_free=%4u "
625 "(port=%d queue=%d)",
626 nb_used, txq->nb_tx_free,
627 txq->port_id, txq->queue_id);
629 if (ixgbe_xmit_cleanup(txq) != 0) {
630 /* Could not clean any descriptors */
636 /* nb_used better be <= txq->tx_rs_thresh */
637 if (unlikely(nb_used > txq->tx_rs_thresh)) {
638 PMD_TX_FREE_LOG(DEBUG,
639 "The number of descriptors needed to "
640 "transmit the packet exceeds the "
641 "RS bit threshold. This will impact "
643 "nb_used=%4u nb_free=%4u "
645 "(port=%d queue=%d)",
646 nb_used, txq->nb_tx_free,
648 txq->port_id, txq->queue_id);
650 * Loop here until there are enough TX
651 * descriptors or until the ring cannot be
654 while (nb_used > txq->nb_tx_free) {
655 if (ixgbe_xmit_cleanup(txq) != 0) {
657 * Could not clean any
669 * By now there are enough free TX descriptors to transmit
674 * Set common flags of all TX Data Descriptors.
676 * The following bits must be set in all Data Descriptors:
677 * - IXGBE_ADVTXD_DTYP_DATA
678 * - IXGBE_ADVTXD_DCMD_DEXT
680 * The following bits must be set in the first Data Descriptor
681 * and are ignored in the other ones:
682 * - IXGBE_ADVTXD_DCMD_IFCS
683 * - IXGBE_ADVTXD_MAC_1588
684 * - IXGBE_ADVTXD_DCMD_VLE
686 * The following bits must only be set in the last Data
688 * - IXGBE_TXD_CMD_EOP
690 * The following bits can be set in any Data Descriptor, but
691 * are only set in the last Data Descriptor:
694 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
695 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
696 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
697 #ifdef RTE_LIBRTE_IEEE1588
698 if (ol_flags & PKT_TX_IEEE1588_TMST)
699 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
704 * Setup the TX Advanced Context Descriptor if required
707 volatile struct ixgbe_adv_tx_context_desc *
710 ctx_txd = (volatile struct
711 ixgbe_adv_tx_context_desc *)
714 txn = &sw_ring[txe->next_id];
715 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
717 if (txe->mbuf != NULL) {
718 rte_pktmbuf_free_seg(txe->mbuf);
722 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
725 txe->last_id = tx_last;
726 tx_id = txe->next_id;
731 * Setup the TX Advanced Data Descriptor,
732 * This path will go through
733 * whatever new/reuse the context descriptor
735 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
736 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
737 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
743 txn = &sw_ring[txe->next_id];
745 if (txe->mbuf != NULL)
746 rte_pktmbuf_free_seg(txe->mbuf);
750 * Set up Transmit Data Descriptor.
752 slen = m_seg->pkt.data_len;
753 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
754 txd->read.buffer_addr =
755 rte_cpu_to_le_64(buf_dma_addr);
756 txd->read.cmd_type_len =
757 rte_cpu_to_le_32(cmd_type_len | slen);
758 txd->read.olinfo_status =
759 rte_cpu_to_le_32(olinfo_status);
760 txe->last_id = tx_last;
761 tx_id = txe->next_id;
763 m_seg = m_seg->pkt.next;
764 } while (m_seg != NULL);
767 * The last packet data descriptor needs End Of Packet (EOP)
769 cmd_type_len |= IXGBE_TXD_CMD_EOP;
770 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
771 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
773 /* Set RS bit only on threshold packets' last descriptor */
774 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
775 PMD_TX_FREE_LOG(DEBUG,
776 "Setting RS bit on TXD id="
777 "%4u (port=%d queue=%d)",
778 tx_last, txq->port_id, txq->queue_id);
780 cmd_type_len |= IXGBE_TXD_CMD_RS;
782 /* Update txq RS bit counters */
785 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
791 * Set the Transmit Descriptor Tail (TDT)
793 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
794 (unsigned) txq->port_id, (unsigned) txq->queue_id,
795 (unsigned) tx_id, (unsigned) nb_tx);
796 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
797 txq->tx_tail = tx_id;
802 /*********************************************************************
806 **********************************************************************/
807 static inline uint16_t
808 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
812 static uint16_t ip_pkt_types_map[16] = {
813 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
814 PKT_RX_IPV6_HDR, 0, 0, 0,
815 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
816 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
819 static uint16_t ip_rss_types_map[16] = {
820 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
821 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
822 PKT_RX_RSS_HASH, 0, 0, 0,
823 0, 0, 0, PKT_RX_FDIR,
826 #ifdef RTE_LIBRTE_IEEE1588
827 static uint32_t ip_pkt_etqf_map[8] = {
828 0, 0, 0, PKT_RX_IEEE1588_PTP,
832 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
833 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
834 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
836 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
837 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
840 return (uint16_t)(pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF]);
843 static inline uint16_t
844 rx_desc_status_to_pkt_flags(uint32_t rx_status)
849 * Check if VLAN present only.
850 * Do not check whether L3/L4 rx checksum done by NIC or not,
851 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
853 pkt_flags = (uint16_t)((rx_status & IXGBE_RXD_STAT_VP) ?
854 PKT_RX_VLAN_PKT : 0);
856 #ifdef RTE_LIBRTE_IEEE1588
857 if (rx_status & IXGBE_RXD_STAT_TMST)
858 pkt_flags = (uint16_t)(pkt_flags | PKT_RX_IEEE1588_TMST);
863 static inline uint16_t
864 rx_desc_error_to_pkt_flags(uint32_t rx_status)
867 * Bit 31: IPE, IPv4 checksum error
868 * Bit 30: L4I, L4I integrity error
870 static uint16_t error_to_pkt_flags_map[4] = {
871 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
872 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
874 return error_to_pkt_flags_map[(rx_status >>
875 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
878 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
880 * LOOK_AHEAD defines how many desc statuses to check beyond the
881 * current descriptor.
882 * It must be a pound define for optimal performance.
883 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
884 * function only works with LOOK_AHEAD=8.
887 #if (LOOK_AHEAD != 8)
888 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
891 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
893 volatile union ixgbe_adv_rx_desc *rxdp;
894 struct igb_rx_entry *rxep;
897 int s[LOOK_AHEAD], nb_dd;
901 /* get references to current descriptor and S/W ring entry */
902 rxdp = &rxq->rx_ring[rxq->rx_tail];
903 rxep = &rxq->sw_ring[rxq->rx_tail];
905 /* check to make sure there is at least 1 packet to receive */
906 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
910 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
911 * reference packets that are ready to be received.
913 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
914 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
916 /* Read desc statuses backwards to avoid race condition */
917 for (j = LOOK_AHEAD-1; j >= 0; --j)
918 s[j] = rxdp[j].wb.upper.status_error;
920 /* Compute how many status bits were set */
922 for (j = 0; j < LOOK_AHEAD; ++j)
923 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
927 /* Translate descriptor info to mbuf format */
928 for (j = 0; j < nb_dd; ++j) {
930 pkt_len = (uint16_t)(rxdp[j].wb.upper.length -
932 mb->pkt.data_len = pkt_len;
933 mb->pkt.pkt_len = pkt_len;
934 mb->pkt.vlan_macip.f.vlan_tci = rxdp[j].wb.upper.vlan;
935 mb->pkt.hash.rss = rxdp[j].wb.lower.hi_dword.rss;
937 /* convert descriptor fields to rte mbuf flags */
938 mb->ol_flags = rx_desc_hlen_type_rss_to_pkt_flags(
939 rxdp[j].wb.lower.lo_dword.data);
940 /* reuse status field from scan list */
941 mb->ol_flags = (uint16_t)(mb->ol_flags |
942 rx_desc_status_to_pkt_flags(s[j]));
943 mb->ol_flags = (uint16_t)(mb->ol_flags |
944 rx_desc_error_to_pkt_flags(s[j]));
947 /* Move mbuf pointers from the S/W ring to the stage */
948 for (j = 0; j < LOOK_AHEAD; ++j) {
949 rxq->rx_stage[i + j] = rxep[j].mbuf;
952 /* stop if all requested packets could not be received */
953 if (nb_dd != LOOK_AHEAD)
957 /* clear software ring entries so we can cleanup correctly */
958 for (i = 0; i < nb_rx; ++i) {
959 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
967 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
969 volatile union ixgbe_adv_rx_desc *rxdp;
970 struct igb_rx_entry *rxep;
976 /* allocate buffers in bulk directly into the S/W ring */
977 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
978 (rxq->rx_free_thresh - 1));
979 rxep = &rxq->sw_ring[alloc_idx];
980 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
981 rxq->rx_free_thresh);
982 if (unlikely(diag != 0))
985 rxdp = &rxq->rx_ring[alloc_idx];
986 for (i = 0; i < rxq->rx_free_thresh; ++i) {
987 /* populate the static rte mbuf fields */
989 rte_mbuf_refcnt_set(mb, 1);
990 mb->type = RTE_MBUF_PKT;
992 mb->pkt.data = (char *)mb->buf_addr + RTE_PKTMBUF_HEADROOM;
994 mb->pkt.in_port = rxq->port_id;
996 /* populate the descriptors */
997 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
998 rxdp[i].read.hdr_addr = dma_addr;
999 rxdp[i].read.pkt_addr = dma_addr;
1002 /* update tail pointer */
1004 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1006 /* update state of internal queue structure */
1007 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1008 rxq->rx_free_thresh);
1009 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1010 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1016 static inline uint16_t
1017 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1020 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1023 /* how many packets are ready to return? */
1024 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1026 /* copy mbuf pointers to the application's packet list */
1027 for (i = 0; i < nb_pkts; ++i)
1028 rx_pkts[i] = stage[i];
1030 /* update internal queue state */
1031 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1032 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1037 static inline uint16_t
1038 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1041 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1044 /* Any previously recv'd pkts will be returned from the Rx stage */
1045 if (rxq->rx_nb_avail)
1046 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1048 /* Scan the H/W ring for packets to receive */
1049 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1051 /* update internal queue state */
1052 rxq->rx_next_avail = 0;
1053 rxq->rx_nb_avail = nb_rx;
1054 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1056 /* if required, allocate new buffers to replenish descriptors */
1057 if (rxq->rx_tail > rxq->rx_free_trigger) {
1058 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1060 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1061 "queue_id=%u\n", (unsigned) rxq->port_id,
1062 (unsigned) rxq->queue_id);
1064 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1065 rxq->rx_free_thresh;
1068 * Need to rewind any previous receives if we cannot
1069 * allocate new buffers to replenish the old ones.
1071 rxq->rx_nb_avail = 0;
1072 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1073 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1074 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1080 if (rxq->rx_tail >= rxq->nb_rx_desc)
1083 /* received any packets this loop? */
1084 if (rxq->rx_nb_avail)
1085 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1090 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1092 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1097 if (unlikely(nb_pkts == 0))
1100 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1101 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1103 /* request is relatively large, chunk it up */
1107 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1108 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1109 nb_rx = (uint16_t)(nb_rx + ret);
1110 nb_pkts = (uint16_t)(nb_pkts - ret);
1117 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1120 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1123 struct igb_rx_queue *rxq;
1124 volatile union ixgbe_adv_rx_desc *rx_ring;
1125 volatile union ixgbe_adv_rx_desc *rxdp;
1126 struct igb_rx_entry *sw_ring;
1127 struct igb_rx_entry *rxe;
1128 struct rte_mbuf *rxm;
1129 struct rte_mbuf *nmb;
1130 union ixgbe_adv_rx_desc rxd;
1133 uint32_t hlen_type_rss;
1143 rx_id = rxq->rx_tail;
1144 rx_ring = rxq->rx_ring;
1145 sw_ring = rxq->sw_ring;
1146 while (nb_rx < nb_pkts) {
1148 * The order of operations here is important as the DD status
1149 * bit must not be read after any other descriptor fields.
1150 * rx_ring and rxdp are pointing to volatile data so the order
1151 * of accesses cannot be reordered by the compiler. If they were
1152 * not volatile, they could be reordered which could lead to
1153 * using invalid descriptor fields when read from rxd.
1155 rxdp = &rx_ring[rx_id];
1156 staterr = rxdp->wb.upper.status_error;
1157 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1164 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1165 * is likely to be invalid and to be dropped by the various
1166 * validation checks performed by the network stack.
1168 * Allocate a new mbuf to replenish the RX ring descriptor.
1169 * If the allocation fails:
1170 * - arrange for that RX descriptor to be the first one
1171 * being parsed the next time the receive function is
1172 * invoked [on the same queue].
1174 * - Stop parsing the RX ring and return immediately.
1176 * This policy do not drop the packet received in the RX
1177 * descriptor for which the allocation of a new mbuf failed.
1178 * Thus, it allows that packet to be later retrieved if
1179 * mbuf have been freed in the mean time.
1180 * As a side effect, holding RX descriptors instead of
1181 * systematically giving them back to the NIC may lead to
1182 * RX ring exhaustion situations.
1183 * However, the NIC can gracefully prevent such situations
1184 * to happen by sending specific "back-pressure" flow control
1185 * frames to its peer(s).
1187 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1188 "ext_err_stat=0x%08x pkt_len=%u\n",
1189 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1190 (unsigned) rx_id, (unsigned) staterr,
1191 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1193 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1195 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1196 "queue_id=%u\n", (unsigned) rxq->port_id,
1197 (unsigned) rxq->queue_id);
1198 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1203 rxe = &sw_ring[rx_id];
1205 if (rx_id == rxq->nb_rx_desc)
1208 /* Prefetch next mbuf while processing current one. */
1209 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1212 * When next RX descriptor is on a cache-line boundary,
1213 * prefetch the next 4 RX descriptors and the next 8 pointers
1216 if ((rx_id & 0x3) == 0) {
1217 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1218 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1224 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1225 rxdp->read.hdr_addr = dma_addr;
1226 rxdp->read.pkt_addr = dma_addr;
1229 * Initialize the returned mbuf.
1230 * 1) setup generic mbuf fields:
1231 * - number of segments,
1234 * - RX port identifier.
1235 * 2) integrate hardware offload data, if any:
1236 * - RSS flag & hash,
1237 * - IP checksum flag,
1238 * - VLAN TCI, if any,
1241 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1243 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1244 rte_packet_prefetch(rxm->pkt.data);
1245 rxm->pkt.nb_segs = 1;
1246 rxm->pkt.next = NULL;
1247 rxm->pkt.pkt_len = pkt_len;
1248 rxm->pkt.data_len = pkt_len;
1249 rxm->pkt.in_port = rxq->port_id;
1251 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1252 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1253 rxm->pkt.vlan_macip.f.vlan_tci =
1254 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1256 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1257 pkt_flags = (uint16_t)(pkt_flags |
1258 rx_desc_status_to_pkt_flags(staterr));
1259 pkt_flags = (uint16_t)(pkt_flags |
1260 rx_desc_error_to_pkt_flags(staterr));
1261 rxm->ol_flags = pkt_flags;
1263 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1264 rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1265 else if (pkt_flags & PKT_RX_FDIR) {
1266 rxm->pkt.hash.fdir.hash =
1267 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1268 & IXGBE_ATR_HASH_MASK);
1269 rxm->pkt.hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1272 * Store the mbuf address into the next entry of the array
1273 * of returned packets.
1275 rx_pkts[nb_rx++] = rxm;
1277 rxq->rx_tail = rx_id;
1280 * If the number of free RX descriptors is greater than the RX free
1281 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1283 * Update the RDT with the value of the last processed RX descriptor
1284 * minus 1, to guarantee that the RDT register is never equal to the
1285 * RDH register, which creates a "full" ring situtation from the
1286 * hardware point of view...
1288 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1289 if (nb_hold > rxq->rx_free_thresh) {
1290 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1291 "nb_hold=%u nb_rx=%u\n",
1292 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1293 (unsigned) rx_id, (unsigned) nb_hold,
1295 rx_id = (uint16_t) ((rx_id == 0) ?
1296 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1297 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1300 rxq->nb_rx_hold = nb_hold;
1305 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1308 struct igb_rx_queue *rxq;
1309 volatile union ixgbe_adv_rx_desc *rx_ring;
1310 volatile union ixgbe_adv_rx_desc *rxdp;
1311 struct igb_rx_entry *sw_ring;
1312 struct igb_rx_entry *rxe;
1313 struct rte_mbuf *first_seg;
1314 struct rte_mbuf *last_seg;
1315 struct rte_mbuf *rxm;
1316 struct rte_mbuf *nmb;
1317 union ixgbe_adv_rx_desc rxd;
1318 uint64_t dma; /* Physical address of mbuf data buffer */
1320 uint32_t hlen_type_rss;
1330 rx_id = rxq->rx_tail;
1331 rx_ring = rxq->rx_ring;
1332 sw_ring = rxq->sw_ring;
1335 * Retrieve RX context of current packet, if any.
1337 first_seg = rxq->pkt_first_seg;
1338 last_seg = rxq->pkt_last_seg;
1340 while (nb_rx < nb_pkts) {
1343 * The order of operations here is important as the DD status
1344 * bit must not be read after any other descriptor fields.
1345 * rx_ring and rxdp are pointing to volatile data so the order
1346 * of accesses cannot be reordered by the compiler. If they were
1347 * not volatile, they could be reordered which could lead to
1348 * using invalid descriptor fields when read from rxd.
1350 rxdp = &rx_ring[rx_id];
1351 staterr = rxdp->wb.upper.status_error;
1352 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1359 * Allocate a new mbuf to replenish the RX ring descriptor.
1360 * If the allocation fails:
1361 * - arrange for that RX descriptor to be the first one
1362 * being parsed the next time the receive function is
1363 * invoked [on the same queue].
1365 * - Stop parsing the RX ring and return immediately.
1367 * This policy does not drop the packet received in the RX
1368 * descriptor for which the allocation of a new mbuf failed.
1369 * Thus, it allows that packet to be later retrieved if
1370 * mbuf have been freed in the mean time.
1371 * As a side effect, holding RX descriptors instead of
1372 * systematically giving them back to the NIC may lead to
1373 * RX ring exhaustion situations.
1374 * However, the NIC can gracefully prevent such situations
1375 * to happen by sending specific "back-pressure" flow control
1376 * frames to its peer(s).
1378 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
1379 "staterr=0x%x data_len=%u\n",
1380 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1381 (unsigned) rx_id, (unsigned) staterr,
1382 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1384 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1386 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1387 "queue_id=%u\n", (unsigned) rxq->port_id,
1388 (unsigned) rxq->queue_id);
1389 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1394 rxe = &sw_ring[rx_id];
1396 if (rx_id == rxq->nb_rx_desc)
1399 /* Prefetch next mbuf while processing current one. */
1400 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1403 * When next RX descriptor is on a cache-line boundary,
1404 * prefetch the next 4 RX descriptors and the next 8 pointers
1407 if ((rx_id & 0x3) == 0) {
1408 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1409 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1413 * Update RX descriptor with the physical address of the new
1414 * data buffer of the new allocated mbuf.
1418 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1419 rxdp->read.hdr_addr = dma;
1420 rxdp->read.pkt_addr = dma;
1423 * Set data length & data buffer address of mbuf.
1425 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1426 rxm->pkt.data_len = data_len;
1427 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1430 * If this is the first buffer of the received packet,
1431 * set the pointer to the first mbuf of the packet and
1432 * initialize its context.
1433 * Otherwise, update the total length and the number of segments
1434 * of the current scattered packet, and update the pointer to
1435 * the last mbuf of the current packet.
1437 if (first_seg == NULL) {
1439 first_seg->pkt.pkt_len = data_len;
1440 first_seg->pkt.nb_segs = 1;
1442 first_seg->pkt.pkt_len = (uint16_t)(first_seg->pkt.pkt_len
1444 first_seg->pkt.nb_segs++;
1445 last_seg->pkt.next = rxm;
1449 * If this is not the last buffer of the received packet,
1450 * update the pointer to the last mbuf of the current scattered
1451 * packet and continue to parse the RX ring.
1453 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1459 * This is the last buffer of the received packet.
1460 * If the CRC is not stripped by the hardware:
1461 * - Subtract the CRC length from the total packet length.
1462 * - If the last buffer only contains the whole CRC or a part
1463 * of it, free the mbuf associated to the last buffer.
1464 * If part of the CRC is also contained in the previous
1465 * mbuf, subtract the length of that CRC part from the
1466 * data length of the previous mbuf.
1468 rxm->pkt.next = NULL;
1469 if (unlikely(rxq->crc_len > 0)) {
1470 first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
1471 if (data_len <= ETHER_CRC_LEN) {
1472 rte_pktmbuf_free_seg(rxm);
1473 first_seg->pkt.nb_segs--;
1474 last_seg->pkt.data_len = (uint16_t)
1475 (last_seg->pkt.data_len -
1476 (ETHER_CRC_LEN - data_len));
1477 last_seg->pkt.next = NULL;
1480 (uint16_t) (data_len - ETHER_CRC_LEN);
1484 * Initialize the first mbuf of the returned packet:
1485 * - RX port identifier,
1486 * - hardware offload data, if any:
1487 * - RSS flag & hash,
1488 * - IP checksum flag,
1489 * - VLAN TCI, if any,
1492 first_seg->pkt.in_port = rxq->port_id;
1495 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1496 * set in the pkt_flags field.
1498 first_seg->pkt.vlan_macip.f.vlan_tci =
1499 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1500 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1501 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1502 pkt_flags = (uint16_t)(pkt_flags |
1503 rx_desc_status_to_pkt_flags(staterr));
1504 pkt_flags = (uint16_t)(pkt_flags |
1505 rx_desc_error_to_pkt_flags(staterr));
1506 first_seg->ol_flags = pkt_flags;
1508 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1509 first_seg->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1510 else if (pkt_flags & PKT_RX_FDIR) {
1511 first_seg->pkt.hash.fdir.hash =
1512 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1513 & IXGBE_ATR_HASH_MASK);
1514 first_seg->pkt.hash.fdir.id =
1515 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1518 /* Prefetch data of first segment, if configured to do so. */
1519 rte_packet_prefetch(first_seg->pkt.data);
1522 * Store the mbuf address into the next entry of the array
1523 * of returned packets.
1525 rx_pkts[nb_rx++] = first_seg;
1528 * Setup receipt context for a new packet.
1534 * Record index of the next RX descriptor to probe.
1536 rxq->rx_tail = rx_id;
1539 * Save receive context.
1541 rxq->pkt_first_seg = first_seg;
1542 rxq->pkt_last_seg = last_seg;
1545 * If the number of free RX descriptors is greater than the RX free
1546 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1548 * Update the RDT with the value of the last processed RX descriptor
1549 * minus 1, to guarantee that the RDT register is never equal to the
1550 * RDH register, which creates a "full" ring situtation from the
1551 * hardware point of view...
1553 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1554 if (nb_hold > rxq->rx_free_thresh) {
1555 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1556 "nb_hold=%u nb_rx=%u\n",
1557 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1558 (unsigned) rx_id, (unsigned) nb_hold,
1560 rx_id = (uint16_t) ((rx_id == 0) ?
1561 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1562 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1565 rxq->nb_rx_hold = nb_hold;
1569 /*********************************************************************
1571 * Queue management functions
1573 **********************************************************************/
1576 * Rings setup and release.
1578 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1579 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1580 * also optimize cache line size effect. H/W supports up to cache line size 128.
1582 #define IXGBE_ALIGN 128
1585 * Maximum number of Ring Descriptors.
1587 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1588 * descriptors should meet the following condition:
1589 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1591 #define IXGBE_MIN_RING_DESC 32
1592 #define IXGBE_MAX_RING_DESC 4096
1595 * Create memzone for HW rings. malloc can't be used as the physical address is
1596 * needed. If the memzone is already created, then this function returns a ptr
1599 static const struct rte_memzone *
1600 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1601 uint16_t queue_id, uint32_t ring_size, int socket_id)
1603 char z_name[RTE_MEMZONE_NAMESIZE];
1604 const struct rte_memzone *mz;
1606 rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1607 dev->driver->pci_drv.name, ring_name,
1608 dev->data->port_id, queue_id);
1610 mz = rte_memzone_lookup(z_name);
1614 #ifdef RTE_LIBRTE_XEN_DOM0
1615 return rte_memzone_reserve_bounded(z_name, ring_size,
1616 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1618 return rte_memzone_reserve_aligned(z_name, ring_size,
1619 socket_id, 0, IXGBE_ALIGN);
1624 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1628 if (txq->sw_ring != NULL) {
1629 for (i = 0; i < txq->nb_tx_desc; i++) {
1630 if (txq->sw_ring[i].mbuf != NULL) {
1631 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1632 txq->sw_ring[i].mbuf = NULL;
1639 ixgbe_tx_free_swring(struct igb_tx_queue *txq)
1642 txq->sw_ring != NULL)
1643 rte_free(txq->sw_ring);
1647 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1649 if (txq != NULL && txq->ops != NULL) {
1650 txq->ops->release_mbufs(txq);
1651 txq->ops->free_swring(txq);
1657 ixgbe_dev_tx_queue_release(void *txq)
1659 ixgbe_tx_queue_release(txq);
1662 /* (Re)set dynamic igb_tx_queue fields to defaults */
1664 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1666 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1668 struct igb_tx_entry *txe = txq->sw_ring;
1671 /* Zero out HW ring memory */
1672 for (i = 0; i < txq->nb_tx_desc; i++) {
1673 txq->tx_ring[i] = zeroed_desc;
1676 /* Initialize SW ring entries */
1677 prev = (uint16_t) (txq->nb_tx_desc - 1);
1678 for (i = 0; i < txq->nb_tx_desc; i++) {
1679 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1680 txd->wb.status = IXGBE_TXD_STAT_DD;
1683 txe[prev].next_id = i;
1687 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1688 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1691 txq->nb_tx_used = 0;
1693 * Always allow 1 descriptor to be un-allocated to avoid
1694 * a H/W race condition
1696 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1697 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1699 memset((void*)&txq->ctx_cache, 0,
1700 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1703 static struct ixgbe_txq_ops def_txq_ops = {
1704 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1705 .free_swring = ixgbe_tx_free_swring,
1706 .reset = ixgbe_reset_tx_queue,
1710 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1713 unsigned int socket_id,
1714 const struct rte_eth_txconf *tx_conf)
1716 const struct rte_memzone *tz;
1717 struct igb_tx_queue *txq;
1718 struct ixgbe_hw *hw;
1719 uint16_t tx_rs_thresh, tx_free_thresh;
1721 PMD_INIT_FUNC_TRACE();
1722 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1725 * Validate number of transmit descriptors.
1726 * It must not exceed hardware maximum, and must be multiple
1729 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1730 (nb_desc > IXGBE_MAX_RING_DESC) ||
1731 (nb_desc < IXGBE_MIN_RING_DESC)) {
1736 * The following two parameters control the setting of the RS bit on
1737 * transmit descriptors.
1738 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1739 * descriptors have been used.
1740 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1741 * descriptors are used or if the number of descriptors required
1742 * to transmit a packet is greater than the number of free TX
1744 * The following constraints must be satisfied:
1745 * tx_rs_thresh must be greater than 0.
1746 * tx_rs_thresh must be less than the size of the ring minus 2.
1747 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1748 * tx_rs_thresh must be a divisor of the ring size.
1749 * tx_free_thresh must be greater than 0.
1750 * tx_free_thresh must be less than the size of the ring minus 3.
1751 * One descriptor in the TX ring is used as a sentinel to avoid a
1752 * H/W race condition, hence the maximum threshold constraints.
1753 * When set to zero use default values.
1755 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1756 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1757 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1758 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1759 if (tx_rs_thresh >= (nb_desc - 2)) {
1760 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the number "
1761 "of TX descriptors minus 2. (tx_rs_thresh=%u port=%d "
1762 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1763 (int)dev->data->port_id, (int)queue_idx);
1766 if (tx_free_thresh >= (nb_desc - 3)) {
1767 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the "
1768 "tx_free_thresh must be less than the number of TX "
1769 "descriptors minus 3. (tx_free_thresh=%u port=%d "
1770 "queue=%d)\n", (unsigned int)tx_free_thresh,
1771 (int)dev->data->port_id, (int)queue_idx);
1774 if (tx_rs_thresh > tx_free_thresh) {
1775 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than or equal to "
1776 "tx_free_thresh. (tx_free_thresh=%u tx_rs_thresh=%u "
1777 "port=%d queue=%d)\n", (unsigned int)tx_free_thresh,
1778 (unsigned int)tx_rs_thresh, (int)dev->data->port_id,
1782 if ((nb_desc % tx_rs_thresh) != 0) {
1783 RTE_LOG(ERR, PMD, "tx_rs_thresh must be a divisor of the "
1784 "number of TX descriptors. (tx_rs_thresh=%u port=%d "
1785 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1786 (int)dev->data->port_id, (int)queue_idx);
1791 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1792 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1793 * by the NIC and all descriptors are written back after the NIC
1794 * accumulates WTHRESH descriptors.
1796 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1797 RTE_LOG(ERR, PMD, "TX WTHRESH must be set to 0 if "
1798 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1799 "port=%d queue=%d)\n", (unsigned int)tx_rs_thresh,
1800 (int)dev->data->port_id, (int)queue_idx);
1804 /* Free memory prior to re-allocation if needed... */
1805 if (dev->data->tx_queues[queue_idx] != NULL) {
1806 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1807 dev->data->tx_queues[queue_idx] = NULL;
1810 /* First allocate the tx queue data structure */
1811 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1812 CACHE_LINE_SIZE, socket_id);
1817 * Allocate TX ring hardware descriptors. A memzone large enough to
1818 * handle the maximum ring size is allocated in order to allow for
1819 * resizing in later calls to the queue setup function.
1821 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1822 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1825 ixgbe_tx_queue_release(txq);
1829 txq->nb_tx_desc = nb_desc;
1830 txq->tx_rs_thresh = tx_rs_thresh;
1831 txq->tx_free_thresh = tx_free_thresh;
1832 txq->pthresh = tx_conf->tx_thresh.pthresh;
1833 txq->hthresh = tx_conf->tx_thresh.hthresh;
1834 txq->wthresh = tx_conf->tx_thresh.wthresh;
1835 txq->queue_id = queue_idx;
1836 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1837 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1838 txq->port_id = dev->data->port_id;
1839 txq->txq_flags = tx_conf->txq_flags;
1840 txq->ops = &def_txq_ops;
1841 txq->start_tx_per_q = tx_conf->start_tx_per_q;
1844 * Modification to set VFTDT for virtual function if vf is detected
1846 if (hw->mac.type == ixgbe_mac_82599_vf)
1847 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1849 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1850 #ifndef RTE_LIBRTE_XEN_DOM0
1851 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1853 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1855 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1857 /* Allocate software ring */
1858 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1859 sizeof(struct igb_tx_entry) * nb_desc,
1860 CACHE_LINE_SIZE, socket_id);
1861 if (txq->sw_ring == NULL) {
1862 ixgbe_tx_queue_release(txq);
1865 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1866 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1868 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1869 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
1870 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1871 PMD_INIT_LOG(INFO, "Using simple tx code path\n");
1872 #ifdef RTE_IXGBE_INC_VECTOR
1873 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1874 ixgbe_txq_vec_setup(txq, socket_id) == 0) {
1875 PMD_INIT_LOG(INFO, "Vector tx enabled.\n");
1876 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1880 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1882 PMD_INIT_LOG(INFO, "Using full-featured tx code path\n");
1883 PMD_INIT_LOG(INFO, " - txq_flags = %lx [IXGBE_SIMPLE_FLAGS=%lx]\n", (long unsigned)txq->txq_flags, (long unsigned)IXGBE_SIMPLE_FLAGS);
1884 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu [RTE_PMD_IXGBE_TX_MAX_BURST=%lu]\n", (long unsigned)txq->tx_rs_thresh, (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
1885 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1888 txq->ops->reset(txq);
1890 dev->data->tx_queues[queue_idx] = txq;
1897 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1901 if (rxq->sw_ring != NULL) {
1902 for (i = 0; i < rxq->nb_rx_desc; i++) {
1903 if (rxq->sw_ring[i].mbuf != NULL) {
1904 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1905 rxq->sw_ring[i].mbuf = NULL;
1908 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1909 if (rxq->rx_nb_avail) {
1910 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1911 struct rte_mbuf *mb;
1912 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1913 rte_pktmbuf_free_seg(mb);
1915 rxq->rx_nb_avail = 0;
1922 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
1925 ixgbe_rx_queue_release_mbufs(rxq);
1926 rte_free(rxq->sw_ring);
1932 ixgbe_dev_rx_queue_release(void *rxq)
1934 ixgbe_rx_queue_release(rxq);
1938 * Check if Rx Burst Bulk Alloc function can be used.
1940 * 0: the preconditions are satisfied and the bulk allocation function
1942 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
1943 * function must be used.
1946 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1947 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
1949 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
1955 * Make sure the following pre-conditions are satisfied:
1956 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
1957 * rxq->rx_free_thresh < rxq->nb_rx_desc
1958 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
1959 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
1960 * Scattered packets are not supported. This should be checked
1961 * outside of this function.
1963 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1964 if (! (rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST))
1966 else if (! (rxq->rx_free_thresh < rxq->nb_rx_desc))
1968 else if (! ((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0))
1970 else if (! (rxq->nb_rx_desc <
1971 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST)))
1980 /* Reset dynamic igb_rx_queue fields back to defaults */
1982 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
1984 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
1990 * By default, the Rx queue setup function allocates enough memory for
1991 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
1992 * extra memory at the end of the descriptor ring to be zero'd out. A
1993 * pre-condition for using the Rx burst bulk alloc function is that the
1994 * number of descriptors is less than or equal to
1995 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
1996 * constraints here to see if we need to zero out memory after the end
1997 * of the H/W descriptor ring.
1999 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2000 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2001 /* zero out extra memory */
2002 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2005 /* do not zero out extra memory */
2006 len = rxq->nb_rx_desc;
2009 * Zero out HW ring memory. Zero out extra memory at the end of
2010 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2011 * reads extra memory as zeros.
2013 for (i = 0; i < len; i++) {
2014 rxq->rx_ring[i] = zeroed_desc;
2017 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2019 * initialize extra software ring entries. Space for these extra
2020 * entries is always allocated
2022 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2023 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2024 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2027 rxq->rx_nb_avail = 0;
2028 rxq->rx_next_avail = 0;
2029 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2030 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2032 rxq->nb_rx_hold = 0;
2033 rxq->pkt_first_seg = NULL;
2034 rxq->pkt_last_seg = NULL;
2038 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2041 unsigned int socket_id,
2042 const struct rte_eth_rxconf *rx_conf,
2043 struct rte_mempool *mp)
2045 const struct rte_memzone *rz;
2046 struct igb_rx_queue *rxq;
2047 struct ixgbe_hw *hw;
2048 int use_def_burst_func = 1;
2051 PMD_INIT_FUNC_TRACE();
2052 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055 * Validate number of receive descriptors.
2056 * It must not exceed hardware maximum, and must be multiple
2059 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2060 (nb_desc > IXGBE_MAX_RING_DESC) ||
2061 (nb_desc < IXGBE_MIN_RING_DESC)) {
2065 /* Free memory prior to re-allocation if needed... */
2066 if (dev->data->rx_queues[queue_idx] != NULL) {
2067 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2068 dev->data->rx_queues[queue_idx] = NULL;
2071 /* First allocate the rx queue data structure */
2072 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2073 CACHE_LINE_SIZE, socket_id);
2077 rxq->nb_rx_desc = nb_desc;
2078 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2079 rxq->queue_id = queue_idx;
2080 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2081 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2082 rxq->port_id = dev->data->port_id;
2083 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2085 rxq->drop_en = rx_conf->rx_drop_en;
2086 rxq->start_rx_per_q = rx_conf->start_rx_per_q;
2089 * Allocate RX ring hardware descriptors. A memzone large enough to
2090 * handle the maximum ring size is allocated in order to allow for
2091 * resizing in later calls to the queue setup function.
2093 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2094 RX_RING_SZ, socket_id);
2096 ixgbe_rx_queue_release(rxq);
2101 * Zero init all the descriptors in the ring.
2103 memset (rz->addr, 0, RX_RING_SZ);
2106 * Modified to setup VFRDT for Virtual Function
2108 if (hw->mac.type == ixgbe_mac_82599_vf) {
2110 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2112 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2116 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2118 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2120 #ifndef RTE_LIBRTE_XEN_DOM0
2121 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2123 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2125 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2128 * Allocate software ring. Allow for space at the end of the
2129 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2130 * function does not access an invalid memory region.
2132 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2133 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2137 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2138 sizeof(struct igb_rx_entry) * len,
2139 CACHE_LINE_SIZE, socket_id);
2140 if (rxq->sw_ring == NULL) {
2141 ixgbe_rx_queue_release(rxq);
2144 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
2145 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2148 * Certain constraints must be met in order to use the bulk buffer
2149 * allocation Rx burst function.
2151 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2153 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2154 if (!use_def_burst_func && !dev->data->scattered_rx) {
2155 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2156 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2157 "satisfied. Rx Burst Bulk Alloc function will be "
2158 "used on port=%d, queue=%d.\n",
2159 rxq->port_id, rxq->queue_id);
2160 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2161 #ifdef RTE_IXGBE_INC_VECTOR
2162 if (!ixgbe_rx_vec_condition_check(dev)) {
2163 PMD_INIT_LOG(INFO, "Vector rx enabled.\n");
2164 ixgbe_rxq_vec_setup(rxq, socket_id);
2165 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
2170 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2171 "are not satisfied, Scattered Rx is requested, "
2172 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2173 "enabled (port=%d, queue=%d).\n",
2174 rxq->port_id, rxq->queue_id);
2176 dev->data->rx_queues[queue_idx] = rxq;
2178 ixgbe_reset_rx_queue(rxq);
2184 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2186 #define IXGBE_RXQ_SCAN_INTERVAL 4
2187 volatile union ixgbe_adv_rx_desc *rxdp;
2188 struct igb_rx_queue *rxq;
2191 if (rx_queue_id >= dev->data->nb_rx_queues) {
2192 PMD_RX_LOG(ERR, "Invalid RX queue id=%d\n", rx_queue_id);
2196 rxq = dev->data->rx_queues[rx_queue_id];
2197 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2199 while ((desc < rxq->nb_rx_desc) &&
2200 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2201 desc += IXGBE_RXQ_SCAN_INTERVAL;
2202 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2203 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2204 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2205 desc - rxq->nb_rx_desc]);
2212 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2214 volatile union ixgbe_adv_rx_desc *rxdp;
2215 struct igb_rx_queue *rxq = rx_queue;
2218 if (unlikely(offset >= rxq->nb_rx_desc))
2220 desc = rxq->rx_tail + offset;
2221 if (desc >= rxq->nb_rx_desc)
2222 desc -= rxq->nb_rx_desc;
2224 rxdp = &rxq->rx_ring[desc];
2225 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2229 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2233 PMD_INIT_FUNC_TRACE();
2235 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2236 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2238 txq->ops->release_mbufs(txq);
2239 txq->ops->reset(txq);
2243 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2244 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2246 ixgbe_rx_queue_release_mbufs(rxq);
2247 ixgbe_reset_rx_queue(rxq);
2252 /*********************************************************************
2254 * Device RX/TX init functions
2256 **********************************************************************/
2259 * Receive Side Scaling (RSS)
2260 * See section 7.1.2.8 in the following document:
2261 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2264 * The source and destination IP addresses of the IP header and the source
2265 * and destination ports of TCP/UDP headers, if any, of received packets are
2266 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2267 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2268 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2269 * RSS output index which is used as the RX queue index where to store the
2271 * The following output is supplied in the RX write-back descriptor:
2272 * - 32-bit result of the Microsoft RSS hash function,
2273 * - 4-bit RSS type field.
2277 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2278 * Used as the default key.
2280 static uint8_t rss_intel_key[40] = {
2281 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2282 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2283 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2284 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2285 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2289 ixgbe_rss_disable(struct rte_eth_dev *dev)
2291 struct ixgbe_hw *hw;
2294 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2295 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2296 mrqc &= ~IXGBE_MRQC_RSSEN;
2297 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2301 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2309 hash_key = rss_conf->rss_key;
2310 if (hash_key != NULL) {
2311 /* Fill in RSS hash key */
2312 for (i = 0; i < 10; i++) {
2313 rss_key = hash_key[(i * 4)];
2314 rss_key |= hash_key[(i * 4) + 1] << 8;
2315 rss_key |= hash_key[(i * 4) + 2] << 16;
2316 rss_key |= hash_key[(i * 4) + 3] << 24;
2317 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2321 /* Set configured hashing protocols in MRQC register */
2322 rss_hf = rss_conf->rss_hf;
2323 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2324 if (rss_hf & ETH_RSS_IPV4)
2325 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2326 if (rss_hf & ETH_RSS_IPV4_TCP)
2327 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2328 if (rss_hf & ETH_RSS_IPV6)
2329 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2330 if (rss_hf & ETH_RSS_IPV6_EX)
2331 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2332 if (rss_hf & ETH_RSS_IPV6_TCP)
2333 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2334 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2335 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2336 if (rss_hf & ETH_RSS_IPV4_UDP)
2337 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2338 if (rss_hf & ETH_RSS_IPV6_UDP)
2339 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2340 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2341 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2342 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2346 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2347 struct rte_eth_rss_conf *rss_conf)
2349 struct ixgbe_hw *hw;
2353 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2356 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2357 * "RSS enabling cannot be done dynamically while it must be
2358 * preceded by a software reset"
2359 * Before changing anything, first check that the update RSS operation
2360 * does not attempt to disable RSS, if RSS was enabled at
2361 * initialization time, or does not attempt to enable RSS, if RSS was
2362 * disabled at initialization time.
2364 rss_hf = rss_conf->rss_hf;
2365 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2366 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2367 if (rss_hf != 0) /* Enable RSS */
2369 return 0; /* Nothing to do */
2372 if (rss_hf == 0) /* Disable RSS */
2374 ixgbe_hw_rss_hash_set(hw, rss_conf);
2379 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2380 struct rte_eth_rss_conf *rss_conf)
2382 struct ixgbe_hw *hw;
2389 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2390 hash_key = rss_conf->rss_key;
2391 if (hash_key != NULL) {
2392 /* Return RSS hash key */
2393 for (i = 0; i < 10; i++) {
2394 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2395 hash_key[(i * 4)] = rss_key & 0x000000FF;
2396 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2397 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2398 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2402 /* Get RSS functions configured in MRQC register */
2403 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2404 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2405 rss_conf->rss_hf = 0;
2409 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2410 rss_hf |= ETH_RSS_IPV4;
2411 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2412 rss_hf |= ETH_RSS_IPV4_TCP;
2413 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2414 rss_hf |= ETH_RSS_IPV6;
2415 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2416 rss_hf |= ETH_RSS_IPV6_EX;
2417 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2418 rss_hf |= ETH_RSS_IPV6_TCP;
2419 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2420 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2421 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2422 rss_hf |= ETH_RSS_IPV4_UDP;
2423 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2424 rss_hf |= ETH_RSS_IPV6_UDP;
2425 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2426 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2427 rss_conf->rss_hf = rss_hf;
2432 ixgbe_rss_configure(struct rte_eth_dev *dev)
2434 struct rte_eth_rss_conf rss_conf;
2435 struct ixgbe_hw *hw;
2440 PMD_INIT_FUNC_TRACE();
2441 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2444 * Fill in redirection table
2445 * The byte-swap is needed because NIC registers are in
2446 * little-endian order.
2449 for (i = 0, j = 0; i < 128; i++, j++) {
2450 if (j == dev->data->nb_rx_queues)
2452 reta = (reta << 8) | j;
2454 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2459 * Configure the RSS key and the RSS protocols used to compute
2460 * the RSS hash of input packets.
2462 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2463 if (rss_conf.rss_hf == 0) {
2464 ixgbe_rss_disable(dev);
2467 if (rss_conf.rss_key == NULL)
2468 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2469 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2472 #define NUM_VFTA_REGISTERS 128
2473 #define NIC_RX_BUFFER_SIZE 0x200
2476 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2478 struct rte_eth_vmdq_dcb_conf *cfg;
2479 struct ixgbe_hw *hw;
2480 enum rte_eth_nb_pools num_pools;
2481 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2483 uint8_t nb_tcs; /* number of traffic classes */
2486 PMD_INIT_FUNC_TRACE();
2487 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2488 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2489 num_pools = cfg->nb_queue_pools;
2490 /* Check we have a valid number of pools */
2491 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2492 ixgbe_rss_disable(dev);
2495 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2496 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2500 * split rx buffer up into sections, each for 1 traffic class
2502 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2503 for (i = 0 ; i < nb_tcs; i++) {
2504 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2505 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2506 /* clear 10 bits. */
2507 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2508 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2510 /* zero alloc all unused TCs */
2511 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2512 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2513 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2514 /* clear 10 bits. */
2515 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2518 /* MRQC: enable vmdq and dcb */
2519 mrqc = ((num_pools == ETH_16_POOLS) ? \
2520 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2521 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2523 /* PFVTCTL: turn on virtualisation and set the default pool */
2524 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2525 if (cfg->enable_default_pool) {
2526 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2528 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2531 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2533 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2535 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2537 * mapping is done with 3 bits per priority,
2538 * so shift by i*3 each time
2540 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2542 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2544 /* RTRPCS: DCB related */
2545 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2547 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2548 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2549 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2550 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2552 /* VFTA - enable all vlan filters */
2553 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2554 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2557 /* VFRE: pool enabling for receive - 16 or 32 */
2558 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2559 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2562 * MPSAR - allow pools to read specific mac addresses
2563 * In this case, all pools should be able to read from mac addr 0
2565 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2566 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2568 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2569 for (i = 0; i < cfg->nb_pool_maps; i++) {
2570 /* set vlan id in VF register and set the valid bit */
2571 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2572 (cfg->pool_map[i].vlan_id & 0xFFF)));
2574 * Put the allowed pools in VFB reg. As we only have 16 or 32
2575 * pools, we only need to use the first half of the register
2578 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2583 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2584 * @hw: pointer to hardware structure
2585 * @dcb_config: pointer to ixgbe_dcb_config structure
2588 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2589 struct ixgbe_dcb_config *dcb_config)
2594 PMD_INIT_FUNC_TRACE();
2595 if (hw->mac.type != ixgbe_mac_82598EB) {
2596 /* Disable the Tx desc arbiter so that MTQC can be changed */
2597 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2598 reg |= IXGBE_RTTDCS_ARBDIS;
2599 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2601 /* Enable DCB for Tx with 8 TCs */
2602 if (dcb_config->num_tcs.pg_tcs == 8) {
2603 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2606 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2608 if (dcb_config->vt_mode)
2609 reg |= IXGBE_MTQC_VT_ENA;
2610 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2612 /* Disable drop for all queues */
2613 for (q = 0; q < 128; q++)
2614 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2615 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2617 /* Enable the Tx desc arbiter */
2618 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2619 reg &= ~IXGBE_RTTDCS_ARBDIS;
2620 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2622 /* Enable Security TX Buffer IFG for DCB */
2623 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2624 reg |= IXGBE_SECTX_DCB;
2625 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2631 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2632 * @dev: pointer to rte_eth_dev structure
2633 * @dcb_config: pointer to ixgbe_dcb_config structure
2636 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2637 struct ixgbe_dcb_config *dcb_config)
2639 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2640 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2641 struct ixgbe_hw *hw =
2642 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2644 PMD_INIT_FUNC_TRACE();
2645 if (hw->mac.type != ixgbe_mac_82598EB)
2646 /*PF VF Transmit Enable*/
2647 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2648 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2650 /*Configure general DCB TX parameters*/
2651 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2656 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2657 struct ixgbe_dcb_config *dcb_config)
2659 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2660 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2661 struct ixgbe_dcb_tc_config *tc;
2664 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2665 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2666 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2667 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2670 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2671 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2673 /* User Priority to Traffic Class mapping */
2674 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2675 j = vmdq_rx_conf->dcb_queue[i];
2676 tc = &dcb_config->tc_config[j];
2677 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2683 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2684 struct ixgbe_dcb_config *dcb_config)
2686 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2687 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2688 struct ixgbe_dcb_tc_config *tc;
2691 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2692 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2693 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2694 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2697 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2698 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2701 /* User Priority to Traffic Class mapping */
2702 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2703 j = vmdq_tx_conf->dcb_queue[i];
2704 tc = &dcb_config->tc_config[j];
2705 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2712 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2713 struct ixgbe_dcb_config *dcb_config)
2715 struct rte_eth_dcb_rx_conf *rx_conf =
2716 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2717 struct ixgbe_dcb_tc_config *tc;
2720 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2721 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2723 /* User Priority to Traffic Class mapping */
2724 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2725 j = rx_conf->dcb_queue[i];
2726 tc = &dcb_config->tc_config[j];
2727 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2733 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2734 struct ixgbe_dcb_config *dcb_config)
2736 struct rte_eth_dcb_tx_conf *tx_conf =
2737 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2738 struct ixgbe_dcb_tc_config *tc;
2741 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2742 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2744 /* User Priority to Traffic Class mapping */
2745 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2746 j = tx_conf->dcb_queue[i];
2747 tc = &dcb_config->tc_config[j];
2748 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2754 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2755 * @hw: pointer to hardware structure
2756 * @dcb_config: pointer to ixgbe_dcb_config structure
2759 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2760 struct ixgbe_dcb_config *dcb_config)
2766 PMD_INIT_FUNC_TRACE();
2768 * Disable the arbiter before changing parameters
2769 * (always enable recycle mode; WSP)
2771 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2772 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2774 if (hw->mac.type != ixgbe_mac_82598EB) {
2775 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2776 if (dcb_config->num_tcs.pg_tcs == 4) {
2777 if (dcb_config->vt_mode)
2778 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2779 IXGBE_MRQC_VMDQRT4TCEN;
2781 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2782 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2786 if (dcb_config->num_tcs.pg_tcs == 8) {
2787 if (dcb_config->vt_mode)
2788 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2789 IXGBE_MRQC_VMDQRT8TCEN;
2791 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2792 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2797 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2800 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2801 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2802 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2803 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2805 /* VFTA - enable all vlan filters */
2806 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2807 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2811 * Configure Rx packet plane (recycle mode; WSP) and
2814 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2815 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2821 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2822 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2824 switch (hw->mac.type) {
2825 case ixgbe_mac_82598EB:
2826 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2828 case ixgbe_mac_82599EB:
2829 case ixgbe_mac_X540:
2830 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2839 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2840 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2842 switch (hw->mac.type) {
2843 case ixgbe_mac_82598EB:
2844 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2845 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2847 case ixgbe_mac_82599EB:
2848 case ixgbe_mac_X540:
2849 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2850 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2857 #define DCB_RX_CONFIG 1
2858 #define DCB_TX_CONFIG 1
2859 #define DCB_TX_PB 1024
2861 * ixgbe_dcb_hw_configure - Enable DCB and configure
2862 * general DCB in VT mode and non-VT mode parameters
2863 * @dev: pointer to rte_eth_dev structure
2864 * @dcb_config: pointer to ixgbe_dcb_config structure
2867 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2868 struct ixgbe_dcb_config *dcb_config)
2871 uint8_t i,pfc_en,nb_tcs;
2873 uint8_t config_dcb_rx = 0;
2874 uint8_t config_dcb_tx = 0;
2875 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2876 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2877 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2878 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2879 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2880 struct ixgbe_dcb_tc_config *tc;
2881 uint32_t max_frame = dev->data->max_frame_size;
2882 struct ixgbe_hw *hw =
2883 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2885 switch(dev->data->dev_conf.rxmode.mq_mode){
2886 case ETH_MQ_RX_VMDQ_DCB:
2887 dcb_config->vt_mode = true;
2888 if (hw->mac.type != ixgbe_mac_82598EB) {
2889 config_dcb_rx = DCB_RX_CONFIG;
2891 *get dcb and VT rx configuration parameters
2894 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2895 /*Configure general VMDQ and DCB RX parameters*/
2896 ixgbe_vmdq_dcb_configure(dev);
2900 dcb_config->vt_mode = false;
2901 config_dcb_rx = DCB_RX_CONFIG;
2902 /* Get dcb TX configuration parameters from rte_eth_conf */
2903 ixgbe_dcb_rx_config(dev,dcb_config);
2904 /*Configure general DCB RX parameters*/
2905 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2908 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration\n");
2911 switch (dev->data->dev_conf.txmode.mq_mode) {
2912 case ETH_MQ_TX_VMDQ_DCB:
2913 dcb_config->vt_mode = true;
2914 config_dcb_tx = DCB_TX_CONFIG;
2915 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2916 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2917 /*Configure general VMDQ and DCB TX parameters*/
2918 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2922 dcb_config->vt_mode = false;
2923 config_dcb_tx = DCB_TX_CONFIG;
2924 /*get DCB TX configuration parameters from rte_eth_conf*/
2925 ixgbe_dcb_tx_config(dev,dcb_config);
2926 /*Configure general DCB TX parameters*/
2927 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2930 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration\n");
2934 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2936 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2937 if(nb_tcs == ETH_4_TCS) {
2938 /* Avoid un-configured priority mapping to TC0 */
2940 uint8_t mask = 0xFF;
2941 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2942 mask = (uint8_t)(mask & (~ (1 << map[i])));
2943 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2944 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2948 /* Re-configure 4 TCs BW */
2949 for (i = 0; i < nb_tcs; i++) {
2950 tc = &dcb_config->tc_config[i];
2951 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
2952 (uint8_t)(100 / nb_tcs);
2953 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
2954 (uint8_t)(100 / nb_tcs);
2956 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2957 tc = &dcb_config->tc_config[i];
2958 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
2959 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
2964 /* Set RX buffer size */
2965 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2966 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
2967 for (i = 0 ; i < nb_tcs; i++) {
2968 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2970 /* zero alloc all unused TCs */
2971 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2972 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
2976 /* Only support an equally distributed Tx packet buffer strategy. */
2977 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
2978 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
2979 for (i = 0; i < nb_tcs; i++) {
2980 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
2981 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
2983 /* Clear unused TCs, if any, to zero buffer size*/
2984 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2985 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
2986 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
2990 /*Calculates traffic class credits*/
2991 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2992 IXGBE_DCB_TX_CONFIG);
2993 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2994 IXGBE_DCB_RX_CONFIG);
2997 /* Unpack CEE standard containers */
2998 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
2999 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3000 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3001 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3002 /* Configure PG(ETS) RX */
3003 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3007 /* Unpack CEE standard containers */
3008 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3009 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3010 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3011 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3012 /* Configure PG(ETS) TX */
3013 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3016 /*Configure queue statistics registers*/
3017 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3019 /* Check if the PFC is supported */
3020 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3021 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3022 for (i = 0; i < nb_tcs; i++) {
3024 * If the TC count is 8,and the default high_water is 48,
3025 * the low_water is 16 as default.
3027 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3028 hw->fc.low_water[i] = pbsize / 4;
3029 /* Enable pfc for this TC */
3030 tc = &dcb_config->tc_config[i];
3031 tc->pfc = ixgbe_dcb_pfc_enabled;
3033 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3034 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3036 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3043 * ixgbe_configure_dcb - Configure DCB Hardware
3044 * @dev: pointer to rte_eth_dev
3046 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3048 struct ixgbe_dcb_config *dcb_cfg =
3049 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3050 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3052 PMD_INIT_FUNC_TRACE();
3054 /* check support mq_mode for DCB */
3055 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3056 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3059 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3062 /** Configure DCB hardware **/
3063 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3069 * VMDq only support for 10 GbE NIC.
3072 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3074 struct rte_eth_vmdq_rx_conf *cfg;
3075 struct ixgbe_hw *hw;
3076 enum rte_eth_nb_pools num_pools;
3077 uint32_t mrqc, vt_ctl, vlanctrl;
3080 PMD_INIT_FUNC_TRACE();
3081 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3082 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3083 num_pools = cfg->nb_queue_pools;
3085 ixgbe_rss_disable(dev);
3087 /* MRQC: enable vmdq */
3088 mrqc = IXGBE_MRQC_VMDQEN;
3089 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3091 /* PFVTCTL: turn on virtualisation and set the default pool */
3092 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3093 if (cfg->enable_default_pool)
3094 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3096 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3098 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3100 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3101 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3102 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3103 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3105 /* VFTA - enable all vlan filters */
3106 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3107 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3109 /* VFRE: pool enabling for receive - 64 */
3110 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3111 if (num_pools == ETH_64_POOLS)
3112 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3115 * MPSAR - allow pools to read specific mac addresses
3116 * In this case, all pools should be able to read from mac addr 0
3118 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3119 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3121 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3122 for (i = 0; i < cfg->nb_pool_maps; i++) {
3123 /* set vlan id in VF register and set the valid bit */
3124 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3125 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3127 * Put the allowed pools in VFB reg. As we only have 16 or 64
3128 * pools, we only need to use the first half of the register
3131 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3132 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3133 (cfg->pool_map[i].pools & UINT32_MAX));
3135 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3136 ((cfg->pool_map[i].pools >> 32) \
3141 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3142 if (cfg->enable_loop_back) {
3143 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3144 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3145 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3148 IXGBE_WRITE_FLUSH(hw);
3152 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3153 * @hw: pointer to hardware structure
3156 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3161 PMD_INIT_FUNC_TRACE();
3162 /*PF VF Transmit Enable*/
3163 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3164 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3166 /* Disable the Tx desc arbiter so that MTQC can be changed */
3167 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3168 reg |= IXGBE_RTTDCS_ARBDIS;
3169 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3171 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3172 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3174 /* Disable drop for all queues */
3175 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3176 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3177 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3179 /* Enable the Tx desc arbiter */
3180 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3181 reg &= ~IXGBE_RTTDCS_ARBDIS;
3182 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3184 IXGBE_WRITE_FLUSH(hw);
3190 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3192 struct igb_rx_entry *rxe = rxq->sw_ring;
3196 /* Initialize software ring entries */
3197 for (i = 0; i < rxq->nb_rx_desc; i++) {
3198 volatile union ixgbe_adv_rx_desc *rxd;
3199 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3201 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u\n",
3202 (unsigned) rxq->queue_id);
3206 rte_mbuf_refcnt_set(mbuf, 1);
3207 mbuf->type = RTE_MBUF_PKT;
3208 mbuf->pkt.next = NULL;
3209 mbuf->pkt.data = (char *)mbuf->buf_addr + RTE_PKTMBUF_HEADROOM;
3210 mbuf->pkt.nb_segs = 1;
3211 mbuf->pkt.in_port = rxq->port_id;
3214 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3215 rxd = &rxq->rx_ring[i];
3216 rxd->read.hdr_addr = dma_addr;
3217 rxd->read.pkt_addr = dma_addr;
3225 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3227 struct ixgbe_hw *hw =
3228 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3230 if (hw->mac.type == ixgbe_mac_82598EB)
3233 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3235 * SRIOV inactive scheme
3236 * any DCB/RSS w/o VMDq multi-queue setting
3238 switch (dev->data->dev_conf.rxmode.mq_mode) {
3240 ixgbe_rss_configure(dev);
3243 case ETH_MQ_RX_VMDQ_DCB:
3244 ixgbe_vmdq_dcb_configure(dev);
3247 case ETH_MQ_RX_VMDQ_ONLY:
3248 ixgbe_vmdq_rx_hw_configure(dev);
3251 case ETH_MQ_RX_NONE:
3252 /* if mq_mode is none, disable rss mode.*/
3253 default: ixgbe_rss_disable(dev);
3256 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3258 * SRIOV active scheme
3259 * FIXME if support DCB/RSS together with VMDq & SRIOV
3262 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3266 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3270 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3273 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3281 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3283 struct ixgbe_hw *hw =
3284 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288 if (hw->mac.type == ixgbe_mac_82598EB)
3291 /* disable arbiter before setting MTQC */
3292 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3293 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3294 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3296 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3298 * SRIOV inactive scheme
3299 * any DCB w/o VMDq multi-queue setting
3301 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3302 ixgbe_vmdq_tx_hw_configure(hw);
3304 mtqc = IXGBE_MTQC_64Q_1PB;
3305 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3308 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3311 * SRIOV active scheme
3312 * FIXME if support DCB together with VMDq & SRIOV
3315 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3318 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3321 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3325 mtqc = IXGBE_MTQC_64Q_1PB;
3326 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3328 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3331 /* re-enable arbiter */
3332 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3333 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3339 * Initializes Receive Unit.
3342 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3344 struct ixgbe_hw *hw;
3345 struct igb_rx_queue *rxq;
3346 struct rte_pktmbuf_pool_private *mbp_priv;
3358 PMD_INIT_FUNC_TRACE();
3359 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3362 * Make sure receives are disabled while setting
3363 * up the RX context (registers, descriptor rings, etc.).
3365 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3366 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3368 /* Enable receipt of broadcasted frames */
3369 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3370 fctrl |= IXGBE_FCTRL_BAM;
3371 fctrl |= IXGBE_FCTRL_DPF;
3372 fctrl |= IXGBE_FCTRL_PMCF;
3373 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3376 * Configure CRC stripping, if any.
3378 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3379 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3380 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3382 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3385 * Configure jumbo frame support, if any.
3387 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3388 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3389 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3390 maxfrs &= 0x0000FFFF;
3391 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3392 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3394 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3397 * If loopback mode is configured for 82599, set LPBK bit.
3399 if (hw->mac.type == ixgbe_mac_82599EB &&
3400 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3401 hlreg0 |= IXGBE_HLREG0_LPBK;
3403 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3405 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3407 /* Setup RX queues */
3408 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3409 rxq = dev->data->rx_queues[i];
3412 * Reset crc_len in case it was changed after queue setup by a
3413 * call to configure.
3415 rxq->crc_len = (uint8_t)
3416 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3419 /* Setup the Base and Length of the Rx Descriptor Rings */
3420 bus_addr = rxq->rx_ring_phys_addr;
3421 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3422 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3423 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3424 (uint32_t)(bus_addr >> 32));
3425 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3426 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3427 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3428 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3430 /* Configure the SRRCTL register */
3431 #ifdef RTE_HEADER_SPLIT_ENABLE
3433 * Configure Header Split
3435 if (dev->data->dev_conf.rxmode.header_split) {
3436 if (hw->mac.type == ixgbe_mac_82599EB) {
3437 /* Must setup the PSRTYPE register */
3439 psrtype = IXGBE_PSRTYPE_TCPHDR |
3440 IXGBE_PSRTYPE_UDPHDR |
3441 IXGBE_PSRTYPE_IPV4HDR |
3442 IXGBE_PSRTYPE_IPV6HDR;
3443 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3445 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3446 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3447 IXGBE_SRRCTL_BSIZEHDR_MASK);
3448 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3451 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3453 /* Set if packets are dropped when no descriptors available */
3455 srrctl |= IXGBE_SRRCTL_DROP_EN;
3458 * Configure the RX buffer size in the BSIZEPACKET field of
3459 * the SRRCTL register of the queue.
3460 * The value is in 1 KB resolution. Valid values can be from
3463 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3464 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3465 RTE_PKTMBUF_HEADROOM);
3466 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3467 IXGBE_SRRCTL_BSIZEPKT_MASK);
3468 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3470 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3471 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3473 /* It adds dual VLAN length for supporting dual VLAN */
3474 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3475 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3476 dev->data->scattered_rx = 1;
3477 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3482 * Device configured with multiple RX queues.
3484 ixgbe_dev_mq_rx_configure(dev);
3487 * Setup the Checksum Register.
3488 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3489 * Enable IP/L4 checkum computation by hardware if requested to do so.
3491 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3492 rxcsum |= IXGBE_RXCSUM_PCSD;
3493 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3494 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3496 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3498 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3500 if (hw->mac.type == ixgbe_mac_82599EB) {
3501 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3502 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3503 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3505 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3506 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3507 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3514 * Initializes Transmit Unit.
3517 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3519 struct ixgbe_hw *hw;
3520 struct igb_tx_queue *txq;
3526 PMD_INIT_FUNC_TRACE();
3527 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3529 /* Enable TX CRC (checksum offload requirement) */
3530 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3531 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3532 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3534 /* Setup the Base and Length of the Tx Descriptor Rings */
3535 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3536 txq = dev->data->tx_queues[i];
3538 bus_addr = txq->tx_ring_phys_addr;
3539 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3540 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3541 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3542 (uint32_t)(bus_addr >> 32));
3543 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3544 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3545 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3546 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3547 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3550 * Disable Tx Head Writeback RO bit, since this hoses
3551 * bookkeeping if things aren't delivered in order.
3553 switch (hw->mac.type) {
3554 case ixgbe_mac_82598EB:
3555 txctrl = IXGBE_READ_REG(hw,
3556 IXGBE_DCA_TXCTRL(txq->reg_idx));
3557 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3558 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3562 case ixgbe_mac_82599EB:
3563 case ixgbe_mac_X540:
3565 txctrl = IXGBE_READ_REG(hw,
3566 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3567 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3568 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3574 /* Device configured with multiple TX queues. */
3575 ixgbe_dev_mq_tx_configure(dev);
3579 * Set up link for 82599 loopback mode Tx->Rx.
3582 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3584 DEBUGFUNC("ixgbe_setup_loopback_link_82599");
3586 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3587 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3589 PMD_INIT_LOG(ERR, "Could not enable loopback mode\n");
3598 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3599 ixgbe_reset_pipeline_82599(hw);
3601 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3607 * Start Transmit and Receive Units.
3610 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3612 struct ixgbe_hw *hw;
3613 struct igb_tx_queue *txq;
3614 struct igb_rx_queue *rxq;
3620 PMD_INIT_FUNC_TRACE();
3621 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3623 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3624 txq = dev->data->tx_queues[i];
3625 /* Setup Transmit Threshold Registers */
3626 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3627 txdctl |= txq->pthresh & 0x7F;
3628 txdctl |= ((txq->hthresh & 0x7F) << 8);
3629 txdctl |= ((txq->wthresh & 0x7F) << 16);
3630 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3633 if (hw->mac.type != ixgbe_mac_82598EB) {
3634 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3635 dmatxctl |= IXGBE_DMATXCTL_TE;
3636 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3639 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3640 txq = dev->data->tx_queues[i];
3641 if (!txq->start_tx_per_q)
3642 ixgbe_dev_tx_queue_start(dev, i);
3645 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3646 rxq = dev->data->rx_queues[i];
3647 if (!rxq->start_rx_per_q)
3648 ixgbe_dev_rx_queue_start(dev, i);
3651 /* Enable Receive engine */
3652 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3653 if (hw->mac.type == ixgbe_mac_82598EB)
3654 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3655 rxctrl |= IXGBE_RXCTRL_RXEN;
3656 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3658 /* If loopback mode is enabled for 82599, set up the link accordingly */
3659 if (hw->mac.type == ixgbe_mac_82599EB &&
3660 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3661 ixgbe_setup_loopback_link_82599(hw);
3666 * Start Receive Units for specified queue.
3669 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3671 struct ixgbe_hw *hw;
3672 struct igb_rx_queue *rxq;
3676 PMD_INIT_FUNC_TRACE();
3677 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3679 if (rx_queue_id < dev->data->nb_rx_queues) {
3680 rxq = dev->data->rx_queues[rx_queue_id];
3682 /* Allocate buffers for descriptor rings */
3683 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
3685 "Could not alloc mbuf for queue:%d\n",
3689 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3690 rxdctl |= IXGBE_RXDCTL_ENABLE;
3691 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3693 /* Wait until RX Enable ready */
3694 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3697 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3698 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3700 PMD_INIT_LOG(ERR, "Could not enable "
3701 "Rx Queue %d\n", rx_queue_id);
3703 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3704 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3712 * Stop Receive Units for specified queue.
3715 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3717 struct ixgbe_hw *hw;
3718 struct igb_rx_queue *rxq;
3722 PMD_INIT_FUNC_TRACE();
3723 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3725 if (rx_queue_id < dev->data->nb_rx_queues) {
3726 rxq = dev->data->rx_queues[rx_queue_id];
3728 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3729 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3730 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3732 /* Wait until RX Enable ready */
3733 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3736 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3737 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
3739 PMD_INIT_LOG(ERR, "Could not disable "
3740 "Rx Queue %d\n", rx_queue_id);
3742 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3744 ixgbe_rx_queue_release_mbufs(rxq);
3745 ixgbe_reset_rx_queue(rxq);
3754 * Start Transmit Units for specified queue.
3757 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3759 struct ixgbe_hw *hw;
3760 struct igb_tx_queue *txq;
3764 PMD_INIT_FUNC_TRACE();
3765 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3767 if (tx_queue_id < dev->data->nb_tx_queues) {
3768 txq = dev->data->tx_queues[tx_queue_id];
3769 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3770 txdctl |= IXGBE_TXDCTL_ENABLE;
3771 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3773 /* Wait until TX Enable ready */
3774 if (hw->mac.type == ixgbe_mac_82599EB) {
3775 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3778 txdctl = IXGBE_READ_REG(hw,
3779 IXGBE_TXDCTL(txq->reg_idx));
3780 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3782 PMD_INIT_LOG(ERR, "Could not enable "
3783 "Tx Queue %d\n", tx_queue_id);
3786 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3787 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3795 * Stop Transmit Units for specified queue.
3798 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3800 struct ixgbe_hw *hw;
3801 struct igb_tx_queue *txq;
3803 uint32_t txtdh, txtdt;
3806 PMD_INIT_FUNC_TRACE();
3807 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3809 if (tx_queue_id < dev->data->nb_tx_queues) {
3810 txq = dev->data->tx_queues[tx_queue_id];
3812 /* Wait until TX queue is empty */
3813 if (hw->mac.type == ixgbe_mac_82599EB) {
3814 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3816 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3817 txtdh = IXGBE_READ_REG(hw,
3818 IXGBE_TDH(txq->reg_idx));
3819 txtdt = IXGBE_READ_REG(hw,
3820 IXGBE_TDT(txq->reg_idx));
3821 } while (--poll_ms && (txtdh != txtdt));
3824 "Tx Queue %d is not empty when stopping.\n",
3828 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3829 txdctl &= ~IXGBE_TXDCTL_ENABLE;
3830 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3832 /* Wait until TX Enable ready */
3833 if (hw->mac.type == ixgbe_mac_82599EB) {
3834 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3837 txdctl = IXGBE_READ_REG(hw,
3838 IXGBE_TXDCTL(txq->reg_idx));
3839 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
3841 PMD_INIT_LOG(ERR, "Could not disable "
3842 "Tx Queue %d\n", tx_queue_id);
3845 if (txq->ops != NULL) {
3846 txq->ops->release_mbufs(txq);
3847 txq->ops->reset(txq);
3856 * [VF] Initializes Receive Unit.
3859 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3861 struct ixgbe_hw *hw;
3862 struct igb_rx_queue *rxq;
3863 struct rte_pktmbuf_pool_private *mbp_priv;
3870 PMD_INIT_FUNC_TRACE();
3871 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3874 ixgbevf_rlpml_set_vf(hw,
3875 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
3877 /* Setup RX queues */
3878 dev->rx_pkt_burst = ixgbe_recv_pkts;
3879 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3880 rxq = dev->data->rx_queues[i];
3882 /* Allocate buffers for descriptor rings */
3883 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3887 /* Setup the Base and Length of the Rx Descriptor Rings */
3888 bus_addr = rxq->rx_ring_phys_addr;
3890 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3891 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3892 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3893 (uint32_t)(bus_addr >> 32));
3894 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3895 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3896 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3897 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3900 /* Configure the SRRCTL register */
3901 #ifdef RTE_HEADER_SPLIT_ENABLE
3903 * Configure Header Split
3905 if (dev->data->dev_conf.rxmode.header_split) {
3907 /* Must setup the PSRTYPE register */
3909 psrtype = IXGBE_PSRTYPE_TCPHDR |
3910 IXGBE_PSRTYPE_UDPHDR |
3911 IXGBE_PSRTYPE_IPV4HDR |
3912 IXGBE_PSRTYPE_IPV6HDR;
3914 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3916 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3917 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3918 IXGBE_SRRCTL_BSIZEHDR_MASK);
3919 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3922 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3924 /* Set if packets are dropped when no descriptors available */
3926 srrctl |= IXGBE_SRRCTL_DROP_EN;
3929 * Configure the RX buffer size in the BSIZEPACKET field of
3930 * the SRRCTL register of the queue.
3931 * The value is in 1 KB resolution. Valid values can be from
3934 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3935 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3936 RTE_PKTMBUF_HEADROOM);
3937 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3938 IXGBE_SRRCTL_BSIZEPKT_MASK);
3941 * VF modification to write virtual function SRRCTL register
3943 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
3945 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3946 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3948 /* It adds dual VLAN length for supporting dual VLAN */
3949 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3950 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
3951 dev->data->scattered_rx = 1;
3952 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3960 * [VF] Initializes Transmit Unit.
3963 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
3965 struct ixgbe_hw *hw;
3966 struct igb_tx_queue *txq;
3971 PMD_INIT_FUNC_TRACE();
3972 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3974 /* Setup the Base and Length of the Tx Descriptor Rings */
3975 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3976 txq = dev->data->tx_queues[i];
3977 bus_addr = txq->tx_ring_phys_addr;
3978 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
3979 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3980 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
3981 (uint32_t)(bus_addr >> 32));
3982 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
3983 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3984 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3985 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
3986 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
3989 * Disable Tx Head Writeback RO bit, since this hoses
3990 * bookkeeping if things aren't delivered in order.
3992 txctrl = IXGBE_READ_REG(hw,
3993 IXGBE_VFDCA_TXCTRL(i));
3994 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3995 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4001 * [VF] Start Transmit and Receive Units.
4004 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4006 struct ixgbe_hw *hw;
4007 struct igb_tx_queue *txq;
4008 struct igb_rx_queue *rxq;
4014 PMD_INIT_FUNC_TRACE();
4015 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4017 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4018 txq = dev->data->tx_queues[i];
4019 /* Setup Transmit Threshold Registers */
4020 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4021 txdctl |= txq->pthresh & 0x7F;
4022 txdctl |= ((txq->hthresh & 0x7F) << 8);
4023 txdctl |= ((txq->wthresh & 0x7F) << 16);
4024 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4027 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4029 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4030 txdctl |= IXGBE_TXDCTL_ENABLE;
4031 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4034 /* Wait until TX Enable ready */
4037 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4038 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4040 PMD_INIT_LOG(ERR, "Could not enable "
4041 "Tx Queue %d\n", i);
4043 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4045 rxq = dev->data->rx_queues[i];
4047 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4048 rxdctl |= IXGBE_RXDCTL_ENABLE;
4049 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4051 /* Wait until RX Enable ready */
4055 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4056 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4058 PMD_INIT_LOG(ERR, "Could not enable "
4059 "Rx Queue %d\n", i);
4061 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);