4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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34 #include <sys/queue.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
47 #include <rte_cycles.h>
49 #include <rte_debug.h>
50 #include <rte_interrupts.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
55 #include <rte_tailq.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
82 #include "ixgbe_rxtx.h"
85 static inline struct rte_mbuf *
86 rte_rxmbuf_alloc(struct rte_mempool *mp)
90 m = __rte_mbuf_raw_alloc(mp);
91 __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
97 #define RTE_PMD_USE_PREFETCH
100 #ifdef RTE_PMD_USE_PREFETCH
102 * Prefetch a cache line into all cache levels.
104 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
106 #define rte_ixgbe_prefetch(p) do {} while(0)
109 /*********************************************************************
113 **********************************************************************/
116 * Check for descriptors with their DD bit set and free mbufs.
117 * Return the total number of buffers freed.
119 static inline int __attribute__((always_inline))
120 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
122 struct igb_tx_entry *txep;
126 /* check DD bit on threshold descriptor */
127 status = txq->tx_ring[txq->tx_next_dd].wb.status;
128 if (! (status & IXGBE_ADVTXD_STAT_DD))
132 * first buffer to free from S/W ring is at index
133 * tx_next_dd - (tx_rs_thresh-1)
135 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
137 /* prefetch the mbufs that are about to be freed */
138 for (i = 0; i < txq->tx_rs_thresh; ++i)
139 rte_prefetch0((txep + i)->mbuf);
141 /* free buffers one at a time */
142 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
143 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
144 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
148 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
149 rte_pktmbuf_free_seg(txep->mbuf);
154 /* buffers were freed, update counters */
155 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
156 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
157 if (txq->tx_next_dd >= txq->nb_tx_desc)
158 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
160 return txq->tx_rs_thresh;
163 /* Populate 4 descriptors with data from 4 mbufs */
165 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
167 uint64_t buf_dma_addr;
171 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
172 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
173 pkt_len = (*pkts)->pkt.data_len;
175 /* write data to descriptor */
176 txdp->read.buffer_addr = buf_dma_addr;
177 txdp->read.cmd_type_len =
178 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
179 txdp->read.olinfo_status =
180 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
184 /* Populate 1 descriptor with data from 1 mbuf */
186 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
188 uint64_t buf_dma_addr;
191 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
192 pkt_len = (*pkts)->pkt.data_len;
194 /* write data to descriptor */
195 txdp->read.buffer_addr = buf_dma_addr;
196 txdp->read.cmd_type_len =
197 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
198 txdp->read.olinfo_status =
199 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
203 * Fill H/W descriptor ring with mbuf data.
204 * Copy mbuf pointers to the S/W ring.
207 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
210 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
211 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
212 const int N_PER_LOOP = 4;
213 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
214 int mainpart, leftover;
218 * Process most of the packets in chunks of N pkts. Any
219 * leftover packets will get processed one at a time.
221 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
222 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
223 for (i = 0; i < mainpart; i += N_PER_LOOP) {
224 /* Copy N mbuf pointers to the S/W ring */
225 for (j = 0; j < N_PER_LOOP; ++j) {
226 (txep + i + j)->mbuf = *(pkts + i + j);
228 tx4(txdp + i, pkts + i);
231 if (unlikely(leftover > 0)) {
232 for (i = 0; i < leftover; ++i) {
233 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
234 tx1(txdp + mainpart + i, pkts + mainpart + i);
239 static inline uint16_t
240 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
243 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
244 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
248 * Begin scanning the H/W ring for done descriptors when the
249 * number of available descriptors drops below tx_free_thresh. For
250 * each done descriptor, free the associated buffer.
252 if (txq->nb_tx_free < txq->tx_free_thresh)
253 ixgbe_tx_free_bufs(txq);
255 /* Only use descriptors that are available */
256 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
257 if (unlikely(nb_pkts == 0))
260 /* Use exactly nb_pkts descriptors */
261 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
264 * At this point, we know there are enough descriptors in the
265 * ring to transmit all the packets. This assumes that each
266 * mbuf contains a single segment, and that no new offloads
267 * are expected, which would require a new context descriptor.
271 * See if we're going to wrap-around. If so, handle the top
272 * of the descriptor ring first, then do the bottom. If not,
273 * the processing looks just like the "bottom" part anyway...
275 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
276 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
277 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
280 * We know that the last descriptor in the ring will need to
281 * have its RS bit set because tx_rs_thresh has to be
282 * a divisor of the ring size
284 tx_r[txq->tx_next_rs].read.cmd_type_len |=
285 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
286 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
291 /* Fill H/W descriptor ring with mbuf data */
292 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
293 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
296 * Determine if RS bit should be set
297 * This is what we actually want:
298 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
299 * but instead of subtracting 1 and doing >=, we can just do
300 * greater than without subtracting.
302 if (txq->tx_tail > txq->tx_next_rs) {
303 tx_r[txq->tx_next_rs].read.cmd_type_len |=
304 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
305 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
307 if (txq->tx_next_rs >= txq->nb_tx_desc)
308 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
312 * Check for wrap-around. This would only happen if we used
313 * up to the last descriptor in the ring, no more, no less.
315 if (txq->tx_tail >= txq->nb_tx_desc)
318 /* update tail pointer */
320 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
326 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
331 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
332 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
333 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
335 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
339 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
340 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
341 nb_tx = (uint16_t)(nb_tx + ret);
342 nb_pkts = (uint16_t)(nb_pkts - ret);
351 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
352 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
353 uint16_t ol_flags, uint32_t vlan_macip_lens)
355 uint32_t type_tucmd_mlhl;
356 uint32_t mss_l4len_idx;
360 ctx_idx = txq->ctx_curr;
364 if (ol_flags & PKT_TX_VLAN_PKT) {
365 cmp_mask |= TX_VLAN_CMP_MASK;
368 if (ol_flags & PKT_TX_IP_CKSUM) {
369 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
370 cmp_mask |= TX_MAC_LEN_CMP_MASK;
373 /* Specify which HW CTX to upload. */
374 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
375 switch (ol_flags & PKT_TX_L4_MASK) {
376 case PKT_TX_UDP_CKSUM:
377 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
378 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
379 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
380 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
382 case PKT_TX_TCP_CKSUM:
383 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
384 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
385 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
386 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
388 case PKT_TX_SCTP_CKSUM:
389 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
390 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
391 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
392 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
395 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
396 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
400 txq->ctx_cache[ctx_idx].flags = ol_flags;
401 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
402 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
403 vlan_macip_lens & cmp_mask;
405 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
406 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
407 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
408 ctx_txd->seqnum_seed = 0;
412 * Check which hardware context can be used. Use the existing match
413 * or create a new context descriptor.
415 static inline uint32_t
416 what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
417 uint32_t vlan_macip_lens)
419 /* If match with the current used context */
420 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
421 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
422 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
423 return txq->ctx_curr;
426 /* What if match with the next context */
428 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
429 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
430 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
431 return txq->ctx_curr;
434 /* Mismatch, use the previous context */
435 return (IXGBE_CTX_NUM);
438 static inline uint32_t
439 tx_desc_cksum_flags_to_olinfo(uint16_t ol_flags)
441 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
442 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
445 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
446 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
450 static inline uint32_t
451 tx_desc_vlan_flags_to_cmdtype(uint16_t ol_flags)
453 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
454 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
457 /* Default RS bit threshold values */
458 #ifndef DEFAULT_TX_RS_THRESH
459 #define DEFAULT_TX_RS_THRESH 32
461 #ifndef DEFAULT_TX_FREE_THRESH
462 #define DEFAULT_TX_FREE_THRESH 32
465 /* Reset transmit descriptors after they have been used */
467 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
469 struct igb_tx_entry *sw_ring = txq->sw_ring;
470 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
471 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
472 uint16_t nb_tx_desc = txq->nb_tx_desc;
473 uint16_t desc_to_clean_to;
474 uint16_t nb_tx_to_clean;
476 /* Determine the last descriptor needing to be cleaned */
477 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
478 if (desc_to_clean_to >= nb_tx_desc)
479 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
481 /* Check to make sure the last descriptor to clean is done */
482 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
483 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
485 PMD_TX_FREE_LOG(DEBUG,
486 "TX descriptor %4u is not done"
487 "(port=%d queue=%d)",
489 txq->port_id, txq->queue_id);
490 /* Failed to clean any descriptors, better luck next time */
494 /* Figure out how many descriptors will be cleaned */
495 if (last_desc_cleaned > desc_to_clean_to)
496 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
499 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
502 PMD_TX_FREE_LOG(DEBUG,
503 "Cleaning %4u TX descriptors: %4u to %4u "
504 "(port=%d queue=%d)",
505 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
506 txq->port_id, txq->queue_id);
509 * The last descriptor to clean is done, so that means all the
510 * descriptors from the last descriptor that was cleaned
511 * up to the last descriptor with the RS bit set
512 * are done. Only reset the threshold descriptor.
514 txr[desc_to_clean_to].wb.status = 0;
516 /* Update the txq to reflect the last descriptor that was cleaned */
517 txq->last_desc_cleaned = desc_to_clean_to;
518 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
525 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
528 struct igb_tx_queue *txq;
529 struct igb_tx_entry *sw_ring;
530 struct igb_tx_entry *txe, *txn;
531 volatile union ixgbe_adv_tx_desc *txr;
532 volatile union ixgbe_adv_tx_desc *txd;
533 struct rte_mbuf *tx_pkt;
534 struct rte_mbuf *m_seg;
535 uint64_t buf_dma_addr;
536 uint32_t olinfo_status;
537 uint32_t cmd_type_len;
546 uint32_t vlan_macip_lens;
551 sw_ring = txq->sw_ring;
553 tx_id = txq->tx_tail;
554 txe = &sw_ring[tx_id];
556 /* Determine if the descriptor ring needs to be cleaned. */
557 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
558 ixgbe_xmit_cleanup(txq);
562 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
565 pkt_len = tx_pkt->pkt.pkt_len;
567 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
570 * Determine how many (if any) context descriptors
571 * are needed for offload functionality.
573 ol_flags = tx_pkt->ol_flags;
574 vlan_macip_lens = tx_pkt->pkt.vlan_macip.data;
576 /* If hardware offload required */
577 tx_ol_req = (uint16_t)(ol_flags & PKT_TX_OFFLOAD_MASK);
579 /* If new context need be built or reuse the exist ctx. */
580 ctx = what_advctx_update(txq, tx_ol_req,
582 /* Only allocate context descriptor if required*/
583 new_ctx = (ctx == IXGBE_CTX_NUM);
588 * Keep track of how many descriptors are used this loop
589 * This will always be the number of segments + the number of
590 * Context descriptors required to transmit the packet
592 nb_used = (uint16_t)(tx_pkt->pkt.nb_segs + new_ctx);
595 * The number of descriptors that must be allocated for a
596 * packet is the number of segments of that packet, plus 1
597 * Context Descriptor for the hardware offload, if any.
598 * Determine the last TX descriptor to allocate in the TX ring
599 * for the packet, starting from the current position (tx_id)
602 tx_last = (uint16_t) (tx_id + nb_used - 1);
605 if (tx_last >= txq->nb_tx_desc)
606 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
608 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
609 " tx_first=%u tx_last=%u\n",
610 (unsigned) txq->port_id,
611 (unsigned) txq->queue_id,
617 * Make sure there are enough TX descriptors available to
618 * transmit the entire packet.
619 * nb_used better be less than or equal to txq->tx_rs_thresh
621 if (nb_used > txq->nb_tx_free) {
622 PMD_TX_FREE_LOG(DEBUG,
623 "Not enough free TX descriptors "
624 "nb_used=%4u nb_free=%4u "
625 "(port=%d queue=%d)",
626 nb_used, txq->nb_tx_free,
627 txq->port_id, txq->queue_id);
629 if (ixgbe_xmit_cleanup(txq) != 0) {
630 /* Could not clean any descriptors */
636 /* nb_used better be <= txq->tx_rs_thresh */
637 if (unlikely(nb_used > txq->tx_rs_thresh)) {
638 PMD_TX_FREE_LOG(DEBUG,
639 "The number of descriptors needed to "
640 "transmit the packet exceeds the "
641 "RS bit threshold. This will impact "
643 "nb_used=%4u nb_free=%4u "
645 "(port=%d queue=%d)",
646 nb_used, txq->nb_tx_free,
648 txq->port_id, txq->queue_id);
650 * Loop here until there are enough TX
651 * descriptors or until the ring cannot be
654 while (nb_used > txq->nb_tx_free) {
655 if (ixgbe_xmit_cleanup(txq) != 0) {
657 * Could not clean any
669 * By now there are enough free TX descriptors to transmit
674 * Set common flags of all TX Data Descriptors.
676 * The following bits must be set in all Data Descriptors:
677 * - IXGBE_ADVTXD_DTYP_DATA
678 * - IXGBE_ADVTXD_DCMD_DEXT
680 * The following bits must be set in the first Data Descriptor
681 * and are ignored in the other ones:
682 * - IXGBE_ADVTXD_DCMD_IFCS
683 * - IXGBE_ADVTXD_MAC_1588
684 * - IXGBE_ADVTXD_DCMD_VLE
686 * The following bits must only be set in the last Data
688 * - IXGBE_TXD_CMD_EOP
690 * The following bits can be set in any Data Descriptor, but
691 * are only set in the last Data Descriptor:
694 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
695 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
696 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
697 #ifdef RTE_LIBRTE_IEEE1588
698 if (ol_flags & PKT_TX_IEEE1588_TMST)
699 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
704 * Setup the TX Advanced Context Descriptor if required
707 volatile struct ixgbe_adv_tx_context_desc *
710 ctx_txd = (volatile struct
711 ixgbe_adv_tx_context_desc *)
714 txn = &sw_ring[txe->next_id];
715 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
717 if (txe->mbuf != NULL) {
718 rte_pktmbuf_free_seg(txe->mbuf);
722 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
725 txe->last_id = tx_last;
726 tx_id = txe->next_id;
731 * Setup the TX Advanced Data Descriptor,
732 * This path will go through
733 * whatever new/reuse the context descriptor
735 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
736 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
737 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
743 txn = &sw_ring[txe->next_id];
745 if (txe->mbuf != NULL)
746 rte_pktmbuf_free_seg(txe->mbuf);
750 * Set up Transmit Data Descriptor.
752 slen = m_seg->pkt.data_len;
753 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
754 txd->read.buffer_addr =
755 rte_cpu_to_le_64(buf_dma_addr);
756 txd->read.cmd_type_len =
757 rte_cpu_to_le_32(cmd_type_len | slen);
758 txd->read.olinfo_status =
759 rte_cpu_to_le_32(olinfo_status);
760 txe->last_id = tx_last;
761 tx_id = txe->next_id;
763 m_seg = m_seg->pkt.next;
764 } while (m_seg != NULL);
767 * The last packet data descriptor needs End Of Packet (EOP)
769 cmd_type_len |= IXGBE_TXD_CMD_EOP;
770 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
771 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
773 /* Set RS bit only on threshold packets' last descriptor */
774 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
775 PMD_TX_FREE_LOG(DEBUG,
776 "Setting RS bit on TXD id="
777 "%4u (port=%d queue=%d)",
778 tx_last, txq->port_id, txq->queue_id);
780 cmd_type_len |= IXGBE_TXD_CMD_RS;
782 /* Update txq RS bit counters */
785 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
791 * Set the Transmit Descriptor Tail (TDT)
793 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
794 (unsigned) txq->port_id, (unsigned) txq->queue_id,
795 (unsigned) tx_id, (unsigned) nb_tx);
796 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
797 txq->tx_tail = tx_id;
802 /*********************************************************************
806 **********************************************************************/
807 static inline uint16_t
808 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
812 static uint16_t ip_pkt_types_map[16] = {
813 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
814 PKT_RX_IPV6_HDR, 0, 0, 0,
815 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
816 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
819 static uint16_t ip_rss_types_map[16] = {
820 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
821 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
822 PKT_RX_RSS_HASH, 0, 0, 0,
823 0, 0, 0, PKT_RX_FDIR,
826 #ifdef RTE_LIBRTE_IEEE1588
827 static uint32_t ip_pkt_etqf_map[8] = {
828 0, 0, 0, PKT_RX_IEEE1588_PTP,
832 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
833 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
834 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
836 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
837 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
840 return (uint16_t)(pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF]);
843 static inline uint16_t
844 rx_desc_status_to_pkt_flags(uint32_t rx_status)
849 * Check if VLAN present only.
850 * Do not check whether L3/L4 rx checksum done by NIC or not,
851 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
853 pkt_flags = (uint16_t)((rx_status & IXGBE_RXD_STAT_VP) ?
854 PKT_RX_VLAN_PKT : 0);
856 #ifdef RTE_LIBRTE_IEEE1588
857 if (rx_status & IXGBE_RXD_STAT_TMST)
858 pkt_flags = (uint16_t)(pkt_flags | PKT_RX_IEEE1588_TMST);
863 static inline uint16_t
864 rx_desc_error_to_pkt_flags(uint32_t rx_status)
867 * Bit 31: IPE, IPv4 checksum error
868 * Bit 30: L4I, L4I integrity error
870 static uint16_t error_to_pkt_flags_map[4] = {
871 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
872 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
874 return error_to_pkt_flags_map[(rx_status >>
875 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
878 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
880 * LOOK_AHEAD defines how many desc statuses to check beyond the
881 * current descriptor.
882 * It must be a pound define for optimal performance.
883 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
884 * function only works with LOOK_AHEAD=8.
887 #if (LOOK_AHEAD != 8)
888 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
891 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
893 volatile union ixgbe_adv_rx_desc *rxdp;
894 struct igb_rx_entry *rxep;
897 int s[LOOK_AHEAD], nb_dd;
901 /* get references to current descriptor and S/W ring entry */
902 rxdp = &rxq->rx_ring[rxq->rx_tail];
903 rxep = &rxq->sw_ring[rxq->rx_tail];
905 /* check to make sure there is at least 1 packet to receive */
906 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
910 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
911 * reference packets that are ready to be received.
913 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
914 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
916 /* Read desc statuses backwards to avoid race condition */
917 for (j = LOOK_AHEAD-1; j >= 0; --j)
918 s[j] = rxdp[j].wb.upper.status_error;
920 /* Compute how many status bits were set */
922 for (j = 0; j < LOOK_AHEAD; ++j)
923 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
927 /* Translate descriptor info to mbuf format */
928 for (j = 0; j < nb_dd; ++j) {
930 pkt_len = (uint16_t)(rxdp[j].wb.upper.length -
932 mb->pkt.data_len = pkt_len;
933 mb->pkt.pkt_len = pkt_len;
934 mb->pkt.vlan_macip.f.vlan_tci = rxdp[j].wb.upper.vlan;
935 mb->pkt.hash.rss = rxdp[j].wb.lower.hi_dword.rss;
937 /* convert descriptor fields to rte mbuf flags */
938 mb->ol_flags = rx_desc_hlen_type_rss_to_pkt_flags(
939 rxdp[j].wb.lower.lo_dword.data);
940 /* reuse status field from scan list */
941 mb->ol_flags = (uint16_t)(mb->ol_flags |
942 rx_desc_status_to_pkt_flags(s[j]));
943 mb->ol_flags = (uint16_t)(mb->ol_flags |
944 rx_desc_error_to_pkt_flags(s[j]));
947 /* Move mbuf pointers from the S/W ring to the stage */
948 for (j = 0; j < LOOK_AHEAD; ++j) {
949 rxq->rx_stage[i + j] = rxep[j].mbuf;
952 /* stop if all requested packets could not be received */
953 if (nb_dd != LOOK_AHEAD)
957 /* clear software ring entries so we can cleanup correctly */
958 for (i = 0; i < nb_rx; ++i) {
959 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
967 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
969 volatile union ixgbe_adv_rx_desc *rxdp;
970 struct igb_rx_entry *rxep;
976 /* allocate buffers in bulk directly into the S/W ring */
977 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
978 (rxq->rx_free_thresh - 1));
979 rxep = &rxq->sw_ring[alloc_idx];
980 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
981 rxq->rx_free_thresh);
982 if (unlikely(diag != 0))
985 rxdp = &rxq->rx_ring[alloc_idx];
986 for (i = 0; i < rxq->rx_free_thresh; ++i) {
987 /* populate the static rte mbuf fields */
989 rte_mbuf_refcnt_set(mb, 1);
990 mb->type = RTE_MBUF_PKT;
992 mb->pkt.data = (char *)mb->buf_addr + RTE_PKTMBUF_HEADROOM;
994 mb->pkt.in_port = rxq->port_id;
996 /* populate the descriptors */
997 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
998 rxdp[i].read.hdr_addr = dma_addr;
999 rxdp[i].read.pkt_addr = dma_addr;
1002 /* update tail pointer */
1004 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1006 /* update state of internal queue structure */
1007 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1008 rxq->rx_free_thresh);
1009 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1010 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1016 static inline uint16_t
1017 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1020 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1023 /* how many packets are ready to return? */
1024 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1026 /* copy mbuf pointers to the application's packet list */
1027 for (i = 0; i < nb_pkts; ++i)
1028 rx_pkts[i] = stage[i];
1030 /* update internal queue state */
1031 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1032 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1037 static inline uint16_t
1038 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1041 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1044 /* Any previously recv'd pkts will be returned from the Rx stage */
1045 if (rxq->rx_nb_avail)
1046 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1048 /* Scan the H/W ring for packets to receive */
1049 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1051 /* update internal queue state */
1052 rxq->rx_next_avail = 0;
1053 rxq->rx_nb_avail = nb_rx;
1054 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1056 /* if required, allocate new buffers to replenish descriptors */
1057 if (rxq->rx_tail > rxq->rx_free_trigger) {
1058 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1060 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1061 "queue_id=%u\n", (unsigned) rxq->port_id,
1062 (unsigned) rxq->queue_id);
1064 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1065 rxq->rx_free_thresh;
1068 * Need to rewind any previous receives if we cannot
1069 * allocate new buffers to replenish the old ones.
1071 rxq->rx_nb_avail = 0;
1072 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1073 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1074 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1080 if (rxq->rx_tail >= rxq->nb_rx_desc)
1083 /* received any packets this loop? */
1084 if (rxq->rx_nb_avail)
1085 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1090 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1092 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1097 if (unlikely(nb_pkts == 0))
1100 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1101 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1103 /* request is relatively large, chunk it up */
1107 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1108 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1109 nb_rx = (uint16_t)(nb_rx + ret);
1110 nb_pkts = (uint16_t)(nb_pkts - ret);
1117 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1120 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1123 struct igb_rx_queue *rxq;
1124 volatile union ixgbe_adv_rx_desc *rx_ring;
1125 volatile union ixgbe_adv_rx_desc *rxdp;
1126 struct igb_rx_entry *sw_ring;
1127 struct igb_rx_entry *rxe;
1128 struct rte_mbuf *rxm;
1129 struct rte_mbuf *nmb;
1130 union ixgbe_adv_rx_desc rxd;
1133 uint32_t hlen_type_rss;
1143 rx_id = rxq->rx_tail;
1144 rx_ring = rxq->rx_ring;
1145 sw_ring = rxq->sw_ring;
1146 while (nb_rx < nb_pkts) {
1148 * The order of operations here is important as the DD status
1149 * bit must not be read after any other descriptor fields.
1150 * rx_ring and rxdp are pointing to volatile data so the order
1151 * of accesses cannot be reordered by the compiler. If they were
1152 * not volatile, they could be reordered which could lead to
1153 * using invalid descriptor fields when read from rxd.
1155 rxdp = &rx_ring[rx_id];
1156 staterr = rxdp->wb.upper.status_error;
1157 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1164 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1165 * is likely to be invalid and to be dropped by the various
1166 * validation checks performed by the network stack.
1168 * Allocate a new mbuf to replenish the RX ring descriptor.
1169 * If the allocation fails:
1170 * - arrange for that RX descriptor to be the first one
1171 * being parsed the next time the receive function is
1172 * invoked [on the same queue].
1174 * - Stop parsing the RX ring and return immediately.
1176 * This policy do not drop the packet received in the RX
1177 * descriptor for which the allocation of a new mbuf failed.
1178 * Thus, it allows that packet to be later retrieved if
1179 * mbuf have been freed in the mean time.
1180 * As a side effect, holding RX descriptors instead of
1181 * systematically giving them back to the NIC may lead to
1182 * RX ring exhaustion situations.
1183 * However, the NIC can gracefully prevent such situations
1184 * to happen by sending specific "back-pressure" flow control
1185 * frames to its peer(s).
1187 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1188 "ext_err_stat=0x%08x pkt_len=%u\n",
1189 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1190 (unsigned) rx_id, (unsigned) staterr,
1191 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1193 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1195 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1196 "queue_id=%u\n", (unsigned) rxq->port_id,
1197 (unsigned) rxq->queue_id);
1198 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1203 rxe = &sw_ring[rx_id];
1205 if (rx_id == rxq->nb_rx_desc)
1208 /* Prefetch next mbuf while processing current one. */
1209 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1212 * When next RX descriptor is on a cache-line boundary,
1213 * prefetch the next 4 RX descriptors and the next 8 pointers
1216 if ((rx_id & 0x3) == 0) {
1217 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1218 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1224 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1225 rxdp->read.hdr_addr = dma_addr;
1226 rxdp->read.pkt_addr = dma_addr;
1229 * Initialize the returned mbuf.
1230 * 1) setup generic mbuf fields:
1231 * - number of segments,
1234 * - RX port identifier.
1235 * 2) integrate hardware offload data, if any:
1236 * - RSS flag & hash,
1237 * - IP checksum flag,
1238 * - VLAN TCI, if any,
1241 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1243 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1244 rte_packet_prefetch(rxm->pkt.data);
1245 rxm->pkt.nb_segs = 1;
1246 rxm->pkt.next = NULL;
1247 rxm->pkt.pkt_len = pkt_len;
1248 rxm->pkt.data_len = pkt_len;
1249 rxm->pkt.in_port = rxq->port_id;
1251 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1252 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1253 rxm->pkt.vlan_macip.f.vlan_tci =
1254 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1256 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1257 pkt_flags = (uint16_t)(pkt_flags |
1258 rx_desc_status_to_pkt_flags(staterr));
1259 pkt_flags = (uint16_t)(pkt_flags |
1260 rx_desc_error_to_pkt_flags(staterr));
1261 rxm->ol_flags = pkt_flags;
1263 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1264 rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1265 else if (pkt_flags & PKT_RX_FDIR) {
1266 rxm->pkt.hash.fdir.hash =
1267 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1268 & IXGBE_ATR_HASH_MASK);
1269 rxm->pkt.hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1272 * Store the mbuf address into the next entry of the array
1273 * of returned packets.
1275 rx_pkts[nb_rx++] = rxm;
1277 rxq->rx_tail = rx_id;
1280 * If the number of free RX descriptors is greater than the RX free
1281 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1283 * Update the RDT with the value of the last processed RX descriptor
1284 * minus 1, to guarantee that the RDT register is never equal to the
1285 * RDH register, which creates a "full" ring situtation from the
1286 * hardware point of view...
1288 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1289 if (nb_hold > rxq->rx_free_thresh) {
1290 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1291 "nb_hold=%u nb_rx=%u\n",
1292 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1293 (unsigned) rx_id, (unsigned) nb_hold,
1295 rx_id = (uint16_t) ((rx_id == 0) ?
1296 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1297 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1300 rxq->nb_rx_hold = nb_hold;
1305 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1308 struct igb_rx_queue *rxq;
1309 volatile union ixgbe_adv_rx_desc *rx_ring;
1310 volatile union ixgbe_adv_rx_desc *rxdp;
1311 struct igb_rx_entry *sw_ring;
1312 struct igb_rx_entry *rxe;
1313 struct rte_mbuf *first_seg;
1314 struct rte_mbuf *last_seg;
1315 struct rte_mbuf *rxm;
1316 struct rte_mbuf *nmb;
1317 union ixgbe_adv_rx_desc rxd;
1318 uint64_t dma; /* Physical address of mbuf data buffer */
1320 uint32_t hlen_type_rss;
1330 rx_id = rxq->rx_tail;
1331 rx_ring = rxq->rx_ring;
1332 sw_ring = rxq->sw_ring;
1335 * Retrieve RX context of current packet, if any.
1337 first_seg = rxq->pkt_first_seg;
1338 last_seg = rxq->pkt_last_seg;
1340 while (nb_rx < nb_pkts) {
1343 * The order of operations here is important as the DD status
1344 * bit must not be read after any other descriptor fields.
1345 * rx_ring and rxdp are pointing to volatile data so the order
1346 * of accesses cannot be reordered by the compiler. If they were
1347 * not volatile, they could be reordered which could lead to
1348 * using invalid descriptor fields when read from rxd.
1350 rxdp = &rx_ring[rx_id];
1351 staterr = rxdp->wb.upper.status_error;
1352 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1359 * Allocate a new mbuf to replenish the RX ring descriptor.
1360 * If the allocation fails:
1361 * - arrange for that RX descriptor to be the first one
1362 * being parsed the next time the receive function is
1363 * invoked [on the same queue].
1365 * - Stop parsing the RX ring and return immediately.
1367 * This policy does not drop the packet received in the RX
1368 * descriptor for which the allocation of a new mbuf failed.
1369 * Thus, it allows that packet to be later retrieved if
1370 * mbuf have been freed in the mean time.
1371 * As a side effect, holding RX descriptors instead of
1372 * systematically giving them back to the NIC may lead to
1373 * RX ring exhaustion situations.
1374 * However, the NIC can gracefully prevent such situations
1375 * to happen by sending specific "back-pressure" flow control
1376 * frames to its peer(s).
1378 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
1379 "staterr=0x%x data_len=%u\n",
1380 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1381 (unsigned) rx_id, (unsigned) staterr,
1382 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1384 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1386 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1387 "queue_id=%u\n", (unsigned) rxq->port_id,
1388 (unsigned) rxq->queue_id);
1389 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1394 rxe = &sw_ring[rx_id];
1396 if (rx_id == rxq->nb_rx_desc)
1399 /* Prefetch next mbuf while processing current one. */
1400 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1403 * When next RX descriptor is on a cache-line boundary,
1404 * prefetch the next 4 RX descriptors and the next 8 pointers
1407 if ((rx_id & 0x3) == 0) {
1408 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1409 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1413 * Update RX descriptor with the physical address of the new
1414 * data buffer of the new allocated mbuf.
1418 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1419 rxdp->read.hdr_addr = dma;
1420 rxdp->read.pkt_addr = dma;
1423 * Set data length & data buffer address of mbuf.
1425 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1426 rxm->pkt.data_len = data_len;
1427 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1430 * If this is the first buffer of the received packet,
1431 * set the pointer to the first mbuf of the packet and
1432 * initialize its context.
1433 * Otherwise, update the total length and the number of segments
1434 * of the current scattered packet, and update the pointer to
1435 * the last mbuf of the current packet.
1437 if (first_seg == NULL) {
1439 first_seg->pkt.pkt_len = data_len;
1440 first_seg->pkt.nb_segs = 1;
1442 first_seg->pkt.pkt_len = (uint16_t)(first_seg->pkt.pkt_len
1444 first_seg->pkt.nb_segs++;
1445 last_seg->pkt.next = rxm;
1449 * If this is not the last buffer of the received packet,
1450 * update the pointer to the last mbuf of the current scattered
1451 * packet and continue to parse the RX ring.
1453 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1459 * This is the last buffer of the received packet.
1460 * If the CRC is not stripped by the hardware:
1461 * - Subtract the CRC length from the total packet length.
1462 * - If the last buffer only contains the whole CRC or a part
1463 * of it, free the mbuf associated to the last buffer.
1464 * If part of the CRC is also contained in the previous
1465 * mbuf, subtract the length of that CRC part from the
1466 * data length of the previous mbuf.
1468 rxm->pkt.next = NULL;
1469 if (unlikely(rxq->crc_len > 0)) {
1470 first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
1471 if (data_len <= ETHER_CRC_LEN) {
1472 rte_pktmbuf_free_seg(rxm);
1473 first_seg->pkt.nb_segs--;
1474 last_seg->pkt.data_len = (uint16_t)
1475 (last_seg->pkt.data_len -
1476 (ETHER_CRC_LEN - data_len));
1477 last_seg->pkt.next = NULL;
1480 (uint16_t) (data_len - ETHER_CRC_LEN);
1484 * Initialize the first mbuf of the returned packet:
1485 * - RX port identifier,
1486 * - hardware offload data, if any:
1487 * - RSS flag & hash,
1488 * - IP checksum flag,
1489 * - VLAN TCI, if any,
1492 first_seg->pkt.in_port = rxq->port_id;
1495 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1496 * set in the pkt_flags field.
1498 first_seg->pkt.vlan_macip.f.vlan_tci =
1499 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1500 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1501 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1502 pkt_flags = (uint16_t)(pkt_flags |
1503 rx_desc_status_to_pkt_flags(staterr));
1504 pkt_flags = (uint16_t)(pkt_flags |
1505 rx_desc_error_to_pkt_flags(staterr));
1506 first_seg->ol_flags = pkt_flags;
1508 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1509 first_seg->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1510 else if (pkt_flags & PKT_RX_FDIR) {
1511 first_seg->pkt.hash.fdir.hash =
1512 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1513 & IXGBE_ATR_HASH_MASK);
1514 first_seg->pkt.hash.fdir.id =
1515 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1518 /* Prefetch data of first segment, if configured to do so. */
1519 rte_packet_prefetch(first_seg->pkt.data);
1522 * Store the mbuf address into the next entry of the array
1523 * of returned packets.
1525 rx_pkts[nb_rx++] = first_seg;
1528 * Setup receipt context for a new packet.
1534 * Record index of the next RX descriptor to probe.
1536 rxq->rx_tail = rx_id;
1539 * Save receive context.
1541 rxq->pkt_first_seg = first_seg;
1542 rxq->pkt_last_seg = last_seg;
1545 * If the number of free RX descriptors is greater than the RX free
1546 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1548 * Update the RDT with the value of the last processed RX descriptor
1549 * minus 1, to guarantee that the RDT register is never equal to the
1550 * RDH register, which creates a "full" ring situtation from the
1551 * hardware point of view...
1553 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1554 if (nb_hold > rxq->rx_free_thresh) {
1555 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1556 "nb_hold=%u nb_rx=%u\n",
1557 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1558 (unsigned) rx_id, (unsigned) nb_hold,
1560 rx_id = (uint16_t) ((rx_id == 0) ?
1561 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1562 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1565 rxq->nb_rx_hold = nb_hold;
1569 /*********************************************************************
1571 * Queue management functions
1573 **********************************************************************/
1576 * Rings setup and release.
1578 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1579 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1580 * also optimize cache line size effect. H/W supports up to cache line size 128.
1582 #define IXGBE_ALIGN 128
1585 * Maximum number of Ring Descriptors.
1587 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1588 * descriptors should meet the following condition:
1589 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1591 #define IXGBE_MIN_RING_DESC 32
1592 #define IXGBE_MAX_RING_DESC 4096
1595 * Create memzone for HW rings. malloc can't be used as the physical address is
1596 * needed. If the memzone is already created, then this function returns a ptr
1599 static const struct rte_memzone *
1600 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1601 uint16_t queue_id, uint32_t ring_size, int socket_id)
1603 char z_name[RTE_MEMZONE_NAMESIZE];
1604 const struct rte_memzone *mz;
1606 rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1607 dev->driver->pci_drv.name, ring_name,
1608 dev->data->port_id, queue_id);
1610 mz = rte_memzone_lookup(z_name);
1614 #ifdef RTE_LIBRTE_XEN_DOM0
1615 return rte_memzone_reserve_bounded(z_name, ring_size,
1616 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1618 return rte_memzone_reserve_aligned(z_name, ring_size,
1619 socket_id, 0, IXGBE_ALIGN);
1624 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1628 if (txq->sw_ring != NULL) {
1629 for (i = 0; i < txq->nb_tx_desc; i++) {
1630 if (txq->sw_ring[i].mbuf != NULL) {
1631 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1632 txq->sw_ring[i].mbuf = NULL;
1639 ixgbe_tx_free_swring(struct igb_tx_queue *txq)
1642 txq->sw_ring != NULL)
1643 rte_free(txq->sw_ring);
1647 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1649 if (txq != NULL && txq->ops != NULL) {
1650 txq->ops->release_mbufs(txq);
1651 txq->ops->free_swring(txq);
1657 ixgbe_dev_tx_queue_release(void *txq)
1659 ixgbe_tx_queue_release(txq);
1662 /* (Re)set dynamic igb_tx_queue fields to defaults */
1664 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1666 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1668 struct igb_tx_entry *txe = txq->sw_ring;
1671 /* Zero out HW ring memory */
1672 for (i = 0; i < txq->nb_tx_desc; i++) {
1673 txq->tx_ring[i] = zeroed_desc;
1676 /* Initialize SW ring entries */
1677 prev = (uint16_t) (txq->nb_tx_desc - 1);
1678 for (i = 0; i < txq->nb_tx_desc; i++) {
1679 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1680 txd->wb.status = IXGBE_TXD_STAT_DD;
1683 txe[prev].next_id = i;
1687 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1688 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1691 txq->nb_tx_used = 0;
1693 * Always allow 1 descriptor to be un-allocated to avoid
1694 * a H/W race condition
1696 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1697 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1699 memset((void*)&txq->ctx_cache, 0,
1700 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1703 static struct ixgbe_txq_ops def_txq_ops = {
1704 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1705 .free_swring = ixgbe_tx_free_swring,
1706 .reset = ixgbe_reset_tx_queue,
1710 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1713 unsigned int socket_id,
1714 const struct rte_eth_txconf *tx_conf)
1716 const struct rte_memzone *tz;
1717 struct igb_tx_queue *txq;
1718 struct ixgbe_hw *hw;
1719 uint16_t tx_rs_thresh, tx_free_thresh;
1721 PMD_INIT_FUNC_TRACE();
1722 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1725 * Validate number of transmit descriptors.
1726 * It must not exceed hardware maximum, and must be multiple
1729 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1730 (nb_desc > IXGBE_MAX_RING_DESC) ||
1731 (nb_desc < IXGBE_MIN_RING_DESC)) {
1736 * The following two parameters control the setting of the RS bit on
1737 * transmit descriptors.
1738 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1739 * descriptors have been used.
1740 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1741 * descriptors are used or if the number of descriptors required
1742 * to transmit a packet is greater than the number of free TX
1744 * The following constraints must be satisfied:
1745 * tx_rs_thresh must be greater than 0.
1746 * tx_rs_thresh must be less than the size of the ring minus 2.
1747 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1748 * tx_rs_thresh must be a divisor of the ring size.
1749 * tx_free_thresh must be greater than 0.
1750 * tx_free_thresh must be less than the size of the ring minus 3.
1751 * One descriptor in the TX ring is used as a sentinel to avoid a
1752 * H/W race condition, hence the maximum threshold constraints.
1753 * When set to zero use default values.
1755 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1756 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1757 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1758 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1759 if (tx_rs_thresh >= (nb_desc - 2)) {
1760 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the number "
1761 "of TX descriptors minus 2. (tx_rs_thresh=%u port=%d "
1762 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1763 (int)dev->data->port_id, (int)queue_idx);
1766 if (tx_free_thresh >= (nb_desc - 3)) {
1767 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the "
1768 "tx_free_thresh must be less than the number of TX "
1769 "descriptors minus 3. (tx_free_thresh=%u port=%d "
1770 "queue=%d)\n", (unsigned int)tx_free_thresh,
1771 (int)dev->data->port_id, (int)queue_idx);
1774 if (tx_rs_thresh > tx_free_thresh) {
1775 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than or equal to "
1776 "tx_free_thresh. (tx_free_thresh=%u tx_rs_thresh=%u "
1777 "port=%d queue=%d)\n", (unsigned int)tx_free_thresh,
1778 (unsigned int)tx_rs_thresh, (int)dev->data->port_id,
1782 if ((nb_desc % tx_rs_thresh) != 0) {
1783 RTE_LOG(ERR, PMD, "tx_rs_thresh must be a divisor of the "
1784 "number of TX descriptors. (tx_rs_thresh=%u port=%d "
1785 "queue=%d)\n", (unsigned int)tx_rs_thresh,
1786 (int)dev->data->port_id, (int)queue_idx);
1791 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1792 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1793 * by the NIC and all descriptors are written back after the NIC
1794 * accumulates WTHRESH descriptors.
1796 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1797 RTE_LOG(ERR, PMD, "TX WTHRESH must be set to 0 if "
1798 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1799 "port=%d queue=%d)\n", (unsigned int)tx_rs_thresh,
1800 (int)dev->data->port_id, (int)queue_idx);
1804 /* Free memory prior to re-allocation if needed... */
1805 if (dev->data->tx_queues[queue_idx] != NULL)
1806 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1808 /* First allocate the tx queue data structure */
1809 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1810 CACHE_LINE_SIZE, socket_id);
1815 * Allocate TX ring hardware descriptors. A memzone large enough to
1816 * handle the maximum ring size is allocated in order to allow for
1817 * resizing in later calls to the queue setup function.
1819 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1820 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1823 ixgbe_tx_queue_release(txq);
1827 txq->nb_tx_desc = nb_desc;
1828 txq->tx_rs_thresh = tx_rs_thresh;
1829 txq->tx_free_thresh = tx_free_thresh;
1830 txq->pthresh = tx_conf->tx_thresh.pthresh;
1831 txq->hthresh = tx_conf->tx_thresh.hthresh;
1832 txq->wthresh = tx_conf->tx_thresh.wthresh;
1833 txq->queue_id = queue_idx;
1834 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1835 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1836 txq->port_id = dev->data->port_id;
1837 txq->txq_flags = tx_conf->txq_flags;
1838 txq->ops = &def_txq_ops;
1839 txq->start_tx_per_q = tx_conf->start_tx_per_q;
1842 * Modification to set VFTDT for virtual function if vf is detected
1844 if (hw->mac.type == ixgbe_mac_82599_vf)
1845 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1847 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1848 #ifndef RTE_LIBRTE_XEN_DOM0
1849 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1851 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1853 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1855 /* Allocate software ring */
1856 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1857 sizeof(struct igb_tx_entry) * nb_desc,
1858 CACHE_LINE_SIZE, socket_id);
1859 if (txq->sw_ring == NULL) {
1860 ixgbe_tx_queue_release(txq);
1863 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1864 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1866 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1867 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
1868 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1869 PMD_INIT_LOG(INFO, "Using simple tx code path\n");
1870 #ifdef RTE_IXGBE_INC_VECTOR
1871 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1872 ixgbe_txq_vec_setup(txq, socket_id) == 0) {
1873 PMD_INIT_LOG(INFO, "Vector tx enabled.\n");
1874 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1878 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1880 PMD_INIT_LOG(INFO, "Using full-featured tx code path\n");
1881 PMD_INIT_LOG(INFO, " - txq_flags = %lx [IXGBE_SIMPLE_FLAGS=%lx]\n", (long unsigned)txq->txq_flags, (long unsigned)IXGBE_SIMPLE_FLAGS);
1882 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu [RTE_PMD_IXGBE_TX_MAX_BURST=%lu]\n", (long unsigned)txq->tx_rs_thresh, (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
1883 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1886 txq->ops->reset(txq);
1888 dev->data->tx_queues[queue_idx] = txq;
1895 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1899 if (rxq->sw_ring != NULL) {
1900 for (i = 0; i < rxq->nb_rx_desc; i++) {
1901 if (rxq->sw_ring[i].mbuf != NULL) {
1902 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1903 rxq->sw_ring[i].mbuf = NULL;
1906 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1907 if (rxq->rx_nb_avail) {
1908 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1909 struct rte_mbuf *mb;
1910 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1911 rte_pktmbuf_free_seg(mb);
1913 rxq->rx_nb_avail = 0;
1920 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
1923 ixgbe_rx_queue_release_mbufs(rxq);
1924 rte_free(rxq->sw_ring);
1930 ixgbe_dev_rx_queue_release(void *rxq)
1932 ixgbe_rx_queue_release(rxq);
1936 * Check if Rx Burst Bulk Alloc function can be used.
1938 * 0: the preconditions are satisfied and the bulk allocation function
1940 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
1941 * function must be used.
1944 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1945 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
1947 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
1953 * Make sure the following pre-conditions are satisfied:
1954 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
1955 * rxq->rx_free_thresh < rxq->nb_rx_desc
1956 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
1957 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
1958 * Scattered packets are not supported. This should be checked
1959 * outside of this function.
1961 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1962 if (! (rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST))
1964 else if (! (rxq->rx_free_thresh < rxq->nb_rx_desc))
1966 else if (! ((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0))
1968 else if (! (rxq->nb_rx_desc <
1969 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST)))
1978 /* Reset dynamic igb_rx_queue fields back to defaults */
1980 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
1982 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
1988 * By default, the Rx queue setup function allocates enough memory for
1989 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
1990 * extra memory at the end of the descriptor ring to be zero'd out. A
1991 * pre-condition for using the Rx burst bulk alloc function is that the
1992 * number of descriptors is less than or equal to
1993 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
1994 * constraints here to see if we need to zero out memory after the end
1995 * of the H/W descriptor ring.
1997 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1998 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
1999 /* zero out extra memory */
2000 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2003 /* do not zero out extra memory */
2004 len = rxq->nb_rx_desc;
2007 * Zero out HW ring memory. Zero out extra memory at the end of
2008 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2009 * reads extra memory as zeros.
2011 for (i = 0; i < len; i++) {
2012 rxq->rx_ring[i] = zeroed_desc;
2015 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2017 * initialize extra software ring entries. Space for these extra
2018 * entries is always allocated
2020 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2021 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2022 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2025 rxq->rx_nb_avail = 0;
2026 rxq->rx_next_avail = 0;
2027 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2028 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2030 rxq->nb_rx_hold = 0;
2031 rxq->pkt_first_seg = NULL;
2032 rxq->pkt_last_seg = NULL;
2036 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2039 unsigned int socket_id,
2040 const struct rte_eth_rxconf *rx_conf,
2041 struct rte_mempool *mp)
2043 const struct rte_memzone *rz;
2044 struct igb_rx_queue *rxq;
2045 struct ixgbe_hw *hw;
2046 int use_def_burst_func = 1;
2049 PMD_INIT_FUNC_TRACE();
2050 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053 * Validate number of receive descriptors.
2054 * It must not exceed hardware maximum, and must be multiple
2057 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2058 (nb_desc > IXGBE_MAX_RING_DESC) ||
2059 (nb_desc < IXGBE_MIN_RING_DESC)) {
2063 /* Free memory prior to re-allocation if needed... */
2064 if (dev->data->rx_queues[queue_idx] != NULL)
2065 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2067 /* First allocate the rx queue data structure */
2068 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2069 CACHE_LINE_SIZE, socket_id);
2073 rxq->nb_rx_desc = nb_desc;
2074 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2075 rxq->queue_id = queue_idx;
2076 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2077 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2078 rxq->port_id = dev->data->port_id;
2079 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2081 rxq->drop_en = rx_conf->rx_drop_en;
2082 rxq->start_rx_per_q = rx_conf->start_rx_per_q;
2085 * Allocate RX ring hardware descriptors. A memzone large enough to
2086 * handle the maximum ring size is allocated in order to allow for
2087 * resizing in later calls to the queue setup function.
2089 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2090 RX_RING_SZ, socket_id);
2092 ixgbe_rx_queue_release(rxq);
2097 * Zero init all the descriptors in the ring.
2099 memset (rz->addr, 0, RX_RING_SZ);
2102 * Modified to setup VFRDT for Virtual Function
2104 if (hw->mac.type == ixgbe_mac_82599_vf) {
2106 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2108 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2112 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2114 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2116 #ifndef RTE_LIBRTE_XEN_DOM0
2117 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2119 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2121 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2124 * Allocate software ring. Allow for space at the end of the
2125 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2126 * function does not access an invalid memory region.
2128 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2129 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2133 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2134 sizeof(struct igb_rx_entry) * len,
2135 CACHE_LINE_SIZE, socket_id);
2136 if (rxq->sw_ring == NULL) {
2137 ixgbe_rx_queue_release(rxq);
2140 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
2141 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2144 * Certain constraints must be met in order to use the bulk buffer
2145 * allocation Rx burst function.
2147 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2149 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2150 if (!use_def_burst_func && !dev->data->scattered_rx) {
2151 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2152 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2153 "satisfied. Rx Burst Bulk Alloc function will be "
2154 "used on port=%d, queue=%d.\n",
2155 rxq->port_id, rxq->queue_id);
2156 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2157 #ifdef RTE_IXGBE_INC_VECTOR
2158 if (!ixgbe_rx_vec_condition_check(dev)) {
2159 PMD_INIT_LOG(INFO, "Vector rx enabled.\n");
2160 ixgbe_rxq_vec_setup(rxq, socket_id);
2161 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
2166 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2167 "are not satisfied, Scattered Rx is requested, "
2168 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2169 "enabled (port=%d, queue=%d).\n",
2170 rxq->port_id, rxq->queue_id);
2172 dev->data->rx_queues[queue_idx] = rxq;
2174 ixgbe_reset_rx_queue(rxq);
2180 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2182 #define IXGBE_RXQ_SCAN_INTERVAL 4
2183 volatile union ixgbe_adv_rx_desc *rxdp;
2184 struct igb_rx_queue *rxq;
2187 if (rx_queue_id >= dev->data->nb_rx_queues) {
2188 PMD_RX_LOG(ERR, "Invalid RX queue id=%d\n", rx_queue_id);
2192 rxq = dev->data->rx_queues[rx_queue_id];
2193 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2195 while ((desc < rxq->nb_rx_desc) &&
2196 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2197 desc += IXGBE_RXQ_SCAN_INTERVAL;
2198 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2199 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2200 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2201 desc - rxq->nb_rx_desc]);
2208 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2210 volatile union ixgbe_adv_rx_desc *rxdp;
2211 struct igb_rx_queue *rxq = rx_queue;
2214 if (unlikely(offset >= rxq->nb_rx_desc))
2216 desc = rxq->rx_tail + offset;
2217 if (desc >= rxq->nb_rx_desc)
2218 desc -= rxq->nb_rx_desc;
2220 rxdp = &rxq->rx_ring[desc];
2221 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2225 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2229 PMD_INIT_FUNC_TRACE();
2231 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2232 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2234 txq->ops->release_mbufs(txq);
2235 txq->ops->reset(txq);
2239 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2240 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2242 ixgbe_rx_queue_release_mbufs(rxq);
2243 ixgbe_reset_rx_queue(rxq);
2248 /*********************************************************************
2250 * Device RX/TX init functions
2252 **********************************************************************/
2255 * Receive Side Scaling (RSS)
2256 * See section 7.1.2.8 in the following document:
2257 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2260 * The source and destination IP addresses of the IP header and the source
2261 * and destination ports of TCP/UDP headers, if any, of received packets are
2262 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2263 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2264 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2265 * RSS output index which is used as the RX queue index where to store the
2267 * The following output is supplied in the RX write-back descriptor:
2268 * - 32-bit result of the Microsoft RSS hash function,
2269 * - 4-bit RSS type field.
2273 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2274 * Used as the default key.
2276 static uint8_t rss_intel_key[40] = {
2277 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2278 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2279 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2280 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2281 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2285 ixgbe_rss_disable(struct rte_eth_dev *dev)
2287 struct ixgbe_hw *hw;
2290 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2292 mrqc &= ~IXGBE_MRQC_RSSEN;
2293 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2297 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2305 hash_key = rss_conf->rss_key;
2306 if (hash_key != NULL) {
2307 /* Fill in RSS hash key */
2308 for (i = 0; i < 10; i++) {
2309 rss_key = hash_key[(i * 4)];
2310 rss_key |= hash_key[(i * 4) + 1] << 8;
2311 rss_key |= hash_key[(i * 4) + 2] << 16;
2312 rss_key |= hash_key[(i * 4) + 3] << 24;
2313 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2317 /* Set configured hashing protocols in MRQC register */
2318 rss_hf = rss_conf->rss_hf;
2319 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2320 if (rss_hf & ETH_RSS_IPV4)
2321 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2322 if (rss_hf & ETH_RSS_IPV4_TCP)
2323 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2324 if (rss_hf & ETH_RSS_IPV6)
2325 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2326 if (rss_hf & ETH_RSS_IPV6_EX)
2327 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2328 if (rss_hf & ETH_RSS_IPV6_TCP)
2329 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2330 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2331 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2332 if (rss_hf & ETH_RSS_IPV4_UDP)
2333 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2334 if (rss_hf & ETH_RSS_IPV6_UDP)
2335 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2336 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2337 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2338 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2342 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2343 struct rte_eth_rss_conf *rss_conf)
2345 struct ixgbe_hw *hw;
2349 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2352 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2353 * "RSS enabling cannot be done dynamically while it must be
2354 * preceded by a software reset"
2355 * Before changing anything, first check that the update RSS operation
2356 * does not attempt to disable RSS, if RSS was enabled at
2357 * initialization time, or does not attempt to enable RSS, if RSS was
2358 * disabled at initialization time.
2360 rss_hf = rss_conf->rss_hf;
2361 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2362 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2363 if (rss_hf != 0) /* Enable RSS */
2365 return 0; /* Nothing to do */
2368 if (rss_hf == 0) /* Disable RSS */
2370 ixgbe_hw_rss_hash_set(hw, rss_conf);
2375 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2376 struct rte_eth_rss_conf *rss_conf)
2378 struct ixgbe_hw *hw;
2385 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2386 hash_key = rss_conf->rss_key;
2387 if (hash_key != NULL) {
2388 /* Return RSS hash key */
2389 for (i = 0; i < 10; i++) {
2390 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2391 hash_key[(i * 4)] = rss_key & 0x000000FF;
2392 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2393 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2394 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2398 /* Get RSS functions configured in MRQC register */
2399 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2400 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2401 rss_conf->rss_hf = 0;
2405 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2406 rss_hf |= ETH_RSS_IPV4;
2407 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2408 rss_hf |= ETH_RSS_IPV4_TCP;
2409 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2410 rss_hf |= ETH_RSS_IPV6;
2411 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2412 rss_hf |= ETH_RSS_IPV6_EX;
2413 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2414 rss_hf |= ETH_RSS_IPV6_TCP;
2415 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2416 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2417 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2418 rss_hf |= ETH_RSS_IPV4_UDP;
2419 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2420 rss_hf |= ETH_RSS_IPV6_UDP;
2421 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2422 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2423 rss_conf->rss_hf = rss_hf;
2428 ixgbe_rss_configure(struct rte_eth_dev *dev)
2430 struct rte_eth_rss_conf rss_conf;
2431 struct ixgbe_hw *hw;
2436 PMD_INIT_FUNC_TRACE();
2437 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2440 * Fill in redirection table
2441 * The byte-swap is needed because NIC registers are in
2442 * little-endian order.
2445 for (i = 0, j = 0; i < 128; i++, j++) {
2446 if (j == dev->data->nb_rx_queues)
2448 reta = (reta << 8) | j;
2450 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2455 * Configure the RSS key and the RSS protocols used to compute
2456 * the RSS hash of input packets.
2458 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2459 if (rss_conf.rss_hf == 0) {
2460 ixgbe_rss_disable(dev);
2463 if (rss_conf.rss_key == NULL)
2464 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2465 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2468 #define NUM_VFTA_REGISTERS 128
2469 #define NIC_RX_BUFFER_SIZE 0x200
2472 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2474 struct rte_eth_vmdq_dcb_conf *cfg;
2475 struct ixgbe_hw *hw;
2476 enum rte_eth_nb_pools num_pools;
2477 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2479 uint8_t nb_tcs; /* number of traffic classes */
2482 PMD_INIT_FUNC_TRACE();
2483 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2484 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2485 num_pools = cfg->nb_queue_pools;
2486 /* Check we have a valid number of pools */
2487 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2488 ixgbe_rss_disable(dev);
2491 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2492 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2496 * split rx buffer up into sections, each for 1 traffic class
2498 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2499 for (i = 0 ; i < nb_tcs; i++) {
2500 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2501 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2502 /* clear 10 bits. */
2503 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2504 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2506 /* zero alloc all unused TCs */
2507 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2508 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2509 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2510 /* clear 10 bits. */
2511 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2514 /* MRQC: enable vmdq and dcb */
2515 mrqc = ((num_pools == ETH_16_POOLS) ? \
2516 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2517 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2519 /* PFVTCTL: turn on virtualisation and set the default pool */
2520 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2521 if (cfg->enable_default_pool) {
2522 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2524 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2527 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2529 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2531 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2533 * mapping is done with 3 bits per priority,
2534 * so shift by i*3 each time
2536 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2538 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2540 /* RTRPCS: DCB related */
2541 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2543 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2544 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2545 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2546 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2548 /* VFTA - enable all vlan filters */
2549 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2550 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2553 /* VFRE: pool enabling for receive - 16 or 32 */
2554 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2555 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2558 * MPSAR - allow pools to read specific mac addresses
2559 * In this case, all pools should be able to read from mac addr 0
2561 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2562 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2564 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2565 for (i = 0; i < cfg->nb_pool_maps; i++) {
2566 /* set vlan id in VF register and set the valid bit */
2567 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2568 (cfg->pool_map[i].vlan_id & 0xFFF)));
2570 * Put the allowed pools in VFB reg. As we only have 16 or 32
2571 * pools, we only need to use the first half of the register
2574 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2579 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2580 * @hw: pointer to hardware structure
2581 * @dcb_config: pointer to ixgbe_dcb_config structure
2584 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2585 struct ixgbe_dcb_config *dcb_config)
2590 PMD_INIT_FUNC_TRACE();
2591 if (hw->mac.type != ixgbe_mac_82598EB) {
2592 /* Disable the Tx desc arbiter so that MTQC can be changed */
2593 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2594 reg |= IXGBE_RTTDCS_ARBDIS;
2595 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2597 /* Enable DCB for Tx with 8 TCs */
2598 if (dcb_config->num_tcs.pg_tcs == 8) {
2599 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2602 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2604 if (dcb_config->vt_mode)
2605 reg |= IXGBE_MTQC_VT_ENA;
2606 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2608 /* Disable drop for all queues */
2609 for (q = 0; q < 128; q++)
2610 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2611 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2613 /* Enable the Tx desc arbiter */
2614 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2615 reg &= ~IXGBE_RTTDCS_ARBDIS;
2616 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2618 /* Enable Security TX Buffer IFG for DCB */
2619 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2620 reg |= IXGBE_SECTX_DCB;
2621 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2627 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2628 * @dev: pointer to rte_eth_dev structure
2629 * @dcb_config: pointer to ixgbe_dcb_config structure
2632 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2633 struct ixgbe_dcb_config *dcb_config)
2635 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2636 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2637 struct ixgbe_hw *hw =
2638 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640 PMD_INIT_FUNC_TRACE();
2641 if (hw->mac.type != ixgbe_mac_82598EB)
2642 /*PF VF Transmit Enable*/
2643 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2644 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2646 /*Configure general DCB TX parameters*/
2647 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2652 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2653 struct ixgbe_dcb_config *dcb_config)
2655 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2656 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2657 struct ixgbe_dcb_tc_config *tc;
2660 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2661 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2662 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2663 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2666 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2667 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2669 /* User Priority to Traffic Class mapping */
2670 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2671 j = vmdq_rx_conf->dcb_queue[i];
2672 tc = &dcb_config->tc_config[j];
2673 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2679 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2680 struct ixgbe_dcb_config *dcb_config)
2682 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2683 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2684 struct ixgbe_dcb_tc_config *tc;
2687 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2688 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2689 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2690 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2693 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2694 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2697 /* User Priority to Traffic Class mapping */
2698 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2699 j = vmdq_tx_conf->dcb_queue[i];
2700 tc = &dcb_config->tc_config[j];
2701 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2708 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2709 struct ixgbe_dcb_config *dcb_config)
2711 struct rte_eth_dcb_rx_conf *rx_conf =
2712 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2713 struct ixgbe_dcb_tc_config *tc;
2716 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2717 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2719 /* User Priority to Traffic Class mapping */
2720 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2721 j = rx_conf->dcb_queue[i];
2722 tc = &dcb_config->tc_config[j];
2723 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2729 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2730 struct ixgbe_dcb_config *dcb_config)
2732 struct rte_eth_dcb_tx_conf *tx_conf =
2733 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2734 struct ixgbe_dcb_tc_config *tc;
2737 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2738 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2740 /* User Priority to Traffic Class mapping */
2741 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2742 j = tx_conf->dcb_queue[i];
2743 tc = &dcb_config->tc_config[j];
2744 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2750 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2751 * @hw: pointer to hardware structure
2752 * @dcb_config: pointer to ixgbe_dcb_config structure
2755 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2756 struct ixgbe_dcb_config *dcb_config)
2762 PMD_INIT_FUNC_TRACE();
2764 * Disable the arbiter before changing parameters
2765 * (always enable recycle mode; WSP)
2767 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2768 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2770 if (hw->mac.type != ixgbe_mac_82598EB) {
2771 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2772 if (dcb_config->num_tcs.pg_tcs == 4) {
2773 if (dcb_config->vt_mode)
2774 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2775 IXGBE_MRQC_VMDQRT4TCEN;
2777 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2778 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2782 if (dcb_config->num_tcs.pg_tcs == 8) {
2783 if (dcb_config->vt_mode)
2784 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2785 IXGBE_MRQC_VMDQRT8TCEN;
2787 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2788 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2793 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2796 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2797 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2798 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2799 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2801 /* VFTA - enable all vlan filters */
2802 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2803 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2807 * Configure Rx packet plane (recycle mode; WSP) and
2810 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2811 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2817 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2818 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2820 switch (hw->mac.type) {
2821 case ixgbe_mac_82598EB:
2822 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2824 case ixgbe_mac_82599EB:
2825 case ixgbe_mac_X540:
2826 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2835 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2836 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2838 switch (hw->mac.type) {
2839 case ixgbe_mac_82598EB:
2840 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2841 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2843 case ixgbe_mac_82599EB:
2844 case ixgbe_mac_X540:
2845 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2846 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2853 #define DCB_RX_CONFIG 1
2854 #define DCB_TX_CONFIG 1
2855 #define DCB_TX_PB 1024
2857 * ixgbe_dcb_hw_configure - Enable DCB and configure
2858 * general DCB in VT mode and non-VT mode parameters
2859 * @dev: pointer to rte_eth_dev structure
2860 * @dcb_config: pointer to ixgbe_dcb_config structure
2863 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2864 struct ixgbe_dcb_config *dcb_config)
2867 uint8_t i,pfc_en,nb_tcs;
2869 uint8_t config_dcb_rx = 0;
2870 uint8_t config_dcb_tx = 0;
2871 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2872 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2873 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2874 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2875 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2876 struct ixgbe_dcb_tc_config *tc;
2877 uint32_t max_frame = dev->data->max_frame_size;
2878 struct ixgbe_hw *hw =
2879 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2881 switch(dev->data->dev_conf.rxmode.mq_mode){
2882 case ETH_MQ_RX_VMDQ_DCB:
2883 dcb_config->vt_mode = true;
2884 if (hw->mac.type != ixgbe_mac_82598EB) {
2885 config_dcb_rx = DCB_RX_CONFIG;
2887 *get dcb and VT rx configuration parameters
2890 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2891 /*Configure general VMDQ and DCB RX parameters*/
2892 ixgbe_vmdq_dcb_configure(dev);
2896 dcb_config->vt_mode = false;
2897 config_dcb_rx = DCB_RX_CONFIG;
2898 /* Get dcb TX configuration parameters from rte_eth_conf */
2899 ixgbe_dcb_rx_config(dev,dcb_config);
2900 /*Configure general DCB RX parameters*/
2901 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2904 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration\n");
2907 switch (dev->data->dev_conf.txmode.mq_mode) {
2908 case ETH_MQ_TX_VMDQ_DCB:
2909 dcb_config->vt_mode = true;
2910 config_dcb_tx = DCB_TX_CONFIG;
2911 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2912 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2913 /*Configure general VMDQ and DCB TX parameters*/
2914 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2918 dcb_config->vt_mode = false;
2919 config_dcb_tx = DCB_TX_CONFIG;
2920 /*get DCB TX configuration parameters from rte_eth_conf*/
2921 ixgbe_dcb_tx_config(dev,dcb_config);
2922 /*Configure general DCB TX parameters*/
2923 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2926 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration\n");
2930 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2932 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2933 if(nb_tcs == ETH_4_TCS) {
2934 /* Avoid un-configured priority mapping to TC0 */
2936 uint8_t mask = 0xFF;
2937 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2938 mask = (uint8_t)(mask & (~ (1 << map[i])));
2939 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2940 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2944 /* Re-configure 4 TCs BW */
2945 for (i = 0; i < nb_tcs; i++) {
2946 tc = &dcb_config->tc_config[i];
2947 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
2948 (uint8_t)(100 / nb_tcs);
2949 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
2950 (uint8_t)(100 / nb_tcs);
2952 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2953 tc = &dcb_config->tc_config[i];
2954 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
2955 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
2960 /* Set RX buffer size */
2961 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2962 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
2963 for (i = 0 ; i < nb_tcs; i++) {
2964 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2966 /* zero alloc all unused TCs */
2967 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2968 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
2972 /* Only support an equally distributed Tx packet buffer strategy. */
2973 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
2974 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
2975 for (i = 0; i < nb_tcs; i++) {
2976 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
2977 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
2979 /* Clear unused TCs, if any, to zero buffer size*/
2980 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2981 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
2982 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
2986 /*Calculates traffic class credits*/
2987 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2988 IXGBE_DCB_TX_CONFIG);
2989 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2990 IXGBE_DCB_RX_CONFIG);
2993 /* Unpack CEE standard containers */
2994 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
2995 ixgbe_dcb_unpack_max_cee(dcb_config, max);
2996 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
2997 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
2998 /* Configure PG(ETS) RX */
2999 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3003 /* Unpack CEE standard containers */
3004 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3005 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3006 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3007 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3008 /* Configure PG(ETS) TX */
3009 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3012 /*Configure queue statistics registers*/
3013 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3015 /* Check if the PFC is supported */
3016 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3017 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3018 for (i = 0; i < nb_tcs; i++) {
3020 * If the TC count is 8,and the default high_water is 48,
3021 * the low_water is 16 as default.
3023 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3024 hw->fc.low_water[i] = pbsize / 4;
3025 /* Enable pfc for this TC */
3026 tc = &dcb_config->tc_config[i];
3027 tc->pfc = ixgbe_dcb_pfc_enabled;
3029 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3030 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3032 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3039 * ixgbe_configure_dcb - Configure DCB Hardware
3040 * @dev: pointer to rte_eth_dev
3042 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3044 struct ixgbe_dcb_config *dcb_cfg =
3045 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3046 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3048 PMD_INIT_FUNC_TRACE();
3050 /* check support mq_mode for DCB */
3051 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3052 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3055 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3058 /** Configure DCB hardware **/
3059 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3065 * VMDq only support for 10 GbE NIC.
3068 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3070 struct rte_eth_vmdq_rx_conf *cfg;
3071 struct ixgbe_hw *hw;
3072 enum rte_eth_nb_pools num_pools;
3073 uint32_t mrqc, vt_ctl, vlanctrl;
3076 PMD_INIT_FUNC_TRACE();
3077 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3078 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3079 num_pools = cfg->nb_queue_pools;
3081 ixgbe_rss_disable(dev);
3083 /* MRQC: enable vmdq */
3084 mrqc = IXGBE_MRQC_VMDQEN;
3085 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3087 /* PFVTCTL: turn on virtualisation and set the default pool */
3088 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3089 if (cfg->enable_default_pool)
3090 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3092 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3094 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3096 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3097 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3098 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3099 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3101 /* VFTA - enable all vlan filters */
3102 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3103 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3105 /* VFRE: pool enabling for receive - 64 */
3106 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3107 if (num_pools == ETH_64_POOLS)
3108 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3111 * MPSAR - allow pools to read specific mac addresses
3112 * In this case, all pools should be able to read from mac addr 0
3114 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3115 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3117 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3118 for (i = 0; i < cfg->nb_pool_maps; i++) {
3119 /* set vlan id in VF register and set the valid bit */
3120 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3121 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3123 * Put the allowed pools in VFB reg. As we only have 16 or 64
3124 * pools, we only need to use the first half of the register
3127 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3128 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3129 (cfg->pool_map[i].pools & UINT32_MAX));
3131 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3132 ((cfg->pool_map[i].pools >> 32) \
3137 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3138 if (cfg->enable_loop_back) {
3139 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3140 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3141 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3144 IXGBE_WRITE_FLUSH(hw);
3148 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3149 * @hw: pointer to hardware structure
3152 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3157 PMD_INIT_FUNC_TRACE();
3158 /*PF VF Transmit Enable*/
3159 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3160 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3162 /* Disable the Tx desc arbiter so that MTQC can be changed */
3163 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3164 reg |= IXGBE_RTTDCS_ARBDIS;
3165 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3167 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3168 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3170 /* Disable drop for all queues */
3171 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3172 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3173 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3175 /* Enable the Tx desc arbiter */
3176 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3177 reg &= ~IXGBE_RTTDCS_ARBDIS;
3178 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3180 IXGBE_WRITE_FLUSH(hw);
3186 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3188 struct igb_rx_entry *rxe = rxq->sw_ring;
3192 /* Initialize software ring entries */
3193 for (i = 0; i < rxq->nb_rx_desc; i++) {
3194 volatile union ixgbe_adv_rx_desc *rxd;
3195 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3197 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u\n",
3198 (unsigned) rxq->queue_id);
3202 rte_mbuf_refcnt_set(mbuf, 1);
3203 mbuf->type = RTE_MBUF_PKT;
3204 mbuf->pkt.next = NULL;
3205 mbuf->pkt.data = (char *)mbuf->buf_addr + RTE_PKTMBUF_HEADROOM;
3206 mbuf->pkt.nb_segs = 1;
3207 mbuf->pkt.in_port = rxq->port_id;
3210 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3211 rxd = &rxq->rx_ring[i];
3212 rxd->read.hdr_addr = dma_addr;
3213 rxd->read.pkt_addr = dma_addr;
3221 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3223 struct ixgbe_hw *hw =
3224 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3226 if (hw->mac.type == ixgbe_mac_82598EB)
3229 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3231 * SRIOV inactive scheme
3232 * any DCB/RSS w/o VMDq multi-queue setting
3234 switch (dev->data->dev_conf.rxmode.mq_mode) {
3236 ixgbe_rss_configure(dev);
3239 case ETH_MQ_RX_VMDQ_DCB:
3240 ixgbe_vmdq_dcb_configure(dev);
3243 case ETH_MQ_RX_VMDQ_ONLY:
3244 ixgbe_vmdq_rx_hw_configure(dev);
3247 case ETH_MQ_RX_NONE:
3248 /* if mq_mode is none, disable rss mode.*/
3249 default: ixgbe_rss_disable(dev);
3252 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3254 * SRIOV active scheme
3255 * FIXME if support DCB/RSS together with VMDq & SRIOV
3258 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3262 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3266 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3269 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3277 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3279 struct ixgbe_hw *hw =
3280 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3284 if (hw->mac.type == ixgbe_mac_82598EB)
3287 /* disable arbiter before setting MTQC */
3288 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3289 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3290 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3292 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3294 * SRIOV inactive scheme
3295 * any DCB w/o VMDq multi-queue setting
3297 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3298 ixgbe_vmdq_tx_hw_configure(hw);
3300 mtqc = IXGBE_MTQC_64Q_1PB;
3301 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3304 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3307 * SRIOV active scheme
3308 * FIXME if support DCB together with VMDq & SRIOV
3311 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3314 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3317 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3321 mtqc = IXGBE_MTQC_64Q_1PB;
3322 RTE_LOG(ERR, PMD, "invalid pool number in IOV mode\n");
3324 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3327 /* re-enable arbiter */
3328 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3329 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3335 * Initializes Receive Unit.
3338 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3340 struct ixgbe_hw *hw;
3341 struct igb_rx_queue *rxq;
3342 struct rte_pktmbuf_pool_private *mbp_priv;
3354 PMD_INIT_FUNC_TRACE();
3355 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3358 * Make sure receives are disabled while setting
3359 * up the RX context (registers, descriptor rings, etc.).
3361 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3362 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3364 /* Enable receipt of broadcasted frames */
3365 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3366 fctrl |= IXGBE_FCTRL_BAM;
3367 fctrl |= IXGBE_FCTRL_DPF;
3368 fctrl |= IXGBE_FCTRL_PMCF;
3369 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3372 * Configure CRC stripping, if any.
3374 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3375 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3376 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3378 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3381 * Configure jumbo frame support, if any.
3383 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3384 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3385 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3386 maxfrs &= 0x0000FFFF;
3387 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3388 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3390 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3393 * If loopback mode is configured for 82599, set LPBK bit.
3395 if (hw->mac.type == ixgbe_mac_82599EB &&
3396 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3397 hlreg0 |= IXGBE_HLREG0_LPBK;
3399 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3401 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3403 /* Setup RX queues */
3404 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3405 rxq = dev->data->rx_queues[i];
3408 * Reset crc_len in case it was changed after queue setup by a
3409 * call to configure.
3411 rxq->crc_len = (uint8_t)
3412 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3415 /* Setup the Base and Length of the Rx Descriptor Rings */
3416 bus_addr = rxq->rx_ring_phys_addr;
3417 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3418 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3419 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3420 (uint32_t)(bus_addr >> 32));
3421 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3422 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3423 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3424 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3426 /* Configure the SRRCTL register */
3427 #ifdef RTE_HEADER_SPLIT_ENABLE
3429 * Configure Header Split
3431 if (dev->data->dev_conf.rxmode.header_split) {
3432 if (hw->mac.type == ixgbe_mac_82599EB) {
3433 /* Must setup the PSRTYPE register */
3435 psrtype = IXGBE_PSRTYPE_TCPHDR |
3436 IXGBE_PSRTYPE_UDPHDR |
3437 IXGBE_PSRTYPE_IPV4HDR |
3438 IXGBE_PSRTYPE_IPV6HDR;
3439 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3441 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3442 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3443 IXGBE_SRRCTL_BSIZEHDR_MASK);
3444 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3447 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3449 /* Set if packets are dropped when no descriptors available */
3451 srrctl |= IXGBE_SRRCTL_DROP_EN;
3454 * Configure the RX buffer size in the BSIZEPACKET field of
3455 * the SRRCTL register of the queue.
3456 * The value is in 1 KB resolution. Valid values can be from
3459 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3460 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3461 RTE_PKTMBUF_HEADROOM);
3462 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3463 IXGBE_SRRCTL_BSIZEPKT_MASK);
3464 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3466 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3467 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3469 /* It adds dual VLAN length for supporting dual VLAN */
3470 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3471 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3472 dev->data->scattered_rx = 1;
3473 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3478 * Device configured with multiple RX queues.
3480 ixgbe_dev_mq_rx_configure(dev);
3483 * Setup the Checksum Register.
3484 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3485 * Enable IP/L4 checkum computation by hardware if requested to do so.
3487 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3488 rxcsum |= IXGBE_RXCSUM_PCSD;
3489 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3490 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3492 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3494 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3496 if (hw->mac.type == ixgbe_mac_82599EB) {
3497 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3498 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3499 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3501 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3502 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3503 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3510 * Initializes Transmit Unit.
3513 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3515 struct ixgbe_hw *hw;
3516 struct igb_tx_queue *txq;
3522 PMD_INIT_FUNC_TRACE();
3523 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3525 /* Enable TX CRC (checksum offload requirement) */
3526 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3527 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3528 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3530 /* Setup the Base and Length of the Tx Descriptor Rings */
3531 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3532 txq = dev->data->tx_queues[i];
3534 bus_addr = txq->tx_ring_phys_addr;
3535 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3536 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3537 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3538 (uint32_t)(bus_addr >> 32));
3539 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3540 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3541 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3542 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3543 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3546 * Disable Tx Head Writeback RO bit, since this hoses
3547 * bookkeeping if things aren't delivered in order.
3549 switch (hw->mac.type) {
3550 case ixgbe_mac_82598EB:
3551 txctrl = IXGBE_READ_REG(hw,
3552 IXGBE_DCA_TXCTRL(txq->reg_idx));
3553 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3554 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3558 case ixgbe_mac_82599EB:
3559 case ixgbe_mac_X540:
3561 txctrl = IXGBE_READ_REG(hw,
3562 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3563 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3564 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3570 /* Device configured with multiple TX queues. */
3571 ixgbe_dev_mq_tx_configure(dev);
3575 * Set up link for 82599 loopback mode Tx->Rx.
3578 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3580 DEBUGFUNC("ixgbe_setup_loopback_link_82599");
3582 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3583 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3585 PMD_INIT_LOG(ERR, "Could not enable loopback mode\n");
3594 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3595 ixgbe_reset_pipeline_82599(hw);
3597 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3603 * Start Transmit and Receive Units.
3606 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3608 struct ixgbe_hw *hw;
3609 struct igb_tx_queue *txq;
3610 struct igb_rx_queue *rxq;
3616 PMD_INIT_FUNC_TRACE();
3617 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3619 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3620 txq = dev->data->tx_queues[i];
3621 /* Setup Transmit Threshold Registers */
3622 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3623 txdctl |= txq->pthresh & 0x7F;
3624 txdctl |= ((txq->hthresh & 0x7F) << 8);
3625 txdctl |= ((txq->wthresh & 0x7F) << 16);
3626 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3629 if (hw->mac.type != ixgbe_mac_82598EB) {
3630 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3631 dmatxctl |= IXGBE_DMATXCTL_TE;
3632 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3635 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3636 txq = dev->data->tx_queues[i];
3637 if (!txq->start_tx_per_q)
3638 ixgbe_dev_tx_queue_start(dev, i);
3641 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3642 rxq = dev->data->rx_queues[i];
3643 if (!rxq->start_rx_per_q)
3644 ixgbe_dev_rx_queue_start(dev, i);
3647 /* Enable Receive engine */
3648 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3649 if (hw->mac.type == ixgbe_mac_82598EB)
3650 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3651 rxctrl |= IXGBE_RXCTRL_RXEN;
3652 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3654 /* If loopback mode is enabled for 82599, set up the link accordingly */
3655 if (hw->mac.type == ixgbe_mac_82599EB &&
3656 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3657 ixgbe_setup_loopback_link_82599(hw);
3662 * Start Receive Units for specified queue.
3665 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3667 struct ixgbe_hw *hw;
3668 struct igb_rx_queue *rxq;
3672 PMD_INIT_FUNC_TRACE();
3673 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3675 if (rx_queue_id < dev->data->nb_rx_queues) {
3676 rxq = dev->data->rx_queues[rx_queue_id];
3678 /* Allocate buffers for descriptor rings */
3679 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
3681 "Could not alloc mbuf for queue:%d\n",
3685 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3686 rxdctl |= IXGBE_RXDCTL_ENABLE;
3687 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3689 /* Wait until RX Enable ready */
3690 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3693 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3694 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3696 PMD_INIT_LOG(ERR, "Could not enable "
3697 "Rx Queue %d\n", rx_queue_id);
3699 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3700 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3708 * Stop Receive Units for specified queue.
3711 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3713 struct ixgbe_hw *hw;
3714 struct igb_rx_queue *rxq;
3718 PMD_INIT_FUNC_TRACE();
3719 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3721 if (rx_queue_id < dev->data->nb_rx_queues) {
3722 rxq = dev->data->rx_queues[rx_queue_id];
3724 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3725 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3726 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3728 /* Wait until RX Enable ready */
3729 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3732 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3733 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
3735 PMD_INIT_LOG(ERR, "Could not disable "
3736 "Rx Queue %d\n", rx_queue_id);
3738 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3740 ixgbe_rx_queue_release_mbufs(rxq);
3741 ixgbe_reset_rx_queue(rxq);
3750 * Start Transmit Units for specified queue.
3753 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3755 struct ixgbe_hw *hw;
3756 struct igb_tx_queue *txq;
3760 PMD_INIT_FUNC_TRACE();
3761 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3763 if (tx_queue_id < dev->data->nb_tx_queues) {
3764 txq = dev->data->tx_queues[tx_queue_id];
3765 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3766 txdctl |= IXGBE_TXDCTL_ENABLE;
3767 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3769 /* Wait until TX Enable ready */
3770 if (hw->mac.type == ixgbe_mac_82599EB) {
3771 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3774 txdctl = IXGBE_READ_REG(hw,
3775 IXGBE_TXDCTL(txq->reg_idx));
3776 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3778 PMD_INIT_LOG(ERR, "Could not enable "
3779 "Tx Queue %d\n", tx_queue_id);
3782 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3783 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3791 * Stop Transmit Units for specified queue.
3794 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3796 struct ixgbe_hw *hw;
3797 struct igb_tx_queue *txq;
3799 uint32_t txtdh, txtdt;
3802 PMD_INIT_FUNC_TRACE();
3803 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3805 if (tx_queue_id < dev->data->nb_tx_queues) {
3806 txq = dev->data->tx_queues[tx_queue_id];
3808 /* Wait until TX queue is empty */
3809 if (hw->mac.type == ixgbe_mac_82599EB) {
3810 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3812 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3813 txtdh = IXGBE_READ_REG(hw,
3814 IXGBE_TDH(txq->reg_idx));
3815 txtdt = IXGBE_READ_REG(hw,
3816 IXGBE_TDT(txq->reg_idx));
3817 } while (--poll_ms && (txtdh != txtdt));
3820 "Tx Queue %d is not empty when stopping.\n",
3824 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3825 txdctl &= ~IXGBE_TXDCTL_ENABLE;
3826 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3828 /* Wait until TX Enable ready */
3829 if (hw->mac.type == ixgbe_mac_82599EB) {
3830 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3833 txdctl = IXGBE_READ_REG(hw,
3834 IXGBE_TXDCTL(txq->reg_idx));
3835 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
3837 PMD_INIT_LOG(ERR, "Could not disable "
3838 "Tx Queue %d\n", tx_queue_id);
3841 if (txq->ops != NULL) {
3842 txq->ops->release_mbufs(txq);
3843 txq->ops->reset(txq);
3852 * [VF] Initializes Receive Unit.
3855 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3857 struct ixgbe_hw *hw;
3858 struct igb_rx_queue *rxq;
3859 struct rte_pktmbuf_pool_private *mbp_priv;
3866 PMD_INIT_FUNC_TRACE();
3867 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3870 ixgbevf_rlpml_set_vf(hw,
3871 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
3873 /* Setup RX queues */
3874 dev->rx_pkt_burst = ixgbe_recv_pkts;
3875 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3876 rxq = dev->data->rx_queues[i];
3878 /* Allocate buffers for descriptor rings */
3879 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3883 /* Setup the Base and Length of the Rx Descriptor Rings */
3884 bus_addr = rxq->rx_ring_phys_addr;
3886 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3887 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3888 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3889 (uint32_t)(bus_addr >> 32));
3890 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3891 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3892 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3893 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3896 /* Configure the SRRCTL register */
3897 #ifdef RTE_HEADER_SPLIT_ENABLE
3899 * Configure Header Split
3901 if (dev->data->dev_conf.rxmode.header_split) {
3903 /* Must setup the PSRTYPE register */
3905 psrtype = IXGBE_PSRTYPE_TCPHDR |
3906 IXGBE_PSRTYPE_UDPHDR |
3907 IXGBE_PSRTYPE_IPV4HDR |
3908 IXGBE_PSRTYPE_IPV6HDR;
3910 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3912 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3913 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3914 IXGBE_SRRCTL_BSIZEHDR_MASK);
3915 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3918 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3920 /* Set if packets are dropped when no descriptors available */
3922 srrctl |= IXGBE_SRRCTL_DROP_EN;
3925 * Configure the RX buffer size in the BSIZEPACKET field of
3926 * the SRRCTL register of the queue.
3927 * The value is in 1 KB resolution. Valid values can be from
3930 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3931 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3932 RTE_PKTMBUF_HEADROOM);
3933 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3934 IXGBE_SRRCTL_BSIZEPKT_MASK);
3937 * VF modification to write virtual function SRRCTL register
3939 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
3941 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3942 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3944 /* It adds dual VLAN length for supporting dual VLAN */
3945 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3946 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
3947 dev->data->scattered_rx = 1;
3948 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3956 * [VF] Initializes Transmit Unit.
3959 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
3961 struct ixgbe_hw *hw;
3962 struct igb_tx_queue *txq;
3967 PMD_INIT_FUNC_TRACE();
3968 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3970 /* Setup the Base and Length of the Tx Descriptor Rings */
3971 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3972 txq = dev->data->tx_queues[i];
3973 bus_addr = txq->tx_ring_phys_addr;
3974 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
3975 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3976 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
3977 (uint32_t)(bus_addr >> 32));
3978 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
3979 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3980 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3981 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
3982 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
3985 * Disable Tx Head Writeback RO bit, since this hoses
3986 * bookkeeping if things aren't delivered in order.
3988 txctrl = IXGBE_READ_REG(hw,
3989 IXGBE_VFDCA_TXCTRL(i));
3990 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3991 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
3997 * [VF] Start Transmit and Receive Units.
4000 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4002 struct ixgbe_hw *hw;
4003 struct igb_tx_queue *txq;
4004 struct igb_rx_queue *rxq;
4010 PMD_INIT_FUNC_TRACE();
4011 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4013 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4014 txq = dev->data->tx_queues[i];
4015 /* Setup Transmit Threshold Registers */
4016 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4017 txdctl |= txq->pthresh & 0x7F;
4018 txdctl |= ((txq->hthresh & 0x7F) << 8);
4019 txdctl |= ((txq->wthresh & 0x7F) << 16);
4020 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4023 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4025 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4026 txdctl |= IXGBE_TXDCTL_ENABLE;
4027 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4030 /* Wait until TX Enable ready */
4033 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4034 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4036 PMD_INIT_LOG(ERR, "Could not enable "
4037 "Tx Queue %d\n", i);
4039 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4041 rxq = dev->data->rx_queues[i];
4043 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4044 rxdctl |= IXGBE_RXDCTL_ENABLE;
4045 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4047 /* Wait until RX Enable ready */
4051 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4052 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4054 PMD_INIT_LOG(ERR, "Could not enable "
4055 "Rx Queue %d\n", i);
4057 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);