4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5 * Copyright 2014 6WIND S.A.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * * Neither the name of Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
46 #include <rte_byteorder.h>
47 #include <rte_common.h>
48 #include <rte_cycles.h>
50 #include <rte_debug.h>
51 #include <rte_interrupts.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_launch.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
80 #include "ixgbe_rxtx.h"
82 /* Bit Mask to indicate what bits required for building TX context */
83 #define IXGBE_TX_OFFLOAD_MASK ( \
89 static inline struct rte_mbuf *
90 rte_rxmbuf_alloc(struct rte_mempool *mp)
94 m = __rte_mbuf_raw_alloc(mp);
95 __rte_mbuf_sanity_check_raw(m, 0);
101 #define RTE_PMD_USE_PREFETCH
104 #ifdef RTE_PMD_USE_PREFETCH
106 * Prefetch a cache line into all cache levels.
108 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
110 #define rte_ixgbe_prefetch(p) do {} while(0)
113 /*********************************************************************
117 **********************************************************************/
120 * Check for descriptors with their DD bit set and free mbufs.
121 * Return the total number of buffers freed.
123 static inline int __attribute__((always_inline))
124 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
126 struct ixgbe_tx_entry *txep;
130 /* check DD bit on threshold descriptor */
131 status = txq->tx_ring[txq->tx_next_dd].wb.status;
132 if (! (status & IXGBE_ADVTXD_STAT_DD))
136 * first buffer to free from S/W ring is at index
137 * tx_next_dd - (tx_rs_thresh-1)
139 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
141 /* free buffers one at a time */
142 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
143 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
144 txep->mbuf->next = NULL;
145 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
149 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
150 rte_pktmbuf_free_seg(txep->mbuf);
155 /* buffers were freed, update counters */
156 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
157 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
158 if (txq->tx_next_dd >= txq->nb_tx_desc)
159 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
161 return txq->tx_rs_thresh;
164 /* Populate 4 descriptors with data from 4 mbufs */
166 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
168 uint64_t buf_dma_addr;
172 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
173 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
174 pkt_len = (*pkts)->data_len;
176 /* write data to descriptor */
177 txdp->read.buffer_addr = buf_dma_addr;
178 txdp->read.cmd_type_len =
179 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
180 txdp->read.olinfo_status =
181 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
182 rte_prefetch0(&(*pkts)->pool);
186 /* Populate 1 descriptor with data from 1 mbuf */
188 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
190 uint64_t buf_dma_addr;
193 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
194 pkt_len = (*pkts)->data_len;
196 /* write data to descriptor */
197 txdp->read.buffer_addr = buf_dma_addr;
198 txdp->read.cmd_type_len =
199 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
200 txdp->read.olinfo_status =
201 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
202 rte_prefetch0(&(*pkts)->pool);
206 * Fill H/W descriptor ring with mbuf data.
207 * Copy mbuf pointers to the S/W ring.
210 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
213 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
214 struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
215 const int N_PER_LOOP = 4;
216 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
217 int mainpart, leftover;
221 * Process most of the packets in chunks of N pkts. Any
222 * leftover packets will get processed one at a time.
224 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
225 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
226 for (i = 0; i < mainpart; i += N_PER_LOOP) {
227 /* Copy N mbuf pointers to the S/W ring */
228 for (j = 0; j < N_PER_LOOP; ++j) {
229 (txep + i + j)->mbuf = *(pkts + i + j);
231 tx4(txdp + i, pkts + i);
234 if (unlikely(leftover > 0)) {
235 for (i = 0; i < leftover; ++i) {
236 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
237 tx1(txdp + mainpart + i, pkts + mainpart + i);
242 static inline uint16_t
243 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
246 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
247 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
251 * Begin scanning the H/W ring for done descriptors when the
252 * number of available descriptors drops below tx_free_thresh. For
253 * each done descriptor, free the associated buffer.
255 if (txq->nb_tx_free < txq->tx_free_thresh)
256 ixgbe_tx_free_bufs(txq);
258 /* Only use descriptors that are available */
259 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
260 if (unlikely(nb_pkts == 0))
263 /* Use exactly nb_pkts descriptors */
264 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
267 * At this point, we know there are enough descriptors in the
268 * ring to transmit all the packets. This assumes that each
269 * mbuf contains a single segment, and that no new offloads
270 * are expected, which would require a new context descriptor.
274 * See if we're going to wrap-around. If so, handle the top
275 * of the descriptor ring first, then do the bottom. If not,
276 * the processing looks just like the "bottom" part anyway...
278 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
279 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
280 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
283 * We know that the last descriptor in the ring will need to
284 * have its RS bit set because tx_rs_thresh has to be
285 * a divisor of the ring size
287 tx_r[txq->tx_next_rs].read.cmd_type_len |=
288 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
289 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
294 /* Fill H/W descriptor ring with mbuf data */
295 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
296 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
299 * Determine if RS bit should be set
300 * This is what we actually want:
301 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
302 * but instead of subtracting 1 and doing >=, we can just do
303 * greater than without subtracting.
305 if (txq->tx_tail > txq->tx_next_rs) {
306 tx_r[txq->tx_next_rs].read.cmd_type_len |=
307 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
308 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
310 if (txq->tx_next_rs >= txq->nb_tx_desc)
311 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
315 * Check for wrap-around. This would only happen if we used
316 * up to the last descriptor in the ring, no more, no less.
318 if (txq->tx_tail >= txq->nb_tx_desc)
321 /* update tail pointer */
323 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
329 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
334 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
335 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
336 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
338 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
342 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
343 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
344 nb_tx = (uint16_t)(nb_tx + ret);
345 nb_pkts = (uint16_t)(nb_pkts - ret);
354 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
355 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
356 uint64_t ol_flags, union ixgbe_tx_offload tx_offload)
358 uint32_t type_tucmd_mlhl;
359 uint32_t mss_l4len_idx = 0;
361 uint32_t vlan_macip_lens;
362 union ixgbe_tx_offload tx_offload_mask;
364 ctx_idx = txq->ctx_curr;
365 tx_offload_mask.data = 0;
368 /* Specify which HW CTX to upload. */
369 mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
371 if (ol_flags & PKT_TX_VLAN_PKT) {
372 tx_offload_mask.vlan_tci |= ~0;
375 /* check if TCP segmentation required for this packet */
376 if (ol_flags & PKT_TX_TCP_SEG) {
377 /* implies IP cksum and TCP cksum */
378 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
379 IXGBE_ADVTXD_TUCMD_L4T_TCP |
380 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
382 tx_offload_mask.l2_len |= ~0;
383 tx_offload_mask.l3_len |= ~0;
384 tx_offload_mask.l4_len |= ~0;
385 tx_offload_mask.tso_segsz |= ~0;
386 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
387 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
388 } else { /* no TSO, check if hardware checksum is needed */
389 if (ol_flags & PKT_TX_IP_CKSUM) {
390 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
391 tx_offload_mask.l2_len |= ~0;
392 tx_offload_mask.l3_len |= ~0;
395 switch (ol_flags & PKT_TX_L4_MASK) {
396 case PKT_TX_UDP_CKSUM:
397 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
398 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
399 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
400 tx_offload_mask.l2_len |= ~0;
401 tx_offload_mask.l3_len |= ~0;
403 case PKT_TX_TCP_CKSUM:
404 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
405 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
406 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
407 tx_offload_mask.l2_len |= ~0;
408 tx_offload_mask.l3_len |= ~0;
409 tx_offload_mask.l4_len |= ~0;
411 case PKT_TX_SCTP_CKSUM:
412 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
413 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
414 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
415 tx_offload_mask.l2_len |= ~0;
416 tx_offload_mask.l3_len |= ~0;
419 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
420 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
425 txq->ctx_cache[ctx_idx].flags = ol_flags;
426 txq->ctx_cache[ctx_idx].tx_offload.data =
427 tx_offload_mask.data & tx_offload.data;
428 txq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;
430 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
431 vlan_macip_lens = tx_offload.l3_len;
432 vlan_macip_lens |= (tx_offload.l2_len << IXGBE_ADVTXD_MACLEN_SHIFT);
433 vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
434 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
435 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
436 ctx_txd->seqnum_seed = 0;
440 * Check which hardware context can be used. Use the existing match
441 * or create a new context descriptor.
443 static inline uint32_t
444 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
445 union ixgbe_tx_offload tx_offload)
447 /* If match with the current used context */
448 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
449 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
450 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
451 return txq->ctx_curr;
454 /* What if match with the next context */
456 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
457 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
458 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
459 return txq->ctx_curr;
462 /* Mismatch, use the previous context */
463 return (IXGBE_CTX_NUM);
466 static inline uint32_t
467 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
470 if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
471 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
472 if (ol_flags & PKT_TX_IP_CKSUM)
473 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
474 if (ol_flags & PKT_TX_TCP_SEG)
475 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
479 static inline uint32_t
480 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
482 uint32_t cmdtype = 0;
483 if (ol_flags & PKT_TX_VLAN_PKT)
484 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
485 if (ol_flags & PKT_TX_TCP_SEG)
486 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
490 /* Default RS bit threshold values */
491 #ifndef DEFAULT_TX_RS_THRESH
492 #define DEFAULT_TX_RS_THRESH 32
494 #ifndef DEFAULT_TX_FREE_THRESH
495 #define DEFAULT_TX_FREE_THRESH 32
498 /* Reset transmit descriptors after they have been used */
500 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
502 struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
503 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
504 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
505 uint16_t nb_tx_desc = txq->nb_tx_desc;
506 uint16_t desc_to_clean_to;
507 uint16_t nb_tx_to_clean;
509 /* Determine the last descriptor needing to be cleaned */
510 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
511 if (desc_to_clean_to >= nb_tx_desc)
512 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
514 /* Check to make sure the last descriptor to clean is done */
515 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
516 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
518 PMD_TX_FREE_LOG(DEBUG,
519 "TX descriptor %4u is not done"
520 "(port=%d queue=%d)",
522 txq->port_id, txq->queue_id);
523 /* Failed to clean any descriptors, better luck next time */
527 /* Figure out how many descriptors will be cleaned */
528 if (last_desc_cleaned > desc_to_clean_to)
529 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
532 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
535 PMD_TX_FREE_LOG(DEBUG,
536 "Cleaning %4u TX descriptors: %4u to %4u "
537 "(port=%d queue=%d)",
538 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
539 txq->port_id, txq->queue_id);
542 * The last descriptor to clean is done, so that means all the
543 * descriptors from the last descriptor that was cleaned
544 * up to the last descriptor with the RS bit set
545 * are done. Only reset the threshold descriptor.
547 txr[desc_to_clean_to].wb.status = 0;
549 /* Update the txq to reflect the last descriptor that was cleaned */
550 txq->last_desc_cleaned = desc_to_clean_to;
551 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
558 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
561 struct ixgbe_tx_queue *txq;
562 struct ixgbe_tx_entry *sw_ring;
563 struct ixgbe_tx_entry *txe, *txn;
564 volatile union ixgbe_adv_tx_desc *txr;
565 volatile union ixgbe_adv_tx_desc *txd;
566 struct rte_mbuf *tx_pkt;
567 struct rte_mbuf *m_seg;
568 uint64_t buf_dma_addr;
569 uint32_t olinfo_status;
570 uint32_t cmd_type_len;
581 union ixgbe_tx_offload tx_offload = { .data = 0 };
584 sw_ring = txq->sw_ring;
586 tx_id = txq->tx_tail;
587 txe = &sw_ring[tx_id];
589 /* Determine if the descriptor ring needs to be cleaned. */
590 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
591 ixgbe_xmit_cleanup(txq);
594 rte_prefetch0(&txe->mbuf->pool);
597 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
600 pkt_len = tx_pkt->pkt_len;
603 * Determine how many (if any) context descriptors
604 * are needed for offload functionality.
606 ol_flags = tx_pkt->ol_flags;
608 /* If hardware offload required */
609 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
611 tx_offload.l2_len = tx_pkt->l2_len;
612 tx_offload.l3_len = tx_pkt->l3_len;
613 tx_offload.l4_len = tx_pkt->l4_len;
614 tx_offload.vlan_tci = tx_pkt->vlan_tci;
615 tx_offload.tso_segsz = tx_pkt->tso_segsz;
617 /* If new context need be built or reuse the exist ctx. */
618 ctx = what_advctx_update(txq, tx_ol_req,
620 /* Only allocate context descriptor if required*/
621 new_ctx = (ctx == IXGBE_CTX_NUM);
626 * Keep track of how many descriptors are used this loop
627 * This will always be the number of segments + the number of
628 * Context descriptors required to transmit the packet
630 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
633 * The number of descriptors that must be allocated for a
634 * packet is the number of segments of that packet, plus 1
635 * Context Descriptor for the hardware offload, if any.
636 * Determine the last TX descriptor to allocate in the TX ring
637 * for the packet, starting from the current position (tx_id)
640 tx_last = (uint16_t) (tx_id + nb_used - 1);
643 if (tx_last >= txq->nb_tx_desc)
644 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
646 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
647 " tx_first=%u tx_last=%u",
648 (unsigned) txq->port_id,
649 (unsigned) txq->queue_id,
655 * Make sure there are enough TX descriptors available to
656 * transmit the entire packet.
657 * nb_used better be less than or equal to txq->tx_rs_thresh
659 if (nb_used > txq->nb_tx_free) {
660 PMD_TX_FREE_LOG(DEBUG,
661 "Not enough free TX descriptors "
662 "nb_used=%4u nb_free=%4u "
663 "(port=%d queue=%d)",
664 nb_used, txq->nb_tx_free,
665 txq->port_id, txq->queue_id);
667 if (ixgbe_xmit_cleanup(txq) != 0) {
668 /* Could not clean any descriptors */
674 /* nb_used better be <= txq->tx_rs_thresh */
675 if (unlikely(nb_used > txq->tx_rs_thresh)) {
676 PMD_TX_FREE_LOG(DEBUG,
677 "The number of descriptors needed to "
678 "transmit the packet exceeds the "
679 "RS bit threshold. This will impact "
681 "nb_used=%4u nb_free=%4u "
683 "(port=%d queue=%d)",
684 nb_used, txq->nb_tx_free,
686 txq->port_id, txq->queue_id);
688 * Loop here until there are enough TX
689 * descriptors or until the ring cannot be
692 while (nb_used > txq->nb_tx_free) {
693 if (ixgbe_xmit_cleanup(txq) != 0) {
695 * Could not clean any
707 * By now there are enough free TX descriptors to transmit
712 * Set common flags of all TX Data Descriptors.
714 * The following bits must be set in all Data Descriptors:
715 * - IXGBE_ADVTXD_DTYP_DATA
716 * - IXGBE_ADVTXD_DCMD_DEXT
718 * The following bits must be set in the first Data Descriptor
719 * and are ignored in the other ones:
720 * - IXGBE_ADVTXD_DCMD_IFCS
721 * - IXGBE_ADVTXD_MAC_1588
722 * - IXGBE_ADVTXD_DCMD_VLE
724 * The following bits must only be set in the last Data
726 * - IXGBE_TXD_CMD_EOP
728 * The following bits can be set in any Data Descriptor, but
729 * are only set in the last Data Descriptor:
732 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
733 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
735 #ifdef RTE_LIBRTE_IEEE1588
736 if (ol_flags & PKT_TX_IEEE1588_TMST)
737 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
743 if (ol_flags & PKT_TX_TCP_SEG) {
744 /* when TSO is on, paylen in descriptor is the
745 * not the packet len but the tcp payload len */
746 pkt_len -= (tx_offload.l2_len +
747 tx_offload.l3_len + tx_offload.l4_len);
751 * Setup the TX Advanced Context Descriptor if required
754 volatile struct ixgbe_adv_tx_context_desc *
757 ctx_txd = (volatile struct
758 ixgbe_adv_tx_context_desc *)
761 txn = &sw_ring[txe->next_id];
762 rte_prefetch0(&txn->mbuf->pool);
764 if (txe->mbuf != NULL) {
765 rte_pktmbuf_free_seg(txe->mbuf);
769 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
772 txe->last_id = tx_last;
773 tx_id = txe->next_id;
778 * Setup the TX Advanced Data Descriptor,
779 * This path will go through
780 * whatever new/reuse the context descriptor
782 cmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);
783 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
784 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
787 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
792 txn = &sw_ring[txe->next_id];
793 rte_prefetch0(&txn->mbuf->pool);
795 if (txe->mbuf != NULL)
796 rte_pktmbuf_free_seg(txe->mbuf);
800 * Set up Transmit Data Descriptor.
802 slen = m_seg->data_len;
803 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
804 txd->read.buffer_addr =
805 rte_cpu_to_le_64(buf_dma_addr);
806 txd->read.cmd_type_len =
807 rte_cpu_to_le_32(cmd_type_len | slen);
808 txd->read.olinfo_status =
809 rte_cpu_to_le_32(olinfo_status);
810 txe->last_id = tx_last;
811 tx_id = txe->next_id;
814 } while (m_seg != NULL);
817 * The last packet data descriptor needs End Of Packet (EOP)
819 cmd_type_len |= IXGBE_TXD_CMD_EOP;
820 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
821 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
823 /* Set RS bit only on threshold packets' last descriptor */
824 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
825 PMD_TX_FREE_LOG(DEBUG,
826 "Setting RS bit on TXD id="
827 "%4u (port=%d queue=%d)",
828 tx_last, txq->port_id, txq->queue_id);
830 cmd_type_len |= IXGBE_TXD_CMD_RS;
832 /* Update txq RS bit counters */
835 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
841 * Set the Transmit Descriptor Tail (TDT)
843 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
844 (unsigned) txq->port_id, (unsigned) txq->queue_id,
845 (unsigned) tx_id, (unsigned) nb_tx);
846 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
847 txq->tx_tail = tx_id;
852 /*********************************************************************
856 **********************************************************************/
857 static inline uint64_t
858 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
862 static const uint64_t ip_pkt_types_map[16] = {
863 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
864 PKT_RX_IPV6_HDR, 0, 0, 0,
865 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
866 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
869 static const uint64_t ip_rss_types_map[16] = {
870 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
871 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
872 PKT_RX_RSS_HASH, 0, 0, 0,
873 0, 0, 0, PKT_RX_FDIR,
876 #ifdef RTE_LIBRTE_IEEE1588
877 static uint64_t ip_pkt_etqf_map[8] = {
878 0, 0, 0, PKT_RX_IEEE1588_PTP,
882 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
883 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
884 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
886 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
887 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
890 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
893 static inline uint64_t
894 rx_desc_status_to_pkt_flags(uint32_t rx_status)
899 * Check if VLAN present only.
900 * Do not check whether L3/L4 rx checksum done by NIC or not,
901 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
903 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
905 #ifdef RTE_LIBRTE_IEEE1588
906 if (rx_status & IXGBE_RXD_STAT_TMST)
907 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
912 static inline uint64_t
913 rx_desc_error_to_pkt_flags(uint32_t rx_status)
916 * Bit 31: IPE, IPv4 checksum error
917 * Bit 30: L4I, L4I integrity error
919 static uint64_t error_to_pkt_flags_map[4] = {
920 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
921 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
923 return error_to_pkt_flags_map[(rx_status >>
924 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
927 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
929 * LOOK_AHEAD defines how many desc statuses to check beyond the
930 * current descriptor.
931 * It must be a pound define for optimal performance.
932 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
933 * function only works with LOOK_AHEAD=8.
936 #if (LOOK_AHEAD != 8)
937 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
940 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
942 volatile union ixgbe_adv_rx_desc *rxdp;
943 struct ixgbe_rx_entry *rxep;
947 int s[LOOK_AHEAD], nb_dd;
951 /* get references to current descriptor and S/W ring entry */
952 rxdp = &rxq->rx_ring[rxq->rx_tail];
953 rxep = &rxq->sw_ring[rxq->rx_tail];
955 /* check to make sure there is at least 1 packet to receive */
956 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
960 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
961 * reference packets that are ready to be received.
963 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
964 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
966 /* Read desc statuses backwards to avoid race condition */
967 for (j = LOOK_AHEAD-1; j >= 0; --j)
968 s[j] = rxdp[j].wb.upper.status_error;
970 /* Compute how many status bits were set */
972 for (j = 0; j < LOOK_AHEAD; ++j)
973 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
977 /* Translate descriptor info to mbuf format */
978 for (j = 0; j < nb_dd; ++j) {
980 pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
981 mb->data_len = pkt_len;
982 mb->pkt_len = pkt_len;
983 mb->vlan_tci = rxdp[j].wb.upper.vlan;
984 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
986 /* convert descriptor fields to rte mbuf flags */
987 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
988 rxdp[j].wb.lower.lo_dword.data);
989 /* reuse status field from scan list */
990 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
991 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
992 mb->ol_flags = pkt_flags;
994 if (likely(pkt_flags & PKT_RX_RSS_HASH))
995 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
996 else if (pkt_flags & PKT_RX_FDIR) {
998 (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
999 & IXGBE_ATR_HASH_MASK);
1000 mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
1004 /* Move mbuf pointers from the S/W ring to the stage */
1005 for (j = 0; j < LOOK_AHEAD; ++j) {
1006 rxq->rx_stage[i + j] = rxep[j].mbuf;
1009 /* stop if all requested packets could not be received */
1010 if (nb_dd != LOOK_AHEAD)
1014 /* clear software ring entries so we can cleanup correctly */
1015 for (i = 0; i < nb_rx; ++i) {
1016 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1024 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq)
1026 volatile union ixgbe_adv_rx_desc *rxdp;
1027 struct ixgbe_rx_entry *rxep;
1028 struct rte_mbuf *mb;
1033 /* allocate buffers in bulk directly into the S/W ring */
1034 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1035 (rxq->rx_free_thresh - 1));
1036 rxep = &rxq->sw_ring[alloc_idx];
1037 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1038 rxq->rx_free_thresh);
1039 if (unlikely(diag != 0))
1042 rxdp = &rxq->rx_ring[alloc_idx];
1043 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1044 /* populate the static rte mbuf fields */
1046 rte_mbuf_refcnt_set(mb, 1);
1048 mb->data_off = RTE_PKTMBUF_HEADROOM;
1050 mb->port = rxq->port_id;
1052 /* populate the descriptors */
1053 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1054 rxdp[i].read.hdr_addr = dma_addr;
1055 rxdp[i].read.pkt_addr = dma_addr;
1058 /* update tail pointer */
1060 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1062 /* update state of internal queue structure */
1063 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1064 rxq->rx_free_thresh);
1065 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1066 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1072 static inline uint16_t
1073 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1076 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1079 /* how many packets are ready to return? */
1080 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1082 /* copy mbuf pointers to the application's packet list */
1083 for (i = 0; i < nb_pkts; ++i)
1084 rx_pkts[i] = stage[i];
1086 /* update internal queue state */
1087 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1088 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1093 static inline uint16_t
1094 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1097 struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1100 /* Any previously recv'd pkts will be returned from the Rx stage */
1101 if (rxq->rx_nb_avail)
1102 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1104 /* Scan the H/W ring for packets to receive */
1105 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1107 /* update internal queue state */
1108 rxq->rx_next_avail = 0;
1109 rxq->rx_nb_avail = nb_rx;
1110 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1112 /* if required, allocate new buffers to replenish descriptors */
1113 if (rxq->rx_tail > rxq->rx_free_trigger) {
1114 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1116 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1117 "queue_id=%u", (unsigned) rxq->port_id,
1118 (unsigned) rxq->queue_id);
1120 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1121 rxq->rx_free_thresh;
1124 * Need to rewind any previous receives if we cannot
1125 * allocate new buffers to replenish the old ones.
1127 rxq->rx_nb_avail = 0;
1128 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1129 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1130 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1136 if (rxq->rx_tail >= rxq->nb_rx_desc)
1139 /* received any packets this loop? */
1140 if (rxq->rx_nb_avail)
1141 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1146 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1148 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1153 if (unlikely(nb_pkts == 0))
1156 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1157 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1159 /* request is relatively large, chunk it up */
1163 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1164 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1165 nb_rx = (uint16_t)(nb_rx + ret);
1166 nb_pkts = (uint16_t)(nb_pkts - ret);
1173 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1176 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1179 struct ixgbe_rx_queue *rxq;
1180 volatile union ixgbe_adv_rx_desc *rx_ring;
1181 volatile union ixgbe_adv_rx_desc *rxdp;
1182 struct ixgbe_rx_entry *sw_ring;
1183 struct ixgbe_rx_entry *rxe;
1184 struct rte_mbuf *rxm;
1185 struct rte_mbuf *nmb;
1186 union ixgbe_adv_rx_desc rxd;
1189 uint32_t hlen_type_rss;
1199 rx_id = rxq->rx_tail;
1200 rx_ring = rxq->rx_ring;
1201 sw_ring = rxq->sw_ring;
1202 while (nb_rx < nb_pkts) {
1204 * The order of operations here is important as the DD status
1205 * bit must not be read after any other descriptor fields.
1206 * rx_ring and rxdp are pointing to volatile data so the order
1207 * of accesses cannot be reordered by the compiler. If they were
1208 * not volatile, they could be reordered which could lead to
1209 * using invalid descriptor fields when read from rxd.
1211 rxdp = &rx_ring[rx_id];
1212 staterr = rxdp->wb.upper.status_error;
1213 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1220 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1221 * is likely to be invalid and to be dropped by the various
1222 * validation checks performed by the network stack.
1224 * Allocate a new mbuf to replenish the RX ring descriptor.
1225 * If the allocation fails:
1226 * - arrange for that RX descriptor to be the first one
1227 * being parsed the next time the receive function is
1228 * invoked [on the same queue].
1230 * - Stop parsing the RX ring and return immediately.
1232 * This policy do not drop the packet received in the RX
1233 * descriptor for which the allocation of a new mbuf failed.
1234 * Thus, it allows that packet to be later retrieved if
1235 * mbuf have been freed in the mean time.
1236 * As a side effect, holding RX descriptors instead of
1237 * systematically giving them back to the NIC may lead to
1238 * RX ring exhaustion situations.
1239 * However, the NIC can gracefully prevent such situations
1240 * to happen by sending specific "back-pressure" flow control
1241 * frames to its peer(s).
1243 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1244 "ext_err_stat=0x%08x pkt_len=%u",
1245 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1246 (unsigned) rx_id, (unsigned) staterr,
1247 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1249 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1251 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1252 "queue_id=%u", (unsigned) rxq->port_id,
1253 (unsigned) rxq->queue_id);
1254 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1259 rxe = &sw_ring[rx_id];
1261 if (rx_id == rxq->nb_rx_desc)
1264 /* Prefetch next mbuf while processing current one. */
1265 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1268 * When next RX descriptor is on a cache-line boundary,
1269 * prefetch the next 4 RX descriptors and the next 8 pointers
1272 if ((rx_id & 0x3) == 0) {
1273 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1274 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1280 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1281 rxdp->read.hdr_addr = dma_addr;
1282 rxdp->read.pkt_addr = dma_addr;
1285 * Initialize the returned mbuf.
1286 * 1) setup generic mbuf fields:
1287 * - number of segments,
1290 * - RX port identifier.
1291 * 2) integrate hardware offload data, if any:
1292 * - RSS flag & hash,
1293 * - IP checksum flag,
1294 * - VLAN TCI, if any,
1297 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1299 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1300 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1303 rxm->pkt_len = pkt_len;
1304 rxm->data_len = pkt_len;
1305 rxm->port = rxq->port_id;
1307 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1308 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1309 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1311 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1312 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1313 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1314 rxm->ol_flags = pkt_flags;
1316 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1317 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1318 else if (pkt_flags & PKT_RX_FDIR) {
1319 rxm->hash.fdir.hash =
1320 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1321 & IXGBE_ATR_HASH_MASK);
1322 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1325 * Store the mbuf address into the next entry of the array
1326 * of returned packets.
1328 rx_pkts[nb_rx++] = rxm;
1330 rxq->rx_tail = rx_id;
1333 * If the number of free RX descriptors is greater than the RX free
1334 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1336 * Update the RDT with the value of the last processed RX descriptor
1337 * minus 1, to guarantee that the RDT register is never equal to the
1338 * RDH register, which creates a "full" ring situtation from the
1339 * hardware point of view...
1341 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1342 if (nb_hold > rxq->rx_free_thresh) {
1343 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1344 "nb_hold=%u nb_rx=%u",
1345 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1346 (unsigned) rx_id, (unsigned) nb_hold,
1348 rx_id = (uint16_t) ((rx_id == 0) ?
1349 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1350 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1353 rxq->nb_rx_hold = nb_hold;
1358 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1361 struct ixgbe_rx_queue *rxq;
1362 volatile union ixgbe_adv_rx_desc *rx_ring;
1363 volatile union ixgbe_adv_rx_desc *rxdp;
1364 struct ixgbe_rx_entry *sw_ring;
1365 struct ixgbe_rx_entry *rxe;
1366 struct rte_mbuf *first_seg;
1367 struct rte_mbuf *last_seg;
1368 struct rte_mbuf *rxm;
1369 struct rte_mbuf *nmb;
1370 union ixgbe_adv_rx_desc rxd;
1371 uint64_t dma; /* Physical address of mbuf data buffer */
1373 uint32_t hlen_type_rss;
1383 rx_id = rxq->rx_tail;
1384 rx_ring = rxq->rx_ring;
1385 sw_ring = rxq->sw_ring;
1388 * Retrieve RX context of current packet, if any.
1390 first_seg = rxq->pkt_first_seg;
1391 last_seg = rxq->pkt_last_seg;
1393 while (nb_rx < nb_pkts) {
1396 * The order of operations here is important as the DD status
1397 * bit must not be read after any other descriptor fields.
1398 * rx_ring and rxdp are pointing to volatile data so the order
1399 * of accesses cannot be reordered by the compiler. If they were
1400 * not volatile, they could be reordered which could lead to
1401 * using invalid descriptor fields when read from rxd.
1403 rxdp = &rx_ring[rx_id];
1404 staterr = rxdp->wb.upper.status_error;
1405 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1412 * Allocate a new mbuf to replenish the RX ring descriptor.
1413 * If the allocation fails:
1414 * - arrange for that RX descriptor to be the first one
1415 * being parsed the next time the receive function is
1416 * invoked [on the same queue].
1418 * - Stop parsing the RX ring and return immediately.
1420 * This policy does not drop the packet received in the RX
1421 * descriptor for which the allocation of a new mbuf failed.
1422 * Thus, it allows that packet to be later retrieved if
1423 * mbuf have been freed in the mean time.
1424 * As a side effect, holding RX descriptors instead of
1425 * systematically giving them back to the NIC may lead to
1426 * RX ring exhaustion situations.
1427 * However, the NIC can gracefully prevent such situations
1428 * to happen by sending specific "back-pressure" flow control
1429 * frames to its peer(s).
1431 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1432 "staterr=0x%x data_len=%u",
1433 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1434 (unsigned) rx_id, (unsigned) staterr,
1435 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1437 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1439 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1440 "queue_id=%u", (unsigned) rxq->port_id,
1441 (unsigned) rxq->queue_id);
1442 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1447 rxe = &sw_ring[rx_id];
1449 if (rx_id == rxq->nb_rx_desc)
1452 /* Prefetch next mbuf while processing current one. */
1453 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1456 * When next RX descriptor is on a cache-line boundary,
1457 * prefetch the next 4 RX descriptors and the next 8 pointers
1460 if ((rx_id & 0x3) == 0) {
1461 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1462 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1466 * Update RX descriptor with the physical address of the new
1467 * data buffer of the new allocated mbuf.
1471 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1472 rxdp->read.hdr_addr = dma;
1473 rxdp->read.pkt_addr = dma;
1476 * Set data length & data buffer address of mbuf.
1478 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1479 rxm->data_len = data_len;
1480 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1483 * If this is the first buffer of the received packet,
1484 * set the pointer to the first mbuf of the packet and
1485 * initialize its context.
1486 * Otherwise, update the total length and the number of segments
1487 * of the current scattered packet, and update the pointer to
1488 * the last mbuf of the current packet.
1490 if (first_seg == NULL) {
1492 first_seg->pkt_len = data_len;
1493 first_seg->nb_segs = 1;
1495 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
1497 first_seg->nb_segs++;
1498 last_seg->next = rxm;
1502 * If this is not the last buffer of the received packet,
1503 * update the pointer to the last mbuf of the current scattered
1504 * packet and continue to parse the RX ring.
1506 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1512 * This is the last buffer of the received packet.
1513 * If the CRC is not stripped by the hardware:
1514 * - Subtract the CRC length from the total packet length.
1515 * - If the last buffer only contains the whole CRC or a part
1516 * of it, free the mbuf associated to the last buffer.
1517 * If part of the CRC is also contained in the previous
1518 * mbuf, subtract the length of that CRC part from the
1519 * data length of the previous mbuf.
1522 if (unlikely(rxq->crc_len > 0)) {
1523 first_seg->pkt_len -= ETHER_CRC_LEN;
1524 if (data_len <= ETHER_CRC_LEN) {
1525 rte_pktmbuf_free_seg(rxm);
1526 first_seg->nb_segs--;
1527 last_seg->data_len = (uint16_t)
1528 (last_seg->data_len -
1529 (ETHER_CRC_LEN - data_len));
1530 last_seg->next = NULL;
1533 (uint16_t) (data_len - ETHER_CRC_LEN);
1537 * Initialize the first mbuf of the returned packet:
1538 * - RX port identifier,
1539 * - hardware offload data, if any:
1540 * - RSS flag & hash,
1541 * - IP checksum flag,
1542 * - VLAN TCI, if any,
1545 first_seg->port = rxq->port_id;
1548 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1549 * set in the pkt_flags field.
1551 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1552 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1553 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1554 pkt_flags = (pkt_flags |
1555 rx_desc_status_to_pkt_flags(staterr));
1556 pkt_flags = (pkt_flags |
1557 rx_desc_error_to_pkt_flags(staterr));
1558 first_seg->ol_flags = pkt_flags;
1560 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1561 first_seg->hash.rss =
1562 rte_le_to_cpu_32(rxd.wb.lower.hi_dword.rss);
1563 else if (pkt_flags & PKT_RX_FDIR) {
1564 first_seg->hash.fdir.hash =
1565 rte_le_to_cpu_16(rxd.wb.lower.hi_dword.csum_ip.csum)
1566 & IXGBE_ATR_HASH_MASK;
1567 first_seg->hash.fdir.id =
1568 rte_le_to_cpu_16(rxd.wb.lower.hi_dword.csum_ip.ip_id);
1571 /* Prefetch data of first segment, if configured to do so. */
1572 rte_packet_prefetch((char *)first_seg->buf_addr +
1573 first_seg->data_off);
1576 * Store the mbuf address into the next entry of the array
1577 * of returned packets.
1579 rx_pkts[nb_rx++] = first_seg;
1582 * Setup receipt context for a new packet.
1588 * Record index of the next RX descriptor to probe.
1590 rxq->rx_tail = rx_id;
1593 * Save receive context.
1595 rxq->pkt_first_seg = first_seg;
1596 rxq->pkt_last_seg = last_seg;
1599 * If the number of free RX descriptors is greater than the RX free
1600 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1602 * Update the RDT with the value of the last processed RX descriptor
1603 * minus 1, to guarantee that the RDT register is never equal to the
1604 * RDH register, which creates a "full" ring situtation from the
1605 * hardware point of view...
1607 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1608 if (nb_hold > rxq->rx_free_thresh) {
1609 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1610 "nb_hold=%u nb_rx=%u",
1611 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1612 (unsigned) rx_id, (unsigned) nb_hold,
1614 rx_id = (uint16_t) ((rx_id == 0) ?
1615 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1616 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1619 rxq->nb_rx_hold = nb_hold;
1623 /*********************************************************************
1625 * Queue management functions
1627 **********************************************************************/
1630 * Rings setup and release.
1632 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1633 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1634 * also optimize cache line size effect. H/W supports up to cache line size 128.
1636 #define IXGBE_ALIGN 128
1639 * Maximum number of Ring Descriptors.
1641 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1642 * descriptors should meet the following condition:
1643 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1645 #define IXGBE_MIN_RING_DESC 32
1646 #define IXGBE_MAX_RING_DESC 4096
1649 * Create memzone for HW rings. malloc can't be used as the physical address is
1650 * needed. If the memzone is already created, then this function returns a ptr
1653 static const struct rte_memzone *
1654 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1655 uint16_t queue_id, uint32_t ring_size, int socket_id)
1657 char z_name[RTE_MEMZONE_NAMESIZE];
1658 const struct rte_memzone *mz;
1660 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1661 dev->driver->pci_drv.name, ring_name,
1662 dev->data->port_id, queue_id);
1664 mz = rte_memzone_lookup(z_name);
1668 #ifdef RTE_LIBRTE_XEN_DOM0
1669 return rte_memzone_reserve_bounded(z_name, ring_size,
1670 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1672 return rte_memzone_reserve_aligned(z_name, ring_size,
1673 socket_id, 0, IXGBE_ALIGN);
1678 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
1682 if (txq->sw_ring != NULL) {
1683 for (i = 0; i < txq->nb_tx_desc; i++) {
1684 if (txq->sw_ring[i].mbuf != NULL) {
1685 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1686 txq->sw_ring[i].mbuf = NULL;
1693 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
1696 txq->sw_ring != NULL)
1697 rte_free(txq->sw_ring);
1701 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
1703 if (txq != NULL && txq->ops != NULL) {
1704 txq->ops->release_mbufs(txq);
1705 txq->ops->free_swring(txq);
1711 ixgbe_dev_tx_queue_release(void *txq)
1713 ixgbe_tx_queue_release(txq);
1716 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
1718 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
1720 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1722 struct ixgbe_tx_entry *txe = txq->sw_ring;
1725 /* Zero out HW ring memory */
1726 for (i = 0; i < txq->nb_tx_desc; i++) {
1727 txq->tx_ring[i] = zeroed_desc;
1730 /* Initialize SW ring entries */
1731 prev = (uint16_t) (txq->nb_tx_desc - 1);
1732 for (i = 0; i < txq->nb_tx_desc; i++) {
1733 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1734 txd->wb.status = IXGBE_TXD_STAT_DD;
1737 txe[prev].next_id = i;
1741 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1742 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1745 txq->nb_tx_used = 0;
1747 * Always allow 1 descriptor to be un-allocated to avoid
1748 * a H/W race condition
1750 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1751 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1753 memset((void*)&txq->ctx_cache, 0,
1754 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1757 static const struct ixgbe_txq_ops def_txq_ops = {
1758 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1759 .free_swring = ixgbe_tx_free_swring,
1760 .reset = ixgbe_reset_tx_queue,
1763 /* Takes an ethdev and a queue and sets up the tx function to be used based on
1764 * the queue parameters. Used in tx_queue_setup by primary process and then
1765 * in dev_init by secondary process when attaching to an existing ethdev.
1768 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
1770 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1771 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS)
1772 && (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1773 PMD_INIT_LOG(INFO, "Using simple tx code path");
1774 #ifdef RTE_IXGBE_INC_VECTOR
1775 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1776 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
1777 ixgbe_txq_vec_setup(txq) == 0)) {
1778 PMD_INIT_LOG(INFO, "Vector tx enabled.");
1779 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1782 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1784 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
1786 " - txq_flags = %lx " "[IXGBE_SIMPLE_FLAGS=%lx]",
1787 (unsigned long)txq->txq_flags,
1788 (unsigned long)IXGBE_SIMPLE_FLAGS);
1790 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
1791 (unsigned long)txq->tx_rs_thresh,
1792 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
1793 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1798 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1801 unsigned int socket_id,
1802 const struct rte_eth_txconf *tx_conf)
1804 const struct rte_memzone *tz;
1805 struct ixgbe_tx_queue *txq;
1806 struct ixgbe_hw *hw;
1807 uint16_t tx_rs_thresh, tx_free_thresh;
1809 PMD_INIT_FUNC_TRACE();
1810 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1813 * Validate number of transmit descriptors.
1814 * It must not exceed hardware maximum, and must be multiple
1817 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1818 (nb_desc > IXGBE_MAX_RING_DESC) ||
1819 (nb_desc < IXGBE_MIN_RING_DESC)) {
1824 * The following two parameters control the setting of the RS bit on
1825 * transmit descriptors.
1826 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1827 * descriptors have been used.
1828 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1829 * descriptors are used or if the number of descriptors required
1830 * to transmit a packet is greater than the number of free TX
1832 * The following constraints must be satisfied:
1833 * tx_rs_thresh must be greater than 0.
1834 * tx_rs_thresh must be less than the size of the ring minus 2.
1835 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1836 * tx_rs_thresh must be a divisor of the ring size.
1837 * tx_free_thresh must be greater than 0.
1838 * tx_free_thresh must be less than the size of the ring minus 3.
1839 * One descriptor in the TX ring is used as a sentinel to avoid a
1840 * H/W race condition, hence the maximum threshold constraints.
1841 * When set to zero use default values.
1843 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1844 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1845 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1846 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1847 if (tx_rs_thresh >= (nb_desc - 2)) {
1848 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
1849 "of TX descriptors minus 2. (tx_rs_thresh=%u "
1850 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1851 (int)dev->data->port_id, (int)queue_idx);
1854 if (tx_free_thresh >= (nb_desc - 3)) {
1855 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1856 "tx_free_thresh must be less than the number of "
1857 "TX descriptors minus 3. (tx_free_thresh=%u "
1858 "port=%d queue=%d)",
1859 (unsigned int)tx_free_thresh,
1860 (int)dev->data->port_id, (int)queue_idx);
1863 if (tx_rs_thresh > tx_free_thresh) {
1864 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1865 "tx_free_thresh. (tx_free_thresh=%u "
1866 "tx_rs_thresh=%u port=%d queue=%d)",
1867 (unsigned int)tx_free_thresh,
1868 (unsigned int)tx_rs_thresh,
1869 (int)dev->data->port_id,
1873 if ((nb_desc % tx_rs_thresh) != 0) {
1874 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1875 "number of TX descriptors. (tx_rs_thresh=%u "
1876 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1877 (int)dev->data->port_id, (int)queue_idx);
1882 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1883 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1884 * by the NIC and all descriptors are written back after the NIC
1885 * accumulates WTHRESH descriptors.
1887 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1888 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1889 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1890 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1891 (int)dev->data->port_id, (int)queue_idx);
1895 /* Free memory prior to re-allocation if needed... */
1896 if (dev->data->tx_queues[queue_idx] != NULL) {
1897 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1898 dev->data->tx_queues[queue_idx] = NULL;
1901 /* First allocate the tx queue data structure */
1902 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
1903 RTE_CACHE_LINE_SIZE, socket_id);
1908 * Allocate TX ring hardware descriptors. A memzone large enough to
1909 * handle the maximum ring size is allocated in order to allow for
1910 * resizing in later calls to the queue setup function.
1912 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1913 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1916 ixgbe_tx_queue_release(txq);
1920 txq->nb_tx_desc = nb_desc;
1921 txq->tx_rs_thresh = tx_rs_thresh;
1922 txq->tx_free_thresh = tx_free_thresh;
1923 txq->pthresh = tx_conf->tx_thresh.pthresh;
1924 txq->hthresh = tx_conf->tx_thresh.hthresh;
1925 txq->wthresh = tx_conf->tx_thresh.wthresh;
1926 txq->queue_id = queue_idx;
1927 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1928 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1929 txq->port_id = dev->data->port_id;
1930 txq->txq_flags = tx_conf->txq_flags;
1931 txq->ops = &def_txq_ops;
1932 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1935 * Modification to set VFTDT for virtual function if vf is detected
1937 if (hw->mac.type == ixgbe_mac_82599_vf ||
1938 hw->mac.type == ixgbe_mac_X540_vf ||
1939 hw->mac.type == ixgbe_mac_X550_vf ||
1940 hw->mac.type == ixgbe_mac_X550EM_x_vf)
1941 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1943 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1944 #ifndef RTE_LIBRTE_XEN_DOM0
1945 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1947 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1949 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1951 /* Allocate software ring */
1952 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1953 sizeof(struct ixgbe_tx_entry) * nb_desc,
1954 RTE_CACHE_LINE_SIZE, socket_id);
1955 if (txq->sw_ring == NULL) {
1956 ixgbe_tx_queue_release(txq);
1959 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1960 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1962 /* set up vector or scalar TX function as appropriate */
1963 ixgbe_set_tx_function(dev, txq);
1965 txq->ops->reset(txq);
1967 dev->data->tx_queues[queue_idx] = txq;
1974 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
1978 if (rxq->sw_ring != NULL) {
1979 for (i = 0; i < rxq->nb_rx_desc; i++) {
1980 if (rxq->sw_ring[i].mbuf != NULL) {
1981 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1982 rxq->sw_ring[i].mbuf = NULL;
1985 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1986 if (rxq->rx_nb_avail) {
1987 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1988 struct rte_mbuf *mb;
1989 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1990 rte_pktmbuf_free_seg(mb);
1992 rxq->rx_nb_avail = 0;
1999 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2002 ixgbe_rx_queue_release_mbufs(rxq);
2003 rte_free(rxq->sw_ring);
2009 ixgbe_dev_rx_queue_release(void *rxq)
2011 ixgbe_rx_queue_release(rxq);
2015 * Check if Rx Burst Bulk Alloc function can be used.
2017 * 0: the preconditions are satisfied and the bulk allocation function
2019 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2020 * function must be used.
2023 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2024 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2026 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct ixgbe_rx_queue *rxq)
2032 * Make sure the following pre-conditions are satisfied:
2033 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2034 * rxq->rx_free_thresh < rxq->nb_rx_desc
2035 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2036 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2037 * Scattered packets are not supported. This should be checked
2038 * outside of this function.
2040 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2041 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2042 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2043 "rxq->rx_free_thresh=%d, "
2044 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2045 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2047 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2048 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2049 "rxq->rx_free_thresh=%d, "
2050 "rxq->nb_rx_desc=%d",
2051 rxq->rx_free_thresh, rxq->nb_rx_desc);
2053 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2054 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2055 "rxq->nb_rx_desc=%d, "
2056 "rxq->rx_free_thresh=%d",
2057 rxq->nb_rx_desc, rxq->rx_free_thresh);
2059 } else if (!(rxq->nb_rx_desc <
2060 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2061 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2062 "rxq->nb_rx_desc=%d, "
2063 "IXGBE_MAX_RING_DESC=%d, "
2064 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2065 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2066 RTE_PMD_IXGBE_RX_MAX_BURST);
2076 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2078 ixgbe_reset_rx_queue(struct ixgbe_rx_queue *rxq)
2080 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
2086 * By default, the Rx queue setup function allocates enough memory for
2087 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2088 * extra memory at the end of the descriptor ring to be zero'd out. A
2089 * pre-condition for using the Rx burst bulk alloc function is that the
2090 * number of descriptors is less than or equal to
2091 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2092 * constraints here to see if we need to zero out memory after the end
2093 * of the H/W descriptor ring.
2095 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2096 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2097 /* zero out extra memory */
2098 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2101 /* do not zero out extra memory */
2102 len = rxq->nb_rx_desc;
2105 * Zero out HW ring memory. Zero out extra memory at the end of
2106 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2107 * reads extra memory as zeros.
2109 for (i = 0; i < len; i++) {
2110 rxq->rx_ring[i] = zeroed_desc;
2113 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2115 * initialize extra software ring entries. Space for these extra
2116 * entries is always allocated
2118 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2119 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2120 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2123 rxq->rx_nb_avail = 0;
2124 rxq->rx_next_avail = 0;
2125 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2126 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2128 rxq->nb_rx_hold = 0;
2129 rxq->pkt_first_seg = NULL;
2130 rxq->pkt_last_seg = NULL;
2134 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2137 unsigned int socket_id,
2138 const struct rte_eth_rxconf *rx_conf,
2139 struct rte_mempool *mp)
2141 const struct rte_memzone *rz;
2142 struct ixgbe_rx_queue *rxq;
2143 struct ixgbe_hw *hw;
2144 int use_def_burst_func = 1;
2147 PMD_INIT_FUNC_TRACE();
2148 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2151 * Validate number of receive descriptors.
2152 * It must not exceed hardware maximum, and must be multiple
2155 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2156 (nb_desc > IXGBE_MAX_RING_DESC) ||
2157 (nb_desc < IXGBE_MIN_RING_DESC)) {
2161 /* Free memory prior to re-allocation if needed... */
2162 if (dev->data->rx_queues[queue_idx] != NULL) {
2163 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2164 dev->data->rx_queues[queue_idx] = NULL;
2167 /* First allocate the rx queue data structure */
2168 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2169 RTE_CACHE_LINE_SIZE, socket_id);
2173 rxq->nb_rx_desc = nb_desc;
2174 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2175 rxq->queue_id = queue_idx;
2176 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2177 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2178 rxq->port_id = dev->data->port_id;
2179 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2181 rxq->drop_en = rx_conf->rx_drop_en;
2182 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2185 * Allocate RX ring hardware descriptors. A memzone large enough to
2186 * handle the maximum ring size is allocated in order to allow for
2187 * resizing in later calls to the queue setup function.
2189 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2190 RX_RING_SZ, socket_id);
2192 ixgbe_rx_queue_release(rxq);
2197 * Zero init all the descriptors in the ring.
2199 memset (rz->addr, 0, RX_RING_SZ);
2202 * Modified to setup VFRDT for Virtual Function
2204 if (hw->mac.type == ixgbe_mac_82599_vf ||
2205 hw->mac.type == ixgbe_mac_X540_vf ||
2206 hw->mac.type == ixgbe_mac_X550_vf ||
2207 hw->mac.type == ixgbe_mac_X550EM_x_vf) {
2209 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2211 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2215 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2217 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2219 #ifndef RTE_LIBRTE_XEN_DOM0
2220 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2222 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2224 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2227 * Allocate software ring. Allow for space at the end of the
2228 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2229 * function does not access an invalid memory region.
2231 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2232 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2236 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2237 sizeof(struct ixgbe_rx_entry) * len,
2238 RTE_CACHE_LINE_SIZE, socket_id);
2239 if (rxq->sw_ring == NULL) {
2240 ixgbe_rx_queue_release(rxq);
2243 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2244 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2247 * Certain constraints must be met in order to use the bulk buffer
2248 * allocation Rx burst function.
2250 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2252 #ifdef RTE_IXGBE_INC_VECTOR
2253 ixgbe_rxq_vec_setup(rxq);
2255 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2256 if (!use_def_burst_func && !dev->data->scattered_rx) {
2257 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2258 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2259 "satisfied. Rx Burst Bulk Alloc function will be "
2260 "used on port=%d, queue=%d.",
2261 rxq->port_id, rxq->queue_id);
2262 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2263 #ifdef RTE_IXGBE_INC_VECTOR
2264 if (!ixgbe_rx_vec_condition_check(dev) &&
2265 (rte_is_power_of_2(nb_desc))) {
2266 PMD_INIT_LOG(INFO, "Vector rx enabled, please make "
2267 "sure RX burst size no less than 32.");
2268 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
2273 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2274 "are not satisfied, Scattered Rx is requested, "
2275 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2276 "enabled (port=%d, queue=%d).",
2277 rxq->port_id, rxq->queue_id);
2279 dev->data->rx_queues[queue_idx] = rxq;
2281 ixgbe_reset_rx_queue(rxq);
2287 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2289 #define IXGBE_RXQ_SCAN_INTERVAL 4
2290 volatile union ixgbe_adv_rx_desc *rxdp;
2291 struct ixgbe_rx_queue *rxq;
2294 if (rx_queue_id >= dev->data->nb_rx_queues) {
2295 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2299 rxq = dev->data->rx_queues[rx_queue_id];
2300 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2302 while ((desc < rxq->nb_rx_desc) &&
2303 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2304 desc += IXGBE_RXQ_SCAN_INTERVAL;
2305 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2306 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2307 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2308 desc - rxq->nb_rx_desc]);
2315 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2317 volatile union ixgbe_adv_rx_desc *rxdp;
2318 struct ixgbe_rx_queue *rxq = rx_queue;
2321 if (unlikely(offset >= rxq->nb_rx_desc))
2323 desc = rxq->rx_tail + offset;
2324 if (desc >= rxq->nb_rx_desc)
2325 desc -= rxq->nb_rx_desc;
2327 rxdp = &rxq->rx_ring[desc];
2328 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2332 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2336 PMD_INIT_FUNC_TRACE();
2338 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2339 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
2341 txq->ops->release_mbufs(txq);
2342 txq->ops->reset(txq);
2346 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2347 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
2349 ixgbe_rx_queue_release_mbufs(rxq);
2350 ixgbe_reset_rx_queue(rxq);
2355 /*********************************************************************
2357 * Device RX/TX init functions
2359 **********************************************************************/
2362 * Receive Side Scaling (RSS)
2363 * See section 7.1.2.8 in the following document:
2364 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2367 * The source and destination IP addresses of the IP header and the source
2368 * and destination ports of TCP/UDP headers, if any, of received packets are
2369 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2370 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2371 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2372 * RSS output index which is used as the RX queue index where to store the
2374 * The following output is supplied in the RX write-back descriptor:
2375 * - 32-bit result of the Microsoft RSS hash function,
2376 * - 4-bit RSS type field.
2380 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2381 * Used as the default key.
2383 static uint8_t rss_intel_key[40] = {
2384 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2385 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2386 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2387 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2388 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2392 ixgbe_rss_disable(struct rte_eth_dev *dev)
2394 struct ixgbe_hw *hw;
2397 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2398 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2399 mrqc &= ~IXGBE_MRQC_RSSEN;
2400 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2404 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2412 hash_key = rss_conf->rss_key;
2413 if (hash_key != NULL) {
2414 /* Fill in RSS hash key */
2415 for (i = 0; i < 10; i++) {
2416 rss_key = hash_key[(i * 4)];
2417 rss_key |= hash_key[(i * 4) + 1] << 8;
2418 rss_key |= hash_key[(i * 4) + 2] << 16;
2419 rss_key |= hash_key[(i * 4) + 3] << 24;
2420 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2424 /* Set configured hashing protocols in MRQC register */
2425 rss_hf = rss_conf->rss_hf;
2426 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2427 if (rss_hf & ETH_RSS_IPV4)
2428 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2429 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2430 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2431 if (rss_hf & ETH_RSS_IPV6)
2432 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2433 if (rss_hf & ETH_RSS_IPV6_EX)
2434 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2435 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2436 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2437 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2438 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2439 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2440 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2441 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2442 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2443 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2444 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2445 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2449 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2450 struct rte_eth_rss_conf *rss_conf)
2452 struct ixgbe_hw *hw;
2456 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2459 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2460 * "RSS enabling cannot be done dynamically while it must be
2461 * preceded by a software reset"
2462 * Before changing anything, first check that the update RSS operation
2463 * does not attempt to disable RSS, if RSS was enabled at
2464 * initialization time, or does not attempt to enable RSS, if RSS was
2465 * disabled at initialization time.
2467 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2468 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2469 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2470 if (rss_hf != 0) /* Enable RSS */
2472 return 0; /* Nothing to do */
2475 if (rss_hf == 0) /* Disable RSS */
2477 ixgbe_hw_rss_hash_set(hw, rss_conf);
2482 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2483 struct rte_eth_rss_conf *rss_conf)
2485 struct ixgbe_hw *hw;
2492 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2493 hash_key = rss_conf->rss_key;
2494 if (hash_key != NULL) {
2495 /* Return RSS hash key */
2496 for (i = 0; i < 10; i++) {
2497 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2498 hash_key[(i * 4)] = rss_key & 0x000000FF;
2499 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2500 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2501 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2505 /* Get RSS functions configured in MRQC register */
2506 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2507 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2508 rss_conf->rss_hf = 0;
2512 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2513 rss_hf |= ETH_RSS_IPV4;
2514 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2515 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2516 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2517 rss_hf |= ETH_RSS_IPV6;
2518 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2519 rss_hf |= ETH_RSS_IPV6_EX;
2520 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2521 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2522 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2523 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2524 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2525 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2526 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2527 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2528 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2529 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2530 rss_conf->rss_hf = rss_hf;
2535 ixgbe_rss_configure(struct rte_eth_dev *dev)
2537 struct rte_eth_rss_conf rss_conf;
2538 struct ixgbe_hw *hw;
2543 PMD_INIT_FUNC_TRACE();
2544 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2547 * Fill in redirection table
2548 * The byte-swap is needed because NIC registers are in
2549 * little-endian order.
2552 for (i = 0, j = 0; i < 128; i++, j++) {
2553 if (j == dev->data->nb_rx_queues)
2555 reta = (reta << 8) | j;
2557 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2562 * Configure the RSS key and the RSS protocols used to compute
2563 * the RSS hash of input packets.
2565 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2566 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2567 ixgbe_rss_disable(dev);
2570 if (rss_conf.rss_key == NULL)
2571 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2572 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2575 #define NUM_VFTA_REGISTERS 128
2576 #define NIC_RX_BUFFER_SIZE 0x200
2579 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2581 struct rte_eth_vmdq_dcb_conf *cfg;
2582 struct ixgbe_hw *hw;
2583 enum rte_eth_nb_pools num_pools;
2584 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2586 uint8_t nb_tcs; /* number of traffic classes */
2589 PMD_INIT_FUNC_TRACE();
2590 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2591 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2592 num_pools = cfg->nb_queue_pools;
2593 /* Check we have a valid number of pools */
2594 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2595 ixgbe_rss_disable(dev);
2598 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2599 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2603 * split rx buffer up into sections, each for 1 traffic class
2605 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2606 for (i = 0 ; i < nb_tcs; i++) {
2607 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2608 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2609 /* clear 10 bits. */
2610 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2611 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2613 /* zero alloc all unused TCs */
2614 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2615 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2616 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2617 /* clear 10 bits. */
2618 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2621 /* MRQC: enable vmdq and dcb */
2622 mrqc = ((num_pools == ETH_16_POOLS) ? \
2623 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2624 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2626 /* PFVTCTL: turn on virtualisation and set the default pool */
2627 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2628 if (cfg->enable_default_pool) {
2629 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2631 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2634 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2636 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2638 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2640 * mapping is done with 3 bits per priority,
2641 * so shift by i*3 each time
2643 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2645 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2647 /* RTRPCS: DCB related */
2648 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2650 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2651 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2652 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2653 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2655 /* VFTA - enable all vlan filters */
2656 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2657 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2660 /* VFRE: pool enabling for receive - 16 or 32 */
2661 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2662 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2665 * MPSAR - allow pools to read specific mac addresses
2666 * In this case, all pools should be able to read from mac addr 0
2668 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2669 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2671 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2672 for (i = 0; i < cfg->nb_pool_maps; i++) {
2673 /* set vlan id in VF register and set the valid bit */
2674 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2675 (cfg->pool_map[i].vlan_id & 0xFFF)));
2677 * Put the allowed pools in VFB reg. As we only have 16 or 32
2678 * pools, we only need to use the first half of the register
2681 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2686 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2687 * @hw: pointer to hardware structure
2688 * @dcb_config: pointer to ixgbe_dcb_config structure
2691 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2692 struct ixgbe_dcb_config *dcb_config)
2697 PMD_INIT_FUNC_TRACE();
2698 if (hw->mac.type != ixgbe_mac_82598EB) {
2699 /* Disable the Tx desc arbiter so that MTQC can be changed */
2700 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2701 reg |= IXGBE_RTTDCS_ARBDIS;
2702 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2704 /* Enable DCB for Tx with 8 TCs */
2705 if (dcb_config->num_tcs.pg_tcs == 8) {
2706 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2709 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2711 if (dcb_config->vt_mode)
2712 reg |= IXGBE_MTQC_VT_ENA;
2713 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2715 /* Disable drop for all queues */
2716 for (q = 0; q < 128; q++)
2717 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2718 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2720 /* Enable the Tx desc arbiter */
2721 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2722 reg &= ~IXGBE_RTTDCS_ARBDIS;
2723 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2725 /* Enable Security TX Buffer IFG for DCB */
2726 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2727 reg |= IXGBE_SECTX_DCB;
2728 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2734 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2735 * @dev: pointer to rte_eth_dev structure
2736 * @dcb_config: pointer to ixgbe_dcb_config structure
2739 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2740 struct ixgbe_dcb_config *dcb_config)
2742 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2743 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2744 struct ixgbe_hw *hw =
2745 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2747 PMD_INIT_FUNC_TRACE();
2748 if (hw->mac.type != ixgbe_mac_82598EB)
2749 /*PF VF Transmit Enable*/
2750 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2751 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2753 /*Configure general DCB TX parameters*/
2754 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2759 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2760 struct ixgbe_dcb_config *dcb_config)
2762 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2763 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2764 struct ixgbe_dcb_tc_config *tc;
2767 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2768 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2769 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2770 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2773 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2774 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2776 /* User Priority to Traffic Class mapping */
2777 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2778 j = vmdq_rx_conf->dcb_queue[i];
2779 tc = &dcb_config->tc_config[j];
2780 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2786 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2787 struct ixgbe_dcb_config *dcb_config)
2789 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2790 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2791 struct ixgbe_dcb_tc_config *tc;
2794 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2795 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2796 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2797 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2800 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2801 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2804 /* User Priority to Traffic Class mapping */
2805 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2806 j = vmdq_tx_conf->dcb_queue[i];
2807 tc = &dcb_config->tc_config[j];
2808 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2815 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2816 struct ixgbe_dcb_config *dcb_config)
2818 struct rte_eth_dcb_rx_conf *rx_conf =
2819 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2820 struct ixgbe_dcb_tc_config *tc;
2823 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2824 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2826 /* User Priority to Traffic Class mapping */
2827 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2828 j = rx_conf->dcb_queue[i];
2829 tc = &dcb_config->tc_config[j];
2830 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2836 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2837 struct ixgbe_dcb_config *dcb_config)
2839 struct rte_eth_dcb_tx_conf *tx_conf =
2840 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2841 struct ixgbe_dcb_tc_config *tc;
2844 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2845 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2847 /* User Priority to Traffic Class mapping */
2848 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2849 j = tx_conf->dcb_queue[i];
2850 tc = &dcb_config->tc_config[j];
2851 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2857 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2858 * @hw: pointer to hardware structure
2859 * @dcb_config: pointer to ixgbe_dcb_config structure
2862 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2863 struct ixgbe_dcb_config *dcb_config)
2869 PMD_INIT_FUNC_TRACE();
2871 * Disable the arbiter before changing parameters
2872 * (always enable recycle mode; WSP)
2874 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2875 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2877 if (hw->mac.type != ixgbe_mac_82598EB) {
2878 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2879 if (dcb_config->num_tcs.pg_tcs == 4) {
2880 if (dcb_config->vt_mode)
2881 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2882 IXGBE_MRQC_VMDQRT4TCEN;
2884 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2885 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2889 if (dcb_config->num_tcs.pg_tcs == 8) {
2890 if (dcb_config->vt_mode)
2891 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2892 IXGBE_MRQC_VMDQRT8TCEN;
2894 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2895 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2900 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2903 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2904 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2905 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2906 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2908 /* VFTA - enable all vlan filters */
2909 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2910 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2914 * Configure Rx packet plane (recycle mode; WSP) and
2917 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2918 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2924 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2925 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2927 switch (hw->mac.type) {
2928 case ixgbe_mac_82598EB:
2929 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2931 case ixgbe_mac_82599EB:
2932 case ixgbe_mac_X540:
2933 case ixgbe_mac_X550:
2934 case ixgbe_mac_X550EM_x:
2935 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2944 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2945 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2947 switch (hw->mac.type) {
2948 case ixgbe_mac_82598EB:
2949 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2950 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2952 case ixgbe_mac_82599EB:
2953 case ixgbe_mac_X540:
2954 case ixgbe_mac_X550:
2955 case ixgbe_mac_X550EM_x:
2956 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2957 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2964 #define DCB_RX_CONFIG 1
2965 #define DCB_TX_CONFIG 1
2966 #define DCB_TX_PB 1024
2968 * ixgbe_dcb_hw_configure - Enable DCB and configure
2969 * general DCB in VT mode and non-VT mode parameters
2970 * @dev: pointer to rte_eth_dev structure
2971 * @dcb_config: pointer to ixgbe_dcb_config structure
2974 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2975 struct ixgbe_dcb_config *dcb_config)
2978 uint8_t i,pfc_en,nb_tcs;
2980 uint8_t config_dcb_rx = 0;
2981 uint8_t config_dcb_tx = 0;
2982 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2983 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2984 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2985 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2986 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2987 struct ixgbe_dcb_tc_config *tc;
2988 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2989 struct ixgbe_hw *hw =
2990 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2992 switch(dev->data->dev_conf.rxmode.mq_mode){
2993 case ETH_MQ_RX_VMDQ_DCB:
2994 dcb_config->vt_mode = true;
2995 if (hw->mac.type != ixgbe_mac_82598EB) {
2996 config_dcb_rx = DCB_RX_CONFIG;
2998 *get dcb and VT rx configuration parameters
3001 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
3002 /*Configure general VMDQ and DCB RX parameters*/
3003 ixgbe_vmdq_dcb_configure(dev);
3007 dcb_config->vt_mode = false;
3008 config_dcb_rx = DCB_RX_CONFIG;
3009 /* Get dcb TX configuration parameters from rte_eth_conf */
3010 ixgbe_dcb_rx_config(dev,dcb_config);
3011 /*Configure general DCB RX parameters*/
3012 ixgbe_dcb_rx_hw_config(hw, dcb_config);
3015 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3018 switch (dev->data->dev_conf.txmode.mq_mode) {
3019 case ETH_MQ_TX_VMDQ_DCB:
3020 dcb_config->vt_mode = true;
3021 config_dcb_tx = DCB_TX_CONFIG;
3022 /* get DCB and VT TX configuration parameters from rte_eth_conf */
3023 ixgbe_dcb_vt_tx_config(dev,dcb_config);
3024 /*Configure general VMDQ and DCB TX parameters*/
3025 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
3029 dcb_config->vt_mode = false;
3030 config_dcb_tx = DCB_TX_CONFIG;
3031 /*get DCB TX configuration parameters from rte_eth_conf*/
3032 ixgbe_dcb_tx_config(dev,dcb_config);
3033 /*Configure general DCB TX parameters*/
3034 ixgbe_dcb_tx_hw_config(hw, dcb_config);
3037 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3041 nb_tcs = dcb_config->num_tcs.pfc_tcs;
3043 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3044 if(nb_tcs == ETH_4_TCS) {
3045 /* Avoid un-configured priority mapping to TC0 */
3047 uint8_t mask = 0xFF;
3048 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3049 mask = (uint8_t)(mask & (~ (1 << map[i])));
3050 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3051 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3055 /* Re-configure 4 TCs BW */
3056 for (i = 0; i < nb_tcs; i++) {
3057 tc = &dcb_config->tc_config[i];
3058 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3059 (uint8_t)(100 / nb_tcs);
3060 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3061 (uint8_t)(100 / nb_tcs);
3063 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3064 tc = &dcb_config->tc_config[i];
3065 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3066 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3071 /* Set RX buffer size */
3072 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3073 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3074 for (i = 0 ; i < nb_tcs; i++) {
3075 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3077 /* zero alloc all unused TCs */
3078 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3079 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3083 /* Only support an equally distributed Tx packet buffer strategy. */
3084 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3085 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3086 for (i = 0; i < nb_tcs; i++) {
3087 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3088 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3090 /* Clear unused TCs, if any, to zero buffer size*/
3091 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3092 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3093 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3097 /*Calculates traffic class credits*/
3098 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3099 IXGBE_DCB_TX_CONFIG);
3100 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3101 IXGBE_DCB_RX_CONFIG);
3104 /* Unpack CEE standard containers */
3105 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3106 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3107 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3108 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3109 /* Configure PG(ETS) RX */
3110 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3114 /* Unpack CEE standard containers */
3115 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3116 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3117 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3118 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3119 /* Configure PG(ETS) TX */
3120 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3123 /*Configure queue statistics registers*/
3124 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3126 /* Check if the PFC is supported */
3127 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3128 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3129 for (i = 0; i < nb_tcs; i++) {
3131 * If the TC count is 8,and the default high_water is 48,
3132 * the low_water is 16 as default.
3134 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3135 hw->fc.low_water[i] = pbsize / 4;
3136 /* Enable pfc for this TC */
3137 tc = &dcb_config->tc_config[i];
3138 tc->pfc = ixgbe_dcb_pfc_enabled;
3140 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3141 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3143 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3150 * ixgbe_configure_dcb - Configure DCB Hardware
3151 * @dev: pointer to rte_eth_dev
3153 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3155 struct ixgbe_dcb_config *dcb_cfg =
3156 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3157 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3159 PMD_INIT_FUNC_TRACE();
3161 /* check support mq_mode for DCB */
3162 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3163 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3166 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3169 /** Configure DCB hardware **/
3170 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3176 * VMDq only support for 10 GbE NIC.
3179 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3181 struct rte_eth_vmdq_rx_conf *cfg;
3182 struct ixgbe_hw *hw;
3183 enum rte_eth_nb_pools num_pools;
3184 uint32_t mrqc, vt_ctl, vlanctrl;
3188 PMD_INIT_FUNC_TRACE();
3189 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3190 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3191 num_pools = cfg->nb_queue_pools;
3193 ixgbe_rss_disable(dev);
3195 /* MRQC: enable vmdq */
3196 mrqc = IXGBE_MRQC_VMDQEN;
3197 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3199 /* PFVTCTL: turn on virtualisation and set the default pool */
3200 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3201 if (cfg->enable_default_pool)
3202 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3204 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3206 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3208 for (i = 0; i < (int)num_pools; i++) {
3209 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3210 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3213 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3214 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3215 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3216 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3218 /* VFTA - enable all vlan filters */
3219 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3220 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3222 /* VFRE: pool enabling for receive - 64 */
3223 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3224 if (num_pools == ETH_64_POOLS)
3225 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3228 * MPSAR - allow pools to read specific mac addresses
3229 * In this case, all pools should be able to read from mac addr 0
3231 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3232 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3234 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3235 for (i = 0; i < cfg->nb_pool_maps; i++) {
3236 /* set vlan id in VF register and set the valid bit */
3237 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3238 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3240 * Put the allowed pools in VFB reg. As we only have 16 or 64
3241 * pools, we only need to use the first half of the register
3244 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3245 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3246 (cfg->pool_map[i].pools & UINT32_MAX));
3248 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3249 ((cfg->pool_map[i].pools >> 32) \
3254 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3255 if (cfg->enable_loop_back) {
3256 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3257 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3258 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3261 IXGBE_WRITE_FLUSH(hw);
3265 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3266 * @hw: pointer to hardware structure
3269 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3274 PMD_INIT_FUNC_TRACE();
3275 /*PF VF Transmit Enable*/
3276 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3277 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3279 /* Disable the Tx desc arbiter so that MTQC can be changed */
3280 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3281 reg |= IXGBE_RTTDCS_ARBDIS;
3282 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3284 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3285 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3287 /* Disable drop for all queues */
3288 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3289 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3290 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3292 /* Enable the Tx desc arbiter */
3293 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3294 reg &= ~IXGBE_RTTDCS_ARBDIS;
3295 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3297 IXGBE_WRITE_FLUSH(hw);
3303 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
3305 struct ixgbe_rx_entry *rxe = rxq->sw_ring;
3309 /* Initialize software ring entries */
3310 for (i = 0; i < rxq->nb_rx_desc; i++) {
3311 volatile union ixgbe_adv_rx_desc *rxd;
3312 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3314 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3315 (unsigned) rxq->queue_id);
3319 rte_mbuf_refcnt_set(mbuf, 1);
3321 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3323 mbuf->port = rxq->port_id;
3326 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3327 rxd = &rxq->rx_ring[i];
3328 rxd->read.hdr_addr = dma_addr;
3329 rxd->read.pkt_addr = dma_addr;
3337 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
3339 struct ixgbe_hw *hw;
3342 ixgbe_rss_configure(dev);
3344 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3346 /* MRQC: enable VF RSS */
3347 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
3348 mrqc &= ~IXGBE_MRQC_MRQE_MASK;
3349 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3351 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
3355 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
3359 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
3363 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3369 ixgbe_config_vf_default(struct rte_eth_dev *dev)
3371 struct ixgbe_hw *hw =
3372 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3374 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3376 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3381 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3382 IXGBE_MRQC_VMDQRT4TCEN);
3386 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3387 IXGBE_MRQC_VMDQRT8TCEN);
3391 "invalid pool number in IOV mode");
3398 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3400 struct ixgbe_hw *hw =
3401 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3403 if (hw->mac.type == ixgbe_mac_82598EB)
3406 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3408 * SRIOV inactive scheme
3409 * any DCB/RSS w/o VMDq multi-queue setting
3411 switch (dev->data->dev_conf.rxmode.mq_mode) {
3413 ixgbe_rss_configure(dev);
3416 case ETH_MQ_RX_VMDQ_DCB:
3417 ixgbe_vmdq_dcb_configure(dev);
3420 case ETH_MQ_RX_VMDQ_ONLY:
3421 ixgbe_vmdq_rx_hw_configure(dev);
3424 case ETH_MQ_RX_NONE:
3425 /* if mq_mode is none, disable rss mode.*/
3426 default: ixgbe_rss_disable(dev);
3430 * SRIOV active scheme
3431 * Support RSS together with VMDq & SRIOV
3433 switch (dev->data->dev_conf.rxmode.mq_mode) {
3435 case ETH_MQ_RX_VMDQ_RSS:
3436 ixgbe_config_vf_rss(dev);
3439 /* FIXME if support DCB/RSS together with VMDq & SRIOV */
3440 case ETH_MQ_RX_VMDQ_DCB:
3441 case ETH_MQ_RX_VMDQ_DCB_RSS:
3443 "Could not support DCB with VMDq & SRIOV");
3446 ixgbe_config_vf_default(dev);
3455 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3457 struct ixgbe_hw *hw =
3458 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462 if (hw->mac.type == ixgbe_mac_82598EB)
3465 /* disable arbiter before setting MTQC */
3466 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3467 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3468 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3470 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3472 * SRIOV inactive scheme
3473 * any DCB w/o VMDq multi-queue setting
3475 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3476 ixgbe_vmdq_tx_hw_configure(hw);
3478 mtqc = IXGBE_MTQC_64Q_1PB;
3479 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3482 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3485 * SRIOV active scheme
3486 * FIXME if support DCB together with VMDq & SRIOV
3489 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3492 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3495 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3499 mtqc = IXGBE_MTQC_64Q_1PB;
3500 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3502 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3505 /* re-enable arbiter */
3506 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3507 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3513 * Initializes Receive Unit.
3516 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3518 struct ixgbe_hw *hw;
3519 struct ixgbe_rx_queue *rxq;
3520 struct rte_pktmbuf_pool_private *mbp_priv;
3532 PMD_INIT_FUNC_TRACE();
3533 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3536 * Make sure receives are disabled while setting
3537 * up the RX context (registers, descriptor rings, etc.).
3539 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3540 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3542 /* Enable receipt of broadcasted frames */
3543 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3544 fctrl |= IXGBE_FCTRL_BAM;
3545 fctrl |= IXGBE_FCTRL_DPF;
3546 fctrl |= IXGBE_FCTRL_PMCF;
3547 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3550 * Configure CRC stripping, if any.
3552 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3553 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3554 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3556 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3559 * Configure jumbo frame support, if any.
3561 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3562 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3563 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3564 maxfrs &= 0x0000FFFF;
3565 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3566 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3568 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3571 * If loopback mode is configured for 82599, set LPBK bit.
3573 if (hw->mac.type == ixgbe_mac_82599EB &&
3574 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3575 hlreg0 |= IXGBE_HLREG0_LPBK;
3577 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3579 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3581 /* Setup RX queues */
3582 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3583 rxq = dev->data->rx_queues[i];
3586 * Reset crc_len in case it was changed after queue setup by a
3587 * call to configure.
3589 rxq->crc_len = (uint8_t)
3590 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3593 /* Setup the Base and Length of the Rx Descriptor Rings */
3594 bus_addr = rxq->rx_ring_phys_addr;
3595 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3596 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3597 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3598 (uint32_t)(bus_addr >> 32));
3599 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3600 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3601 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3602 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3604 /* Configure the SRRCTL register */
3605 #ifdef RTE_HEADER_SPLIT_ENABLE
3607 * Configure Header Split
3609 if (dev->data->dev_conf.rxmode.header_split) {
3610 if (hw->mac.type == ixgbe_mac_82599EB) {
3611 /* Must setup the PSRTYPE register */
3613 psrtype = IXGBE_PSRTYPE_TCPHDR |
3614 IXGBE_PSRTYPE_UDPHDR |
3615 IXGBE_PSRTYPE_IPV4HDR |
3616 IXGBE_PSRTYPE_IPV6HDR;
3617 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3619 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3620 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3621 IXGBE_SRRCTL_BSIZEHDR_MASK);
3622 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3625 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3627 /* Set if packets are dropped when no descriptors available */
3629 srrctl |= IXGBE_SRRCTL_DROP_EN;
3632 * Configure the RX buffer size in the BSIZEPACKET field of
3633 * the SRRCTL register of the queue.
3634 * The value is in 1 KB resolution. Valid values can be from
3637 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3638 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3639 RTE_PKTMBUF_HEADROOM);
3640 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3641 IXGBE_SRRCTL_BSIZEPKT_MASK);
3642 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3644 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3645 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3647 if (dev->data->dev_conf.rxmode.enable_scatter ||
3648 /* It adds dual VLAN length for supporting dual VLAN */
3649 (dev->data->dev_conf.rxmode.max_rx_pkt_len +
3650 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3651 if (!dev->data->scattered_rx)
3652 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
3653 dev->data->scattered_rx = 1;
3654 #ifdef RTE_IXGBE_INC_VECTOR
3655 if (rte_is_power_of_2(rxq->nb_rx_desc))
3657 ixgbe_recv_scattered_pkts_vec;
3660 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3665 * Device configured with multiple RX queues.
3667 ixgbe_dev_mq_rx_configure(dev);
3670 * Setup the Checksum Register.
3671 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3672 * Enable IP/L4 checkum computation by hardware if requested to do so.
3674 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3675 rxcsum |= IXGBE_RXCSUM_PCSD;
3676 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3677 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3679 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3681 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3683 if (hw->mac.type == ixgbe_mac_82599EB ||
3684 hw->mac.type == ixgbe_mac_X540) {
3685 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3686 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3687 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3689 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3690 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3691 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3698 * Initializes Transmit Unit.
3701 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3703 struct ixgbe_hw *hw;
3704 struct ixgbe_tx_queue *txq;
3710 PMD_INIT_FUNC_TRACE();
3711 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3713 /* Enable TX CRC (checksum offload requirement) and hw padding
3714 * (TSO requirement) */
3715 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3716 hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
3717 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3719 /* Setup the Base and Length of the Tx Descriptor Rings */
3720 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3721 txq = dev->data->tx_queues[i];
3723 bus_addr = txq->tx_ring_phys_addr;
3724 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3725 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3726 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3727 (uint32_t)(bus_addr >> 32));
3728 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3729 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3730 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3731 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3732 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3735 * Disable Tx Head Writeback RO bit, since this hoses
3736 * bookkeeping if things aren't delivered in order.
3738 switch (hw->mac.type) {
3739 case ixgbe_mac_82598EB:
3740 txctrl = IXGBE_READ_REG(hw,
3741 IXGBE_DCA_TXCTRL(txq->reg_idx));
3742 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3743 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3747 case ixgbe_mac_82599EB:
3748 case ixgbe_mac_X540:
3749 case ixgbe_mac_X550:
3750 case ixgbe_mac_X550EM_x:
3752 txctrl = IXGBE_READ_REG(hw,
3753 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3754 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3755 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3761 /* Device configured with multiple TX queues. */
3762 ixgbe_dev_mq_tx_configure(dev);
3766 * Set up link for 82599 loopback mode Tx->Rx.
3769 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3771 PMD_INIT_FUNC_TRACE();
3773 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3774 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3776 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
3785 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3786 ixgbe_reset_pipeline_82599(hw);
3788 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3794 * Start Transmit and Receive Units.
3797 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3799 struct ixgbe_hw *hw;
3800 struct ixgbe_tx_queue *txq;
3801 struct ixgbe_rx_queue *rxq;
3808 PMD_INIT_FUNC_TRACE();
3809 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3811 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3812 txq = dev->data->tx_queues[i];
3813 /* Setup Transmit Threshold Registers */
3814 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3815 txdctl |= txq->pthresh & 0x7F;
3816 txdctl |= ((txq->hthresh & 0x7F) << 8);
3817 txdctl |= ((txq->wthresh & 0x7F) << 16);
3818 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3821 if (hw->mac.type != ixgbe_mac_82598EB) {
3822 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3823 dmatxctl |= IXGBE_DMATXCTL_TE;
3824 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3827 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3828 txq = dev->data->tx_queues[i];
3829 if (!txq->tx_deferred_start) {
3830 ret = ixgbe_dev_tx_queue_start(dev, i);
3836 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3837 rxq = dev->data->rx_queues[i];
3838 if (!rxq->rx_deferred_start) {
3839 ret = ixgbe_dev_rx_queue_start(dev, i);
3845 /* Enable Receive engine */
3846 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3847 if (hw->mac.type == ixgbe_mac_82598EB)
3848 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3849 rxctrl |= IXGBE_RXCTRL_RXEN;
3850 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3852 /* If loopback mode is enabled for 82599, set up the link accordingly */
3853 if (hw->mac.type == ixgbe_mac_82599EB &&
3854 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3855 ixgbe_setup_loopback_link_82599(hw);
3861 * Start Receive Units for specified queue.
3864 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3866 struct ixgbe_hw *hw;
3867 struct ixgbe_rx_queue *rxq;
3871 PMD_INIT_FUNC_TRACE();
3872 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3874 if (rx_queue_id < dev->data->nb_rx_queues) {
3875 rxq = dev->data->rx_queues[rx_queue_id];
3877 /* Allocate buffers for descriptor rings */
3878 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
3879 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
3883 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3884 rxdctl |= IXGBE_RXDCTL_ENABLE;
3885 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3887 /* Wait until RX Enable ready */
3888 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3891 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3892 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3894 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
3897 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3898 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3906 * Stop Receive Units for specified queue.
3909 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3911 struct ixgbe_hw *hw;
3912 struct ixgbe_rx_queue *rxq;
3916 PMD_INIT_FUNC_TRACE();
3917 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3919 if (rx_queue_id < dev->data->nb_rx_queues) {
3920 rxq = dev->data->rx_queues[rx_queue_id];
3922 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3923 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3924 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3926 /* Wait until RX Enable ready */
3927 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3930 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3931 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
3933 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
3936 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3938 ixgbe_rx_queue_release_mbufs(rxq);
3939 ixgbe_reset_rx_queue(rxq);
3948 * Start Transmit Units for specified queue.
3951 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3953 struct ixgbe_hw *hw;
3954 struct ixgbe_tx_queue *txq;
3958 PMD_INIT_FUNC_TRACE();
3959 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3961 if (tx_queue_id < dev->data->nb_tx_queues) {
3962 txq = dev->data->tx_queues[tx_queue_id];
3963 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3964 txdctl |= IXGBE_TXDCTL_ENABLE;
3965 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3967 /* Wait until TX Enable ready */
3968 if (hw->mac.type == ixgbe_mac_82599EB) {
3969 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3972 txdctl = IXGBE_READ_REG(hw,
3973 IXGBE_TXDCTL(txq->reg_idx));
3974 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3976 PMD_INIT_LOG(ERR, "Could not enable "
3977 "Tx Queue %d", tx_queue_id);
3980 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3981 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3989 * Stop Transmit Units for specified queue.
3992 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3994 struct ixgbe_hw *hw;
3995 struct ixgbe_tx_queue *txq;
3997 uint32_t txtdh, txtdt;
4000 PMD_INIT_FUNC_TRACE();
4001 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4003 if (tx_queue_id < dev->data->nb_tx_queues) {
4004 txq = dev->data->tx_queues[tx_queue_id];
4006 /* Wait until TX queue is empty */
4007 if (hw->mac.type == ixgbe_mac_82599EB) {
4008 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4010 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4011 txtdh = IXGBE_READ_REG(hw,
4012 IXGBE_TDH(txq->reg_idx));
4013 txtdt = IXGBE_READ_REG(hw,
4014 IXGBE_TDT(txq->reg_idx));
4015 } while (--poll_ms && (txtdh != txtdt));
4017 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
4018 "when stopping.", tx_queue_id);
4021 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4022 txdctl &= ~IXGBE_TXDCTL_ENABLE;
4023 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4025 /* Wait until TX Enable ready */
4026 if (hw->mac.type == ixgbe_mac_82599EB) {
4027 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4030 txdctl = IXGBE_READ_REG(hw,
4031 IXGBE_TXDCTL(txq->reg_idx));
4032 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
4034 PMD_INIT_LOG(ERR, "Could not disable "
4035 "Tx Queue %d", tx_queue_id);
4038 if (txq->ops != NULL) {
4039 txq->ops->release_mbufs(txq);
4040 txq->ops->reset(txq);
4049 * [VF] Initializes Receive Unit.
4052 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
4054 struct ixgbe_hw *hw;
4055 struct ixgbe_rx_queue *rxq;
4056 struct rte_pktmbuf_pool_private *mbp_priv;
4058 uint32_t srrctl, psrtype = 0;
4063 PMD_INIT_FUNC_TRACE();
4064 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4066 if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
4067 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4068 "it should be power of 2");
4072 if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
4073 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4074 "it should be equal to or less than %d",
4075 hw->mac.max_rx_queues);
4080 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
4081 * disables the VF receipt of packets if the PF MTU is > 1500.
4082 * This is done to deal with 82599 limitations that imposes
4083 * the PF and all VFs to share the same MTU.
4084 * Then, the PF driver enables again the VF receipt of packet when
4085 * the VF driver issues a IXGBE_VF_SET_LPE request.
4086 * In the meantime, the VF device cannot be used, even if the VF driver
4087 * and the Guest VM network stack are ready to accept packets with a
4088 * size up to the PF MTU.
4089 * As a work-around to this PF behaviour, force the call to
4090 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
4091 * VF packets received can work in all cases.
4093 ixgbevf_rlpml_set_vf(hw,
4094 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
4096 /* Setup RX queues */
4097 dev->rx_pkt_burst = ixgbe_recv_pkts;
4098 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4099 rxq = dev->data->rx_queues[i];
4101 /* Allocate buffers for descriptor rings */
4102 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
4106 /* Setup the Base and Length of the Rx Descriptor Rings */
4107 bus_addr = rxq->rx_ring_phys_addr;
4109 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
4110 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4111 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
4112 (uint32_t)(bus_addr >> 32));
4113 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
4114 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4115 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
4116 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
4119 /* Configure the SRRCTL register */
4120 #ifdef RTE_HEADER_SPLIT_ENABLE
4122 * Configure Header Split
4124 if (dev->data->dev_conf.rxmode.header_split) {
4125 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
4126 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4127 IXGBE_SRRCTL_BSIZEHDR_MASK);
4128 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4131 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4133 /* Set if packets are dropped when no descriptors available */
4135 srrctl |= IXGBE_SRRCTL_DROP_EN;
4138 * Configure the RX buffer size in the BSIZEPACKET field of
4139 * the SRRCTL register of the queue.
4140 * The value is in 1 KB resolution. Valid values can be from
4143 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
4144 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
4145 RTE_PKTMBUF_HEADROOM);
4146 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4147 IXGBE_SRRCTL_BSIZEPKT_MASK);
4150 * VF modification to write virtual function SRRCTL register
4152 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4154 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4155 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4157 if (dev->data->dev_conf.rxmode.enable_scatter ||
4158 /* It adds dual VLAN length for supporting dual VLAN */
4159 (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4160 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4161 if (!dev->data->scattered_rx)
4162 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4163 dev->data->scattered_rx = 1;
4164 #ifdef RTE_IXGBE_INC_VECTOR
4165 if (rte_is_power_of_2(rxq->nb_rx_desc))
4167 ixgbe_recv_scattered_pkts_vec;
4170 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4174 #ifdef RTE_HEADER_SPLIT_ENABLE
4175 if (dev->data->dev_conf.rxmode.header_split)
4176 /* Must setup the PSRTYPE register */
4177 psrtype = IXGBE_PSRTYPE_TCPHDR |
4178 IXGBE_PSRTYPE_UDPHDR |
4179 IXGBE_PSRTYPE_IPV4HDR |
4180 IXGBE_PSRTYPE_IPV6HDR;
4183 /* Set RQPL for VF RSS according to max Rx queue */
4184 psrtype |= (dev->data->nb_rx_queues >> 1) <<
4185 IXGBE_PSRTYPE_RQPL_SHIFT;
4186 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
4192 * [VF] Initializes Transmit Unit.
4195 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4197 struct ixgbe_hw *hw;
4198 struct ixgbe_tx_queue *txq;
4203 PMD_INIT_FUNC_TRACE();
4204 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4206 /* Setup the Base and Length of the Tx Descriptor Rings */
4207 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4208 txq = dev->data->tx_queues[i];
4209 bus_addr = txq->tx_ring_phys_addr;
4210 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4211 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4212 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4213 (uint32_t)(bus_addr >> 32));
4214 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4215 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4216 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4217 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4218 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4221 * Disable Tx Head Writeback RO bit, since this hoses
4222 * bookkeeping if things aren't delivered in order.
4224 txctrl = IXGBE_READ_REG(hw,
4225 IXGBE_VFDCA_TXCTRL(i));
4226 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4227 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4233 * [VF] Start Transmit and Receive Units.
4236 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4238 struct ixgbe_hw *hw;
4239 struct ixgbe_tx_queue *txq;
4240 struct ixgbe_rx_queue *rxq;
4246 PMD_INIT_FUNC_TRACE();
4247 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4249 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4250 txq = dev->data->tx_queues[i];
4251 /* Setup Transmit Threshold Registers */
4252 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4253 txdctl |= txq->pthresh & 0x7F;
4254 txdctl |= ((txq->hthresh & 0x7F) << 8);
4255 txdctl |= ((txq->wthresh & 0x7F) << 16);
4256 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4259 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4261 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4262 txdctl |= IXGBE_TXDCTL_ENABLE;
4263 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4266 /* Wait until TX Enable ready */
4269 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4270 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4272 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4274 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4276 rxq = dev->data->rx_queues[i];
4278 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4279 rxdctl |= IXGBE_RXDCTL_ENABLE;
4280 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4282 /* Wait until RX Enable ready */
4286 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4287 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4289 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4291 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);