4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <rte_common.h>
39 #include <rte_memory.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
42 #include <rte_prefetch.h>
43 #include <rte_branch_prediction.h>
46 #include "rte_sched.h"
47 #include "rte_bitmap.h"
48 #include "rte_sched_common.h"
49 #include "rte_approx.h"
51 #ifdef __INTEL_COMPILER
52 #pragma warning(disable:2259) /* conversion may lose significant bits */
55 #ifndef RTE_SCHED_OPTIMIZATIONS
56 #define RTE_SCHED_OPTIMIZATIONS 0
59 #if RTE_SCHED_OPTIMIZATIONS
60 #include <immintrin.h>
63 #ifndef RTE_SCHED_TB_RATE_CONFIG_ERR
64 #define RTE_SCHED_TB_RATE_CONFIG_ERR (1e-7)
67 #define RTE_SCHED_WRR 1
69 #ifndef RTE_SCHED_WRR_SHIFT
70 #define RTE_SCHED_WRR_SHIFT 3
73 #ifndef RTE_SCHED_PORT_N_GRINDERS
74 #define RTE_SCHED_PORT_N_GRINDERS 8
76 #if (RTE_SCHED_PORT_N_GRINDERS == 0) || (RTE_SCHED_PORT_N_GRINDERS & (RTE_SCHED_PORT_N_GRINDERS - 1))
77 #error Number of grinders must be non-zero and a power of 2
79 #if (RTE_SCHED_OPTIMIZATIONS && (RTE_SCHED_PORT_N_GRINDERS != 8))
80 #error Number of grinders must be 8 when RTE_SCHED_OPTIMIZATIONS is set
83 #define RTE_SCHED_GRINDER_PCACHE_SIZE (64 / RTE_SCHED_QUEUES_PER_PIPE)
85 #define RTE_SCHED_PIPE_INVALID UINT32_MAX
87 #define RTE_SCHED_BMP_POS_INVALID UINT32_MAX
89 struct rte_sched_subport {
90 /* Token bucket (TB) */
91 uint64_t tb_time; /* time of last update */
93 uint32_t tb_credits_per_period;
97 /* Traffic classes (TCs) */
98 uint64_t tc_time; /* time of next update */
99 uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
100 uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
103 /* TC oversubscription */
105 uint32_t tc_ov_wm_min;
106 uint32_t tc_ov_wm_max;
107 uint8_t tc_ov_period_id;
113 struct rte_sched_subport_stats stats;
116 struct rte_sched_pipe_profile {
117 /* Token bucket (TB) */
119 uint32_t tb_credits_per_period;
122 /* Pipe traffic classes */
124 uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
125 uint8_t tc_ov_weight;
128 uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_PIPE];
131 struct rte_sched_pipe {
132 /* Token bucket (TB) */
133 uint64_t tb_time; /* time of last update */
136 /* Pipe profile and flags */
139 /* Traffic classes (TCs) */
140 uint64_t tc_time; /* time of next update */
141 uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
143 /* Weighted Round Robin (WRR) */
144 uint8_t wrr_tokens[RTE_SCHED_QUEUES_PER_PIPE];
146 /* TC oversubscription */
147 uint32_t tc_ov_credits;
148 uint8_t tc_ov_period_id;
150 } __rte_cache_aligned;
152 struct rte_sched_queue {
157 struct rte_sched_queue_extra {
158 struct rte_sched_queue_stats stats;
165 e_GRINDER_PREFETCH_PIPE = 0,
166 e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS,
167 e_GRINDER_PREFETCH_MBUF,
172 * Path through the scheduler hierarchy used by the scheduler enqueue
173 * operation to identify the destination queue for the current
174 * packet. Stored in the field pkt.hash.sched of struct rte_mbuf of
175 * each packet, typically written by the classification stage and read
176 * by scheduler enqueue.
178 struct rte_sched_port_hierarchy {
179 uint32_t queue:2; /**< Queue ID (0 .. 3) */
180 uint32_t traffic_class:2; /**< Traffic class ID (0 .. 3)*/
181 uint32_t pipe:20; /**< Pipe ID */
182 uint32_t subport:6; /**< Subport ID */
183 uint32_t color:2; /**< Color */
186 struct rte_sched_grinder {
188 uint16_t pcache_qmask[RTE_SCHED_GRINDER_PCACHE_SIZE];
189 uint32_t pcache_qindex[RTE_SCHED_GRINDER_PCACHE_SIZE];
194 enum grinder_state state;
197 struct rte_sched_subport *subport;
198 struct rte_sched_pipe *pipe;
199 struct rte_sched_pipe_profile *pipe_params;
202 uint8_t tccache_qmask[4];
203 uint32_t tccache_qindex[4];
209 struct rte_sched_queue *queue[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
210 struct rte_mbuf **qbase[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
211 uint32_t qindex[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
215 struct rte_mbuf *pkt;
218 uint16_t wrr_tokens[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
219 uint16_t wrr_mask[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
220 uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
223 struct rte_sched_port {
224 /* User parameters */
225 uint32_t n_subports_per_port;
226 uint32_t n_pipes_per_subport;
229 uint32_t frame_overhead;
230 uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
231 uint32_t n_pipe_profiles;
232 uint32_t pipe_tc3_rate_max;
234 struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][e_RTE_METER_COLORS];
238 uint64_t time_cpu_cycles; /* Current CPU time measured in CPU cyles */
239 uint64_t time_cpu_bytes; /* Current CPU time measured in bytes */
240 uint64_t time; /* Current NIC TX time measured in bytes */
241 double cycles_per_byte; /* CPU cycles per byte */
243 /* Scheduling loop detection */
245 uint32_t pipe_exhaustion;
248 struct rte_bitmap *bmp;
249 uint32_t grinder_base_bmp_pos[RTE_SCHED_PORT_N_GRINDERS] __rte_aligned_16;
252 struct rte_sched_grinder grinder[RTE_SCHED_PORT_N_GRINDERS];
253 uint32_t busy_grinders;
254 struct rte_mbuf **pkts_out;
257 /* Queue base calculation */
258 uint32_t qsize_add[RTE_SCHED_QUEUES_PER_PIPE];
261 /* Large data structures */
262 struct rte_sched_subport *subport;
263 struct rte_sched_pipe *pipe;
264 struct rte_sched_queue *queue;
265 struct rte_sched_queue_extra *queue_extra;
266 struct rte_sched_pipe_profile *pipe_profiles;
268 struct rte_mbuf **queue_array;
269 uint8_t memory[0] __rte_cache_aligned;
270 } __rte_cache_aligned;
272 enum rte_sched_port_array {
273 e_RTE_SCHED_PORT_ARRAY_SUBPORT = 0,
274 e_RTE_SCHED_PORT_ARRAY_PIPE,
275 e_RTE_SCHED_PORT_ARRAY_QUEUE,
276 e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA,
277 e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES,
278 e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY,
279 e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY,
280 e_RTE_SCHED_PORT_ARRAY_TOTAL,
283 #ifdef RTE_SCHED_COLLECT_STATS
285 static inline uint32_t
286 rte_sched_port_queues_per_subport(struct rte_sched_port *port)
288 return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport;
293 static inline uint32_t
294 rte_sched_port_queues_per_port(struct rte_sched_port *port)
296 return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport * port->n_subports_per_port;
300 rte_sched_port_check_params(struct rte_sched_port_params *params)
304 if (params == NULL) {
309 if ((params->socket < 0) || (params->socket >= RTE_MAX_NUMA_NODES)) {
314 if (params->rate == 0) {
319 if (params->mtu == 0) {
323 /* n_subports_per_port: non-zero, power of 2 */
324 if ((params->n_subports_per_port == 0) || (!rte_is_power_of_2(params->n_subports_per_port))) {
328 /* n_pipes_per_subport: non-zero, power of 2 */
329 if ((params->n_pipes_per_subport == 0) || (!rte_is_power_of_2(params->n_pipes_per_subport))) {
333 /* qsize: non-zero, power of 2,
334 * no bigger than 32K (due to 16-bit read/write pointers) */
335 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
336 uint16_t qsize = params->qsize[i];
338 if ((qsize == 0) || (!rte_is_power_of_2(qsize))) {
343 /* pipe_profiles and n_pipe_profiles */
344 if ((params->pipe_profiles == NULL) ||
345 (params->n_pipe_profiles == 0) ||
346 (params->n_pipe_profiles > RTE_SCHED_PIPE_PROFILES_PER_PORT)) {
350 for (i = 0; i < params->n_pipe_profiles; i ++) {
351 struct rte_sched_pipe_params *p = params->pipe_profiles + i;
353 /* TB rate: non-zero, not greater than port rate */
354 if ((p->tb_rate == 0) || (p->tb_rate > params->rate)) {
358 /* TB size: non-zero */
359 if (p->tb_size == 0) {
363 /* TC rate: non-zero, less than pipe rate */
364 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
365 if ((p->tc_rate[j] == 0) || (p->tc_rate[j] > p->tb_rate)) {
370 /* TC period: non-zero */
371 if (p->tc_period == 0) {
375 #ifdef RTE_SCHED_SUBPORT_TC_OV
376 /* TC3 oversubscription weight: non-zero */
377 if (p->tc_ov_weight == 0) {
382 /* Queue WRR weights: non-zero */
383 for (j = 0; j < RTE_SCHED_QUEUES_PER_PIPE; j ++) {
384 if (p->wrr_weights[j] == 0) {
394 rte_sched_port_get_array_base(struct rte_sched_port_params *params, enum rte_sched_port_array array)
396 uint32_t n_subports_per_port = params->n_subports_per_port;
397 uint32_t n_pipes_per_subport = params->n_pipes_per_subport;
398 uint32_t n_pipes_per_port = n_pipes_per_subport * n_subports_per_port;
399 uint32_t n_queues_per_port = RTE_SCHED_QUEUES_PER_PIPE * n_pipes_per_subport * n_subports_per_port;
401 uint32_t size_subport = n_subports_per_port * sizeof(struct rte_sched_subport);
402 uint32_t size_pipe = n_pipes_per_port * sizeof(struct rte_sched_pipe);
403 uint32_t size_queue = n_queues_per_port * sizeof(struct rte_sched_queue);
404 uint32_t size_queue_extra = n_queues_per_port * sizeof(struct rte_sched_queue_extra);
405 uint32_t size_pipe_profiles = RTE_SCHED_PIPE_PROFILES_PER_PORT * sizeof(struct rte_sched_pipe_profile);
406 uint32_t size_bmp_array = rte_bitmap_get_memory_footprint(n_queues_per_port);
407 uint32_t size_per_pipe_queue_array, size_queue_array;
411 size_per_pipe_queue_array = 0;
412 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
413 size_per_pipe_queue_array += RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS * params->qsize[i] * sizeof(struct rte_mbuf *);
415 size_queue_array = n_pipes_per_port * size_per_pipe_queue_array;
419 if (array == e_RTE_SCHED_PORT_ARRAY_SUBPORT) return base;
420 base += RTE_CACHE_LINE_ROUNDUP(size_subport);
422 if (array == e_RTE_SCHED_PORT_ARRAY_PIPE) return base;
423 base += RTE_CACHE_LINE_ROUNDUP(size_pipe);
425 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE) return base;
426 base += RTE_CACHE_LINE_ROUNDUP(size_queue);
428 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA) return base;
429 base += RTE_CACHE_LINE_ROUNDUP(size_queue_extra);
431 if (array == e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES) return base;
432 base += RTE_CACHE_LINE_ROUNDUP(size_pipe_profiles);
434 if (array == e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY) return base;
435 base += RTE_CACHE_LINE_ROUNDUP(size_bmp_array);
437 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY) return base;
438 base += RTE_CACHE_LINE_ROUNDUP(size_queue_array);
444 rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)
446 uint32_t size0, size1;
449 status = rte_sched_port_check_params(params);
451 RTE_LOG(NOTICE, SCHED,
452 "Port scheduler params check failed (%d)\n", status);
457 size0 = sizeof(struct rte_sched_port);
458 size1 = rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_TOTAL);
460 return (size0 + size1);
464 rte_sched_port_config_qsize(struct rte_sched_port *port)
467 port->qsize_add[0] = 0;
468 port->qsize_add[1] = port->qsize_add[0] + port->qsize[0];
469 port->qsize_add[2] = port->qsize_add[1] + port->qsize[0];
470 port->qsize_add[3] = port->qsize_add[2] + port->qsize[0];
473 port->qsize_add[4] = port->qsize_add[3] + port->qsize[0];
474 port->qsize_add[5] = port->qsize_add[4] + port->qsize[1];
475 port->qsize_add[6] = port->qsize_add[5] + port->qsize[1];
476 port->qsize_add[7] = port->qsize_add[6] + port->qsize[1];
479 port->qsize_add[8] = port->qsize_add[7] + port->qsize[1];
480 port->qsize_add[9] = port->qsize_add[8] + port->qsize[2];
481 port->qsize_add[10] = port->qsize_add[9] + port->qsize[2];
482 port->qsize_add[11] = port->qsize_add[10] + port->qsize[2];
485 port->qsize_add[12] = port->qsize_add[11] + port->qsize[2];
486 port->qsize_add[13] = port->qsize_add[12] + port->qsize[3];
487 port->qsize_add[14] = port->qsize_add[13] + port->qsize[3];
488 port->qsize_add[15] = port->qsize_add[14] + port->qsize[3];
490 port->qsize_sum = port->qsize_add[15] + port->qsize[3];
494 rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)
496 struct rte_sched_pipe_profile *p = port->pipe_profiles + i;
498 RTE_LOG(DEBUG, SCHED, "Low level config for pipe profile %u:\n"
499 " Token bucket: period = %u, credits per period = %u, size = %u\n"
500 " Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\n"
501 " Traffic class 3 oversubscription: weight = %hhu\n"
502 " WRR cost: [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu]\n",
507 p->tb_credits_per_period,
510 /* Traffic classes */
512 p->tc_credits_per_period[0],
513 p->tc_credits_per_period[1],
514 p->tc_credits_per_period[2],
515 p->tc_credits_per_period[3],
517 /* Traffic class 3 oversubscription */
521 p->wrr_cost[ 0], p->wrr_cost[ 1], p->wrr_cost[ 2], p->wrr_cost[ 3],
522 p->wrr_cost[ 4], p->wrr_cost[ 5], p->wrr_cost[ 6], p->wrr_cost[ 7],
523 p->wrr_cost[ 8], p->wrr_cost[ 9], p->wrr_cost[10], p->wrr_cost[11],
524 p->wrr_cost[12], p->wrr_cost[13], p->wrr_cost[14], p->wrr_cost[15]);
527 static inline uint64_t
528 rte_sched_time_ms_to_bytes(uint32_t time_ms, uint32_t rate)
530 uint64_t time = time_ms;
531 time = (time * rate) / 1000;
537 rte_sched_port_config_pipe_profile_table(struct rte_sched_port *port, struct rte_sched_port_params *params)
541 for (i = 0; i < port->n_pipe_profiles; i ++) {
542 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
543 struct rte_sched_pipe_profile *dst = port->pipe_profiles + i;
546 if (src->tb_rate == params->rate) {
547 dst->tb_credits_per_period = 1;
550 double tb_rate = ((double) src->tb_rate) / ((double) params->rate);
551 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
553 rte_approx(tb_rate, d, &dst->tb_credits_per_period, &dst->tb_period);
555 dst->tb_size = src->tb_size;
557 /* Traffic Classes */
558 dst->tc_period = (uint32_t) rte_sched_time_ms_to_bytes(src->tc_period, params->rate);
559 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
560 dst->tc_credits_per_period[j] = (uint32_t) rte_sched_time_ms_to_bytes(src->tc_period, src->tc_rate[j]);
562 #ifdef RTE_SCHED_SUBPORT_TC_OV
563 dst->tc_ov_weight = src->tc_ov_weight;
567 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
568 uint32_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
569 uint32_t lcd, lcd1, lcd2;
572 qindex = j * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS;
574 wrr_cost[0] = src->wrr_weights[qindex];
575 wrr_cost[1] = src->wrr_weights[qindex + 1];
576 wrr_cost[2] = src->wrr_weights[qindex + 2];
577 wrr_cost[3] = src->wrr_weights[qindex + 3];
579 lcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);
580 lcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);
581 lcd = rte_get_lcd(lcd1, lcd2);
583 wrr_cost[0] = lcd / wrr_cost[0];
584 wrr_cost[1] = lcd / wrr_cost[1];
585 wrr_cost[2] = lcd / wrr_cost[2];
586 wrr_cost[3] = lcd / wrr_cost[3];
588 dst->wrr_cost[qindex] = (uint8_t) wrr_cost[0];
589 dst->wrr_cost[qindex + 1] = (uint8_t) wrr_cost[1];
590 dst->wrr_cost[qindex + 2] = (uint8_t) wrr_cost[2];
591 dst->wrr_cost[qindex + 3] = (uint8_t) wrr_cost[3];
594 rte_sched_port_log_pipe_profile(port, i);
597 port->pipe_tc3_rate_max = 0;
598 for (i = 0; i < port->n_pipe_profiles; i ++) {
599 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
600 uint32_t pipe_tc3_rate = src->tc_rate[3];
602 if (port->pipe_tc3_rate_max < pipe_tc3_rate) {
603 port->pipe_tc3_rate_max = pipe_tc3_rate;
608 struct rte_sched_port *
609 rte_sched_port_config(struct rte_sched_port_params *params)
611 struct rte_sched_port *port = NULL;
612 uint32_t mem_size, bmp_mem_size, n_queues_per_port, i;
614 /* Check user parameters. Determine the amount of memory to allocate */
615 mem_size = rte_sched_port_get_memory_footprint(params);
620 /* Allocate memory to store the data structures */
621 port = rte_zmalloc("qos_params", mem_size, RTE_CACHE_LINE_SIZE);
626 /* User parameters */
627 port->n_subports_per_port = params->n_subports_per_port;
628 port->n_pipes_per_subport = params->n_pipes_per_subport;
629 port->rate = params->rate;
630 port->mtu = params->mtu + params->frame_overhead;
631 port->frame_overhead = params->frame_overhead;
632 memcpy(port->qsize, params->qsize, sizeof(params->qsize));
633 port->n_pipe_profiles = params->n_pipe_profiles;
636 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
639 for (j = 0; j < e_RTE_METER_COLORS; j++) {
640 /* if min/max are both zero, then RED is disabled */
641 if ((params->red_params[i][j].min_th |
642 params->red_params[i][j].max_th) == 0) {
646 if (rte_red_config_init(&port->red_config[i][j],
647 params->red_params[i][j].wq_log2,
648 params->red_params[i][j].min_th,
649 params->red_params[i][j].max_th,
650 params->red_params[i][j].maxp_inv) != 0) {
658 port->time_cpu_cycles = rte_get_tsc_cycles();
659 port->time_cpu_bytes = 0;
661 port->cycles_per_byte = ((double) rte_get_tsc_hz()) / ((double) params->rate);
663 /* Scheduling loop detection */
664 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
665 port->pipe_exhaustion = 0;
668 port->busy_grinders = 0;
669 port->pkts_out = NULL;
670 port->n_pkts_out = 0;
672 /* Queue base calculation */
673 rte_sched_port_config_qsize(port);
675 /* Large data structures */
676 port->subport = (struct rte_sched_subport *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_SUBPORT));
677 port->pipe = (struct rte_sched_pipe *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_PIPE));
678 port->queue = (struct rte_sched_queue *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE));
679 port->queue_extra = (struct rte_sched_queue_extra *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA));
680 port->pipe_profiles = (struct rte_sched_pipe_profile *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES));
681 port->bmp_array = port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY);
682 port->queue_array = (struct rte_mbuf **) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY));
684 /* Pipe profile table */
685 rte_sched_port_config_pipe_profile_table(port, params);
688 n_queues_per_port = rte_sched_port_queues_per_port(port);
689 bmp_mem_size = rte_bitmap_get_memory_footprint(n_queues_per_port);
690 port->bmp = rte_bitmap_init(n_queues_per_port, port->bmp_array, bmp_mem_size);
691 if (port->bmp == NULL) {
692 RTE_LOG(ERR, SCHED, "Bitmap init error\n");
695 for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i ++) {
696 port->grinder_base_bmp_pos[i] = RTE_SCHED_PIPE_INVALID;
703 rte_sched_port_free(struct rte_sched_port *port)
705 /* Check user parameters */
710 rte_bitmap_free(port->bmp);
715 rte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)
717 struct rte_sched_subport *s = port->subport + i;
719 RTE_LOG(DEBUG, SCHED, "Low level config for subport %u:\n"
720 " Token bucket: period = %u, credits per period = %u, size = %u\n"
721 " Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\n"
722 " Traffic class 3 oversubscription: wm min = %u, wm max = %u\n",
727 s->tb_credits_per_period,
730 /* Traffic classes */
732 s->tc_credits_per_period[0],
733 s->tc_credits_per_period[1],
734 s->tc_credits_per_period[2],
735 s->tc_credits_per_period[3],
737 /* Traffic class 3 oversubscription */
743 rte_sched_subport_config(struct rte_sched_port *port,
745 struct rte_sched_subport_params *params)
747 struct rte_sched_subport *s;
750 /* Check user parameters */
751 if ((port == NULL) ||
752 (subport_id >= port->n_subports_per_port) ||
757 if ((params->tb_rate == 0) || (params->tb_rate > port->rate)) {
761 if (params->tb_size == 0) {
765 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
766 if ((params->tc_rate[i] == 0) || (params->tc_rate[i] > params->tb_rate)) {
771 if (params->tc_period == 0) {
775 s = port->subport + subport_id;
777 /* Token Bucket (TB) */
778 if (params->tb_rate == port->rate) {
779 s->tb_credits_per_period = 1;
782 double tb_rate = ((double) params->tb_rate) / ((double) port->rate);
783 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
785 rte_approx(tb_rate, d, &s->tb_credits_per_period, &s->tb_period);
787 s->tb_size = params->tb_size;
788 s->tb_time = port->time;
789 s->tb_credits = s->tb_size / 2;
791 /* Traffic Classes (TCs) */
792 s->tc_period = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, port->rate);
793 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
794 s->tc_credits_per_period[i] = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, params->tc_rate[i]);
796 s->tc_time = port->time + s->tc_period;
797 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
798 s->tc_credits[i] = s->tc_credits_per_period[i];
801 #ifdef RTE_SCHED_SUBPORT_TC_OV
802 /* TC oversubscription */
803 s->tc_ov_wm_min = port->mtu;
804 s->tc_ov_wm_max = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, port->pipe_tc3_rate_max);
805 s->tc_ov_wm = s->tc_ov_wm_max;
806 s->tc_ov_period_id = 0;
812 rte_sched_port_log_subport_config(port, subport_id);
818 rte_sched_pipe_config(struct rte_sched_port *port,
821 int32_t pipe_profile)
823 struct rte_sched_subport *s;
824 struct rte_sched_pipe *p;
825 struct rte_sched_pipe_profile *params;
826 uint32_t deactivate, profile, i;
828 /* Check user parameters */
829 profile = (uint32_t) pipe_profile;
830 deactivate = (pipe_profile < 0);
831 if ((port == NULL) ||
832 (subport_id >= port->n_subports_per_port) ||
833 (pipe_id >= port->n_pipes_per_subport) ||
834 ((!deactivate) && (profile >= port->n_pipe_profiles))) {
838 /* Check that subport configuration is valid */
839 s = port->subport + subport_id;
840 if (s->tb_period == 0) {
844 p = port->pipe + (subport_id * port->n_pipes_per_subport + pipe_id);
846 /* Handle the case when pipe already has a valid configuration */
848 params = port->pipe_profiles + p->profile;
850 #ifdef RTE_SCHED_SUBPORT_TC_OV
851 double subport_tc3_rate = ((double) s->tc_credits_per_period[3]) / ((double) s->tc_period);
852 double pipe_tc3_rate = ((double) params->tc_credits_per_period[3]) / ((double) params->tc_period);
853 uint32_t tc3_ov = s->tc_ov;
855 /* Unplug pipe from its subport */
856 s->tc_ov_n -= params->tc_ov_weight;
857 s->tc_ov_rate -= pipe_tc3_rate;
858 s->tc_ov = s->tc_ov_rate > subport_tc3_rate;
860 if (s->tc_ov != tc3_ov) {
861 RTE_LOG(DEBUG, SCHED,
862 "Subport %u TC3 oversubscription is OFF (%.4lf >= %.4lf)\n",
863 subport_id, subport_tc3_rate, s->tc_ov_rate);
868 memset(p, 0, sizeof(struct rte_sched_pipe));
875 /* Apply the new pipe configuration */
876 p->profile = profile;
877 params = port->pipe_profiles + p->profile;
879 /* Token Bucket (TB) */
880 p->tb_time = port->time;
881 p->tb_credits = params->tb_size / 2;
883 /* Traffic Classes (TCs) */
884 p->tc_time = port->time + params->tc_period;
885 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
886 p->tc_credits[i] = params->tc_credits_per_period[i];
889 #ifdef RTE_SCHED_SUBPORT_TC_OV
891 /* Subport TC3 oversubscription */
892 double subport_tc3_rate = ((double) s->tc_credits_per_period[3]) / ((double) s->tc_period);
893 double pipe_tc3_rate = ((double) params->tc_credits_per_period[3]) / ((double) params->tc_period);
894 uint32_t tc3_ov = s->tc_ov;
896 s->tc_ov_n += params->tc_ov_weight;
897 s->tc_ov_rate += pipe_tc3_rate;
898 s->tc_ov = s->tc_ov_rate > subport_tc3_rate;
900 if (s->tc_ov != tc3_ov) {
901 RTE_LOG(DEBUG, SCHED,
902 "Subport %u TC3 oversubscription is ON (%.4lf < %.4lf)\n",
903 subport_id, subport_tc3_rate, s->tc_ov_rate);
905 p->tc_ov_period_id = s->tc_ov_period_id;
906 p->tc_ov_credits = s->tc_ov_wm;
914 rte_sched_port_pkt_write(struct rte_mbuf *pkt,
915 uint32_t subport, uint32_t pipe, uint32_t traffic_class,
916 uint32_t queue, enum rte_meter_color color)
918 struct rte_sched_port_hierarchy *sched
919 = (struct rte_sched_port_hierarchy *) &pkt->hash.sched;
921 sched->color = (uint32_t) color;
922 sched->subport = subport;
924 sched->traffic_class = traffic_class;
925 sched->queue = queue;
929 rte_sched_port_pkt_read_tree_path(const struct rte_mbuf *pkt,
930 uint32_t *subport, uint32_t *pipe,
931 uint32_t *traffic_class, uint32_t *queue)
933 const struct rte_sched_port_hierarchy *sched
934 = (const struct rte_sched_port_hierarchy *) &pkt->hash.sched;
936 *subport = sched->subport;
938 *traffic_class = sched->traffic_class;
939 *queue = sched->queue;
944 rte_sched_port_pkt_read_color(const struct rte_mbuf *pkt)
946 const struct rte_sched_port_hierarchy *sched
947 = (const struct rte_sched_port_hierarchy *) &pkt->hash.sched;
949 return (enum rte_meter_color) sched->color;
953 rte_sched_subport_read_stats(struct rte_sched_port *port,
955 struct rte_sched_subport_stats *stats,
958 struct rte_sched_subport *s;
960 /* Check user parameters */
961 if ((port == NULL) ||
962 (subport_id >= port->n_subports_per_port) ||
967 s = port->subport + subport_id;
969 /* Copy subport stats and clear */
970 memcpy(stats, &s->stats, sizeof(struct rte_sched_subport_stats));
971 memset(&s->stats, 0, sizeof(struct rte_sched_subport_stats));
973 /* Subport TC ovesubscription status */
980 rte_sched_queue_read_stats(struct rte_sched_port *port,
982 struct rte_sched_queue_stats *stats,
985 struct rte_sched_queue *q;
986 struct rte_sched_queue_extra *qe;
988 /* Check user parameters */
989 if ((port == NULL) ||
990 (queue_id >= rte_sched_port_queues_per_port(port)) ||
995 q = port->queue + queue_id;
996 qe = port->queue_extra + queue_id;
998 /* Copy queue stats and clear */
999 memcpy(stats, &qe->stats, sizeof(struct rte_sched_queue_stats));
1000 memset(&qe->stats, 0, sizeof(struct rte_sched_queue_stats));
1003 *qlen = q->qw - q->qr;
1008 static inline uint32_t
1009 rte_sched_port_qindex(struct rte_sched_port *port, uint32_t subport, uint32_t pipe, uint32_t traffic_class, uint32_t queue)
1013 result = subport * port->n_pipes_per_subport + pipe;
1014 result = result * RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE + traffic_class;
1015 result = result * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + queue;
1020 static inline struct rte_mbuf **
1021 rte_sched_port_qbase(struct rte_sched_port *port, uint32_t qindex)
1023 uint32_t pindex = qindex >> 4;
1024 uint32_t qpos = qindex & 0xF;
1026 return (port->queue_array + pindex * port->qsize_sum + port->qsize_add[qpos]);
1029 static inline uint16_t
1030 rte_sched_port_qsize(struct rte_sched_port *port, uint32_t qindex)
1032 uint32_t tc = (qindex >> 2) & 0x3;
1034 return port->qsize[tc];
1037 #ifdef RTE_SCHED_DEBUG
1040 rte_sched_port_queue_is_empty(struct rte_sched_port *port, uint32_t qindex)
1042 struct rte_sched_queue *queue = port->queue + qindex;
1044 return (queue->qr == queue->qw);
1048 rte_sched_port_queue_is_full(struct rte_sched_port *port, uint32_t qindex)
1050 struct rte_sched_queue *queue = port->queue + qindex;
1051 uint16_t qsize = rte_sched_port_qsize(port, qindex);
1052 uint16_t qlen = queue->qw - queue->qr;
1054 return (qlen >= qsize);
1057 #endif /* RTE_SCHED_DEBUG */
1059 #ifdef RTE_SCHED_COLLECT_STATS
1062 rte_sched_port_update_subport_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1064 struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1065 uint32_t tc_index = (qindex >> 2) & 0x3;
1066 uint32_t pkt_len = pkt->pkt_len;
1068 s->stats.n_pkts_tc[tc_index] += 1;
1069 s->stats.n_bytes_tc[tc_index] += pkt_len;
1073 rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1075 struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1076 uint32_t tc_index = (qindex >> 2) & 0x3;
1077 uint32_t pkt_len = pkt->pkt_len;
1079 s->stats.n_pkts_tc_dropped[tc_index] += 1;
1080 s->stats.n_bytes_tc_dropped[tc_index] += pkt_len;
1084 rte_sched_port_update_queue_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1086 struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1087 uint32_t pkt_len = pkt->pkt_len;
1089 qe->stats.n_pkts += 1;
1090 qe->stats.n_bytes += pkt_len;
1094 rte_sched_port_update_queue_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1096 struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1097 uint32_t pkt_len = pkt->pkt_len;
1099 qe->stats.n_pkts_dropped += 1;
1100 qe->stats.n_bytes_dropped += pkt_len;
1103 #endif /* RTE_SCHED_COLLECT_STATS */
1105 #ifdef RTE_SCHED_RED
1108 rte_sched_port_red_drop(struct rte_sched_port *port, struct rte_mbuf *pkt, uint32_t qindex, uint16_t qlen)
1110 struct rte_sched_queue_extra *qe;
1111 struct rte_red_config *red_cfg;
1112 struct rte_red *red;
1114 enum rte_meter_color color;
1116 tc_index = (qindex >> 2) & 0x3;
1117 color = rte_sched_port_pkt_read_color(pkt);
1118 red_cfg = &port->red_config[tc_index][color];
1120 if ((red_cfg->min_th | red_cfg->max_th) == 0)
1123 qe = port->queue_extra + qindex;
1126 return rte_red_enqueue(red_cfg, red, qlen, port->time);
1130 rte_sched_port_set_queue_empty_timestamp(struct rte_sched_port *port, uint32_t qindex)
1132 struct rte_sched_queue_extra *qe;
1133 struct rte_red *red;
1135 qe = port->queue_extra + qindex;
1138 rte_red_mark_queue_empty(red, port->time);
1143 #define rte_sched_port_red_drop(port, pkt, qindex, qlen) 0
1145 #define rte_sched_port_set_queue_empty_timestamp(port, qindex)
1147 #endif /* RTE_SCHED_RED */
1149 #ifdef RTE_SCHED_DEBUG
1152 debug_pipe_is_empty(struct rte_sched_port *port, uint32_t pindex)
1156 qindex = pindex << 4;
1158 for (i = 0; i < 16; i ++){
1159 uint32_t queue_empty = rte_sched_port_queue_is_empty(port, qindex + i);
1160 uint32_t bmp_bit_clear = (rte_bitmap_get(port->bmp, qindex + i) == 0);
1162 if (queue_empty != bmp_bit_clear){
1163 rte_panic("Queue status mismatch for queue %u of pipe %u\n", i, pindex);
1175 debug_check_queue_slab(struct rte_sched_port *port, uint32_t bmp_pos, uint64_t bmp_slab)
1181 rte_panic("Empty slab at position %u\n", bmp_pos);
1185 for (i = 0, mask = 1; i < 64; i ++, mask <<= 1) {
1186 if (mask & bmp_slab){
1187 if (rte_sched_port_queue_is_empty(port, bmp_pos + i)) {
1188 printf("Queue %u (slab offset %u) is empty\n", bmp_pos + i, i);
1195 rte_panic("Empty queues in slab 0x%" PRIx64 "starting at position %u\n",
1200 #endif /* RTE_SCHED_DEBUG */
1202 static inline uint32_t
1203 rte_sched_port_enqueue_qptrs_prefetch0(struct rte_sched_port *port, struct rte_mbuf *pkt)
1205 struct rte_sched_queue *q;
1206 #ifdef RTE_SCHED_COLLECT_STATS
1207 struct rte_sched_queue_extra *qe;
1209 uint32_t subport, pipe, traffic_class, queue, qindex;
1211 rte_sched_port_pkt_read_tree_path(pkt, &subport, &pipe, &traffic_class, &queue);
1213 qindex = rte_sched_port_qindex(port, subport, pipe, traffic_class, queue);
1214 q = port->queue + qindex;
1216 #ifdef RTE_SCHED_COLLECT_STATS
1217 qe = port->queue_extra + qindex;
1225 rte_sched_port_enqueue_qwa_prefetch0(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf **qbase)
1227 struct rte_sched_queue *q;
1228 struct rte_mbuf **q_qw;
1231 q = port->queue + qindex;
1232 qsize = rte_sched_port_qsize(port, qindex);
1233 q_qw = qbase + (q->qw & (qsize - 1));
1235 rte_prefetch0(q_qw);
1236 rte_bitmap_prefetch0(port->bmp, qindex);
1240 rte_sched_port_enqueue_qwa(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf **qbase, struct rte_mbuf *pkt)
1242 struct rte_sched_queue *q;
1246 q = port->queue + qindex;
1247 qsize = rte_sched_port_qsize(port, qindex);
1248 qlen = q->qw - q->qr;
1250 /* Drop the packet (and update drop stats) when queue is full */
1251 if (unlikely(rte_sched_port_red_drop(port, pkt, qindex, qlen) || (qlen >= qsize))) {
1252 rte_pktmbuf_free(pkt);
1253 #ifdef RTE_SCHED_COLLECT_STATS
1254 rte_sched_port_update_subport_stats_on_drop(port, qindex, pkt);
1255 rte_sched_port_update_queue_stats_on_drop(port, qindex, pkt);
1260 /* Enqueue packet */
1261 qbase[q->qw & (qsize - 1)] = pkt;
1264 /* Activate queue in the port bitmap */
1265 rte_bitmap_set(port->bmp, qindex);
1268 #ifdef RTE_SCHED_COLLECT_STATS
1269 rte_sched_port_update_subport_stats(port, qindex, pkt);
1270 rte_sched_port_update_queue_stats(port, qindex, pkt);
1278 * The enqueue function implements a 4-level pipeline with each stage processing
1279 * two different packets. The purpose of using a pipeline is to hide the latency
1280 * of prefetching the data structures. The naming convention is presented in the
1283 * p00 _______ p10 _______ p20 _______ p30 _______
1284 * ----->| |----->| |----->| |----->| |----->
1285 * | 0 | | 1 | | 2 | | 3 |
1286 * ----->|_______|----->|_______|----->|_______|----->|_______|----->
1291 rte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
1293 struct rte_mbuf *pkt00, *pkt01, *pkt10, *pkt11, *pkt20, *pkt21, *pkt30, *pkt31, *pkt_last;
1294 struct rte_mbuf **q00_base, **q01_base, **q10_base, **q11_base, **q20_base, **q21_base, **q30_base, **q31_base, **q_last_base;
1295 uint32_t q00, q01, q10, q11, q20, q21, q30, q31, q_last;
1296 uint32_t r00, r01, r10, r11, r20, r21, r30, r31, r_last;
1301 /* Less then 6 input packets available, which is not enough to feed the pipeline */
1302 if (unlikely(n_pkts < 6)) {
1303 struct rte_mbuf **q_base[5];
1306 /* Prefetch the mbuf structure of each packet */
1307 for (i = 0; i < n_pkts; i ++) {
1308 rte_prefetch0(pkts[i]);
1311 /* Prefetch the queue structure for each queue */
1312 for (i = 0; i < n_pkts; i ++) {
1313 q[i] = rte_sched_port_enqueue_qptrs_prefetch0(port, pkts[i]);
1316 /* Prefetch the write pointer location of each queue */
1317 for (i = 0; i < n_pkts; i ++) {
1318 q_base[i] = rte_sched_port_qbase(port, q[i]);
1319 rte_sched_port_enqueue_qwa_prefetch0(port, q[i], q_base[i]);
1322 /* Write each packet to its queue */
1323 for (i = 0; i < n_pkts; i ++) {
1324 result += rte_sched_port_enqueue_qwa(port, q[i], q_base[i], pkts[i]);
1330 /* Feed the first 3 stages of the pipeline (6 packets needed) */
1333 rte_prefetch0(pkt20);
1334 rte_prefetch0(pkt21);
1338 rte_prefetch0(pkt10);
1339 rte_prefetch0(pkt11);
1341 q20 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt20);
1342 q21 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt21);
1346 rte_prefetch0(pkt00);
1347 rte_prefetch0(pkt01);
1349 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1350 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1352 q20_base = rte_sched_port_qbase(port, q20);
1353 q21_base = rte_sched_port_qbase(port, q21);
1354 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1355 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1357 /* Run the pipeline */
1358 for (i = 6; i < (n_pkts & (~1)); i += 2) {
1359 /* Propagate stage inputs */
1370 q30_base = q20_base;
1371 q31_base = q21_base;
1373 /* Stage 0: Get packets in */
1375 pkt01 = pkts[i + 1];
1376 rte_prefetch0(pkt00);
1377 rte_prefetch0(pkt01);
1379 /* Stage 1: Prefetch queue structure storing queue pointers */
1380 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1381 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1383 /* Stage 2: Prefetch queue write location */
1384 q20_base = rte_sched_port_qbase(port, q20);
1385 q21_base = rte_sched_port_qbase(port, q21);
1386 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1387 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1389 /* Stage 3: Write packet to queue and activate queue */
1390 r30 = rte_sched_port_enqueue_qwa(port, q30, q30_base, pkt30);
1391 r31 = rte_sched_port_enqueue_qwa(port, q31, q31_base, pkt31);
1392 result += r30 + r31;
1395 /* Drain the pipeline (exactly 6 packets). Handle the last packet in the case
1396 of an odd number of input packets. */
1397 pkt_last = pkts[n_pkts - 1];
1398 rte_prefetch0(pkt_last);
1400 q00 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt00);
1401 q01 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt01);
1403 q10_base = rte_sched_port_qbase(port, q10);
1404 q11_base = rte_sched_port_qbase(port, q11);
1405 rte_sched_port_enqueue_qwa_prefetch0(port, q10, q10_base);
1406 rte_sched_port_enqueue_qwa_prefetch0(port, q11, q11_base);
1408 r20 = rte_sched_port_enqueue_qwa(port, q20, q20_base, pkt20);
1409 r21 = rte_sched_port_enqueue_qwa(port, q21, q21_base, pkt21);
1410 result += r20 + r21;
1412 q_last = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt_last);
1414 q00_base = rte_sched_port_qbase(port, q00);
1415 q01_base = rte_sched_port_qbase(port, q01);
1416 rte_sched_port_enqueue_qwa_prefetch0(port, q00, q00_base);
1417 rte_sched_port_enqueue_qwa_prefetch0(port, q01, q01_base);
1419 r10 = rte_sched_port_enqueue_qwa(port, q10, q10_base, pkt10);
1420 r11 = rte_sched_port_enqueue_qwa(port, q11, q11_base, pkt11);
1421 result += r10 + r11;
1423 q_last_base = rte_sched_port_qbase(port, q_last);
1424 rte_sched_port_enqueue_qwa_prefetch0(port, q_last, q_last_base);
1426 r00 = rte_sched_port_enqueue_qwa(port, q00, q00_base, pkt00);
1427 r01 = rte_sched_port_enqueue_qwa(port, q01, q01_base, pkt01);
1428 result += r00 + r01;
1431 r_last = rte_sched_port_enqueue_qwa(port, q_last, q_last_base, pkt_last);
1438 #ifndef RTE_SCHED_SUBPORT_TC_OV
1441 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1443 struct rte_sched_grinder *grinder = port->grinder + pos;
1444 struct rte_sched_subport *subport = grinder->subport;
1445 struct rte_sched_pipe *pipe = grinder->pipe;
1446 struct rte_sched_pipe_profile *params = grinder->pipe_params;
1450 n_periods = (port->time - subport->tb_time) / subport->tb_period;
1451 subport->tb_credits += n_periods * subport->tb_credits_per_period;
1452 subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1453 subport->tb_time += n_periods * subport->tb_period;
1456 n_periods = (port->time - pipe->tb_time) / params->tb_period;
1457 pipe->tb_credits += n_periods * params->tb_credits_per_period;
1458 pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1459 pipe->tb_time += n_periods * params->tb_period;
1462 if (unlikely(port->time >= subport->tc_time)) {
1463 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1464 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1465 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1466 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1467 subport->tc_time = port->time + subport->tc_period;
1471 if (unlikely(port->time >= pipe->tc_time)) {
1472 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1473 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1474 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1475 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1476 pipe->tc_time = port->time + params->tc_period;
1482 static inline uint32_t
1483 grinder_tc_ov_credits_update(struct rte_sched_port *port, uint32_t pos)
1485 struct rte_sched_grinder *grinder = port->grinder + pos;
1486 struct rte_sched_subport *subport = grinder->subport;
1487 uint32_t tc_ov_consumption[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
1488 uint32_t tc_ov_consumption_max;
1489 uint32_t tc_ov_wm = subport->tc_ov_wm;
1491 if (subport->tc_ov == 0) {
1492 return subport->tc_ov_wm_max;
1495 tc_ov_consumption[0] = subport->tc_credits_per_period[0] - subport->tc_credits[0];
1496 tc_ov_consumption[1] = subport->tc_credits_per_period[1] - subport->tc_credits[1];
1497 tc_ov_consumption[2] = subport->tc_credits_per_period[2] - subport->tc_credits[2];
1498 tc_ov_consumption[3] = subport->tc_credits_per_period[3] - subport->tc_credits[3];
1500 tc_ov_consumption_max = subport->tc_credits_per_period[3] -
1501 (tc_ov_consumption[0] + tc_ov_consumption[1] + tc_ov_consumption[2]);
1503 if (tc_ov_consumption[3] > (tc_ov_consumption_max - port->mtu)) {
1504 tc_ov_wm -= tc_ov_wm >> 7;
1505 if (tc_ov_wm < subport->tc_ov_wm_min) {
1506 tc_ov_wm = subport->tc_ov_wm_min;
1511 tc_ov_wm += (tc_ov_wm >> 7) + 1;
1512 if (tc_ov_wm > subport->tc_ov_wm_max) {
1513 tc_ov_wm = subport->tc_ov_wm_max;
1519 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1521 struct rte_sched_grinder *grinder = port->grinder + pos;
1522 struct rte_sched_subport *subport = grinder->subport;
1523 struct rte_sched_pipe *pipe = grinder->pipe;
1524 struct rte_sched_pipe_profile *params = grinder->pipe_params;
1528 n_periods = (port->time - subport->tb_time) / subport->tb_period;
1529 subport->tb_credits += n_periods * subport->tb_credits_per_period;
1530 subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1531 subport->tb_time += n_periods * subport->tb_period;
1534 n_periods = (port->time - pipe->tb_time) / params->tb_period;
1535 pipe->tb_credits += n_periods * params->tb_credits_per_period;
1536 pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1537 pipe->tb_time += n_periods * params->tb_period;
1540 if (unlikely(port->time >= subport->tc_time)) {
1541 subport->tc_ov_wm = grinder_tc_ov_credits_update(port, pos);
1543 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1544 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1545 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1546 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1548 subport->tc_time = port->time + subport->tc_period;
1549 subport->tc_ov_period_id ++;
1553 if (unlikely(port->time >= pipe->tc_time)) {
1554 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1555 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1556 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1557 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1558 pipe->tc_time = port->time + params->tc_period;
1561 /* Pipe TCs - Oversubscription */
1562 if (unlikely(pipe->tc_ov_period_id != subport->tc_ov_period_id)) {
1563 pipe->tc_ov_credits = subport->tc_ov_wm * params->tc_ov_weight;
1565 pipe->tc_ov_period_id = subport->tc_ov_period_id;
1569 #endif /* RTE_SCHED_TS_CREDITS_UPDATE, RTE_SCHED_SUBPORT_TC_OV */
1572 #ifndef RTE_SCHED_SUBPORT_TC_OV
1575 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1577 struct rte_sched_grinder *grinder = port->grinder + pos;
1578 struct rte_sched_subport *subport = grinder->subport;
1579 struct rte_sched_pipe *pipe = grinder->pipe;
1580 struct rte_mbuf *pkt = grinder->pkt;
1581 uint32_t tc_index = grinder->tc_index;
1582 uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1583 uint32_t subport_tb_credits = subport->tb_credits;
1584 uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1585 uint32_t pipe_tb_credits = pipe->tb_credits;
1586 uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1589 /* Check queue credits */
1590 enough_credits = (pkt_len <= subport_tb_credits) &&
1591 (pkt_len <= subport_tc_credits) &&
1592 (pkt_len <= pipe_tb_credits) &&
1593 (pkt_len <= pipe_tc_credits);
1595 if (!enough_credits) {
1599 /* Update port credits */
1600 subport->tb_credits -= pkt_len;
1601 subport->tc_credits[tc_index] -= pkt_len;
1602 pipe->tb_credits -= pkt_len;
1603 pipe->tc_credits[tc_index] -= pkt_len;
1611 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1613 struct rte_sched_grinder *grinder = port->grinder + pos;
1614 struct rte_sched_subport *subport = grinder->subport;
1615 struct rte_sched_pipe *pipe = grinder->pipe;
1616 struct rte_mbuf *pkt = grinder->pkt;
1617 uint32_t tc_index = grinder->tc_index;
1618 uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1619 uint32_t subport_tb_credits = subport->tb_credits;
1620 uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1621 uint32_t pipe_tb_credits = pipe->tb_credits;
1622 uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1623 uint32_t pipe_tc_ov_mask1[] = {UINT32_MAX, UINT32_MAX, UINT32_MAX, pipe->tc_ov_credits};
1624 uint32_t pipe_tc_ov_mask2[] = {0, 0, 0, UINT32_MAX};
1625 uint32_t pipe_tc_ov_credits = pipe_tc_ov_mask1[tc_index];
1628 /* Check pipe and subport credits */
1629 enough_credits = (pkt_len <= subport_tb_credits) &&
1630 (pkt_len <= subport_tc_credits) &&
1631 (pkt_len <= pipe_tb_credits) &&
1632 (pkt_len <= pipe_tc_credits) &&
1633 (pkt_len <= pipe_tc_ov_credits);
1635 if (!enough_credits) {
1639 /* Update pipe and subport credits */
1640 subport->tb_credits -= pkt_len;
1641 subport->tc_credits[tc_index] -= pkt_len;
1642 pipe->tb_credits -= pkt_len;
1643 pipe->tc_credits[tc_index] -= pkt_len;
1644 pipe->tc_ov_credits -= pipe_tc_ov_mask2[tc_index] & pkt_len;
1649 #endif /* RTE_SCHED_SUBPORT_TC_OV */
1653 grinder_schedule(struct rte_sched_port *port, uint32_t pos)
1655 struct rte_sched_grinder *grinder = port->grinder + pos;
1656 struct rte_sched_queue *queue = grinder->queue[grinder->qpos];
1657 struct rte_mbuf *pkt = grinder->pkt;
1658 uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1660 if (!grinder_credits_check(port, pos)) {
1664 /* Advance port time */
1665 port->time += pkt_len;
1668 port->pkts_out[port->n_pkts_out ++] = pkt;
1670 grinder->wrr_tokens[grinder->qpos] += pkt_len * grinder->wrr_cost[grinder->qpos];
1671 if (queue->qr == queue->qw) {
1672 uint32_t qindex = grinder->qindex[grinder->qpos];
1674 rte_bitmap_clear(port->bmp, qindex);
1675 grinder->qmask &= ~(1 << grinder->qpos);
1676 grinder->wrr_mask[grinder->qpos] = 0;
1677 rte_sched_port_set_queue_empty_timestamp(port, qindex);
1680 /* Reset pipe loop detection */
1681 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1682 grinder->productive = 1;
1687 #if RTE_SCHED_OPTIMIZATIONS
1690 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1692 __m128i index = _mm_set1_epi32 (base_pipe);
1693 __m128i pipes = _mm_load_si128((__m128i *)port->grinder_base_bmp_pos);
1694 __m128i res = _mm_cmpeq_epi32(pipes, index);
1695 pipes = _mm_load_si128((__m128i *)(port->grinder_base_bmp_pos + 4));
1696 pipes = _mm_cmpeq_epi32(pipes, index);
1697 res = _mm_or_si128(res, pipes);
1699 if (_mm_testz_si128(res, res))
1708 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1712 for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i ++) {
1713 if (port->grinder_base_bmp_pos[i] == base_pipe) {
1721 #endif /* RTE_SCHED_OPTIMIZATIONS */
1724 grinder_pcache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t bmp_pos, uint64_t bmp_slab)
1726 struct rte_sched_grinder *grinder = port->grinder + pos;
1729 grinder->pcache_w = 0;
1730 grinder->pcache_r = 0;
1732 w[0] = (uint16_t) bmp_slab;
1733 w[1] = (uint16_t) (bmp_slab >> 16);
1734 w[2] = (uint16_t) (bmp_slab >> 32);
1735 w[3] = (uint16_t) (bmp_slab >> 48);
1737 grinder->pcache_qmask[grinder->pcache_w] = w[0];
1738 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos;
1739 grinder->pcache_w += (w[0] != 0);
1741 grinder->pcache_qmask[grinder->pcache_w] = w[1];
1742 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 16;
1743 grinder->pcache_w += (w[1] != 0);
1745 grinder->pcache_qmask[grinder->pcache_w] = w[2];
1746 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 32;
1747 grinder->pcache_w += (w[2] != 0);
1749 grinder->pcache_qmask[grinder->pcache_w] = w[3];
1750 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 48;
1751 grinder->pcache_w += (w[3] != 0);
1755 grinder_tccache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t qindex, uint16_t qmask)
1757 struct rte_sched_grinder *grinder = port->grinder + pos;
1760 grinder->tccache_w = 0;
1761 grinder->tccache_r = 0;
1763 b[0] = (uint8_t) (qmask & 0xF);
1764 b[1] = (uint8_t) ((qmask >> 4) & 0xF);
1765 b[2] = (uint8_t) ((qmask >> 8) & 0xF);
1766 b[3] = (uint8_t) ((qmask >> 12) & 0xF);
1768 grinder->tccache_qmask[grinder->tccache_w] = b[0];
1769 grinder->tccache_qindex[grinder->tccache_w] = qindex;
1770 grinder->tccache_w += (b[0] != 0);
1772 grinder->tccache_qmask[grinder->tccache_w] = b[1];
1773 grinder->tccache_qindex[grinder->tccache_w] = qindex + 4;
1774 grinder->tccache_w += (b[1] != 0);
1776 grinder->tccache_qmask[grinder->tccache_w] = b[2];
1777 grinder->tccache_qindex[grinder->tccache_w] = qindex + 8;
1778 grinder->tccache_w += (b[2] != 0);
1780 grinder->tccache_qmask[grinder->tccache_w] = b[3];
1781 grinder->tccache_qindex[grinder->tccache_w] = qindex + 12;
1782 grinder->tccache_w += (b[3] != 0);
1786 grinder_next_tc(struct rte_sched_port *port, uint32_t pos)
1788 struct rte_sched_grinder *grinder = port->grinder + pos;
1789 struct rte_mbuf **qbase;
1793 if (grinder->tccache_r == grinder->tccache_w) {
1797 qindex = grinder->tccache_qindex[grinder->tccache_r];
1798 qbase = rte_sched_port_qbase(port, qindex);
1799 qsize = rte_sched_port_qsize(port, qindex);
1801 grinder->tc_index = (qindex >> 2) & 0x3;
1802 grinder->qmask = grinder->tccache_qmask[grinder->tccache_r];
1803 grinder->qsize = qsize;
1805 grinder->qindex[0] = qindex;
1806 grinder->qindex[1] = qindex + 1;
1807 grinder->qindex[2] = qindex + 2;
1808 grinder->qindex[3] = qindex + 3;
1810 grinder->queue[0] = port->queue + qindex;
1811 grinder->queue[1] = port->queue + qindex + 1;
1812 grinder->queue[2] = port->queue + qindex + 2;
1813 grinder->queue[3] = port->queue + qindex + 3;
1815 grinder->qbase[0] = qbase;
1816 grinder->qbase[1] = qbase + qsize;
1817 grinder->qbase[2] = qbase + 2 * qsize;
1818 grinder->qbase[3] = qbase + 3 * qsize;
1820 grinder->tccache_r ++;
1825 grinder_next_pipe(struct rte_sched_port *port, uint32_t pos)
1827 struct rte_sched_grinder *grinder = port->grinder + pos;
1828 uint32_t pipe_qindex;
1829 uint16_t pipe_qmask;
1831 if (grinder->pcache_r < grinder->pcache_w) {
1832 pipe_qmask = grinder->pcache_qmask[grinder->pcache_r];
1833 pipe_qindex = grinder->pcache_qindex[grinder->pcache_r];
1834 grinder->pcache_r ++;
1836 uint64_t bmp_slab = 0;
1837 uint32_t bmp_pos = 0;
1839 /* Get another non-empty pipe group */
1840 if (unlikely(rte_bitmap_scan(port->bmp, &bmp_pos, &bmp_slab) <= 0)) {
1844 #ifdef RTE_SCHED_DEBUG
1845 debug_check_queue_slab(port, bmp_pos, bmp_slab);
1848 /* Return if pipe group already in one of the other grinders */
1849 port->grinder_base_bmp_pos[pos] = RTE_SCHED_BMP_POS_INVALID;
1850 if (unlikely(grinder_pipe_exists(port, bmp_pos))) {
1853 port->grinder_base_bmp_pos[pos] = bmp_pos;
1855 /* Install new pipe group into grinder's pipe cache */
1856 grinder_pcache_populate(port, pos, bmp_pos, bmp_slab);
1858 pipe_qmask = grinder->pcache_qmask[0];
1859 pipe_qindex = grinder->pcache_qindex[0];
1860 grinder->pcache_r = 1;
1863 /* Install new pipe in the grinder */
1864 grinder->pindex = pipe_qindex >> 4;
1865 grinder->subport = port->subport + (grinder->pindex / port->n_pipes_per_subport);
1866 grinder->pipe = port->pipe + grinder->pindex;
1867 grinder->pipe_params = NULL; /* to be set after the pipe structure is prefetched */
1868 grinder->productive = 0;
1870 grinder_tccache_populate(port, pos, pipe_qindex, pipe_qmask);
1871 grinder_next_tc(port, pos);
1873 /* Check for pipe exhaustion */
1874 if (grinder->pindex == port->pipe_loop) {
1875 port->pipe_exhaustion = 1;
1876 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1882 #if RTE_SCHED_WRR == 0
1884 #define grinder_wrr_load(a,b)
1886 #define grinder_wrr_store(a,b)
1889 grinder_wrr(struct rte_sched_port *port, uint32_t pos)
1891 struct rte_sched_grinder *grinder = port->grinder + pos;
1892 uint64_t slab = grinder->qmask;
1894 if (rte_bsf64(slab, &grinder->qpos) == 0) {
1895 rte_panic("grinder wrr\n");
1899 #elif RTE_SCHED_WRR == 1
1902 grinder_wrr_load(struct rte_sched_port *port, uint32_t pos)
1904 struct rte_sched_grinder *grinder = port->grinder + pos;
1905 struct rte_sched_pipe *pipe = grinder->pipe;
1906 struct rte_sched_pipe_profile *pipe_params = grinder->pipe_params;
1907 uint32_t tc_index = grinder->tc_index;
1908 uint32_t qmask = grinder->qmask;
1911 qindex = tc_index * 4;
1913 grinder->wrr_tokens[0] = ((uint16_t) pipe->wrr_tokens[qindex]) << RTE_SCHED_WRR_SHIFT;
1914 grinder->wrr_tokens[1] = ((uint16_t) pipe->wrr_tokens[qindex + 1]) << RTE_SCHED_WRR_SHIFT;
1915 grinder->wrr_tokens[2] = ((uint16_t) pipe->wrr_tokens[qindex + 2]) << RTE_SCHED_WRR_SHIFT;
1916 grinder->wrr_tokens[3] = ((uint16_t) pipe->wrr_tokens[qindex + 3]) << RTE_SCHED_WRR_SHIFT;
1918 grinder->wrr_mask[0] = (qmask & 0x1) * 0xFFFF;
1919 grinder->wrr_mask[1] = ((qmask >> 1) & 0x1) * 0xFFFF;
1920 grinder->wrr_mask[2] = ((qmask >> 2) & 0x1) * 0xFFFF;
1921 grinder->wrr_mask[3] = ((qmask >> 3) & 0x1) * 0xFFFF;
1923 grinder->wrr_cost[0] = pipe_params->wrr_cost[qindex];
1924 grinder->wrr_cost[1] = pipe_params->wrr_cost[qindex + 1];
1925 grinder->wrr_cost[2] = pipe_params->wrr_cost[qindex + 2];
1926 grinder->wrr_cost[3] = pipe_params->wrr_cost[qindex + 3];
1930 grinder_wrr_store(struct rte_sched_port *port, uint32_t pos)
1932 struct rte_sched_grinder *grinder = port->grinder + pos;
1933 struct rte_sched_pipe *pipe = grinder->pipe;
1934 uint32_t tc_index = grinder->tc_index;
1937 qindex = tc_index * 4;
1939 pipe->wrr_tokens[qindex] = (uint8_t) ((grinder->wrr_tokens[0] & grinder->wrr_mask[0]) >> RTE_SCHED_WRR_SHIFT);
1940 pipe->wrr_tokens[qindex + 1] = (uint8_t) ((grinder->wrr_tokens[1] & grinder->wrr_mask[1]) >> RTE_SCHED_WRR_SHIFT);
1941 pipe->wrr_tokens[qindex + 2] = (uint8_t) ((grinder->wrr_tokens[2] & grinder->wrr_mask[2]) >> RTE_SCHED_WRR_SHIFT);
1942 pipe->wrr_tokens[qindex + 3] = (uint8_t) ((grinder->wrr_tokens[3] & grinder->wrr_mask[3]) >> RTE_SCHED_WRR_SHIFT);
1946 grinder_wrr(struct rte_sched_port *port, uint32_t pos)
1948 struct rte_sched_grinder *grinder = port->grinder + pos;
1949 uint16_t wrr_tokens_min;
1951 grinder->wrr_tokens[0] |= ~grinder->wrr_mask[0];
1952 grinder->wrr_tokens[1] |= ~grinder->wrr_mask[1];
1953 grinder->wrr_tokens[2] |= ~grinder->wrr_mask[2];
1954 grinder->wrr_tokens[3] |= ~grinder->wrr_mask[3];
1956 grinder->qpos = rte_min_pos_4_u16(grinder->wrr_tokens);
1957 wrr_tokens_min = grinder->wrr_tokens[grinder->qpos];
1959 grinder->wrr_tokens[0] -= wrr_tokens_min;
1960 grinder->wrr_tokens[1] -= wrr_tokens_min;
1961 grinder->wrr_tokens[2] -= wrr_tokens_min;
1962 grinder->wrr_tokens[3] -= wrr_tokens_min;
1967 #error Invalid value for RTE_SCHED_WRR
1969 #endif /* RTE_SCHED_WRR */
1971 #define grinder_evict(port, pos)
1974 grinder_prefetch_pipe(struct rte_sched_port *port, uint32_t pos)
1976 struct rte_sched_grinder *grinder = port->grinder + pos;
1978 rte_prefetch0(grinder->pipe);
1979 rte_prefetch0(grinder->queue[0]);
1983 grinder_prefetch_tc_queue_arrays(struct rte_sched_port *port, uint32_t pos)
1985 struct rte_sched_grinder *grinder = port->grinder + pos;
1986 uint16_t qsize, qr[4];
1988 qsize = grinder->qsize;
1989 qr[0] = grinder->queue[0]->qr & (qsize - 1);
1990 qr[1] = grinder->queue[1]->qr & (qsize - 1);
1991 qr[2] = grinder->queue[2]->qr & (qsize - 1);
1992 qr[3] = grinder->queue[3]->qr & (qsize - 1);
1994 rte_prefetch0(grinder->qbase[0] + qr[0]);
1995 rte_prefetch0(grinder->qbase[1] + qr[1]);
1997 grinder_wrr_load(port, pos);
1998 grinder_wrr(port, pos);
2000 rte_prefetch0(grinder->qbase[2] + qr[2]);
2001 rte_prefetch0(grinder->qbase[3] + qr[3]);
2005 grinder_prefetch_mbuf(struct rte_sched_port *port, uint32_t pos)
2007 struct rte_sched_grinder *grinder = port->grinder + pos;
2008 uint32_t qpos = grinder->qpos;
2009 struct rte_mbuf **qbase = grinder->qbase[qpos];
2010 uint16_t qsize = grinder->qsize;
2011 uint16_t qr = grinder->queue[qpos]->qr & (qsize - 1);
2013 grinder->pkt = qbase[qr];
2014 rte_prefetch0(grinder->pkt);
2016 if (unlikely((qr & 0x7) == 7)) {
2017 uint16_t qr_next = (grinder->queue[qpos]->qr + 1) & (qsize - 1);
2019 rte_prefetch0(qbase + qr_next);
2023 static inline uint32_t
2024 grinder_handle(struct rte_sched_port *port, uint32_t pos)
2026 struct rte_sched_grinder *grinder = port->grinder + pos;
2028 switch (grinder->state) {
2029 case e_GRINDER_PREFETCH_PIPE:
2031 if (grinder_next_pipe(port, pos)) {
2032 grinder_prefetch_pipe(port, pos);
2033 port->busy_grinders ++;
2035 grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2042 case e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS:
2044 struct rte_sched_pipe *pipe = grinder->pipe;
2046 grinder->pipe_params = port->pipe_profiles + pipe->profile;
2047 grinder_prefetch_tc_queue_arrays(port, pos);
2048 grinder_credits_update(port, pos);
2050 grinder->state = e_GRINDER_PREFETCH_MBUF;
2054 case e_GRINDER_PREFETCH_MBUF:
2056 grinder_prefetch_mbuf(port, pos);
2058 grinder->state = e_GRINDER_READ_MBUF;
2062 case e_GRINDER_READ_MBUF:
2064 uint32_t result = 0;
2066 result = grinder_schedule(port, pos);
2068 /* Look for next packet within the same TC */
2069 if (result && grinder->qmask) {
2070 grinder_wrr(port, pos);
2071 grinder_prefetch_mbuf(port, pos);
2075 grinder_wrr_store(port, pos);
2077 /* Look for another active TC within same pipe */
2078 if (grinder_next_tc(port, pos)) {
2079 grinder_prefetch_tc_queue_arrays(port, pos);
2081 grinder->state = e_GRINDER_PREFETCH_MBUF;
2084 if ((grinder->productive == 0) && (port->pipe_loop == RTE_SCHED_PIPE_INVALID)) {
2085 port->pipe_loop = grinder->pindex;
2087 grinder_evict(port, pos);
2089 /* Look for another active pipe */
2090 if (grinder_next_pipe(port, pos)) {
2091 grinder_prefetch_pipe(port, pos);
2093 grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2097 /* No active pipe found */
2098 port->busy_grinders --;
2100 grinder->state = e_GRINDER_PREFETCH_PIPE;
2105 rte_panic("Algorithmic error (invalid state)\n");
2111 rte_sched_port_time_resync(struct rte_sched_port *port)
2113 uint64_t cycles = rte_get_tsc_cycles();
2114 uint64_t cycles_diff = cycles - port->time_cpu_cycles;
2115 double bytes_diff = ((double) cycles_diff) / port->cycles_per_byte;
2117 /* Advance port time */
2118 port->time_cpu_cycles = cycles;
2119 port->time_cpu_bytes += (uint64_t) bytes_diff;
2120 if (port->time < port->time_cpu_bytes) {
2121 port->time = port->time_cpu_bytes;
2124 /* Reset pipe loop detection */
2125 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
2129 rte_sched_port_exceptions(struct rte_sched_port *port, int second_pass)
2133 /* Check if any exception flag is set */
2134 exceptions = (second_pass && port->busy_grinders == 0) ||
2135 (port->pipe_exhaustion == 1);
2137 /* Clear exception flags */
2138 port->pipe_exhaustion = 0;
2144 rte_sched_port_dequeue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
2148 port->pkts_out = pkts;
2149 port->n_pkts_out = 0;
2151 rte_sched_port_time_resync(port);
2153 /* Take each queue in the grinder one step further */
2154 for (i = 0, count = 0; ; i ++) {
2155 count += grinder_handle(port, i & (RTE_SCHED_PORT_N_GRINDERS - 1));
2156 if ((count == n_pkts) ||
2157 rte_sched_port_exceptions(port, i >= RTE_SCHED_PORT_N_GRINDERS)) {